| stats.txt (9134:275232ad377d) | stats.txt (9199:2a5516167688) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.172545 # Number of seconds simulated 4sim_ticks 1172544977000 # Number of ticks simulated 5final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.207291 # Number of seconds simulated 4sim_ticks 1207290627000 # Number of ticks simulated 5final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 706392 # Simulator instruction rate (inst/s) 8host_op_rate 900233 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13469238975 # Simulator tick rate (ticks/s) 10host_mem_usage 389548 # Number of bytes of host memory used 11host_seconds 87.05 # Real time elapsed on the host 12sim_insts 61493926 # Number of instructions simulated 13sim_ops 78368454 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory 22system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 218 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 275118 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6656529 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57734290 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 1000042 # Simulator instruction rate (inst/s) 8host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19638848032 # Simulator tick rate (ticks/s) 10host_mem_usage 383956 # Number of bytes of host memory used 11host_seconds 61.47 # Real time elapsed on the host 12sim_insts 61477134 # Number of instructions simulated 13sim_ops 78349023 # Number of ops (including micro ops) simulated |
| 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) | 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) |
| 79system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) | 24system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) |
| 81system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) | 26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) |
| 82system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) | 27system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) |
| 84system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) | 29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) |
| 85system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 69301 # number of replacements 88system.l2c.tagsinuse 52667.431766 # Cycle average of tags in use 89system.l2c.total_refs 1645571 # Total number of references to valid blocks. 90system.l2c.sampled_refs 134500 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.234729 # Average number of references to valid blocks. | 30system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory 41system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory 42system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory 45system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 47system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 48system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory 49system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory 58system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory 59system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory 60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 61system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 62system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory 63system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 69267 # number of replacements 92system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use 93system.l2c.total_refs 1645693 # Total number of references to valid blocks. 94system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. 95system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. |
| 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 93system.l2c.occ_blocks::writebacks 39900.139395 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.001242 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3730.644795 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 4216.663550 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.734150 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 2763.076938 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 2054.171414 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.608828 # Average percentage of cache occupancy | 97system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy |
| 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 104system.l2c.occ_percent::cpu0.inst 0.056925 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.064341 # Average percentage of cache occupancy | 109system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy |
| 106system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy | 111system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy |
| 107system.l2c.occ_percent::cpu1.inst 0.042161 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.031344 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.803641 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 4102 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1845 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 402958 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 205810 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5738 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 449307 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 144268 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1215990 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 572486 # number of Writeback hits 120system.l2c.Writeback_hits::total 572486 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1720 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 206 # number of SCUpgradeReq hits | 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits 126system.l2c.Writeback_hits::total 572580 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits |
| 125system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits | 131system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits |
| 126system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 56781 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 53046 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109827 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 4102 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1845 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 402958 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 262591 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5738 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 449307 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 197314 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1325817 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 4102 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1845 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 402958 # number of overall hits 142system.l2c.overall_hits::cpu0.data 262591 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5738 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 449307 # number of overall hits 146system.l2c.overall_hits::cpu1.data 197314 # number of overall hits 147system.l2c.overall_hits::total 1325817 # number of overall hits | 132system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits 148system.l2c.overall_hits::cpu0.data 262598 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits 152system.l2c.overall_hits::cpu1.data 197108 # number of overall hits 153system.l2c.overall_hits::total 1325620 # number of overall hits |
| 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 154system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 155system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 150system.l2c.ReadReq_misses::cpu0.inst 5755 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 7866 # number of ReadReq misses | 156system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses |
| 152system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses | 158system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses |
| 153system.l2c.ReadReq_misses::cpu1.inst 5035 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 3646 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22309 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4696 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 3601 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 568 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 498 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1066 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 67165 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 72394 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 139559 # number of ReadExReq misses | 159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 160system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses 161system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses 162system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses 163system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses 164system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses 165system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses 166system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses 167system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses 168system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses 169system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses 170system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses 171system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses |
| 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 172system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 173system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 167system.l2c.demand_misses::cpu0.inst 5755 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 75031 # number of demand (read+write) misses | 174system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses 175system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses |
| 169system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses | 176system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses |
| 170system.l2c.demand_misses::cpu1.inst 5035 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 76040 # number of demand (read+write) misses 172system.l2c.demand_misses::total 161868 # number of demand (read+write) misses | 177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses 180system.l2c.demand_misses::total 161841 # number of demand (read+write) misses |
| 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 181system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 182system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 175system.l2c.overall_misses::cpu0.inst 5755 # number of overall misses 176system.l2c.overall_misses::cpu0.data 75031 # number of overall misses | 183system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses 184system.l2c.overall_misses::cpu0.data 75067 # number of overall misses |
| 177system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses | 185system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses |
| 178system.l2c.overall_misses::cpu1.inst 5035 # number of overall misses 179system.l2c.overall_misses::cpu1.data 76040 # number of overall misses 180system.l2c.overall_misses::total 161868 # number of overall misses | 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses 188system.l2c.overall_misses::cpu1.data 75979 # number of overall misses 189system.l2c.overall_misses::total 161841 # number of overall misses |
| 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles | 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles |
| 183system.l2c.ReadReq_miss_latency::cpu0.inst 299823500 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 409333998 # number of ReadReq miss cycles | 192system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles |
| 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles | 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles |
| 186system.l2c.ReadReq_miss_latency::cpu1.inst 262768000 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 190087500 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1162377498 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 29968997 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27317000 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 57285997 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3654000 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6100000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 9754000 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3493697466 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 3769025494 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7262722960 # number of ReadExReq miss cycles | 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles 196system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 189491500 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 1161637500 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 30055000 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 27347000 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 57402000 # number of UpgradeReq miss cycles 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6038000 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 9730000 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3494564965 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 3764669994 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7259234959 # number of ReadExReq miss cycles |
| 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles | 208system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles |
| 200system.l2c.demand_miss_latency::cpu0.inst 299823500 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3903031464 # number of demand (read+write) miss cycles | 210system.l2c.demand_miss_latency::cpu0.inst 298918500 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 3904253465 # number of demand (read+write) miss cycles |
| 202system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles | 212system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles |
| 203system.l2c.demand_miss_latency::cpu1.inst 262768000 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 3959112994 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8425100458 # number of demand (read+write) miss cycles | 213system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles 214system.l2c.demand_miss_latency::cpu1.inst 263122000 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 3954161494 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 8420872459 # number of demand (read+write) miss cycles |
| 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles | 217system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 218system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles |
| 208system.l2c.overall_miss_latency::cpu0.inst 299823500 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3903031464 # number of overall miss cycles | 219system.l2c.overall_miss_latency::cpu0.inst 298918500 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 3904253465 # number of overall miss cycles |
| 210system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles | 221system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles |
| 211system.l2c.overall_miss_latency::cpu1.inst 262768000 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 3959112994 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8425100458 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 4103 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1847 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 408713 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 213676 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5742 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1962 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 454342 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 147914 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1238299 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 572486 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 572486 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 5828 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 4189 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 10017 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 774 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 602 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1376 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 123946 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 125440 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 249386 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 4103 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 1847 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 408713 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 337622 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 5742 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 1962 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 454342 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 273354 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1487685 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 4103 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1847 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 408713 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 337622 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5742 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1962 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 454342 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 273354 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1487685 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001083 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.014081 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.036813 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.011082 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.024649 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.018016 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805765 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.859632 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.828292 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.733850 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827243 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.774709 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.541889 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.577121 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.559610 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.001083 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.014081 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.222234 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.011082 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.278174 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.108805 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.001083 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.014081 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.222234 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.011082 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.278174 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.108805 # miss rate for overall accesses | 222system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles 223system.l2c.overall_miss_latency::cpu1.inst 263122000 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 3954161494 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 8420872459 # number of overall miss cycles 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::total 1238188 # number of ReadReq accesses(hits+misses) 235system.l2c.Writeback_accesses::writebacks 572580 # number of Writeback accesses(hits+misses) 236system.l2c.Writeback_accesses::total 572580 # number of Writeback accesses(hits+misses) 237system.l2c.UpgradeReq_accesses::cpu0.data 5834 # number of UpgradeReq accesses(hits+misses) 238system.l2c.UpgradeReq_accesses::cpu1.data 4156 # number of UpgradeReq accesses(hits+misses) 239system.l2c.UpgradeReq_accesses::total 9990 # number of UpgradeReq accesses(hits+misses) 240system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) 241system.l2c.SCUpgradeReq_accesses::cpu1.data 589 # number of SCUpgradeReq accesses(hits+misses) 242system.l2c.SCUpgradeReq_accesses::total 1370 # number of SCUpgradeReq accesses(hits+misses) 243system.l2c.ReadExReq_accesses::cpu0.data 123916 # number of ReadExReq accesses(hits+misses) 244system.l2c.ReadExReq_accesses::cpu1.data 125357 # number of ReadExReq accesses(hits+misses) 245system.l2c.ReadExReq_accesses::total 249273 # number of ReadExReq accesses(hits+misses) 246system.l2c.demand_accesses::cpu0.dtb.walker 4115 # number of demand (read+write) accesses 247system.l2c.demand_accesses::cpu0.itb.walker 1843 # number of demand (read+write) accesses 248system.l2c.demand_accesses::cpu0.inst 408051 # number of demand (read+write) accesses 249system.l2c.demand_accesses::cpu0.data 337665 # number of demand (read+write) accesses 250system.l2c.demand_accesses::cpu1.dtb.walker 5727 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu1.itb.walker 1960 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu1.inst 455013 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu1.data 273087 # number of demand (read+write) accesses 254system.l2c.demand_accesses::total 1487461 # number of demand (read+write) accesses 255system.l2c.overall_accesses::cpu0.dtb.walker 4115 # number of overall (read+write) accesses 256system.l2c.overall_accesses::cpu0.itb.walker 1843 # number of overall (read+write) accesses 257system.l2c.overall_accesses::cpu0.inst 408051 # number of overall (read+write) accesses 258system.l2c.overall_accesses::cpu0.data 337665 # number of overall (read+write) accesses 259system.l2c.overall_accesses::cpu1.dtb.walker 5727 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu1.itb.walker 1960 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu1.inst 455013 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu1.data 273087 # number of overall (read+write) accesses 263system.l2c.overall_accesses::total 1487461 # number of overall (read+write) accesses 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001085 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.014077 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.036838 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000510 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.011083 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.024633 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806308 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862368 # miss rate for UpgradeReq accesses 275system.l2c.UpgradeReq_miss_rate::total 0.829630 # miss rate for UpgradeReq accesses 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728553 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823430 # miss rate for SCUpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::total 0.769343 # miss rate for SCUpgradeReq accesses 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.542246 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.577072 # miss rate for ReadExReq accesses 281system.l2c.ReadExReq_miss_rate::total 0.559760 # miss rate for ReadExReq accesses 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.001085 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.014077 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.222312 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.000510 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.011083 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.278223 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.108804 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.001085 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.014077 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses |
| 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency | 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency |
| 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52097.914857 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52038.392830 # average ReadReq miss latency | 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561 # average ReadReq miss latency |
| 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency | 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency |
| 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52188.282026 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52135.902359 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52103.523152 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6381.813671 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7585.948348 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 6904.422924 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6433.098592 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12248.995984 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 9150.093809 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52016.637624 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52062.677763 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52040.520210 # average ReadExReq miss latency | 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52072.686928 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.243197 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7630.301339 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 6925.916988 # average UpgradeReq miss latency 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 9231.499051 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 52025.219547 # average ReadExReq miss latency |
| 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency | 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency |
| 304system.l2c.demand_avg_miss_latency::cpu0.inst 52097.914857 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52018.918367 # average overall miss latency | 320system.l2c.demand_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency |
| 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency | 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency |
| 307system.l2c.demand_avg_miss_latency::cpu1.inst 52188.282026 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52066.188769 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52049.203413 # average overall miss latency | 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52031.762403 # average overall miss latency |
| 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency | 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency |
| 312system.l2c.overall_avg_miss_latency::cpu0.inst 52097.914857 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52018.918367 # average overall miss latency | 329system.l2c.overall_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency |
| 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency | 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency |
| 315system.l2c.overall_avg_miss_latency::cpu1.inst 52188.282026 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52066.188769 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52049.203413 # average overall miss latency | 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52031.762403 # average overall miss latency |
| 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed | 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 339system.l2c.blocked::no_targets 0 # number of cycles access was blocked 340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 342system.l2c.fast_writes 0 # number of fast writes performed 343system.l2c.cache_copies 0 # number of cache copies performed |
| 326system.l2c.writebacks::writebacks 64176 # number of writebacks 327system.l2c.writebacks::total 64176 # number of writebacks | 344system.l2c.writebacks::writebacks 64155 # number of writebacks 345system.l2c.writebacks::total 64155 # number of writebacks |
| 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses | 346system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 347system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 348system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 349system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 350system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 351system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 352system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 353system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses |
| 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5754 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 7866 # number of ReadReq MSHR misses | 354system.l2c.ReadReq_mshr_misses::cpu0.inst 5743 # number of ReadReq MSHR misses 355system.l2c.ReadReq_mshr_misses::cpu0.data 7874 # number of ReadReq MSHR misses |
| 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses | 356system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses |
| 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5035 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 3646 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22308 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4696 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 3601 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8297 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 568 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 498 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1066 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 67165 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 72394 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 139559 # number of ReadExReq MSHR misses | 357system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 358system.l2c.ReadReq_mshr_misses::cpu1.inst 5043 # number of ReadReq MSHR misses 359system.l2c.ReadReq_mshr_misses::cpu1.data 3639 # number of ReadReq MSHR misses 360system.l2c.ReadReq_mshr_misses::total 22307 # number of ReadReq MSHR misses 361system.l2c.UpgradeReq_mshr_misses::cpu0.data 4704 # number of UpgradeReq MSHR misses 362system.l2c.UpgradeReq_mshr_misses::cpu1.data 3584 # number of UpgradeReq MSHR misses 363system.l2c.UpgradeReq_mshr_misses::total 8288 # number of UpgradeReq MSHR misses 364system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 569 # number of SCUpgradeReq MSHR misses 365system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 485 # number of SCUpgradeReq MSHR misses 366system.l2c.SCUpgradeReq_mshr_misses::total 1054 # number of SCUpgradeReq MSHR misses 367system.l2c.ReadExReq_mshr_misses::cpu0.data 67193 # number of ReadExReq MSHR misses 368system.l2c.ReadExReq_mshr_misses::cpu1.data 72340 # number of ReadExReq MSHR misses 369system.l2c.ReadExReq_mshr_misses::total 139533 # number of ReadExReq MSHR misses |
| 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 352system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses | 370system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 371system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses |
| 353system.l2c.demand_mshr_misses::cpu0.inst 5754 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 75031 # number of demand (read+write) MSHR misses | 372system.l2c.demand_mshr_misses::cpu0.inst 5743 # number of demand (read+write) MSHR misses 373system.l2c.demand_mshr_misses::cpu0.data 75067 # number of demand (read+write) MSHR misses |
| 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses | 374system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses |
| 356system.l2c.demand_mshr_misses::cpu1.inst 5035 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 76040 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 161867 # number of demand (read+write) MSHR misses | 375system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 376system.l2c.demand_mshr_misses::cpu1.inst 5043 # number of demand (read+write) MSHR misses 377system.l2c.demand_mshr_misses::cpu1.data 75979 # number of demand (read+write) MSHR misses 378system.l2c.demand_mshr_misses::total 161840 # number of demand (read+write) MSHR misses |
| 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 360system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses | 379system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 380system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses |
| 361system.l2c.overall_mshr_misses::cpu0.inst 5754 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 75031 # number of overall MSHR misses | 381system.l2c.overall_mshr_misses::cpu0.inst 5743 # number of overall MSHR misses 382system.l2c.overall_mshr_misses::cpu0.data 75067 # number of overall MSHR misses |
| 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses | 383system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses |
| 364system.l2c.overall_mshr_misses::cpu1.inst 5035 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 76040 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 161867 # number of overall MSHR misses | 384system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 385system.l2c.overall_mshr_misses::cpu1.inst 5043 # number of overall MSHR misses 386system.l2c.overall_mshr_misses::cpu1.data 75979 # number of overall MSHR misses 387system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses |
| 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles | 388system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 389system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles |
| 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230747000 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314937000 # number of ReadReq MSHR miss cycles | 390system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229974000 # number of ReadReq MSHR miss cycles 391system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315198000 # number of ReadReq MSHR miss cycles |
| 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles | 392system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles |
| 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202344000 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 146333000 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 894641000 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187986000 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 144285000 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 332271000 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22750000 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19953000 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 42703000 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2687673000 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2900282000 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5587955000 # number of ReadExReq MSHR miss cycles | 393system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles 394system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202602000 # number of ReadReq MSHR miss cycles 395system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145821000 # number of ReadReq MSHR miss cycles 396system.l2c.ReadReq_mshr_miss_latency::total 893915000 # number of ReadReq MSHR miss cycles 397system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188555000 # number of UpgradeReq MSHR miss cycles 398system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143675000 # number of UpgradeReq MSHR miss cycles 399system.l2c.UpgradeReq_mshr_miss_latency::total 332230000 # number of UpgradeReq MSHR miss cycles 400system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22768000 # number of SCUpgradeReq MSHR miss cycles 401system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19442000 # number of SCUpgradeReq MSHR miss cycles 402system.l2c.SCUpgradeReq_mshr_miss_latency::total 42210000 # number of SCUpgradeReq MSHR miss cycles 403system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688204000 # number of ReadExReq MSHR miss cycles 404system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896575000 # number of ReadExReq MSHR miss cycles 405system.l2c.ReadExReq_mshr_miss_latency::total 5584779000 # number of ReadExReq MSHR miss cycles |
| 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles | 406system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 407system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles |
| 386system.l2c.demand_mshr_miss_latency::cpu0.inst 230747000 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 3002610000 # number of demand (read+write) MSHR miss cycles | 408system.l2c.demand_mshr_miss_latency::cpu0.inst 229974000 # number of demand (read+write) MSHR miss cycles 409system.l2c.demand_mshr_miss_latency::cpu0.data 3003402000 # number of demand (read+write) MSHR miss cycles |
| 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles | 410system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles |
| 389system.l2c.demand_mshr_miss_latency::cpu1.inst 202344000 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3046615000 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6482596000 # number of demand (read+write) MSHR miss cycles | 411system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles 412system.l2c.demand_mshr_miss_latency::cpu1.inst 202602000 # number of demand (read+write) MSHR miss cycles 413system.l2c.demand_mshr_miss_latency::cpu1.data 3042396000 # number of demand (read+write) MSHR miss cycles 414system.l2c.demand_mshr_miss_latency::total 6478694000 # number of demand (read+write) MSHR miss cycles |
| 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles | 415system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 416system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles |
| 394system.l2c.overall_mshr_miss_latency::cpu0.inst 230747000 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 3002610000 # number of overall MSHR miss cycles | 417system.l2c.overall_mshr_miss_latency::cpu0.inst 229974000 # number of overall MSHR miss cycles 418system.l2c.overall_mshr_miss_latency::cpu0.data 3003402000 # number of overall MSHR miss cycles |
| 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles | 419system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles |
| 397system.l2c.overall_mshr_miss_latency::cpu1.inst 202344000 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3046615000 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6482596000 # number of overall MSHR miss cycles | 420system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles 421system.l2c.overall_mshr_miss_latency::cpu1.inst 202602000 # number of overall MSHR miss cycles 422system.l2c.overall_mshr_miss_latency::cpu1.data 3042396000 # number of overall MSHR miss cycles 423system.l2c.overall_mshr_miss_latency::total 6478694000 # number of overall MSHR miss cycles |
| 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles | 424system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles |
| 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9314941499 # number of ReadReq MSHR uncacheable cycles | 425system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448668498 # number of ReadReq MSHR uncacheable cycles |
| 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles | 426system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles |
| 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122157234000 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 131741656499 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 694839000 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30621237500 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31316076500 # number of WriteReq MSHR uncacheable cycles | 427system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365734497 # number of ReadReq MSHR uncacheable cycles 428system.l2c.ReadReq_mshr_uncacheable_latency::total 167083883995 # number of ReadReq MSHR uncacheable cycles 429system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles 430system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843793500 # number of WriteReq MSHR uncacheable cycles 431system.l2c.WriteReq_mshr_uncacheable_latency::total 31972096500 # number of WriteReq MSHR uncacheable cycles |
| 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles | 432system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles |
| 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10009780499 # number of overall MSHR uncacheable cycles | 433system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576971498 # number of overall MSHR uncacheable cycles |
| 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles | 434system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles |
| 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152778471500 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 163057732999 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036813 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024649 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018015 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805765 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859632 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.828292 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.733850 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827243 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.774709 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541889 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577121 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.559610 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.108805 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.108805 # mshr miss rate for overall accesses | 435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::total 199055980495 # number of overall MSHR uncacheable cycles 437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses 438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses 443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses 444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses 445system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses 446system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses 447system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses 448system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses 449system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses 450system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses 451system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses 452system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses 453system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses 454system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses 455system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses 457system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses 458system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses 459system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses 460system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses 461system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses 464system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses 465system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses 471system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses 472system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses |
| 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency | 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency |
| 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437 # average ReadReq mshr miss latency | 475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency 476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency |
| 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency | 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency |
| 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571 # average ReadExReq mshr miss latency | 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835 # average ReadExReq mshr miss latency |
| 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency | 493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency |
| 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency | 495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency |
| 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency | 496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency 498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency 499system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency |
| 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency | 502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency 503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency |
| 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency | 504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency |
| 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency | 505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency 507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency 508system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency |
| 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses | 509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 523system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 524system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 525system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 526system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 527system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 528system.cf0.dma_write_txs 0 # Number of DMA write transactions. 529system.cpu0.dtb.inst_hits 0 # ITB inst hits 530system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 501system.cpu0.dtb.read_hits 7082876 # DTB read hits 502system.cpu0.dtb.read_misses 3736 # DTB read misses 503system.cpu0.dtb.write_hits 5665319 # DTB write hits | 531system.cpu0.dtb.read_hits 7076084 # DTB read hits 532system.cpu0.dtb.read_misses 3743 # DTB read misses 533system.cpu0.dtb.write_hits 5660386 # DTB write hits |
| 504system.cpu0.dtb.write_misses 804 # DTB write misses 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 534system.cpu0.dtb.write_misses 804 # DTB write misses 535system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 536system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 537system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 538system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 509system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB | 539system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB |
| 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 511system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 513system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions | 540system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 541system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch 542system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 543system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions |
| 514system.cpu0.dtb.read_accesses 7086612 # DTB read accesses 515system.cpu0.dtb.write_accesses 5666123 # DTB write accesses | 544system.cpu0.dtb.read_accesses 7079827 # DTB read accesses 545system.cpu0.dtb.write_accesses 5661190 # DTB write accesses |
| 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 546system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 517system.cpu0.dtb.hits 12748195 # DTB hits 518system.cpu0.dtb.misses 4540 # DTB misses 519system.cpu0.dtb.accesses 12752735 # DTB accesses 520system.cpu0.itb.inst_hits 29606138 # ITB inst hits | 547system.cpu0.dtb.hits 12736470 # DTB hits 548system.cpu0.dtb.misses 4547 # DTB misses 549system.cpu0.dtb.accesses 12741017 # DTB accesses 550system.cpu0.itb.inst_hits 29574655 # ITB inst hits |
| 521system.cpu0.itb.inst_misses 2205 # ITB inst misses 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 530system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses | 551system.cpu0.itb.inst_misses 2205 # ITB inst misses 552system.cpu0.itb.read_hits 0 # DTB read hits 553system.cpu0.itb.read_misses 0 # DTB read misses 554system.cpu0.itb.write_hits 0 # DTB write hits 555system.cpu0.itb.write_misses 0 # DTB write misses 556system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 558system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 559system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 560system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 565system.cpu0.itb.read_accesses 0 # DTB read accesses 566system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 537system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses 538system.cpu0.itb.hits 29606138 # DTB hits | 567system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses 568system.cpu0.itb.hits 29574655 # DTB hits |
| 539system.cpu0.itb.misses 2205 # DTB misses | 569system.cpu0.itb.misses 2205 # DTB misses |
| 540system.cpu0.itb.accesses 29608343 # DTB accesses 541system.cpu0.numCycles 2345089954 # number of cpu cycles simulated | 570system.cpu0.itb.accesses 29576860 # DTB accesses 571system.cpu0.numCycles 2414581254 # number of cpu cycles simulated |
| 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 544system.cpu0.committedInsts 28907917 # Number of instructions committed 545system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses | 574system.cpu0.committedInsts 28876799 # Number of instructions committed 575system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed 576system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses |
| 547system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses | 577system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses |
| 548system.cpu0.num_func_calls 1243107 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 33149705 # number of integer instructions | 578system.cpu0.num_func_calls 1241592 # number of times a function call or return occured 579system.cpu0.num_conditional_control_insts 4354316 # number of instructions that are conditional controls 580system.cpu0.num_int_insts 33114839 # number of integer instructions |
| 551system.cpu0.num_fp_insts 3860 # number of float instructions | 581system.cpu0.num_fp_insts 3860 # number of float instructions |
| 552system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written | 582system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read 583system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written |
| 554system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written | 584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written |
| 556system.cpu0.num_mem_refs 13418689 # number of memory refs 557system.cpu0.num_load_insts 7420825 # Number of load instructions 558system.cpu0.num_store_insts 5997864 # Number of store instructions 559system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles 560system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles | 586system.cpu0.num_mem_refs 13404188 # number of memory refs 587system.cpu0.num_load_insts 7413537 # Number of load instructions 588system.cpu0.num_store_insts 5990651 # Number of store instructions 589system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles 590system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles 591system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles 592system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles |
| 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 593system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 564system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed 565system.cpu0.icache.replacements 408797 # number of replacements 566system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use 567system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits 579system.cpu0.icache.overall_hits::total 29196812 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 409309 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 409309 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 409309 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 409309 # number of overall misses 585system.cpu0.icache.overall_misses::total 409309 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6108172000 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 6108172000 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 6108172000 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 6108172000 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 6108172000 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 6108172000 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 29606121 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 29606121 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 29606121 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 29606121 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 29606121 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 29606121 # number of overall (read+write) accesses 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013825 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.013825 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013825 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.013825 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013825 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.013825 # miss rate for overall accesses 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 14923.131424 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 14923.131424 # average overall miss latency | 594system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed 595system.cpu0.icache.replacements 408135 # number of replacements 596system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use 597system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. 598system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. 599system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. 600system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. 601system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor 602system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy 603system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy 604system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits 605system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits 606system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits 607system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits 608system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits 609system.cpu0.icache.overall_hits::total 29165991 # number of overall hits 610system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses 611system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses 612system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses 613system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses 614system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses 615system.cpu0.icache.overall_misses::total 408647 # number of overall misses 616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles 617system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # number of ReadReq miss cycles 618system.cpu0.icache.demand_miss_latency::cpu0.inst 6096214000 # number of demand (read+write) miss cycles 619system.cpu0.icache.demand_miss_latency::total 6096214000 # number of demand (read+write) miss cycles 620system.cpu0.icache.overall_miss_latency::cpu0.inst 6096214000 # number of overall miss cycles 621system.cpu0.icache.overall_miss_latency::total 6096214000 # number of overall miss cycles 622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) 623system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) 624system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses 625system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses 626system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses 627system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses 628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses 629system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses 630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses 631system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses 632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses 633system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses 634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency 635system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency 636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency 637system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency 638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency 639system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency |
| 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed | 640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu0.icache.fast_writes 0 # number of fast writes performed 647system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 618system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 409309 # number of ReadReq MSHR misses 619system.cpu0.icache.ReadReq_mshr_misses::total 409309 # number of ReadReq MSHR misses 620system.cpu0.icache.demand_mshr_misses::cpu0.inst 409309 # number of demand (read+write) MSHR misses 621system.cpu0.icache.demand_mshr_misses::total 409309 # number of demand (read+write) MSHR misses 622system.cpu0.icache.overall_mshr_misses::cpu0.inst 409309 # number of overall MSHR misses 623system.cpu0.icache.overall_mshr_misses::total 409309 # number of overall MSHR misses 624system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4879387500 # number of ReadReq MSHR miss cycles 625system.cpu0.icache.ReadReq_mshr_miss_latency::total 4879387500 # number of ReadReq MSHR miss cycles 626system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4879387500 # number of demand (read+write) MSHR miss cycles 627system.cpu0.icache.demand_mshr_miss_latency::total 4879387500 # number of demand (read+write) MSHR miss cycles 628system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4879387500 # number of overall MSHR miss cycles 629system.cpu0.icache.overall_mshr_miss_latency::total 4879387500 # number of overall MSHR miss cycles | 648system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses 649system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses 650system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses 651system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses 652system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses 653system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses 654system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869428500 # number of ReadReq MSHR miss cycles 655system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles 656system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles 657system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles 658system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles 659system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles |
| 630system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 631system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 632system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 633system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles | 660system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 661system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 662system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 663system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles |
| 634system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for ReadReq accesses 635system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013825 # mshr miss rate for ReadReq accesses 636system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for demand accesses 637system.cpu0.icache.demand_mshr_miss_rate::total 0.013825 # mshr miss rate for demand accesses 638system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for overall accesses 639system.cpu0.icache.overall_mshr_miss_rate::total 0.013825 # mshr miss rate for overall accesses 640system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average ReadReq mshr miss latency 641system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430 # average ReadReq mshr miss latency 642system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency 643system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency 644system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency 645system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency | 664system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses 665system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses 666system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses 667system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses 668system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses 669system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses 670system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency 671system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency 672system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency 673system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency 674system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency 675system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency |
| 646system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 647system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 649system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 650system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 676system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 677system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 678system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 679system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 680system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 651system.cpu0.dcache.replacements 330813 # number of replacements 652system.cpu0.dcache.tagsinuse 457.939353 # Cycle average of tags in use 653system.cpu0.dcache.total_refs 12292528 # Total number of references to valid blocks. 654system.cpu0.dcache.sampled_refs 331325 # Sample count of references to valid blocks. 655system.cpu0.dcache.avg_refs 37.101118 # Average number of references to valid blocks. | 681system.cpu0.dcache.replacements 330734 # number of replacements 682system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use 683system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. 684system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. 685system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. |
| 656system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. | 686system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. |
| 657system.cpu0.dcache.occ_blocks::cpu0.data 457.939353 # Average occupied blocks per requestor 658system.cpu0.dcache.occ_percent::cpu0.data 0.894413 # Average percentage of cache occupancy 659system.cpu0.dcache.occ_percent::total 0.894413 # Average percentage of cache occupancy 660system.cpu0.dcache.ReadReq_hits::cpu0.data 6612408 # number of ReadReq hits 661system.cpu0.dcache.ReadReq_hits::total 6612408 # number of ReadReq hits 662system.cpu0.dcache.WriteReq_hits::cpu0.data 5360091 # number of WriteReq hits 663system.cpu0.dcache.WriteReq_hits::total 5360091 # number of WriteReq hits 664system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147992 # number of LoadLockedReq hits 665system.cpu0.dcache.LoadLockedReq_hits::total 147992 # number of LoadLockedReq hits 666system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149726 # number of StoreCondReq hits 667system.cpu0.dcache.StoreCondReq_hits::total 149726 # number of StoreCondReq hits 668system.cpu0.dcache.demand_hits::cpu0.data 11972499 # number of demand (read+write) hits 669system.cpu0.dcache.demand_hits::total 11972499 # number of demand (read+write) hits 670system.cpu0.dcache.overall_hits::cpu0.data 11972499 # number of overall hits 671system.cpu0.dcache.overall_hits::total 11972499 # number of overall hits 672system.cpu0.dcache.ReadReq_misses::cpu0.data 228125 # number of ReadReq misses 673system.cpu0.dcache.ReadReq_misses::total 228125 # number of ReadReq misses 674system.cpu0.dcache.WriteReq_misses::cpu0.data 141749 # number of WriteReq misses 675system.cpu0.dcache.WriteReq_misses::total 141749 # number of WriteReq misses 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9279 # number of LoadLockedReq misses 677system.cpu0.dcache.LoadLockedReq_misses::total 9279 # number of LoadLockedReq misses 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses 679system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses 680system.cpu0.dcache.demand_misses::cpu0.data 369874 # number of demand (read+write) misses 681system.cpu0.dcache.demand_misses::total 369874 # number of demand (read+write) misses 682system.cpu0.dcache.overall_misses::cpu0.data 369874 # number of overall misses 683system.cpu0.dcache.overall_misses::total 369874 # number of overall misses 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443081500 # number of ReadReq miss cycles 685system.cpu0.dcache.ReadReq_miss_latency::total 3443081500 # number of ReadReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917870500 # number of WriteReq miss cycles 687system.cpu0.dcache.WriteReq_miss_latency::total 4917870500 # number of WriteReq miss cycles 688system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100339500 # number of LoadLockedReq miss cycles 689system.cpu0.dcache.LoadLockedReq_miss_latency::total 100339500 # number of LoadLockedReq miss cycles 690system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74628000 # number of StoreCondReq miss cycles 691system.cpu0.dcache.StoreCondReq_miss_latency::total 74628000 # number of StoreCondReq miss cycles 692system.cpu0.dcache.demand_miss_latency::cpu0.data 8360952000 # number of demand (read+write) miss cycles 693system.cpu0.dcache.demand_miss_latency::total 8360952000 # number of demand (read+write) miss cycles 694system.cpu0.dcache.overall_miss_latency::cpu0.data 8360952000 # number of overall miss cycles 695system.cpu0.dcache.overall_miss_latency::total 8360952000 # number of overall miss cycles 696system.cpu0.dcache.ReadReq_accesses::cpu0.data 6840533 # number of ReadReq accesses(hits+misses) 697system.cpu0.dcache.ReadReq_accesses::total 6840533 # number of ReadReq accesses(hits+misses) 698system.cpu0.dcache.WriteReq_accesses::cpu0.data 5501840 # number of WriteReq accesses(hits+misses) 699system.cpu0.dcache.WriteReq_accesses::total 5501840 # number of WriteReq accesses(hits+misses) 700system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157271 # number of LoadLockedReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::total 157271 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157218 # number of StoreCondReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::total 157218 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.demand_accesses::cpu0.data 12342373 # number of demand (read+write) accesses 705system.cpu0.dcache.demand_accesses::total 12342373 # number of demand (read+write) accesses 706system.cpu0.dcache.overall_accesses::cpu0.data 12342373 # number of overall (read+write) accesses 707system.cpu0.dcache.overall_accesses::total 12342373 # number of overall (read+write) accesses 708system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033349 # miss rate for ReadReq accesses 709system.cpu0.dcache.ReadReq_miss_rate::total 0.033349 # miss rate for ReadReq accesses 710system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses 712system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059000 # miss rate for LoadLockedReq accesses 713system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses 714system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses 715system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses 716system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses 717system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses 718system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses 719system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses 720system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency 721system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency 722system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency 723system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency 728system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency 729system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency 730system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency 731system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency | 687system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor 688system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy 689system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy 690system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits 691system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits 692system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits 693system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits 694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits 695system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits 696system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits 697system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits 698system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits 699system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits 700system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits 701system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits 702system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses 703system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses 704system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses 705system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses 706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses 707system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses 708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses 709system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses 710system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses 711system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses 712system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses 713system.cpu0.dcache.overall_misses::total 369775 # number of overall misses 714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles 715system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles 716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles 717system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles 718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles 719system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles 720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles 721system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles 722system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles 723system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles 724system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles 725system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles 726system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) 727system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) 728system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) 729system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) 734system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses 735system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses 736system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses 737system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses 738system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses 739system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses 740system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses 741system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses 742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses 743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses 744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses 745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses 746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses 747system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses 748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses 749system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses 750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency 751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency 752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency 753system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency 754system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency 755system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency 756system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency 757system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency 758system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency 759system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency 760system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency 761system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency |
| 732system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 737system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 738system.cpu0.dcache.fast_writes 0 # number of fast writes performed 739system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 762system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.dcache.fast_writes 0 # number of fast writes performed 769system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 740system.cpu0.dcache.writebacks::writebacks 306322 # number of writebacks 741system.cpu0.dcache.writebacks::total 306322 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses 743system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses 744system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses 745system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses 746system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses 747system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses 748system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses 749system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses 750system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses 751system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses 752system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses 753system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses 754system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles 755system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles 756system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles 757system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles 758system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles 759system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles 760system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles 761system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles 762system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles 763system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles 764system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles 765system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles 766system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles 767system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles 768system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles 769system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles 770system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles 771system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles 772system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses 773system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses 774system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses 775system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses 776system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses 777system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses 778system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses 779system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses 780system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses 781system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses 782system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses 783system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses 784system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency 785system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency 786system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency 787system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency 788system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency 789system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency 790system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency 791system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency 792system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency 793system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency 794system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency 795system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency | 770system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks 771system.cpu0.dcache.writebacks::total 306480 # number of writebacks 772system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses 773system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses 774system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses 775system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses 776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses 777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses 778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses 779system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses 780system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses 781system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses 782system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses 783system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses 784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles 785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles 786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles 787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency 824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 826system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency 828system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency |
| 796system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 797system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 798system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 799system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 800system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 801system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 802system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 803system.cpu1.dtb.inst_hits 0 # ITB inst hits 804system.cpu1.dtb.inst_misses 0 # ITB inst misses | 830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 836system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 837system.cpu1.dtb.inst_hits 0 # ITB inst hits 838system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 805system.cpu1.dtb.read_hits 8314117 # DTB read hits 806system.cpu1.dtb.read_misses 3669 # DTB read misses 807system.cpu1.dtb.write_hits 5830380 # DTB write hits 808system.cpu1.dtb.write_misses 1436 # DTB write misses | 839system.cpu1.dtb.read_hits 8318170 # DTB read hits 840system.cpu1.dtb.read_misses 3663 # DTB read misses 841system.cpu1.dtb.write_hits 5832653 # DTB write hits 842system.cpu1.dtb.write_misses 1435 # DTB write misses |
| 809system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 810system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 811system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 812system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 843system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 844system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 845system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 846system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 813system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB | 847system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB |
| 814system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 848system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 815system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch | 849system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch |
| 816system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 817system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions | 850system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 851system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions |
| 818system.cpu1.dtb.read_accesses 8317786 # DTB read accesses 819system.cpu1.dtb.write_accesses 5831816 # DTB write accesses | 852system.cpu1.dtb.read_accesses 8321833 # DTB read accesses 853system.cpu1.dtb.write_accesses 5834088 # DTB write accesses |
| 820system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 854system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 821system.cpu1.dtb.hits 14144497 # DTB hits 822system.cpu1.dtb.misses 5105 # DTB misses 823system.cpu1.dtb.accesses 14149602 # DTB accesses 824system.cpu1.itb.inst_hits 33196626 # ITB inst hits | 855system.cpu1.dtb.hits 14150823 # DTB hits 856system.cpu1.dtb.misses 5098 # DTB misses 857system.cpu1.dtb.accesses 14155921 # DTB accesses 858system.cpu1.itb.inst_hits 33211066 # ITB inst hits |
| 825system.cpu1.itb.inst_misses 2171 # ITB inst misses 826system.cpu1.itb.read_hits 0 # DTB read hits 827system.cpu1.itb.read_misses 0 # DTB read misses 828system.cpu1.itb.write_hits 0 # DTB write hits 829system.cpu1.itb.write_misses 0 # DTB write misses 830system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 831system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 832system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 833system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 834system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 835system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 836system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 837system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 838system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 839system.cpu1.itb.read_accesses 0 # DTB read accesses 840system.cpu1.itb.write_accesses 0 # DTB write accesses | 859system.cpu1.itb.inst_misses 2171 # ITB inst misses 860system.cpu1.itb.read_hits 0 # DTB read hits 861system.cpu1.itb.read_misses 0 # DTB read misses 862system.cpu1.itb.write_hits 0 # DTB write hits 863system.cpu1.itb.write_misses 0 # DTB write misses 864system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 865system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 866system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 867system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 868system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 869system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 870system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 871system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 872system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 873system.cpu1.itb.read_accesses 0 # DTB read accesses 874system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 841system.cpu1.itb.inst_accesses 33198797 # ITB inst accesses 842system.cpu1.itb.hits 33196626 # DTB hits | 875system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses 876system.cpu1.itb.hits 33211066 # DTB hits |
| 843system.cpu1.itb.misses 2171 # DTB misses | 877system.cpu1.itb.misses 2171 # DTB misses |
| 844system.cpu1.itb.accesses 33198797 # DTB accesses 845system.cpu1.numCycles 2343593518 # number of cpu cycles simulated | 878system.cpu1.itb.accesses 33213237 # DTB accesses 879system.cpu1.numCycles 2413083038 # number of cpu cycles simulated |
| 846system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 847system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 880system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 881system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 848system.cpu1.committedInsts 32586009 # Number of instructions committed 849system.cpu1.committedOps 41102854 # Number of ops (including micro ops) committed 850system.cpu1.num_int_alu_accesses 37326288 # Number of integer alu accesses | 882system.cpu1.committedInsts 32600335 # Number of instructions committed 883system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed 884system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses |
| 851system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses | 885system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses |
| 852system.cpu1.num_func_calls 962171 # number of times a function call or return occured 853system.cpu1.num_conditional_control_insts 3714570 # number of instructions that are conditional controls 854system.cpu1.num_int_insts 37326288 # number of integer instructions | 886system.cpu1.num_func_calls 963082 # number of times a function call or return occured 887system.cpu1.num_conditional_control_insts 3716244 # number of instructions that are conditional controls 888system.cpu1.num_int_insts 37342001 # number of integer instructions |
| 855system.cpu1.num_fp_insts 6793 # number of float instructions | 889system.cpu1.num_fp_insts 6793 # number of float instructions |
| 856system.cpu1.num_int_register_reads 213739964 # number of times the integer registers were read 857system.cpu1.num_int_register_writes 39466250 # number of times the integer registers were written | 890system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read 891system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written |
| 858system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 859system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written | 892system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 893system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written |
| 860system.cpu1.num_mem_refs 14682267 # number of memory refs 861system.cpu1.num_load_insts 8636040 # Number of load instructions 862system.cpu1.num_store_insts 6046227 # Number of store instructions 863system.cpu1.num_idle_cycles 1858750530.714142 # Number of idle cycles 864system.cpu1.num_busy_cycles 484842987.285858 # Number of busy cycles 865system.cpu1.not_idle_fraction 0.206880 # Percentage of non-idle cycles 866system.cpu1.idle_fraction 0.793120 # Percentage of idle cycles | 894system.cpu1.num_mem_refs 14689113 # number of memory refs 895system.cpu1.num_load_insts 8640454 # Number of load instructions 896system.cpu1.num_store_insts 6048659 # Number of store instructions 897system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles 898system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles 899system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles 900system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles |
| 867system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 901system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 868system.cpu1.kern.inst.quiesce 43921 # number of quiesce instructions executed 869system.cpu1.icache.replacements 454393 # number of replacements 870system.cpu1.icache.tagsinuse 478.384673 # Cycle average of tags in use 871system.cpu1.icache.total_refs 32741717 # Total number of references to valid blocks. 872system.cpu1.icache.sampled_refs 454905 # Sample count of references to valid blocks. 873system.cpu1.icache.avg_refs 71.974845 # Average number of references to valid blocks. 874system.cpu1.icache.warmup_cycle 92994898000 # Cycle when the warmup percentage was hit. 875system.cpu1.icache.occ_blocks::cpu1.inst 478.384673 # Average occupied blocks per requestor 876system.cpu1.icache.occ_percent::cpu1.inst 0.934345 # Average percentage of cache occupancy 877system.cpu1.icache.occ_percent::total 0.934345 # Average percentage of cache occupancy 878system.cpu1.icache.ReadReq_hits::cpu1.inst 32741717 # number of ReadReq hits 879system.cpu1.icache.ReadReq_hits::total 32741717 # number of ReadReq hits 880system.cpu1.icache.demand_hits::cpu1.inst 32741717 # number of demand (read+write) hits 881system.cpu1.icache.demand_hits::total 32741717 # number of demand (read+write) hits 882system.cpu1.icache.overall_hits::cpu1.inst 32741717 # number of overall hits 883system.cpu1.icache.overall_hits::total 32741717 # number of overall hits 884system.cpu1.icache.ReadReq_misses::cpu1.inst 454905 # number of ReadReq misses 885system.cpu1.icache.ReadReq_misses::total 454905 # number of ReadReq misses 886system.cpu1.icache.demand_misses::cpu1.inst 454905 # number of demand (read+write) misses 887system.cpu1.icache.demand_misses::total 454905 # number of demand (read+write) misses 888system.cpu1.icache.overall_misses::cpu1.inst 454905 # number of overall misses 889system.cpu1.icache.overall_misses::total 454905 # number of overall misses 890system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6718353500 # number of ReadReq miss cycles 891system.cpu1.icache.ReadReq_miss_latency::total 6718353500 # number of ReadReq miss cycles 892system.cpu1.icache.demand_miss_latency::cpu1.inst 6718353500 # number of demand (read+write) miss cycles 893system.cpu1.icache.demand_miss_latency::total 6718353500 # number of demand (read+write) miss cycles 894system.cpu1.icache.overall_miss_latency::cpu1.inst 6718353500 # number of overall miss cycles 895system.cpu1.icache.overall_miss_latency::total 6718353500 # number of overall miss cycles 896system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196622 # number of ReadReq accesses(hits+misses) 897system.cpu1.icache.ReadReq_accesses::total 33196622 # number of ReadReq accesses(hits+misses) 898system.cpu1.icache.demand_accesses::cpu1.inst 33196622 # number of demand (read+write) accesses 899system.cpu1.icache.demand_accesses::total 33196622 # number of demand (read+write) accesses 900system.cpu1.icache.overall_accesses::cpu1.inst 33196622 # number of overall (read+write) accesses 901system.cpu1.icache.overall_accesses::total 33196622 # number of overall (read+write) accesses 902system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013703 # miss rate for ReadReq accesses 903system.cpu1.icache.ReadReq_miss_rate::total 0.013703 # miss rate for ReadReq accesses 904system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013703 # miss rate for demand accesses 905system.cpu1.icache.demand_miss_rate::total 0.013703 # miss rate for demand accesses 906system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013703 # miss rate for overall accesses 907system.cpu1.icache.overall_miss_rate::total 0.013703 # miss rate for overall accesses 908system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662 # average ReadReq miss latency 909system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662 # average ReadReq miss latency 910system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency 911system.cpu1.icache.demand_avg_miss_latency::total 14768.695662 # average overall miss latency 912system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency 913system.cpu1.icache.overall_avg_miss_latency::total 14768.695662 # average overall miss latency | 902system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed 903system.cpu1.icache.replacements 455071 # number of replacements 904system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use 905system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. 906system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. 907system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. 908system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. 909system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor 910system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy 911system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy 912system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits 913system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits 914system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits 915system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits 916system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits 917system.cpu1.icache.overall_hits::total 32755479 # number of overall hits 918system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses 919system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses 920system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses 921system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses 922system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses 923system.cpu1.icache.overall_misses::total 455583 # number of overall misses 924system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles 925system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles 926system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles 927system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles 928system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles 929system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles 930system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) 931system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) 932system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses 933system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses 934system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses 935system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses 936system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses 937system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses 938system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses 939system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses 940system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses 941system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses 942system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency 943system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency 944system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency 945system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency 946system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency 947system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency |
| 914system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 915system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 916system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 917system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 918system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 919system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 920system.cpu1.icache.fast_writes 0 # number of fast writes performed 921system.cpu1.icache.cache_copies 0 # number of cache copies performed | 948system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 949system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 950system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 951system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 952system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 953system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 954system.cpu1.icache.fast_writes 0 # number of fast writes performed 955system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 922system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454905 # number of ReadReq MSHR misses 923system.cpu1.icache.ReadReq_mshr_misses::total 454905 # number of ReadReq MSHR misses 924system.cpu1.icache.demand_mshr_misses::cpu1.inst 454905 # number of demand (read+write) MSHR misses 925system.cpu1.icache.demand_mshr_misses::total 454905 # number of demand (read+write) MSHR misses 926system.cpu1.icache.overall_mshr_misses::cpu1.inst 454905 # number of overall MSHR misses 927system.cpu1.icache.overall_mshr_misses::total 454905 # number of overall MSHR misses 928system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5352734000 # number of ReadReq MSHR miss cycles 929system.cpu1.icache.ReadReq_mshr_miss_latency::total 5352734000 # number of ReadReq MSHR miss cycles 930system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5352734000 # number of demand (read+write) MSHR miss cycles 931system.cpu1.icache.demand_mshr_miss_latency::total 5352734000 # number of demand (read+write) MSHR miss cycles 932system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5352734000 # number of overall MSHR miss cycles 933system.cpu1.icache.overall_mshr_miss_latency::total 5352734000 # number of overall MSHR miss cycles | 956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses 957system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses 958system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses 959system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses 960system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses 961system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses 962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles 963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles 964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles 965system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles 966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles 967system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles |
| 934system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 935system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 936system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 937system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles | 968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles |
| 938system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for ReadReq accesses 939system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013703 # mshr miss rate for ReadReq accesses 940system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for demand accesses 941system.cpu1.icache.demand_mshr_miss_rate::total 0.013703 # mshr miss rate for demand accesses 942system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for overall accesses 943system.cpu1.icache.overall_mshr_miss_rate::total 0.013703 # mshr miss rate for overall accesses 944system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average ReadReq mshr miss latency 945system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334 # average ReadReq mshr miss latency 946system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency 947system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency 948system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency 949system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency | 972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses 973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses 974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses 975system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses 976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses 977system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses 978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency 979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency 980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency 981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency 982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency 983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency |
| 950system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 951system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 952system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 953system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 954system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 955system.cpu1.dcache.replacements 292476 # number of replacements 956system.cpu1.dcache.tagsinuse 472.237187 # Cycle average of tags in use 957system.cpu1.dcache.total_refs 11966907 # Total number of references to valid blocks. 958system.cpu1.dcache.sampled_refs 292816 # Sample count of references to valid blocks. 959system.cpu1.dcache.avg_refs 40.868351 # Average number of references to valid blocks. 960system.cpu1.dcache.warmup_cycle 84138671000 # Cycle when the warmup percentage was hit. 961system.cpu1.dcache.occ_blocks::cpu1.data 472.237187 # Average occupied blocks per requestor 962system.cpu1.dcache.occ_percent::cpu1.data 0.922338 # Average percentage of cache occupancy 963system.cpu1.dcache.occ_percent::total 0.922338 # Average percentage of cache occupancy 964system.cpu1.dcache.ReadReq_hits::cpu1.data 6949314 # number of ReadReq hits 965system.cpu1.dcache.ReadReq_hits::total 6949314 # number of ReadReq hits 966system.cpu1.dcache.WriteReq_hits::cpu1.data 4829723 # number of WriteReq hits 967system.cpu1.dcache.WriteReq_hits::total 4829723 # number of WriteReq hits 968system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81817 # number of LoadLockedReq hits 969system.cpu1.dcache.LoadLockedReq_hits::total 81817 # number of LoadLockedReq hits 970system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82772 # number of StoreCondReq hits 971system.cpu1.dcache.StoreCondReq_hits::total 82772 # number of StoreCondReq hits 972system.cpu1.dcache.demand_hits::cpu1.data 11779037 # number of demand (read+write) hits 973system.cpu1.dcache.demand_hits::total 11779037 # number of demand (read+write) hits 974system.cpu1.dcache.overall_hits::cpu1.data 11779037 # number of overall hits 975system.cpu1.dcache.overall_hits::total 11779037 # number of overall hits 976system.cpu1.dcache.ReadReq_misses::cpu1.data 170766 # number of ReadReq misses 977system.cpu1.dcache.ReadReq_misses::total 170766 # number of ReadReq misses 978system.cpu1.dcache.WriteReq_misses::cpu1.data 150259 # number of WriteReq misses 979system.cpu1.dcache.WriteReq_misses::total 150259 # number of WriteReq misses 980system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11112 # number of LoadLockedReq misses 981system.cpu1.dcache.LoadLockedReq_misses::total 11112 # number of LoadLockedReq misses 982system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10077 # number of StoreCondReq misses 983system.cpu1.dcache.StoreCondReq_misses::total 10077 # number of StoreCondReq misses 984system.cpu1.dcache.demand_misses::cpu1.data 321025 # number of demand (read+write) misses 985system.cpu1.dcache.demand_misses::total 321025 # number of demand (read+write) misses 986system.cpu1.dcache.overall_misses::cpu1.data 321025 # number of overall misses 987system.cpu1.dcache.overall_misses::total 321025 # number of overall misses 988system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2375372000 # number of ReadReq miss cycles 989system.cpu1.dcache.ReadReq_miss_latency::total 2375372000 # number of ReadReq miss cycles 990system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5143695000 # number of WriteReq miss cycles 991system.cpu1.dcache.WriteReq_miss_latency::total 5143695000 # number of WriteReq miss cycles 992system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106521500 # number of LoadLockedReq miss cycles 993system.cpu1.dcache.LoadLockedReq_miss_latency::total 106521500 # number of LoadLockedReq miss cycles 994system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 88394000 # number of StoreCondReq miss cycles 995system.cpu1.dcache.StoreCondReq_miss_latency::total 88394000 # number of StoreCondReq miss cycles 996system.cpu1.dcache.demand_miss_latency::cpu1.data 7519067000 # number of demand (read+write) miss cycles 997system.cpu1.dcache.demand_miss_latency::total 7519067000 # number of demand (read+write) miss cycles 998system.cpu1.dcache.overall_miss_latency::cpu1.data 7519067000 # number of overall miss cycles 999system.cpu1.dcache.overall_miss_latency::total 7519067000 # number of overall miss cycles 1000system.cpu1.dcache.ReadReq_accesses::cpu1.data 7120080 # number of ReadReq accesses(hits+misses) 1001system.cpu1.dcache.ReadReq_accesses::total 7120080 # number of ReadReq accesses(hits+misses) 1002system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979982 # number of WriteReq accesses(hits+misses) 1003system.cpu1.dcache.WriteReq_accesses::total 4979982 # number of WriteReq accesses(hits+misses) 1004system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92929 # number of LoadLockedReq accesses(hits+misses) 1005system.cpu1.dcache.LoadLockedReq_accesses::total 92929 # number of LoadLockedReq accesses(hits+misses) 1006system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92849 # number of StoreCondReq accesses(hits+misses) 1007system.cpu1.dcache.StoreCondReq_accesses::total 92849 # number of StoreCondReq accesses(hits+misses) 1008system.cpu1.dcache.demand_accesses::cpu1.data 12100062 # number of demand (read+write) accesses 1009system.cpu1.dcache.demand_accesses::total 12100062 # number of demand (read+write) accesses 1010system.cpu1.dcache.overall_accesses::cpu1.data 12100062 # number of overall (read+write) accesses 1011system.cpu1.dcache.overall_accesses::total 12100062 # number of overall (read+write) accesses 1012system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023984 # miss rate for ReadReq accesses 1013system.cpu1.dcache.ReadReq_miss_rate::total 0.023984 # miss rate for ReadReq accesses 1014system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030173 # miss rate for WriteReq accesses 1015system.cpu1.dcache.WriteReq_miss_rate::total 0.030173 # miss rate for WriteReq accesses 1016system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119575 # miss rate for LoadLockedReq accesses 1017system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119575 # miss rate for LoadLockedReq accesses 1018system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108531 # miss rate for StoreCondReq accesses 1019system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108531 # miss rate for StoreCondReq accesses 1020system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026531 # miss rate for demand accesses 1021system.cpu1.dcache.demand_miss_rate::total 0.026531 # miss rate for demand accesses 1022system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026531 # miss rate for overall accesses 1023system.cpu1.dcache.overall_miss_rate::total 0.026531 # miss rate for overall accesses 1024system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13910.099200 # average ReadReq miss latency 1025system.cpu1.dcache.ReadReq_avg_miss_latency::total 13910.099200 # average ReadReq miss latency 1026system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34232.192414 # average WriteReq miss latency 1027system.cpu1.dcache.WriteReq_avg_miss_latency::total 34232.192414 # average WriteReq miss latency 1028system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9586.168107 # average LoadLockedReq miss latency 1029system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9586.168107 # average LoadLockedReq miss latency 1030system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8771.856703 # average StoreCondReq miss latency 1031system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8771.856703 # average StoreCondReq miss latency 1032system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency 1033system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587 # average overall miss latency 1034system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency 1035system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587 # average overall miss latency | 989system.cpu1.dcache.replacements 292605 # number of replacements 990system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use 991system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. 992system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. 993system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. 994system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. 995system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor 996system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy 997system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy 998system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits 999system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits 1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits 1001system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits 1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits 1003system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits 1004system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits 1005system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits 1006system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits 1007system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits 1008system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits 1009system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits 1010system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses 1011system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses 1012system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses 1013system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses 1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses 1015system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses 1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses 1017system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses 1018system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses 1019system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses 1020system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses 1021system.cpu1.dcache.overall_misses::total 321159 # number of overall misses 1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles 1023system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles 1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles 1025system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles 1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles 1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles 1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles 1029system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles 1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles 1031system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles 1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles 1033system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles 1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) 1035system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) 1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) 1037system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) 1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) 1039system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) 1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) 1041system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) 1042system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses 1043system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses 1044system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses 1045system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses 1046system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses 1047system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses 1048system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses 1049system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses 1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses 1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses 1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses 1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses 1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses 1055system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses 1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses 1057system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses 1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency 1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency 1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency 1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency 1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency 1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency 1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency 1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency 1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency 1067system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency 1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency 1069system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency |
| 1036system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1037system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1038system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1039system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1040system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1041system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1042system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1043system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1044system.cpu1.dcache.writebacks::writebacks 266164 # number of writebacks 1045system.cpu1.dcache.writebacks::total 266164 # number of writebacks 1046system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170766 # number of ReadReq MSHR misses 1047system.cpu1.dcache.ReadReq_mshr_misses::total 170766 # number of ReadReq MSHR misses 1048system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150259 # number of WriteReq MSHR misses 1049system.cpu1.dcache.WriteReq_mshr_misses::total 150259 # number of WriteReq MSHR misses 1050system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11112 # number of LoadLockedReq MSHR misses 1051system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11112 # number of LoadLockedReq MSHR misses 1052system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10067 # number of StoreCondReq MSHR misses 1053system.cpu1.dcache.StoreCondReq_mshr_misses::total 10067 # number of StoreCondReq MSHR misses 1054system.cpu1.dcache.demand_mshr_misses::cpu1.data 321025 # number of demand (read+write) MSHR misses 1055system.cpu1.dcache.demand_mshr_misses::total 321025 # number of demand (read+write) MSHR misses 1056system.cpu1.dcache.overall_mshr_misses::cpu1.data 321025 # number of overall MSHR misses 1057system.cpu1.dcache.overall_mshr_misses::total 321025 # number of overall MSHR misses 1058system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862452631 # number of ReadReq MSHR miss cycles 1059system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862452631 # number of ReadReq MSHR miss cycles 1060system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4692688176 # number of WriteReq MSHR miss cycles 1061system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4692688176 # number of WriteReq MSHR miss cycles 1062system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73165002 # number of LoadLockedReq MSHR miss cycles 1063system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73165002 # number of LoadLockedReq MSHR miss cycles 1064system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 58182011 # number of StoreCondReq MSHR miss cycles 1065system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 58182011 # number of StoreCondReq MSHR miss cycles 1066system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6555140807 # number of demand (read+write) MSHR miss cycles 1067system.cpu1.dcache.demand_mshr_miss_latency::total 6555140807 # number of demand (read+write) MSHR miss cycles 1068system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6555140807 # number of overall MSHR miss cycles 1069system.cpu1.dcache.overall_mshr_miss_latency::total 6555140807 # number of overall MSHR miss cycles 1070system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500 # number of ReadReq MSHR uncacheable cycles 1071system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500 # number of ReadReq MSHR uncacheable cycles 1072system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39709759000 # number of WriteReq MSHR uncacheable cycles 1073system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39709759000 # number of WriteReq MSHR uncacheable cycles 1074system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500 # number of overall MSHR uncacheable cycles 1075system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500 # number of overall MSHR uncacheable cycles 1076system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023984 # mshr miss rate for ReadReq accesses 1077system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023984 # mshr miss rate for ReadReq accesses 1078system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030173 # mshr miss rate for WriteReq accesses 1079system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030173 # mshr miss rate for WriteReq accesses 1080system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119575 # mshr miss rate for LoadLockedReq accesses 1081system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119575 # mshr miss rate for LoadLockedReq accesses 1082system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108423 # mshr miss rate for StoreCondReq accesses 1083system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108423 # mshr miss rate for StoreCondReq accesses 1084system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for demand accesses 1085system.cpu1.dcache.demand_mshr_miss_rate::total 0.026531 # mshr miss rate for demand accesses 1086system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for overall accesses 1087system.cpu1.dcache.overall_mshr_miss_rate::total 0.026531 # mshr miss rate for overall accesses 1088system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484 # average ReadReq mshr miss latency 1089system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484 # average ReadReq mshr miss latency 1090system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895 # average WriteReq mshr miss latency 1091system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895 # average WriteReq mshr miss latency 1092system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6584.323434 # average LoadLockedReq mshr miss latency 1093system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6584.323434 # average LoadLockedReq mshr miss latency 1094system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5779.478593 # average StoreCondReq mshr miss latency 1095system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5779.478593 # average StoreCondReq mshr miss latency 1096system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency 1097system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency 1098system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency 1099system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency | 1078system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks 1079system.cpu1.dcache.writebacks::total 266100 # number of writebacks 1080system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses 1081system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses 1082system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses 1083system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses 1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses 1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses 1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses 1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses 1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses 1089system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses 1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses 1091system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses 1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles 1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles 1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles 1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles 1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles 1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles 1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles 1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles 1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles 1101system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles 1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles 1103system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles 1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles 1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles 1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles 1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles 1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles 1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles 1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses 1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses 1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses 1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses 1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses 1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses 1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses 1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses 1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses 1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses 1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses 1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses 1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency 1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency 1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency 1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency 1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency 1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency 1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency 1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency 1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency 1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency 1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency 1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency |
| 1100system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1101system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1102system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1103system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1104system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1105system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1106system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1107system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1113system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1114system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1115system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1116system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1117system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1118system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1119system.iocache.fast_writes 0 # number of fast writes performed 1120system.iocache.cache_copies 0 # number of cache copies performed | 1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.iocache.fast_writes 0 # number of fast writes performed 1154system.iocache.cache_copies 0 # number of cache copies performed |
| 1121system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles 1122system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles 1123system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles 1124system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles | 1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles 1156system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles 1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles 1158system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles |
| 1125system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1126system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1127system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1128system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1129system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1130 1131---------- End Simulation Statistics ---------- | 1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1164 1165---------- End Simulation Statistics ---------- |