| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.169301 # Number of seconds simulated 4sim_ticks 1169301297000 # Number of ticks simulated 5final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.171613 # Number of seconds simulated 4sim_ticks 1171612619000 # Number of ticks simulated 5final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 971844 # Simulator instruction rate (inst/s) 8host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18805861990 # Simulator tick rate (ticks/s) 10host_mem_usage 384788 # Number of bytes of host memory used 11host_seconds 62.18 # Real time elapsed on the host 12sim_insts 60426768 # Number of instructions simulated 13sim_ops 77275723 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 639669 # Simulator instruction rate (inst/s) 8host_op_rate 818158 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12399663305 # Simulator tick rate (ticks/s) 10host_mem_usage 384708 # Number of bytes of host memory used 11host_seconds 94.49 # Real time elapsed on the host 12sim_insts 60440687 # Number of instructions simulated 13sim_ops 77305655 # Number of ops (including micro ops) simulated |
| 32system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 35system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory |
| 37system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory |
| 38system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory 40system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory 41system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory 42system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory 44system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory | 20system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory 22system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory |
| 45system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 47system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory | 29system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory |
| 48system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory 49system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 30system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 51system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory |
| 53system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory |
| 54system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory | 36system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory |
| 58system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 60system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) | 42system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) | 44system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) |
| 67system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s) |
| 79system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) |
| 81system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s) |
| 83system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) |
| 84system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 69045 # number of replacements 88system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use 89system.l2c.total_refs 1684870 # Total number of references to valid blocks. 90system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. | 66system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 69306 # number of replacements 88system.l2c.tagsinuse 52659.016481 # Cycle average of tags in use 89system.l2c.total_refs 1685686 # Total number of references to valid blocks. 90system.l2c.sampled_refs 134505 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.532516 # Average number of references to valid blocks. |
| 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 93system.l2c.occ_blocks::writebacks 39883.931908 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000281 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.001232 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3733.911815 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 4222.338805 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.732261 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 2761.000373 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 2056.498545 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.608581 # Average percentage of cache occupancy | 93system.l2c.occ_blocks::writebacks 39891.573384 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.001243 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3742.951187 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 4216.912189 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.733680 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 2750.765696 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 2054.078820 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.608697 # Average percentage of cache occupancy |
| 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 104system.l2c.occ_percent::cpu0.inst 0.056975 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.064428 # Average percentage of cache occupancy | 104system.l2c.occ_percent::cpu0.inst 0.057113 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.064345 # Average percentage of cache occupancy |
| 106system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy | 106system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy |
| 107system.l2c.occ_percent::cpu1.inst 0.042130 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.031380 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.803534 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 4332 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1875 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 401384 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 204711 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5503 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1891 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 448240 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 143182 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1211118 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 615916 # number of Writeback hits 120system.l2c.Writeback_hits::total 615916 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1171 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 482 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1653 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 105 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 56705 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 52894 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109599 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 4332 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1875 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 401384 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 261416 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5503 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1891 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 448240 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 196076 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1320717 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 4332 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1875 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 401384 # number of overall hits 142system.l2c.overall_hits::cpu0.data 261416 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5503 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1891 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 448240 # number of overall hits 146system.l2c.overall_hits::cpu1.data 196076 # number of overall hits 147system.l2c.overall_hits::total 1320717 # number of overall hits | 107system.l2c.occ_percent::cpu1.inst 0.041973 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.031343 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.803513 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 4104 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1844 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 401511 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 204865 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5725 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 448415 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 143316 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1211742 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 616867 # number of Writeback hits 120system.l2c.Writeback_hits::total 616867 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1168 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1743 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 56775 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 52975 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109750 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 4104 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1844 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 401511 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 261640 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5725 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 448415 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 196291 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1321492 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 4104 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1844 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 401511 # number of overall hits 142system.l2c.overall_hits::cpu0.data 261640 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5725 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 448415 # number of overall hits 146system.l2c.overall_hits::cpu1.data 196291 # number of overall hits 147system.l2c.overall_hits::total 1321492 # number of overall hits |
| 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 150system.l2c.ReadReq_misses::cpu0.inst 5749 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 7868 # number of ReadReq misses | 150system.l2c.ReadReq_misses::cpu0.inst 5773 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 7865 # number of ReadReq misses |
| 152system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses | 152system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses |
| 153system.l2c.ReadReq_misses::cpu1.inst 5038 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 3631 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22293 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4671 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 3578 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8249 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 565 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 471 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1036 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 66836 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 72487 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 139323 # number of ReadExReq misses | 153system.l2c.ReadReq_misses::cpu1.inst 5025 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 3646 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22316 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4668 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 3562 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8230 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 67164 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 72393 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 139557 # number of ReadExReq misses |
| 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 167system.l2c.demand_misses::cpu0.inst 5749 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 74704 # number of demand (read+write) misses | 167system.l2c.demand_misses::cpu0.inst 5773 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 75029 # number of demand (read+write) misses |
| 169system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses | 169system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses |
| 170system.l2c.demand_misses::cpu1.inst 5038 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 76118 # number of demand (read+write) misses 172system.l2c.demand_misses::total 161616 # number of demand (read+write) misses | 170system.l2c.demand_misses::cpu1.inst 5025 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 76039 # number of demand (read+write) misses 172system.l2c.demand_misses::total 161873 # number of demand (read+write) misses |
| 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 175system.l2c.overall_misses::cpu0.inst 5749 # number of overall misses 176system.l2c.overall_misses::cpu0.data 74704 # number of overall misses | 175system.l2c.overall_misses::cpu0.inst 5773 # number of overall misses 176system.l2c.overall_misses::cpu0.data 75029 # number of overall misses |
| 177system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses | 177system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses |
| 178system.l2c.overall_misses::cpu1.inst 5038 # number of overall misses 179system.l2c.overall_misses::cpu1.data 76118 # number of overall misses 180system.l2c.overall_misses::total 161616 # number of overall misses | 178system.l2c.overall_misses::cpu1.inst 5025 # number of overall misses 179system.l2c.overall_misses::cpu1.data 76039 # number of overall misses 180system.l2c.overall_misses::total 161873 # number of overall misses |
| 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles | 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles |
| 183system.l2c.ReadReq_miss_latency::cpu0.inst 299700000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 409350000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 211000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 263300500 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 189429000 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1162146500 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 29698000 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27084000 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 56782000 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4004000 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5670000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 9674000 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3477668000 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 3777626000 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7255294000 # number of ReadExReq miss cycles | 183system.l2c.ReadReq_miss_latency::cpu0.inst 300844500 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 409319998 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 262047000 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 190080500 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1162656498 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 28957997 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27214000 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 56171997 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3588000 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6004000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 9592000 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3493801976 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 3769288495 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7263090471 # number of ReadExReq miss cycles |
| 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles | 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles |
| 200system.l2c.demand_miss_latency::cpu0.inst 299700000 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3887018000 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 211000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 263300500 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 3967055000 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8417440500 # number of demand (read+write) miss cycles | 200system.l2c.demand_miss_latency::cpu0.inst 300844500 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3903121974 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 262047000 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 3959368995 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8425746969 # number of demand (read+write) miss cycles |
| 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles | 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles |
| 208system.l2c.overall_miss_latency::cpu0.inst 299700000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3887018000 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 211000 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 263300500 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 3967055000 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8417440500 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 4333 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1877 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 407133 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 212579 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5507 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1891 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 453278 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 146813 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1233411 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 615916 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 615916 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 5842 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 4060 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 9902 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1355 # 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number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1482333 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 4333 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1877 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 407133 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 336120 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5507 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1891 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 453278 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 272194 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1482333 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000231 # 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number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 3959368995 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8425746969 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 4105 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1846 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 407284 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 212730 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5729 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1962 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 453440 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 146962 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1234058 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 616867 # 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number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 1846 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 407284 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 336669 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 5729 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 1962 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 453440 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 272330 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1483365 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 4105 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1846 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 407284 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 336669 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5729 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1962 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 453440 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 272330 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1483365 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001083 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.014174 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.036972 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.011082 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.024809 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.018083 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.799863 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861010 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.825228 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728682 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.825862 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.770310 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.541912 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.577444 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.559780 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.001083 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.014174 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.222857 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.011082 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.279216 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.109126 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.001083 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.014174 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.222857 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.011082 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.279216 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.109126 # miss rate for overall accesses |
| 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency | 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency |
| 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52130.805357 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52027.198780 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52750 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52262.901945 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52169.925640 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52130.556677 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6357.953329 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7569.591951 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 6883.501030 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7086.725664 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12038.216561 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 9337.837838 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.856544 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52114.530881 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52075.350086 # average ReadExReq miss latency | 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52112.333276 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52043.229243 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52148.656716 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52133.982447 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52099.681753 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6203.512639 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7640.089837 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 6825.273026 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6361.702128 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12534.446764 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 9196.548418 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52018.968138 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52067.029892 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52043.899417 # average ReadExReq miss latency |
| 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency | 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency |
| 304system.l2c.demand_avg_miss_latency::cpu0.inst 52130.805357 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52032.260655 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52750 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 52262.901945 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52117.173336 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52082.965177 # average overall miss latency | 304system.l2c.demand_avg_miss_latency::cpu0.inst 52112.333276 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52021.511336 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 52148.656716 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52070.240206 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52051.589635 # average overall miss latency |
| 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency | 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency |
| 312system.l2c.overall_avg_miss_latency::cpu0.inst 52130.805357 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52032.260655 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52750 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 52262.901945 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52117.173336 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52082.965177 # average overall miss latency | 312system.l2c.overall_avg_miss_latency::cpu0.inst 52112.333276 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52021.511336 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 52148.656716 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52070.240206 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52051.589635 # average overall miss latency |
| 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed | 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed |
| 326system.l2c.writebacks::writebacks 63941 # number of writebacks 327system.l2c.writebacks::total 63941 # number of writebacks | 326system.l2c.writebacks::writebacks 64180 # number of writebacks 327system.l2c.writebacks::total 64180 # number of writebacks |
| 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses | 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses |
| 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5748 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 7868 # number of ReadReq MSHR misses | 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5772 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 7865 # number of ReadReq MSHR misses |
| 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses | 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses |
| 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5038 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 3631 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22292 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4671 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 3578 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8249 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 565 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 471 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1036 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 66836 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 72487 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 139323 # number of ReadExReq MSHR misses | 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5025 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 3646 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22315 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4668 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 3562 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8230 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 67164 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 72393 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 139557 # number of ReadExReq MSHR misses |
| 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 352system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses | 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 352system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses |
| 353system.l2c.demand_mshr_misses::cpu0.inst 5748 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 74704 # number of demand (read+write) MSHR misses | 353system.l2c.demand_mshr_misses::cpu0.inst 5772 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 75029 # number of demand (read+write) MSHR misses |
| 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses | 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses |
| 356system.l2c.demand_mshr_misses::cpu1.inst 5038 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 76118 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 161615 # number of demand (read+write) MSHR misses | 356system.l2c.demand_mshr_misses::cpu1.inst 5025 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 76039 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 161872 # number of demand (read+write) MSHR misses |
| 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 360system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses | 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 360system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses |
| 361system.l2c.overall_mshr_misses::cpu0.inst 5748 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 74704 # number of overall MSHR misses | 361system.l2c.overall_mshr_misses::cpu0.inst 5772 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 75029 # number of overall MSHR misses |
| 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses | 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses |
| 364system.l2c.overall_mshr_misses::cpu1.inst 5038 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 76118 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 161615 # number of overall MSHR misses | 364system.l2c.overall_mshr_misses::cpu1.inst 5025 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 76039 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 161872 # number of overall MSHR misses |
| 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles | 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles |
| 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230696000 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314934000 # number of ReadReq MSHR miss cycles 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 163000 # number of ReadReq MSHR miss cycles 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202841000 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145857000 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 894611000 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186977000 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143294000 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 330271000 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22610000 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18883000 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 41493000 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2675636000 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2907782000 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5583418000 # number of ReadExReq MSHR miss cycles | 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 231552000 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314935000 # number of ReadReq MSHR miss cycles 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 201743000 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 146326000 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 894836000 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186889000 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 142710000 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 329599000 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22593000 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19208000 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 41801000 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2687800500 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2900558000 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5588358500 # number of ReadExReq MSHR miss cycles |
| 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles | 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles |
| 386system.l2c.demand_mshr_miss_latency::cpu0.inst 230696000 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 2990570000 # number of demand (read+write) MSHR miss cycles 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 163000 # number of demand (read+write) MSHR miss cycles 389system.l2c.demand_mshr_miss_latency::cpu1.inst 202841000 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3053639000 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6478029000 # number of demand (read+write) MSHR miss cycles | 386system.l2c.demand_mshr_miss_latency::cpu0.inst 231552000 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 3002735500 # number of demand (read+write) MSHR miss cycles 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles 389system.l2c.demand_mshr_miss_latency::cpu1.inst 201743000 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3046884000 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6483194500 # number of demand (read+write) MSHR miss cycles |
| 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles | 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles |
| 394system.l2c.overall_mshr_miss_latency::cpu0.inst 230696000 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 2990570000 # number of overall MSHR miss cycles 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 163000 # number of overall MSHR miss cycles 397system.l2c.overall_mshr_miss_latency::cpu1.inst 202841000 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3053639000 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6478029000 # number of overall MSHR miss cycles | 394system.l2c.overall_mshr_miss_latency::cpu0.inst 231552000 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 3002735500 # number of overall MSHR miss cycles 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles 397system.l2c.overall_mshr_miss_latency::cpu1.inst 201743000 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3046884000 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6483194500 # number of overall MSHR miss cycles |
| 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles | 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles |
| 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9317572500 # number of ReadReq MSHR uncacheable cycles | 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9312662000 # number of ReadReq MSHR uncacheable cycles |
| 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles | 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles |
| 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122235998500 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 131823052000 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699470000 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30625900500 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31325370500 # number of WriteReq MSHR uncacheable cycles | 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122159781000 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 131741924000 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 694882000 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30588601000 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31283483000 # number of WriteReq MSHR uncacheable cycles |
| 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles | 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles |
| 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10017042500 # number of overall MSHR uncacheable cycles | 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10007544000 # number of overall MSHR uncacheable cycles |
| 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles | 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles |
| 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152861899000 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 163148422500 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.037012 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024732 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799555 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.881281 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.833064 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725289 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817708 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764576 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541003 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578134 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.559705 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.109027 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.109027 # mshr miss rate for overall accesses | 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152748382000 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 163025407000 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036972 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024809 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018083 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799863 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861010 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.825228 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728682 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770310 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541912 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577444 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.559780 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.109125 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.109125 # mshr miss rate for overall accesses |
| 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency | 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency |
| 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency | 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770 # average ReadReq mshr miss latency 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680 # average ReadExReq mshr miss latency |
| 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency | 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency |
| 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency | 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency |
| 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses | 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 501system.cpu0.dtb.read_hits 7070010 # DTB read hits 502system.cpu0.dtb.read_misses 3742 # DTB read misses 503system.cpu0.dtb.write_hits 5655317 # DTB write hits 504system.cpu0.dtb.write_misses 808 # DTB write misses | 501system.cpu0.dtb.read_hits 7077919 # DTB read hits 502system.cpu0.dtb.read_misses 3740 # DTB read misses 503system.cpu0.dtb.write_hits 5661726 # DTB write hits 504system.cpu0.dtb.write_misses 804 # DTB write misses |
| 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 509system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 511system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 513system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions | 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 509system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 511system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 513system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions |
| 514system.cpu0.dtb.read_accesses 7073752 # DTB read accesses 515system.cpu0.dtb.write_accesses 5656125 # DTB write accesses | 514system.cpu0.dtb.read_accesses 7081659 # DTB read accesses 515system.cpu0.dtb.write_accesses 5662530 # DTB write accesses |
| 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 517system.cpu0.dtb.hits 12725327 # DTB hits 518system.cpu0.dtb.misses 4550 # DTB misses 519system.cpu0.dtb.accesses 12729877 # DTB accesses 520system.cpu0.itb.inst_hits 29439174 # ITB inst hits | 517system.cpu0.dtb.hits 12739645 # DTB hits 518system.cpu0.dtb.misses 4544 # DTB misses 519system.cpu0.dtb.accesses 12744189 # DTB accesses 520system.cpu0.itb.inst_hits 29451654 # ITB inst hits |
| 521system.cpu0.itb.inst_misses 2205 # ITB inst misses 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 530system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses | 521system.cpu0.itb.inst_misses 2205 # ITB inst misses 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 530system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 537system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses 538system.cpu0.itb.hits 29439174 # DTB hits | 537system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses 538system.cpu0.itb.hits 29451654 # DTB hits |
| 539system.cpu0.itb.misses 2205 # DTB misses | 539system.cpu0.itb.misses 2205 # DTB misses |
| 540system.cpu0.itb.accesses 29441379 # DTB accesses 541system.cpu0.numCycles 2338602594 # number of cpu cycles simulated | 540system.cpu0.itb.accesses 29453859 # DTB accesses 541system.cpu0.numCycles 2343225238 # number of cpu cycles simulated |
| 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 544system.cpu0.committedInsts 28746820 # Number of instructions committed 545system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses | 544system.cpu0.committedInsts 28759206 # Number of instructions committed 545system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses |
| 547system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses | 547system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses |
| 548system.cpu0.num_func_calls 1241704 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 33031249 # number of integer instructions | 548system.cpu0.num_func_calls 1242118 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 33058293 # number of integer instructions |
| 551system.cpu0.num_fp_insts 3860 # number of float instructions | 551system.cpu0.num_fp_insts 3860 # number of float instructions |
| 552system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written | 552system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written |
| 554system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written | 554system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written |
| 556system.cpu0.num_mem_refs 13393278 # number of memory refs 557system.cpu0.num_load_insts 7407523 # Number of load instructions 558system.cpu0.num_store_insts 5985755 # Number of store instructions 559system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles 560system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles | 556system.cpu0.num_mem_refs 13408219 # number of memory refs 557system.cpu0.num_load_insts 7415624 # Number of load instructions 558system.cpu0.num_store_insts 5992595 # Number of store instructions 559system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles 560system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles |
| 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 564system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed 565system.cpu0.icache.replacements 408143 # number of replacements 566system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use 567system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits 579system.cpu0.icache.overall_hits::total 29030502 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses 585system.cpu0.icache.overall_misses::total 408655 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses | 564system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed 565system.cpu0.icache.replacements 408292 # number of replacements 566system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use 567system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits 579system.cpu0.icache.overall_hits::total 29042833 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 408804 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 408804 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 408804 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 408804 # number of overall misses 585system.cpu0.icache.overall_misses::total 408804 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6099412500 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 6099412500 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 6099412500 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 6099412500 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 6099412500 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 6099412500 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 29451637 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses |
| 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses | 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses |
| 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency | 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 14920.138991 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 14920.138991 # average overall miss latency |
| 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed | 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 618system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks 619system.cpu0.icache.writebacks::total 20759 # number of writebacks 620system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses 621system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses 622system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses 623system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses 624system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses 625system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses 626system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # number of ReadReq MSHR miss cycles 627system.cpu0.icache.ReadReq_mshr_miss_latency::total 4737808500 # number of ReadReq MSHR miss cycles 628system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4737808500 # number of demand (read+write) MSHR miss cycles 629system.cpu0.icache.demand_mshr_miss_latency::total 4737808500 # number of demand (read+write) MSHR miss cycles 630system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4737808500 # number of overall MSHR miss cycles 631system.cpu0.icache.overall_mshr_miss_latency::total 4737808500 # number of overall MSHR miss cycles | 618system.cpu0.icache.writebacks::writebacks 20827 # number of writebacks 619system.cpu0.icache.writebacks::total 20827 # number of writebacks 620system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408804 # number of ReadReq MSHR misses 621system.cpu0.icache.ReadReq_mshr_misses::total 408804 # number of ReadReq MSHR misses 622system.cpu0.icache.demand_mshr_misses::cpu0.inst 408804 # number of demand (read+write) MSHR misses 623system.cpu0.icache.demand_mshr_misses::total 408804 # number of demand (read+write) MSHR misses 624system.cpu0.icache.overall_mshr_misses::cpu0.inst 408804 # number of overall MSHR misses 625system.cpu0.icache.overall_mshr_misses::total 408804 # number of overall MSHR misses 626system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4872150503 # number of ReadReq MSHR miss cycles 627system.cpu0.icache.ReadReq_mshr_miss_latency::total 4872150503 # number of ReadReq MSHR miss cycles 628system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4872150503 # number of demand (read+write) MSHR miss cycles 629system.cpu0.icache.demand_mshr_miss_latency::total 4872150503 # number of demand (read+write) MSHR miss cycles 630system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4872150503 # number of overall MSHR miss cycles 631system.cpu0.icache.overall_mshr_miss_latency::total 4872150503 # number of overall MSHR miss cycles |
| 632system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 633system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 634system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 635system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles 636system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses 637system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses 638system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses 639system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses 640system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses 641system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses | 632system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 633system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 634system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 635system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles 636system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses 637system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses 638system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses 639system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses 640system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses 641system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses |
| 642system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency 643system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency 644system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency 645system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency 646system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency 647system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency | 642system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average ReadReq mshr miss latency 643system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762 # average ReadReq mshr miss latency 644system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency 645system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency 646system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency 647system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency |
| 648system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 649system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 650system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 651system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 652system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 648system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 649system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 650system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 651system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 652system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 653system.cpu0.dcache.replacements 330129 # number of replacements 654system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use 655system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. 656system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. 657system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. 658system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. 659system.cpu0.dcache.occ_blocks::cpu0.data 459.697251 # Average occupied blocks per requestor 660system.cpu0.dcache.occ_percent::cpu0.data 0.897846 # Average percentage of cache occupancy 661system.cpu0.dcache.occ_percent::total 0.897846 # Average percentage of cache occupancy 662system.cpu0.dcache.ReadReq_hits::cpu0.data 6600245 # number of ReadReq hits 663system.cpu0.dcache.ReadReq_hits::total 6600245 # number of ReadReq hits 664system.cpu0.dcache.WriteReq_hits::cpu0.data 5350394 # number of WriteReq hits 665system.cpu0.dcache.WriteReq_hits::total 5350394 # number of WriteReq hits 666system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147923 # number of LoadLockedReq hits 667system.cpu0.dcache.LoadLockedReq_hits::total 147923 # number of LoadLockedReq hits 668system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149677 # number of StoreCondReq hits 669system.cpu0.dcache.StoreCondReq_hits::total 149677 # number of StoreCondReq hits 670system.cpu0.dcache.demand_hits::cpu0.data 11950639 # number of demand (read+write) hits 671system.cpu0.dcache.demand_hits::total 11950639 # number of demand (read+write) hits 672system.cpu0.dcache.overall_hits::cpu0.data 11950639 # number of overall hits 673system.cpu0.dcache.overall_hits::total 11950639 # number of overall hits 674system.cpu0.dcache.ReadReq_misses::cpu0.data 227470 # number of ReadReq misses 675system.cpu0.dcache.ReadReq_misses::total 227470 # number of ReadReq misses 676system.cpu0.dcache.WriteReq_misses::cpu0.data 141496 # number of WriteReq misses 677system.cpu0.dcache.WriteReq_misses::total 141496 # number of WriteReq misses 678system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9302 # number of LoadLockedReq misses 679system.cpu0.dcache.LoadLockedReq_misses::total 9302 # number of LoadLockedReq misses 680system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses 681system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses 682system.cpu0.dcache.demand_misses::cpu0.data 368966 # number of demand (read+write) misses 683system.cpu0.dcache.demand_misses::total 368966 # number of demand (read+write) misses 684system.cpu0.dcache.overall_misses::cpu0.data 368966 # number of overall misses 685system.cpu0.dcache.overall_misses::total 368966 # number of overall misses 686system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3341792500 # number of ReadReq miss cycles 687system.cpu0.dcache.ReadReq_miss_latency::total 3341792500 # number of ReadReq miss cycles 688system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4877331500 # number of WriteReq miss cycles 689system.cpu0.dcache.WriteReq_miss_latency::total 4877331500 # number of WriteReq miss cycles 690system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98417500 # number of LoadLockedReq miss cycles 691system.cpu0.dcache.LoadLockedReq_miss_latency::total 98417500 # number of LoadLockedReq miss cycles 692system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles 693system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles 694system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles 695system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles 696system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles 697system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles 698system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) 699system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) 700system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) 701system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) 706system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses 707system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses 708system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses 709system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses 710system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses 711system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses 713system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses 714system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses 715system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses 716system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses 717system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses 718system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses 719system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses 720system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses 721system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses 722system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency 723system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency 724system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency 725system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency 726system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency 727system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency 728system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency 729system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency | 653system.cpu0.dcache.replacements 330880 # number of replacements 654system.cpu0.dcache.tagsinuse 457.764906 # Cycle average of tags in use 655system.cpu0.dcache.total_refs 12284019 # Total number of references to valid blocks. 656system.cpu0.dcache.sampled_refs 331392 # Sample count of references to valid blocks. 657system.cpu0.dcache.avg_refs 37.067941 # Average number of references to valid blocks. 658system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. 659system.cpu0.dcache.occ_blocks::cpu0.data 457.764906 # Average occupied blocks per requestor 660system.cpu0.dcache.occ_percent::cpu0.data 0.894072 # Average percentage of cache occupancy 661system.cpu0.dcache.occ_percent::total 0.894072 # Average percentage of cache occupancy 662system.cpu0.dcache.ReadReq_hits::cpu0.data 6607497 # number of ReadReq hits 663system.cpu0.dcache.ReadReq_hits::total 6607497 # number of ReadReq hits 664system.cpu0.dcache.WriteReq_hits::cpu0.data 5356507 # number of WriteReq hits 665system.cpu0.dcache.WriteReq_hits::total 5356507 # number of WriteReq hits 666system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147994 # number of LoadLockedReq hits 667system.cpu0.dcache.LoadLockedReq_hits::total 147994 # number of LoadLockedReq hits 668system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149732 # number of StoreCondReq hits 669system.cpu0.dcache.StoreCondReq_hits::total 149732 # number of StoreCondReq hits 670system.cpu0.dcache.demand_hits::cpu0.data 11964004 # number of demand (read+write) hits 671system.cpu0.dcache.demand_hits::total 11964004 # number of demand (read+write) hits 672system.cpu0.dcache.overall_hits::cpu0.data 11964004 # number of overall hits 673system.cpu0.dcache.overall_hits::total 11964004 # number of overall hits 674system.cpu0.dcache.ReadReq_misses::cpu0.data 228069 # number of ReadReq misses 675system.cpu0.dcache.ReadReq_misses::total 228069 # number of ReadReq misses 676system.cpu0.dcache.WriteReq_misses::cpu0.data 141727 # number of WriteReq misses 677system.cpu0.dcache.WriteReq_misses::total 141727 # number of WriteReq misses 678system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9289 # number of LoadLockedReq misses 679system.cpu0.dcache.LoadLockedReq_misses::total 9289 # number of LoadLockedReq misses 680system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7498 # number of StoreCondReq misses 681system.cpu0.dcache.StoreCondReq_misses::total 7498 # number of StoreCondReq misses 682system.cpu0.dcache.demand_misses::cpu0.data 369796 # number of demand (read+write) misses 683system.cpu0.dcache.demand_misses::total 369796 # number of demand (read+write) misses 684system.cpu0.dcache.overall_misses::cpu0.data 369796 # number of overall misses 685system.cpu0.dcache.overall_misses::total 369796 # number of overall misses 686system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3436407000 # number of ReadReq miss cycles 687system.cpu0.dcache.ReadReq_miss_latency::total 3436407000 # number of ReadReq miss cycles 688system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917296000 # number of WriteReq miss cycles 689system.cpu0.dcache.WriteReq_miss_latency::total 4917296000 # number of WriteReq miss cycles 690system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100570500 # number of LoadLockedReq miss cycles 691system.cpu0.dcache.LoadLockedReq_miss_latency::total 100570500 # number of LoadLockedReq miss cycles 692system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74480000 # number of StoreCondReq miss cycles 693system.cpu0.dcache.StoreCondReq_miss_latency::total 74480000 # number of StoreCondReq miss cycles 694system.cpu0.dcache.demand_miss_latency::cpu0.data 8353703000 # number of demand (read+write) miss cycles 695system.cpu0.dcache.demand_miss_latency::total 8353703000 # number of demand (read+write) miss cycles 696system.cpu0.dcache.overall_miss_latency::cpu0.data 8353703000 # number of overall miss cycles 697system.cpu0.dcache.overall_miss_latency::total 8353703000 # number of overall miss cycles 698system.cpu0.dcache.ReadReq_accesses::cpu0.data 6835566 # number of ReadReq accesses(hits+misses) 699system.cpu0.dcache.ReadReq_accesses::total 6835566 # number of ReadReq accesses(hits+misses) 700system.cpu0.dcache.WriteReq_accesses::cpu0.data 5498234 # number of WriteReq accesses(hits+misses) 701system.cpu0.dcache.WriteReq_accesses::total 5498234 # number of WriteReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157283 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.LoadLockedReq_accesses::total 157283 # number of LoadLockedReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157230 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.StoreCondReq_accesses::total 157230 # number of StoreCondReq accesses(hits+misses) 706system.cpu0.dcache.demand_accesses::cpu0.data 12333800 # number of demand (read+write) accesses 707system.cpu0.dcache.demand_accesses::total 12333800 # number of demand (read+write) accesses 708system.cpu0.dcache.overall_accesses::cpu0.data 12333800 # number of overall (read+write) accesses 709system.cpu0.dcache.overall_accesses::total 12333800 # number of overall (read+write) accesses 710system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033365 # miss rate for ReadReq accesses 711system.cpu0.dcache.ReadReq_miss_rate::total 0.033365 # miss rate for ReadReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025777 # miss rate for WriteReq accesses 713system.cpu0.dcache.WriteReq_miss_rate::total 0.025777 # miss rate for WriteReq accesses 714system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059059 # miss rate for LoadLockedReq accesses 715system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059059 # miss rate for LoadLockedReq accesses 716system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047688 # miss rate for StoreCondReq accesses 717system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047688 # miss rate for StoreCondReq accesses 718system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029982 # miss rate for demand accesses 719system.cpu0.dcache.demand_miss_rate::total 0.029982 # miss rate for demand accesses 720system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029982 # miss rate for overall accesses 721system.cpu0.dcache.overall_miss_rate::total 0.029982 # miss rate for overall accesses 722system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655 # average ReadReq miss latency 723system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655 # average ReadReq miss latency 724system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484 # average WriteReq miss latency 725system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484 # average WriteReq miss latency 726system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196 # average LoadLockedReq miss latency 727system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196 # average LoadLockedReq miss latency 728system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9933.315551 # average StoreCondReq miss latency 729system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9933.315551 # average StoreCondReq miss latency 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720 # average overall miss latency |
| 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu0.dcache.fast_writes 0 # number of fast writes performed 741system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu0.dcache.fast_writes 0 # number of fast writes performed 741system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 742system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks 743system.cpu0.dcache.writebacks::total 306018 # number of writebacks 744system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses 745system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses 746system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses 747system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses 748system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses 749system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses 750system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses 751system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses 752system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses 753system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses 754system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses 755system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses 756system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles 757system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles 758system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles 759system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles 760system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles 761system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles 762system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles 763system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles 764system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles 768system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles 771system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles 774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses 783system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses 784system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses 785system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency 790system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency 794system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency 795system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency 796system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency 797system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency | 742system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks 743system.cpu0.dcache.writebacks::total 306522 # number of writebacks 744system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses 745system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses 746system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses 747system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses 748system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses 749system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # number of LoadLockedReq MSHR misses 750system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7492 # number of StoreCondReq MSHR misses 751system.cpu0.dcache.StoreCondReq_mshr_misses::total 7492 # number of StoreCondReq MSHR misses 752system.cpu0.dcache.demand_mshr_misses::cpu0.data 369796 # number of demand (read+write) MSHR misses 753system.cpu0.dcache.demand_mshr_misses::total 369796 # number of demand (read+write) MSHR misses 754system.cpu0.dcache.overall_mshr_misses::cpu0.data 369796 # number of overall MSHR misses 755system.cpu0.dcache.overall_mshr_misses::total 369796 # number of overall MSHR misses 756system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2751577168 # number of ReadReq MSHR miss cycles 757system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2751577168 # number of ReadReq MSHR miss cycles 758system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4491927564 # number of WriteReq MSHR miss cycles 759system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4491927564 # number of WriteReq MSHR miss cycles 760system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72683507 # number of LoadLockedReq MSHR miss cycles 761system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72683507 # number of LoadLockedReq MSHR miss cycles 762system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 51983021 # number of StoreCondReq MSHR miss cycles 763system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 51983021 # number of StoreCondReq MSHR miss cycles 764system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7243504732 # number of demand (read+write) MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::total 7243504732 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7243504732 # number of overall MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::total 7243504732 # number of overall MSHR miss cycles 768system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423590500 # number of ReadReq MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423590500 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles 771system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles 774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047650 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047650 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for demand accesses 783system.cpu0.dcache.demand_mshr_miss_rate::total 0.029982 # mshr miss rate for demand accesses 784system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for overall accesses 785system.cpu0.dcache.overall_mshr_miss_rate::total 0.029982 # mshr miss rate for overall accesses 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762 # average ReadReq mshr miss latency 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762 # average ReadReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970 # average WriteReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970 # average WriteReq mshr miss latency 790system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7824.685865 # average LoadLockedReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7824.685865 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6938.470502 # average StoreCondReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6938.470502 # average StoreCondReq mshr miss latency 794system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency 795system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency 796system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency 797system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency |
| 798system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 799system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 800system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 801system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 802system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 803system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 804system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu1.dtb.inst_hits 0 # ITB inst hits 806system.cpu1.dtb.inst_misses 0 # ITB inst misses | 798system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 799system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 800system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 801system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 802system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 803system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 804system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu1.dtb.inst_hits 0 # ITB inst hits 806system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 807system.cpu1.dtb.read_hits 8311514 # DTB read hits 808system.cpu1.dtb.read_misses 3660 # DTB read misses 809system.cpu1.dtb.write_hits 5828200 # DTB write hits 810system.cpu1.dtb.write_misses 1442 # DTB write misses | 807system.cpu1.dtb.read_hits 8311872 # DTB read hits 808system.cpu1.dtb.read_misses 3663 # DTB read misses 809system.cpu1.dtb.write_hits 5828412 # DTB write hits 810system.cpu1.dtb.write_misses 1436 # DTB write misses |
| 811system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 812system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 813system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 814system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 815system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB 816system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 811system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 812system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 813system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 814system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 815system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB 816system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 817system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch | 817system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch |
| 818system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 819system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions | 818system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 819system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions |
| 820system.cpu1.dtb.read_accesses 8315174 # DTB read accesses 821system.cpu1.dtb.write_accesses 5829642 # DTB write accesses | 820system.cpu1.dtb.read_accesses 8315535 # DTB read accesses 821system.cpu1.dtb.write_accesses 5829848 # DTB write accesses |
| 822system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 822system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 823system.cpu1.dtb.hits 14139714 # DTB hits 824system.cpu1.dtb.misses 5102 # DTB misses 825system.cpu1.dtb.accesses 14144816 # DTB accesses 826system.cpu1.itb.inst_hits 32283727 # ITB inst hits | 823system.cpu1.dtb.hits 14140284 # DTB hits 824system.cpu1.dtb.misses 5099 # DTB misses 825system.cpu1.dtb.accesses 14145383 # DTB accesses 826system.cpu1.itb.inst_hits 32285286 # ITB inst hits |
| 827system.cpu1.itb.inst_misses 2171 # ITB inst misses 828system.cpu1.itb.read_hits 0 # DTB read hits 829system.cpu1.itb.read_misses 0 # DTB read misses 830system.cpu1.itb.write_hits 0 # DTB write hits 831system.cpu1.itb.write_misses 0 # DTB write misses 832system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 833system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 834system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 835system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 836system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 837system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 838system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 839system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 840system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 841system.cpu1.itb.read_accesses 0 # DTB read accesses 842system.cpu1.itb.write_accesses 0 # DTB write accesses | 827system.cpu1.itb.inst_misses 2171 # ITB inst misses 828system.cpu1.itb.read_hits 0 # DTB read hits 829system.cpu1.itb.read_misses 0 # DTB read misses 830system.cpu1.itb.write_hits 0 # DTB write hits 831system.cpu1.itb.write_misses 0 # DTB write misses 832system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 833system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 834system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 835system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 836system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 837system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 838system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 839system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 840system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 841system.cpu1.itb.read_accesses 0 # DTB read accesses 842system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 843system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses 844system.cpu1.itb.hits 32283727 # DTB hits | 843system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses 844system.cpu1.itb.hits 32285286 # DTB hits |
| 845system.cpu1.itb.misses 2171 # DTB misses | 845system.cpu1.itb.misses 2171 # DTB misses |
| 846system.cpu1.itb.accesses 32285898 # DTB accesses 847system.cpu1.numCycles 2337184534 # number of cpu cycles simulated | 846system.cpu1.itb.accesses 32287457 # DTB accesses 847system.cpu1.numCycles 2341739150 # number of cpu cycles simulated |
| 848system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 849system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 848system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 849system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 850system.cpu1.committedInsts 31679948 # Number of instructions committed 851system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed 852system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses | 850system.cpu1.committedInsts 31681481 # Number of instructions committed 851system.cpu1.committedOps 40192806 # Number of ops (including micro ops) committed 852system.cpu1.num_int_alu_accesses 36864445 # Number of integer alu accesses |
| 853system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses | 853system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses |
| 854system.cpu1.num_func_calls 962114 # number of times a function call or return occured 855system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls 856system.cpu1.num_int_insts 36862651 # number of integer instructions | 854system.cpu1.num_func_calls 962202 # number of times a function call or return occured 855system.cpu1.num_conditional_control_insts 3487066 # number of instructions that are conditional controls 856system.cpu1.num_int_insts 36864445 # number of integer instructions |
| 857system.cpu1.num_fp_insts 6793 # number of float instructions | 857system.cpu1.num_fp_insts 6793 # number of float instructions |
| 858system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read 859system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written | 858system.cpu1.num_int_register_reads 210742691 # number of times the integer registers were read 859system.cpu1.num_int_register_writes 38544620 # number of times the integer registers were written |
| 860system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 861system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written | 860system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 861system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written |
| 862system.cpu1.num_mem_refs 14677413 # number of memory refs 863system.cpu1.num_load_insts 8633313 # Number of load instructions 864system.cpu1.num_store_insts 6044100 # Number of store instructions 865system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles 866system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles 867system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles 868system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles | 862system.cpu1.num_mem_refs 14678127 # number of memory refs 863system.cpu1.num_load_insts 8633777 # Number of load instructions 864system.cpu1.num_store_insts 6044350 # Number of store instructions 865system.cpu1.num_idle_cycles 1858809543.114650 # Number of idle cycles 866system.cpu1.num_busy_cycles 482929606.885350 # Number of busy cycles 867system.cpu1.not_idle_fraction 0.206227 # Percentage of non-idle cycles 868system.cpu1.idle_fraction 0.793773 # Percentage of idle cycles |
| 869system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 869system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 870system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed 871system.cpu1.icache.replacements 454250 # number of replacements 872system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use 873system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. 874system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. 875system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. 876system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. 877system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor 878system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy 879system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy 880system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits 881system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits 882system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits 883system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits 884system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits 885system.cpu1.icache.overall_hits::total 31828961 # number of overall hits 886system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses 887system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses 888system.cpu1.icache.demand_misses::cpu1.inst 454762 # number of demand (read+write) misses 889system.cpu1.icache.demand_misses::total 454762 # number of demand (read+write) misses 890system.cpu1.icache.overall_misses::cpu1.inst 454762 # number of overall misses 891system.cpu1.icache.overall_misses::total 454762 # number of overall misses 892system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6579254500 # number of ReadReq miss cycles 893system.cpu1.icache.ReadReq_miss_latency::total 6579254500 # number of ReadReq miss cycles 894system.cpu1.icache.demand_miss_latency::cpu1.inst 6579254500 # number of demand (read+write) miss cycles 895system.cpu1.icache.demand_miss_latency::total 6579254500 # number of demand (read+write) miss cycles 896system.cpu1.icache.overall_miss_latency::cpu1.inst 6579254500 # number of overall miss cycles 897system.cpu1.icache.overall_miss_latency::total 6579254500 # number of overall miss cycles 898system.cpu1.icache.ReadReq_accesses::cpu1.inst 32283723 # number of ReadReq accesses(hits+misses) 899system.cpu1.icache.ReadReq_accesses::total 32283723 # number of ReadReq accesses(hits+misses) 900system.cpu1.icache.demand_accesses::cpu1.inst 32283723 # number of demand (read+write) accesses 901system.cpu1.icache.demand_accesses::total 32283723 # number of demand (read+write) accesses 902system.cpu1.icache.overall_accesses::cpu1.inst 32283723 # number of overall (read+write) accesses 903system.cpu1.icache.overall_accesses::total 32283723 # number of overall (read+write) accesses 904system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014086 # miss rate for ReadReq accesses 905system.cpu1.icache.ReadReq_miss_rate::total 0.014086 # miss rate for ReadReq accesses 906system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014086 # miss rate for demand accesses 907system.cpu1.icache.demand_miss_rate::total 0.014086 # miss rate for demand accesses 908system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014086 # miss rate for overall accesses 909system.cpu1.icache.overall_miss_rate::total 0.014086 # miss rate for overall accesses 910system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598 # average ReadReq miss latency 911system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency 912system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency 913system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency 914system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency 915system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency | 870system.cpu1.kern.inst.quiesce 43917 # number of quiesce instructions executed 871system.cpu1.icache.replacements 454429 # number of replacements 872system.cpu1.icache.tagsinuse 478.358537 # Cycle average of tags in use 873system.cpu1.icache.total_refs 31830341 # Total number of references to valid blocks. 874system.cpu1.icache.sampled_refs 454941 # Sample count of references to valid blocks. 875system.cpu1.icache.avg_refs 69.965866 # Average number of references to valid blocks. 876system.cpu1.icache.warmup_cycle 92993102000 # Cycle when the warmup percentage was hit. 877system.cpu1.icache.occ_blocks::cpu1.inst 478.358537 # Average occupied blocks per requestor 878system.cpu1.icache.occ_percent::cpu1.inst 0.934294 # Average percentage of cache occupancy 879system.cpu1.icache.occ_percent::total 0.934294 # Average percentage of cache occupancy 880system.cpu1.icache.ReadReq_hits::cpu1.inst 31830341 # number of ReadReq hits 881system.cpu1.icache.ReadReq_hits::total 31830341 # number of ReadReq hits 882system.cpu1.icache.demand_hits::cpu1.inst 31830341 # number of demand (read+write) hits 883system.cpu1.icache.demand_hits::total 31830341 # number of demand (read+write) hits 884system.cpu1.icache.overall_hits::cpu1.inst 31830341 # number of overall hits 885system.cpu1.icache.overall_hits::total 31830341 # number of overall hits 886system.cpu1.icache.ReadReq_misses::cpu1.inst 454941 # number of ReadReq misses 887system.cpu1.icache.ReadReq_misses::total 454941 # number of ReadReq misses 888system.cpu1.icache.demand_misses::cpu1.inst 454941 # number of demand (read+write) misses 889system.cpu1.icache.demand_misses::total 454941 # number of demand (read+write) misses 890system.cpu1.icache.overall_misses::cpu1.inst 454941 # number of overall misses 891system.cpu1.icache.overall_misses::total 454941 # number of overall misses 892system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6716097000 # number of ReadReq miss cycles 893system.cpu1.icache.ReadReq_miss_latency::total 6716097000 # number of ReadReq miss cycles 894system.cpu1.icache.demand_miss_latency::cpu1.inst 6716097000 # number of demand (read+write) miss cycles 895system.cpu1.icache.demand_miss_latency::total 6716097000 # number of demand (read+write) miss cycles 896system.cpu1.icache.overall_miss_latency::cpu1.inst 6716097000 # number of overall miss cycles 897system.cpu1.icache.overall_miss_latency::total 6716097000 # number of overall miss cycles 898system.cpu1.icache.ReadReq_accesses::cpu1.inst 32285282 # number of ReadReq accesses(hits+misses) 899system.cpu1.icache.ReadReq_accesses::total 32285282 # number of ReadReq accesses(hits+misses) 900system.cpu1.icache.demand_accesses::cpu1.inst 32285282 # number of demand (read+write) accesses 901system.cpu1.icache.demand_accesses::total 32285282 # number of demand (read+write) accesses 902system.cpu1.icache.overall_accesses::cpu1.inst 32285282 # number of overall (read+write) accesses 903system.cpu1.icache.overall_accesses::total 32285282 # number of overall (read+write) accesses 904system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014091 # miss rate for ReadReq accesses 905system.cpu1.icache.ReadReq_miss_rate::total 0.014091 # miss rate for ReadReq accesses 906system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014091 # miss rate for demand accesses 907system.cpu1.icache.demand_miss_rate::total 0.014091 # miss rate for demand accesses 908system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014091 # miss rate for overall accesses 909system.cpu1.icache.overall_miss_rate::total 0.014091 # miss rate for overall accesses 910system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14762.567014 # average ReadReq miss latency 911system.cpu1.icache.ReadReq_avg_miss_latency::total 14762.567014 # average ReadReq miss latency 912system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency 913system.cpu1.icache.demand_avg_miss_latency::total 14762.567014 # average overall miss latency 914system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency 915system.cpu1.icache.overall_avg_miss_latency::total 14762.567014 # average overall miss latency |
| 916system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 917system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 918system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 921system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 922system.cpu1.icache.fast_writes 0 # number of fast writes performed 923system.cpu1.icache.cache_copies 0 # number of cache copies performed | 916system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 917system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 918system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 921system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 922system.cpu1.icache.fast_writes 0 # number of fast writes performed 923system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 924system.cpu1.icache.writebacks::writebacks 23283 # number of writebacks 925system.cpu1.icache.writebacks::total 23283 # number of writebacks 926system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454762 # number of ReadReq MSHR misses 927system.cpu1.icache.ReadReq_mshr_misses::total 454762 # number of ReadReq MSHR misses 928system.cpu1.icache.demand_mshr_misses::cpu1.inst 454762 # number of demand (read+write) MSHR misses 929system.cpu1.icache.demand_mshr_misses::total 454762 # number of demand (read+write) MSHR misses 930system.cpu1.icache.overall_mshr_misses::cpu1.inst 454762 # number of overall MSHR misses 931system.cpu1.icache.overall_mshr_misses::total 454762 # number of overall MSHR misses 932system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5213754000 # number of ReadReq MSHR miss cycles 933system.cpu1.icache.ReadReq_mshr_miss_latency::total 5213754000 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5213754000 # number of demand (read+write) MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::total 5213754000 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5213754000 # number of overall MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::total 5213754000 # number of overall MSHR miss cycles | 924system.cpu1.icache.writebacks::writebacks 23436 # number of writebacks 925system.cpu1.icache.writebacks::total 23436 # number of writebacks 926system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454941 # number of ReadReq MSHR misses 927system.cpu1.icache.ReadReq_mshr_misses::total 454941 # number of ReadReq MSHR misses 928system.cpu1.icache.demand_mshr_misses::cpu1.inst 454941 # number of demand (read+write) MSHR misses 929system.cpu1.icache.demand_mshr_misses::total 454941 # number of demand (read+write) MSHR misses 930system.cpu1.icache.overall_mshr_misses::cpu1.inst 454941 # number of overall MSHR misses 931system.cpu1.icache.overall_mshr_misses::total 454941 # number of overall MSHR misses 932system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5350372502 # number of ReadReq MSHR miss cycles 933system.cpu1.icache.ReadReq_mshr_miss_latency::total 5350372502 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5350372502 # number of demand (read+write) MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::total 5350372502 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5350372502 # number of overall MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::total 5350372502 # number of overall MSHR miss cycles |
| 938system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 939system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 940system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 941system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles | 938system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 939system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 940system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 941system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles |
| 942system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for ReadReq accesses 943system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014086 # mshr miss rate for ReadReq accesses 944system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for demand accesses 945system.cpu1.icache.demand_mshr_miss_rate::total 0.014086 # mshr miss rate for demand accesses 946system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for overall accesses 947system.cpu1.icache.overall_mshr_miss_rate::total 0.014086 # mshr miss rate for overall accesses 948system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average ReadReq mshr miss latency 949system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11464.796971 # average ReadReq mshr miss latency 950system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency 951system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency 952system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency 953system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency | 942system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for ReadReq accesses 943system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014091 # mshr miss rate for ReadReq accesses 944system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for demand accesses 945system.cpu1.icache.demand_mshr_miss_rate::total 0.014091 # mshr miss rate for demand accesses 946system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for overall accesses 947system.cpu1.icache.overall_mshr_miss_rate::total 0.014091 # mshr miss rate for overall accesses 948system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average ReadReq mshr miss latency 949system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443 # average ReadReq mshr miss latency 950system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency 951system.cpu1.icache.demand_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency 952system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency 953system.cpu1.icache.overall_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency |
| 954system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 955system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 956system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 957system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 958system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 954system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 955system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 956system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 957system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 958system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 959system.cpu1.dcache.replacements 292077 # number of replacements 960system.cpu1.dcache.tagsinuse 472.260521 # Cycle average of tags in use 961system.cpu1.dcache.total_refs 11962886 # Total number of references to valid blocks. 962system.cpu1.dcache.sampled_refs 292453 # Sample count of references to valid blocks. 963system.cpu1.dcache.avg_refs 40.905328 # Average number of references to valid blocks. 964system.cpu1.dcache.warmup_cycle 83467733000 # Cycle when the warmup percentage was hit. 965system.cpu1.dcache.occ_blocks::cpu1.data 472.260521 # Average occupied blocks per requestor 966system.cpu1.dcache.occ_percent::cpu1.data 0.922384 # Average percentage of cache occupancy 967system.cpu1.dcache.occ_percent::total 0.922384 # Average percentage of cache occupancy 968system.cpu1.dcache.ReadReq_hits::cpu1.data 6946947 # number of ReadReq hits 969system.cpu1.dcache.ReadReq_hits::total 6946947 # number of ReadReq hits 970system.cpu1.dcache.WriteReq_hits::cpu1.data 4827784 # number of WriteReq hits 971system.cpu1.dcache.WriteReq_hits::total 4827784 # number of WriteReq hits 972system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81815 # number of LoadLockedReq hits 973system.cpu1.dcache.LoadLockedReq_hits::total 81815 # number of LoadLockedReq hits 974system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82770 # number of StoreCondReq hits 975system.cpu1.dcache.StoreCondReq_hits::total 82770 # number of StoreCondReq hits 976system.cpu1.dcache.demand_hits::cpu1.data 11774731 # number of demand (read+write) hits 977system.cpu1.dcache.demand_hits::total 11774731 # number of demand (read+write) hits 978system.cpu1.dcache.overall_hits::cpu1.data 11774731 # number of overall hits 979system.cpu1.dcache.overall_hits::total 11774731 # number of overall hits 980system.cpu1.dcache.ReadReq_misses::cpu1.data 170577 # number of ReadReq misses 981system.cpu1.dcache.ReadReq_misses::total 170577 # number of ReadReq misses 982system.cpu1.dcache.WriteReq_misses::cpu1.data 150060 # number of WriteReq misses 983system.cpu1.dcache.WriteReq_misses::total 150060 # number of WriteReq misses 984system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11061 # number of LoadLockedReq misses 985system.cpu1.dcache.LoadLockedReq_misses::total 11061 # number of LoadLockedReq misses 986system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10037 # number of StoreCondReq misses 987system.cpu1.dcache.StoreCondReq_misses::total 10037 # number of StoreCondReq misses 988system.cpu1.dcache.demand_misses::cpu1.data 320637 # number of demand (read+write) misses 989system.cpu1.dcache.demand_misses::total 320637 # number of demand (read+write) misses 990system.cpu1.dcache.overall_misses::cpu1.data 320637 # number of overall misses 991system.cpu1.dcache.overall_misses::total 320637 # number of overall misses 992system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2293338000 # number of ReadReq miss cycles 993system.cpu1.dcache.ReadReq_miss_latency::total 2293338000 # number of ReadReq miss cycles 994system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5119779000 # number of WriteReq miss cycles 995system.cpu1.dcache.WriteReq_miss_latency::total 5119779000 # number of WriteReq miss cycles 996system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102150000 # number of LoadLockedReq miss cycles 997system.cpu1.dcache.LoadLockedReq_miss_latency::total 102150000 # number of LoadLockedReq miss cycles 998system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 75382000 # number of StoreCondReq miss cycles 999system.cpu1.dcache.StoreCondReq_miss_latency::total 75382000 # number of StoreCondReq miss cycles 1000system.cpu1.dcache.demand_miss_latency::cpu1.data 7413117000 # number of demand (read+write) miss cycles 1001system.cpu1.dcache.demand_miss_latency::total 7413117000 # number of demand (read+write) miss cycles 1002system.cpu1.dcache.overall_miss_latency::cpu1.data 7413117000 # number of overall miss cycles 1003system.cpu1.dcache.overall_miss_latency::total 7413117000 # number of overall miss cycles 1004system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117524 # number of ReadReq accesses(hits+misses) 1005system.cpu1.dcache.ReadReq_accesses::total 7117524 # number of ReadReq accesses(hits+misses) 1006system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977844 # number of WriteReq accesses(hits+misses) 1007system.cpu1.dcache.WriteReq_accesses::total 4977844 # number of WriteReq accesses(hits+misses) 1008system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92876 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu1.dcache.LoadLockedReq_accesses::total 92876 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92807 # number of StoreCondReq accesses(hits+misses) 1011system.cpu1.dcache.StoreCondReq_accesses::total 92807 # number of StoreCondReq accesses(hits+misses) 1012system.cpu1.dcache.demand_accesses::cpu1.data 12095368 # number of demand (read+write) accesses 1013system.cpu1.dcache.demand_accesses::total 12095368 # number of demand (read+write) accesses 1014system.cpu1.dcache.overall_accesses::cpu1.data 12095368 # number of overall (read+write) accesses 1015system.cpu1.dcache.overall_accesses::total 12095368 # number of overall (read+write) accesses 1016system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023966 # miss rate for ReadReq accesses 1017system.cpu1.dcache.ReadReq_miss_rate::total 0.023966 # miss rate for ReadReq accesses 1018system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030146 # miss rate for WriteReq accesses 1019system.cpu1.dcache.WriteReq_miss_rate::total 0.030146 # miss rate for WriteReq accesses 1020system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119094 # miss rate for LoadLockedReq accesses 1021system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119094 # miss rate for LoadLockedReq accesses 1022system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108149 # miss rate for StoreCondReq accesses 1023system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108149 # miss rate for StoreCondReq accesses 1024system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026509 # miss rate for demand accesses 1025system.cpu1.dcache.demand_miss_rate::total 0.026509 # miss rate for demand accesses 1026system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026509 # miss rate for overall accesses 1027system.cpu1.dcache.overall_miss_rate::total 0.026509 # miss rate for overall accesses 1028system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006 # average ReadReq miss latency 1029system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006 # average ReadReq miss latency 1030system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715 # average WriteReq miss latency 1031system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715 # average WriteReq miss latency 1032system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9235.150529 # average LoadLockedReq miss latency 1033system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9235.150529 # average LoadLockedReq miss latency 1034system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7510.411478 # average StoreCondReq miss latency 1035system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7510.411478 # average StoreCondReq miss latency 1036system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency 1037system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440 # average overall miss latency 1038system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency 1039system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440 # average overall miss latency | 959system.cpu1.dcache.replacements 292285 # number of replacements 960system.cpu1.dcache.tagsinuse 472.233445 # Cycle average of tags in use 961system.cpu1.dcache.total_refs 11962904 # Total number of references to valid blocks. 962system.cpu1.dcache.sampled_refs 292625 # Sample count of references to valid blocks. 963system.cpu1.dcache.avg_refs 40.881346 # Average number of references to valid blocks. 964system.cpu1.dcache.warmup_cycle 84136899000 # Cycle when the warmup percentage was hit. 965system.cpu1.dcache.occ_blocks::cpu1.data 472.233445 # Average occupied blocks per requestor 966system.cpu1.dcache.occ_percent::cpu1.data 0.922331 # Average percentage of cache occupancy 967system.cpu1.dcache.occ_percent::total 0.922331 # Average percentage of cache occupancy 968system.cpu1.dcache.ReadReq_hits::cpu1.data 6947233 # number of ReadReq hits 969system.cpu1.dcache.ReadReq_hits::total 6947233 # number of ReadReq hits 970system.cpu1.dcache.WriteReq_hits::cpu1.data 4827936 # number of WriteReq hits 971system.cpu1.dcache.WriteReq_hits::total 4827936 # number of WriteReq hits 972system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81814 # number of LoadLockedReq hits 973system.cpu1.dcache.LoadLockedReq_hits::total 81814 # number of LoadLockedReq hits 974system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82788 # number of StoreCondReq hits 975system.cpu1.dcache.StoreCondReq_hits::total 82788 # number of StoreCondReq hits 976system.cpu1.dcache.demand_hits::cpu1.data 11775169 # number of demand (read+write) hits 977system.cpu1.dcache.demand_hits::total 11775169 # number of demand (read+write) hits 978system.cpu1.dcache.overall_hits::cpu1.data 11775169 # number of overall hits 979system.cpu1.dcache.overall_hits::total 11775169 # number of overall hits 980system.cpu1.dcache.ReadReq_misses::cpu1.data 170612 # number of ReadReq misses 981system.cpu1.dcache.ReadReq_misses::total 170612 # number of ReadReq misses 982system.cpu1.dcache.WriteReq_misses::cpu1.data 150091 # number of WriteReq misses 983system.cpu1.dcache.WriteReq_misses::total 150091 # number of WriteReq misses 984system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11098 # number of LoadLockedReq misses 985system.cpu1.dcache.LoadLockedReq_misses::total 11098 # number of LoadLockedReq misses 986system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10047 # number of StoreCondReq misses 987system.cpu1.dcache.StoreCondReq_misses::total 10047 # number of StoreCondReq misses 988system.cpu1.dcache.demand_misses::cpu1.data 320703 # number of demand (read+write) misses 989system.cpu1.dcache.demand_misses::total 320703 # number of demand (read+write) misses 990system.cpu1.dcache.overall_misses::cpu1.data 320703 # number of overall misses 991system.cpu1.dcache.overall_misses::total 320703 # number of overall misses 992system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2368289000 # number of ReadReq miss cycles 993system.cpu1.dcache.ReadReq_miss_latency::total 2368289000 # number of ReadReq miss cycles 994system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5141096000 # number of WriteReq miss cycles 995system.cpu1.dcache.WriteReq_miss_latency::total 5141096000 # number of WriteReq miss cycles 996system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106270500 # number of LoadLockedReq miss cycles 997system.cpu1.dcache.LoadLockedReq_miss_latency::total 106270500 # number of LoadLockedReq miss cycles 998system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87322000 # number of StoreCondReq miss cycles 999system.cpu1.dcache.StoreCondReq_miss_latency::total 87322000 # number of StoreCondReq miss cycles 1000system.cpu1.dcache.demand_miss_latency::cpu1.data 7509385000 # number of demand (read+write) miss cycles 1001system.cpu1.dcache.demand_miss_latency::total 7509385000 # number of demand (read+write) miss cycles 1002system.cpu1.dcache.overall_miss_latency::cpu1.data 7509385000 # number of overall miss cycles 1003system.cpu1.dcache.overall_miss_latency::total 7509385000 # number of overall miss cycles 1004system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117845 # number of ReadReq accesses(hits+misses) 1005system.cpu1.dcache.ReadReq_accesses::total 7117845 # number of ReadReq accesses(hits+misses) 1006system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978027 # number of WriteReq accesses(hits+misses) 1007system.cpu1.dcache.WriteReq_accesses::total 4978027 # number of WriteReq accesses(hits+misses) 1008system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92912 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu1.dcache.LoadLockedReq_accesses::total 92912 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92835 # number of StoreCondReq accesses(hits+misses) 1011system.cpu1.dcache.StoreCondReq_accesses::total 92835 # number of StoreCondReq accesses(hits+misses) 1012system.cpu1.dcache.demand_accesses::cpu1.data 12095872 # number of demand (read+write) accesses 1013system.cpu1.dcache.demand_accesses::total 12095872 # number of demand (read+write) accesses 1014system.cpu1.dcache.overall_accesses::cpu1.data 12095872 # number of overall (read+write) accesses 1015system.cpu1.dcache.overall_accesses::total 12095872 # number of overall (read+write) accesses 1016system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023970 # miss rate for ReadReq accesses 1017system.cpu1.dcache.ReadReq_miss_rate::total 0.023970 # miss rate for ReadReq accesses 1018system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030151 # miss rate for WriteReq accesses 1019system.cpu1.dcache.WriteReq_miss_rate::total 0.030151 # miss rate for WriteReq accesses 1020system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119446 # miss rate for LoadLockedReq accesses 1021system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119446 # miss rate for LoadLockedReq accesses 1022system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108224 # miss rate for StoreCondReq accesses 1023system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108224 # miss rate for StoreCondReq accesses 1024system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses 1025system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses 1026system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses 1027system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses 1028system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13881.139662 # average ReadReq miss latency 1029system.cpu1.dcache.ReadReq_avg_miss_latency::total 13881.139662 # average ReadReq miss latency 1030system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34253.193063 # average WriteReq miss latency 1031system.cpu1.dcache.WriteReq_avg_miss_latency::total 34253.193063 # average WriteReq miss latency 1032system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9575.644260 # average LoadLockedReq miss latency 1033system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9575.644260 # average LoadLockedReq miss latency 1034system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8691.350652 # average StoreCondReq miss latency 1035system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8691.350652 # average StoreCondReq miss latency 1036system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency 1037system.cpu1.dcache.demand_avg_miss_latency::total 23415.387446 # average overall miss latency 1038system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency 1039system.cpu1.dcache.overall_avg_miss_latency::total 23415.387446 # average overall miss latency |
| 1040system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1040system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1048system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks 1049system.cpu1.dcache.writebacks::total 265856 # number of writebacks 1050system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses 1051system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses 1052system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses 1053system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses 1054system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses 1055system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses 1056system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses 1057system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses 1058system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses 1059system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses 1060system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses 1061system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses 1062system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles 1063system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles 1064system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles 1065system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles 1066system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles 1067system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles 1068system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles 1069system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles 1070system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1071system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles 1073system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles 1074system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles 1075system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles 1076system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles 1077system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles 1078system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles 1079system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles 1080system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles 1081system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles 1082system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses 1083system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses 1084system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses 1085system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses 1086system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses 1087system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses 1088system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses 1089system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses 1090system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses 1091system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses 1092system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses 1093system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses 1094system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency 1095system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency 1096system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency 1097system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency 1098system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency 1099system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency 1100system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency 1101system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency 1102system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1103system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1104system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency 1105system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency 1106system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency 1107system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency | 1048system.cpu1.dcache.writebacks::writebacks 266082 # number of writebacks 1049system.cpu1.dcache.writebacks::total 266082 # number of writebacks 1050system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170612 # number of ReadReq MSHR misses 1051system.cpu1.dcache.ReadReq_mshr_misses::total 170612 # number of ReadReq MSHR misses 1052system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150091 # number of WriteReq MSHR misses 1053system.cpu1.dcache.WriteReq_mshr_misses::total 150091 # number of WriteReq MSHR misses 1054system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11098 # number of LoadLockedReq MSHR misses 1055system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11098 # number of LoadLockedReq MSHR misses 1056system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10038 # number of StoreCondReq MSHR misses 1057system.cpu1.dcache.StoreCondReq_mshr_misses::total 10038 # number of StoreCondReq MSHR misses 1058system.cpu1.dcache.demand_mshr_misses::cpu1.data 320703 # number of demand (read+write) MSHR misses 1059system.cpu1.dcache.demand_mshr_misses::total 320703 # number of demand (read+write) MSHR misses 1060system.cpu1.dcache.overall_mshr_misses::cpu1.data 320703 # number of overall MSHR misses 1061system.cpu1.dcache.overall_mshr_misses::total 320703 # number of overall MSHR misses 1062system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855824122 # number of ReadReq MSHR miss cycles 1063system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855824122 # number of ReadReq MSHR miss cycles 1064system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4690597670 # number of WriteReq MSHR miss cycles 1065system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4690597670 # number of WriteReq MSHR miss cycles 1066system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72957002 # number of LoadLockedReq MSHR miss cycles 1067system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72957002 # number of LoadLockedReq MSHR miss cycles 1068system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57198010 # number of StoreCondReq MSHR miss cycles 1069system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57198010 # number of StoreCondReq MSHR miss cycles 1070system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6546421792 # number of demand (read+write) MSHR miss cycles 1071system.cpu1.dcache.demand_mshr_miss_latency::total 6546421792 # number of demand (read+write) MSHR miss cycles 1072system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6546421792 # number of overall MSHR miss cycles 1073system.cpu1.dcache.overall_mshr_miss_latency::total 6546421792 # number of overall MSHR miss cycles 1074system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000 # number of ReadReq MSHR uncacheable cycles 1075system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000 # number of ReadReq MSHR uncacheable cycles 1076system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39677118500 # number of WriteReq MSHR uncacheable cycles 1077system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39677118500 # number of WriteReq MSHR uncacheable cycles 1078system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500 # number of overall MSHR uncacheable cycles 1079system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500 # number of overall MSHR uncacheable cycles 1080system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023970 # mshr miss rate for ReadReq accesses 1081system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023970 # mshr miss rate for ReadReq accesses 1082system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030151 # mshr miss rate for WriteReq accesses 1083system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030151 # mshr miss rate for WriteReq accesses 1084system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119446 # mshr miss rate for LoadLockedReq accesses 1085system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119446 # mshr miss rate for LoadLockedReq accesses 1086system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108127 # mshr miss rate for StoreCondReq accesses 1087system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108127 # mshr miss rate for StoreCondReq accesses 1088system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses 1089system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses 1090system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses 1091system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses 1092system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649 # average ReadReq mshr miss latency 1093system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649 # average ReadReq mshr miss latency 1094system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774 # average WriteReq mshr miss latency 1095system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774 # average WriteReq mshr miss latency 1096system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6573.887367 # average LoadLockedReq mshr miss latency 1097system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6573.887367 # average LoadLockedReq mshr miss latency 1098system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5698.148037 # average StoreCondReq mshr miss latency 1099system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5698.148037 # average StoreCondReq mshr miss latency 1100system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency 1101system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency 1102system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency 1103system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency |
| 1108system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1109system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1110system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1111system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1112system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1113system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1114system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1115system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1121system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1125system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.iocache.fast_writes 0 # number of fast writes performed 1128system.iocache.cache_copies 0 # number of cache copies performed | 1104system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1105system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1106system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1107system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1108system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1109system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1110system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1111system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1117system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1118system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1119system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1120system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1121system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1122system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1123system.iocache.fast_writes 0 # number of fast writes performed 1124system.iocache.cache_copies 0 # number of cache copies performed |
| 1129system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles 1130system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles 1131system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles 1132system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles | 1125system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles 1126system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles 1127system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles 1128system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles |
| 1133system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1134system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1135system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1136system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1137system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1138 1139---------- End Simulation Statistics ---------- | 1129system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1130system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1131system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1132system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1133system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1134 1135---------- End Simulation Statistics ---------- |