| stats.txt (9055:38f1926fb599) | stats.txt (9079:9a244ebdc3c9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.169707 # Number of seconds simulated 4sim_ticks 1169707043000 # Number of ticks simulated 5final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.169301 # Number of seconds simulated 4sim_ticks 1169301297000 # Number of ticks simulated 5final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 657704 # Simulator instruction rate (inst/s) 8host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12730829062 # Simulator tick rate (ticks/s) 10host_mem_usage 382856 # Number of bytes of host memory used 11host_seconds 91.88 # Real time elapsed on the host 12sim_insts 60429704 # Number of instructions simulated 13sim_ops 77281862 # Number of ops (including micro ops) simulated | 7host_inst_rate 971844 # Simulator instruction rate (inst/s) 8host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18805861990 # Simulator tick rate (ticks/s) 10host_mem_usage 384788 # Number of bytes of host memory used 11host_seconds 62.18 # Real time elapsed on the host 12sim_insts 60426768 # Number of instructions simulated 13sim_ops 77275723 # Number of ops (including micro ops) simulated |
| 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory | 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory |
| 33system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory 41system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory 42system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory 45system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory | 33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory 40system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory 41system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory 42system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory 44system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory |
| 46system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 47system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 45system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 48system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory | 47system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory |
| 49system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory | 48system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory |
| 50system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory 58system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory 59system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory | 49system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory |
| 60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 61system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 58system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 62system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory 63system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 125934 # number of replacements 92system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use 93system.l2c.total_refs 1500548 # Total number of references to valid blocks. 94system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. 95system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. | 60system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) 87system.l2c.replacements 69045 # number of replacements 88system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use 89system.l2c.total_refs 1684870 # Total number of references to valid blocks. 90system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. 91system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. |
| 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 92system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 97system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy 109system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits 126system.l2c.Writeback_hits::total 577354 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits 131system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits 132system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 5680 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 1949 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 446193 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 190485 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1309210 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 4097 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 1763 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 399350 # number of overall hits 148system.l2c.overall_hits::cpu0.data 259693 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 5680 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 1949 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 446193 # number of overall hits 152system.l2c.overall_hits::cpu1.data 190485 # number of overall hits 153system.l2c.overall_hits::total 1309210 # number of overall hits 154system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses 155system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 156system.l2c.ReadReq_misses::cpu0.inst 7942 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu0.data 11318 # number of ReadReq misses 158system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses 159system.l2c.ReadReq_misses::cpu1.itb.walker 5 # number of ReadReq misses 160system.l2c.ReadReq_misses::cpu1.inst 7342 # number of ReadReq misses 161system.l2c.ReadReq_misses::cpu1.data 8301 # number of ReadReq misses 162system.l2c.ReadReq_misses::total 34940 # number of ReadReq misses 163system.l2c.UpgradeReq_misses::cpu0.data 4674 # number of UpgradeReq misses 164system.l2c.UpgradeReq_misses::cpu1.data 3622 # number of UpgradeReq misses 165system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses 166system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses 167system.l2c.SCUpgradeReq_misses::cpu1.data 452 # number of SCUpgradeReq misses 168system.l2c.SCUpgradeReq_misses::total 1019 # number of SCUpgradeReq misses 169system.l2c.ReadExReq_misses::cpu0.data 71101 # number of ReadExReq misses 170system.l2c.ReadExReq_misses::cpu1.data 76239 # number of ReadExReq misses 171system.l2c.ReadExReq_misses::total 147340 # number of ReadExReq misses 172system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses 173system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 174system.l2c.demand_misses::cpu0.inst 7942 # number of demand (read+write) misses 175system.l2c.demand_misses::cpu0.data 82419 # number of demand (read+write) misses 176system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses 177system.l2c.demand_misses::cpu1.itb.walker 5 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu1.inst 7342 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu1.data 84540 # number of demand (read+write) misses 180system.l2c.demand_misses::total 182280 # number of demand (read+write) misses 181system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses 182system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 183system.l2c.overall_misses::cpu0.inst 7942 # number of overall misses 184system.l2c.overall_misses::cpu0.data 82419 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 5 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 7342 # number of overall misses 188system.l2c.overall_misses::cpu1.data 84540 # number of overall misses 189system.l2c.overall_misses::total 182280 # number of overall misses 190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 520000 # number of ReadReq miss cycles 191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 208500 # number of ReadReq miss cycles 192system.l2c.ReadReq_miss_latency::cpu0.inst 414166000 # number of ReadReq miss cycles 193system.l2c.ReadReq_miss_latency::cpu0.data 589465000 # number of ReadReq miss cycles 194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 940000 # number of ReadReq miss cycles 195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 260000 # number of ReadReq miss cycles 196system.l2c.ReadReq_miss_latency::cpu1.inst 383790500 # number of ReadReq miss cycles 197system.l2c.ReadReq_miss_latency::cpu1.data 432860500 # number of ReadReq miss cycles 198system.l2c.ReadReq_miss_latency::total 1822210500 # number of ReadReq miss cycles 199system.l2c.UpgradeReq_miss_latency::cpu0.data 30607000 # number of UpgradeReq miss cycles 200system.l2c.UpgradeReq_miss_latency::cpu1.data 30466000 # number of UpgradeReq miss cycles 201system.l2c.UpgradeReq_miss_latency::total 61073000 # number of UpgradeReq miss cycles 202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4060000 # number of SCUpgradeReq miss cycles 203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5045000 # number of SCUpgradeReq miss cycles 204system.l2c.SCUpgradeReq_miss_latency::total 9105000 # number of SCUpgradeReq miss cycles 205system.l2c.ReadExReq_miss_latency::cpu0.data 3700498000 # number of ReadExReq miss cycles 206system.l2c.ReadExReq_miss_latency::cpu1.data 3973370000 # number of ReadExReq miss cycles 207system.l2c.ReadExReq_miss_latency::total 7673868000 # number of ReadExReq miss cycles 208system.l2c.demand_miss_latency::cpu0.dtb.walker 520000 # number of demand (read+write) miss cycles 209system.l2c.demand_miss_latency::cpu0.itb.walker 208500 # number of demand (read+write) miss cycles 210system.l2c.demand_miss_latency::cpu0.inst 414166000 # number of demand (read+write) miss cycles 211system.l2c.demand_miss_latency::cpu0.data 4289963000 # number of demand (read+write) miss cycles 212system.l2c.demand_miss_latency::cpu1.dtb.walker 940000 # number of demand (read+write) miss cycles 213system.l2c.demand_miss_latency::cpu1.itb.walker 260000 # number of demand (read+write) miss cycles 214system.l2c.demand_miss_latency::cpu1.inst 383790500 # number of demand (read+write) miss cycles 215system.l2c.demand_miss_latency::cpu1.data 4406230500 # number of demand (read+write) miss cycles 216system.l2c.demand_miss_latency::total 9496078500 # number of demand (read+write) miss cycles 217system.l2c.overall_miss_latency::cpu0.dtb.walker 520000 # number of overall miss cycles 218system.l2c.overall_miss_latency::cpu0.itb.walker 208500 # number of overall miss cycles 219system.l2c.overall_miss_latency::cpu0.inst 414166000 # number of overall miss cycles 220system.l2c.overall_miss_latency::cpu0.data 4289963000 # number of overall miss cycles 221system.l2c.overall_miss_latency::cpu1.dtb.walker 940000 # number of overall miss cycles 222system.l2c.overall_miss_latency::cpu1.itb.walker 260000 # number of overall miss cycles 223system.l2c.overall_miss_latency::cpu1.inst 383790500 # number of overall miss cycles 224system.l2c.overall_miss_latency::cpu1.data 4406230500 # number of overall miss cycles 225system.l2c.overall_miss_latency::total 9496078500 # number of overall miss cycles 226system.l2c.ReadReq_accesses::cpu0.dtb.walker 4107 # number of ReadReq accesses(hits+misses) 227system.l2c.ReadReq_accesses::cpu0.itb.walker 1767 # number of ReadReq accesses(hits+misses) 228system.l2c.ReadReq_accesses::cpu0.inst 407292 # number of ReadReq accesses(hits+misses) 229system.l2c.ReadReq_accesses::cpu0.data 217184 # number of ReadReq accesses(hits+misses) 230system.l2c.ReadReq_accesses::cpu1.dtb.walker 5698 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu1.inst 453535 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu1.data 149081 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::total 1240618 # number of ReadReq accesses(hits+misses) 235system.l2c.Writeback_accesses::writebacks 577354 # number of Writeback accesses(hits+misses) 236system.l2c.Writeback_accesses::total 577354 # number of Writeback accesses(hits+misses) 237system.l2c.UpgradeReq_accesses::cpu0.data 5863 # number of UpgradeReq accesses(hits+misses) 238system.l2c.UpgradeReq_accesses::cpu1.data 4171 # number of UpgradeReq accesses(hits+misses) 239system.l2c.UpgradeReq_accesses::total 10034 # number of UpgradeReq accesses(hits+misses) 240system.l2c.SCUpgradeReq_accesses::cpu0.data 790 # number of SCUpgradeReq accesses(hits+misses) 241system.l2c.SCUpgradeReq_accesses::cpu1.data 645 # number of SCUpgradeReq accesses(hits+misses) 242system.l2c.SCUpgradeReq_accesses::total 1435 # number of SCUpgradeReq accesses(hits+misses) 243system.l2c.ReadExReq_accesses::cpu0.data 124928 # number of ReadExReq accesses(hits+misses) 244system.l2c.ReadExReq_accesses::cpu1.data 125944 # number of ReadExReq accesses(hits+misses) 245system.l2c.ReadExReq_accesses::total 250872 # number of ReadExReq accesses(hits+misses) 246system.l2c.demand_accesses::cpu0.dtb.walker 4107 # number of demand (read+write) accesses 247system.l2c.demand_accesses::cpu0.itb.walker 1767 # number of demand (read+write) accesses 248system.l2c.demand_accesses::cpu0.inst 407292 # number of demand (read+write) accesses 249system.l2c.demand_accesses::cpu0.data 342112 # number of demand (read+write) accesses 250system.l2c.demand_accesses::cpu1.dtb.walker 5698 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu1.inst 453535 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu1.data 275025 # number of demand (read+write) accesses 254system.l2c.demand_accesses::total 1491490 # number of demand (read+write) accesses 255system.l2c.overall_accesses::cpu0.dtb.walker 4107 # number of overall (read+write) accesses 256system.l2c.overall_accesses::cpu0.itb.walker 1767 # number of overall (read+write) accesses 257system.l2c.overall_accesses::cpu0.inst 407292 # number of overall (read+write) accesses 258system.l2c.overall_accesses::cpu0.data 342112 # number of overall (read+write) accesses 259system.l2c.overall_accesses::cpu1.dtb.walker 5698 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu1.inst 453535 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu1.data 275025 # number of overall (read+write) accesses 263system.l2c.overall_accesses::total 1491490 # number of overall (read+write) accesses 264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses 265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses 266system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses 267system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses 268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::total 0.028163 # miss rate for ReadReq accesses 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses 274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses 275system.l2c.UpgradeReq_miss_rate::total 0.826789 # miss rate for UpgradeReq accesses 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses 277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::total 0.710105 # miss rate for SCUpgradeReq accesses 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses 280system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses 281system.l2c.ReadExReq_miss_rate::total 0.587311 # miss rate for ReadExReq accesses 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses 283system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses 284system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.122213 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses 297system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses 298system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses 299system.l2c.overall_miss_rate::total 0.122213 # miss rate for overall accesses | 93system.l2c.occ_blocks::writebacks 39883.931908 # Average occupied blocks per requestor 94system.l2c.occ_blocks::cpu0.dtb.walker 0.000281 # Average occupied blocks per requestor 95system.l2c.occ_blocks::cpu0.itb.walker 0.001232 # Average occupied blocks per requestor 96system.l2c.occ_blocks::cpu0.inst 3733.911815 # Average occupied blocks per requestor 97system.l2c.occ_blocks::cpu0.data 4222.338805 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu1.dtb.walker 2.732261 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu1.inst 2761.000373 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu1.data 2056.498545 # Average occupied blocks per requestor 101system.l2c.occ_percent::writebacks 0.608581 # Average percentage of cache occupancy 102system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 103system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 104system.l2c.occ_percent::cpu0.inst 0.056975 # Average percentage of cache occupancy 105system.l2c.occ_percent::cpu0.data 0.064428 # Average percentage of cache occupancy 106system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu1.inst 0.042130 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu1.data 0.031380 # Average percentage of cache occupancy 109system.l2c.occ_percent::total 0.803534 # Average percentage of cache occupancy 110system.l2c.ReadReq_hits::cpu0.dtb.walker 4332 # number of ReadReq hits 111system.l2c.ReadReq_hits::cpu0.itb.walker 1875 # number of ReadReq hits 112system.l2c.ReadReq_hits::cpu0.inst 401384 # number of ReadReq hits 113system.l2c.ReadReq_hits::cpu0.data 204711 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu1.dtb.walker 5503 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu1.itb.walker 1891 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu1.inst 448240 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.data 143182 # number of ReadReq hits 118system.l2c.ReadReq_hits::total 1211118 # number of ReadReq hits 119system.l2c.Writeback_hits::writebacks 615916 # number of Writeback hits 120system.l2c.Writeback_hits::total 615916 # number of Writeback hits 121system.l2c.UpgradeReq_hits::cpu0.data 1171 # number of UpgradeReq hits 122system.l2c.UpgradeReq_hits::cpu1.data 482 # number of UpgradeReq hits 123system.l2c.UpgradeReq_hits::total 1653 # number of UpgradeReq hits 124system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits 125system.l2c.SCUpgradeReq_hits::cpu1.data 105 # number of SCUpgradeReq hits 126system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits 127system.l2c.ReadExReq_hits::cpu0.data 56705 # number of ReadExReq hits 128system.l2c.ReadExReq_hits::cpu1.data 52894 # number of ReadExReq hits 129system.l2c.ReadExReq_hits::total 109599 # number of ReadExReq hits 130system.l2c.demand_hits::cpu0.dtb.walker 4332 # number of demand (read+write) hits 131system.l2c.demand_hits::cpu0.itb.walker 1875 # number of demand (read+write) hits 132system.l2c.demand_hits::cpu0.inst 401384 # number of demand (read+write) hits 133system.l2c.demand_hits::cpu0.data 261416 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu1.dtb.walker 5503 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu1.itb.walker 1891 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu1.inst 448240 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.data 196076 # number of demand (read+write) hits 138system.l2c.demand_hits::total 1320717 # number of demand (read+write) hits 139system.l2c.overall_hits::cpu0.dtb.walker 4332 # number of overall hits 140system.l2c.overall_hits::cpu0.itb.walker 1875 # number of overall hits 141system.l2c.overall_hits::cpu0.inst 401384 # number of overall hits 142system.l2c.overall_hits::cpu0.data 261416 # number of overall hits 143system.l2c.overall_hits::cpu1.dtb.walker 5503 # number of overall hits 144system.l2c.overall_hits::cpu1.itb.walker 1891 # number of overall hits 145system.l2c.overall_hits::cpu1.inst 448240 # number of overall hits 146system.l2c.overall_hits::cpu1.data 196076 # number of overall hits 147system.l2c.overall_hits::total 1320717 # number of overall hits 148system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 149system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 150system.l2c.ReadReq_misses::cpu0.inst 5749 # number of ReadReq misses 151system.l2c.ReadReq_misses::cpu0.data 7868 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu1.inst 5038 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu1.data 3631 # number of ReadReq misses 155system.l2c.ReadReq_misses::total 22293 # number of ReadReq misses 156system.l2c.UpgradeReq_misses::cpu0.data 4671 # number of UpgradeReq misses 157system.l2c.UpgradeReq_misses::cpu1.data 3578 # number of UpgradeReq misses 158system.l2c.UpgradeReq_misses::total 8249 # number of UpgradeReq misses 159system.l2c.SCUpgradeReq_misses::cpu0.data 565 # number of SCUpgradeReq misses 160system.l2c.SCUpgradeReq_misses::cpu1.data 471 # number of SCUpgradeReq misses 161system.l2c.SCUpgradeReq_misses::total 1036 # number of SCUpgradeReq misses 162system.l2c.ReadExReq_misses::cpu0.data 66836 # number of ReadExReq misses 163system.l2c.ReadExReq_misses::cpu1.data 72487 # number of ReadExReq misses 164system.l2c.ReadExReq_misses::total 139323 # number of ReadExReq misses 165system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 166system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 167system.l2c.demand_misses::cpu0.inst 5749 # number of demand (read+write) misses 168system.l2c.demand_misses::cpu0.data 74704 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu1.inst 5038 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu1.data 76118 # number of demand (read+write) misses 172system.l2c.demand_misses::total 161616 # number of demand (read+write) misses 173system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 174system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 175system.l2c.overall_misses::cpu0.inst 5749 # number of overall misses 176system.l2c.overall_misses::cpu0.data 74704 # number of overall misses 177system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 178system.l2c.overall_misses::cpu1.inst 5038 # number of overall misses 179system.l2c.overall_misses::cpu1.data 76118 # number of overall misses 180system.l2c.overall_misses::total 161616 # number of overall misses 181system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles 182system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles 183system.l2c.ReadReq_miss_latency::cpu0.inst 299700000 # number of ReadReq miss cycles 184system.l2c.ReadReq_miss_latency::cpu0.data 409350000 # number of ReadReq miss cycles 185system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 211000 # number of ReadReq miss cycles 186system.l2c.ReadReq_miss_latency::cpu1.inst 263300500 # number of ReadReq miss cycles 187system.l2c.ReadReq_miss_latency::cpu1.data 189429000 # number of ReadReq miss cycles 188system.l2c.ReadReq_miss_latency::total 1162146500 # number of ReadReq miss cycles 189system.l2c.UpgradeReq_miss_latency::cpu0.data 29698000 # number of UpgradeReq miss cycles 190system.l2c.UpgradeReq_miss_latency::cpu1.data 27084000 # number of UpgradeReq miss cycles 191system.l2c.UpgradeReq_miss_latency::total 56782000 # number of UpgradeReq miss cycles 192system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4004000 # number of SCUpgradeReq miss cycles 193system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5670000 # number of SCUpgradeReq miss cycles 194system.l2c.SCUpgradeReq_miss_latency::total 9674000 # number of SCUpgradeReq miss cycles 195system.l2c.ReadExReq_miss_latency::cpu0.data 3477668000 # number of ReadExReq miss cycles 196system.l2c.ReadExReq_miss_latency::cpu1.data 3777626000 # number of ReadExReq miss cycles 197system.l2c.ReadExReq_miss_latency::total 7255294000 # number of ReadExReq miss cycles 198system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles 199system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles 200system.l2c.demand_miss_latency::cpu0.inst 299700000 # number of demand (read+write) miss cycles 201system.l2c.demand_miss_latency::cpu0.data 3887018000 # number of demand (read+write) miss cycles 202system.l2c.demand_miss_latency::cpu1.dtb.walker 211000 # number of demand (read+write) miss cycles 203system.l2c.demand_miss_latency::cpu1.inst 263300500 # number of demand (read+write) miss cycles 204system.l2c.demand_miss_latency::cpu1.data 3967055000 # number of demand (read+write) miss cycles 205system.l2c.demand_miss_latency::total 8417440500 # number of demand (read+write) miss cycles 206system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles 207system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles 208system.l2c.overall_miss_latency::cpu0.inst 299700000 # number of overall miss cycles 209system.l2c.overall_miss_latency::cpu0.data 3887018000 # number of overall miss cycles 210system.l2c.overall_miss_latency::cpu1.dtb.walker 211000 # number of overall miss cycles 211system.l2c.overall_miss_latency::cpu1.inst 263300500 # number of overall miss cycles 212system.l2c.overall_miss_latency::cpu1.data 3967055000 # number of overall miss cycles 213system.l2c.overall_miss_latency::total 8417440500 # number of overall miss cycles 214system.l2c.ReadReq_accesses::cpu0.dtb.walker 4333 # number of ReadReq accesses(hits+misses) 215system.l2c.ReadReq_accesses::cpu0.itb.walker 1877 # number of ReadReq accesses(hits+misses) 216system.l2c.ReadReq_accesses::cpu0.inst 407133 # number of ReadReq accesses(hits+misses) 217system.l2c.ReadReq_accesses::cpu0.data 212579 # number of ReadReq accesses(hits+misses) 218system.l2c.ReadReq_accesses::cpu1.dtb.walker 5507 # number of ReadReq accesses(hits+misses) 219system.l2c.ReadReq_accesses::cpu1.itb.walker 1891 # number of ReadReq accesses(hits+misses) 220system.l2c.ReadReq_accesses::cpu1.inst 453278 # number of ReadReq accesses(hits+misses) 221system.l2c.ReadReq_accesses::cpu1.data 146813 # number of ReadReq accesses(hits+misses) 222system.l2c.ReadReq_accesses::total 1233411 # number of ReadReq accesses(hits+misses) 223system.l2c.Writeback_accesses::writebacks 615916 # number of Writeback accesses(hits+misses) 224system.l2c.Writeback_accesses::total 615916 # number of Writeback accesses(hits+misses) 225system.l2c.UpgradeReq_accesses::cpu0.data 5842 # number of UpgradeReq accesses(hits+misses) 226system.l2c.UpgradeReq_accesses::cpu1.data 4060 # number of UpgradeReq accesses(hits+misses) 227system.l2c.UpgradeReq_accesses::total 9902 # number of UpgradeReq accesses(hits+misses) 228system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) 229system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) 230system.l2c.SCUpgradeReq_accesses::total 1355 # number of SCUpgradeReq accesses(hits+misses) 231system.l2c.ReadExReq_accesses::cpu0.data 123541 # number of ReadExReq accesses(hits+misses) 232system.l2c.ReadExReq_accesses::cpu1.data 125381 # number of ReadExReq accesses(hits+misses) 233system.l2c.ReadExReq_accesses::total 248922 # number of ReadExReq accesses(hits+misses) 234system.l2c.demand_accesses::cpu0.dtb.walker 4333 # number of demand (read+write) accesses 235system.l2c.demand_accesses::cpu0.itb.walker 1877 # number of demand (read+write) accesses 236system.l2c.demand_accesses::cpu0.inst 407133 # number of demand (read+write) accesses 237system.l2c.demand_accesses::cpu0.data 336120 # number of demand (read+write) accesses 238system.l2c.demand_accesses::cpu1.dtb.walker 5507 # number of demand (read+write) accesses 239system.l2c.demand_accesses::cpu1.itb.walker 1891 # number of demand (read+write) accesses 240system.l2c.demand_accesses::cpu1.inst 453278 # number of demand (read+write) accesses 241system.l2c.demand_accesses::cpu1.data 272194 # number of demand (read+write) accesses 242system.l2c.demand_accesses::total 1482333 # number of demand (read+write) accesses 243system.l2c.overall_accesses::cpu0.dtb.walker 4333 # number of overall (read+write) accesses 244system.l2c.overall_accesses::cpu0.itb.walker 1877 # number of overall (read+write) accesses 245system.l2c.overall_accesses::cpu0.inst 407133 # number of overall (read+write) accesses 246system.l2c.overall_accesses::cpu0.data 336120 # number of overall (read+write) accesses 247system.l2c.overall_accesses::cpu1.dtb.walker 5507 # number of overall (read+write) accesses 248system.l2c.overall_accesses::cpu1.itb.walker 1891 # number of overall (read+write) accesses 249system.l2c.overall_accesses::cpu1.inst 453278 # number of overall (read+write) accesses 250system.l2c.overall_accesses::cpu1.data 272194 # number of overall (read+write) accesses 251system.l2c.overall_accesses::total 1482333 # number of overall (read+write) accesses 252system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000231 # miss rate for ReadReq accesses 253system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses 254system.l2c.ReadReq_miss_rate::cpu0.inst 0.014121 # miss rate for ReadReq accesses 255system.l2c.ReadReq_miss_rate::cpu0.data 0.037012 # miss rate for ReadReq accesses 256system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses 257system.l2c.ReadReq_miss_rate::cpu1.inst 0.011115 # miss rate for ReadReq accesses 258system.l2c.ReadReq_miss_rate::cpu1.data 0.024732 # miss rate for ReadReq accesses 259system.l2c.ReadReq_miss_rate::total 0.018074 # miss rate for ReadReq accesses 260system.l2c.UpgradeReq_miss_rate::cpu0.data 0.799555 # miss rate for UpgradeReq accesses 261system.l2c.UpgradeReq_miss_rate::cpu1.data 0.881281 # miss rate for UpgradeReq accesses 262system.l2c.UpgradeReq_miss_rate::total 0.833064 # miss rate for UpgradeReq accesses 263system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725289 # miss rate for SCUpgradeReq accesses 264system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.817708 # miss rate for SCUpgradeReq accesses 265system.l2c.SCUpgradeReq_miss_rate::total 0.764576 # miss rate for SCUpgradeReq accesses 266system.l2c.ReadExReq_miss_rate::cpu0.data 0.541003 # miss rate for ReadExReq accesses 267system.l2c.ReadExReq_miss_rate::cpu1.data 0.578134 # miss rate for ReadExReq accesses 268system.l2c.ReadExReq_miss_rate::total 0.559705 # miss rate for ReadExReq accesses 269system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000231 # miss rate for demand accesses 270system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses 271system.l2c.demand_miss_rate::cpu0.inst 0.014121 # miss rate for demand accesses 272system.l2c.demand_miss_rate::cpu0.data 0.222254 # miss rate for demand accesses 273system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses 274system.l2c.demand_miss_rate::cpu1.inst 0.011115 # miss rate for demand accesses 275system.l2c.demand_miss_rate::cpu1.data 0.279646 # miss rate for demand accesses 276system.l2c.demand_miss_rate::total 0.109028 # miss rate for demand accesses 277system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000231 # miss rate for overall accesses 278system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses 279system.l2c.overall_miss_rate::cpu0.inst 0.014121 # miss rate for overall accesses 280system.l2c.overall_miss_rate::cpu0.data 0.222254 # miss rate for overall accesses 281system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses 282system.l2c.overall_miss_rate::cpu1.inst 0.011115 # miss rate for overall accesses 283system.l2c.overall_miss_rate::cpu1.data 0.279646 # miss rate for overall accesses 284system.l2c.overall_miss_rate::total 0.109028 # miss rate for overall accesses |
| 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency | 285system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency |
| 301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency 302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency 303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency 304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency 305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency 306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency 307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency 308system.l2c.ReadReq_avg_miss_latency::total 52152.561534 # average ReadReq miss latency 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency 310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency 311system.l2c.UpgradeReq_avg_miss_latency::total 7361.740598 # average UpgradeReq miss latency 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency 313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency 314system.l2c.SCUpgradeReq_avg_miss_latency::total 8935.230618 # average SCUpgradeReq miss latency 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency 316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency 317system.l2c.ReadExReq_avg_miss_latency::total 52082.720239 # average ReadExReq miss latency | 286system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency 287system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52130.805357 # average ReadReq miss latency 288system.l2c.ReadReq_avg_miss_latency::cpu0.data 52027.198780 # average ReadReq miss latency 289system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52750 # average ReadReq miss latency 290system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52262.901945 # average ReadReq miss latency 291system.l2c.ReadReq_avg_miss_latency::cpu1.data 52169.925640 # average ReadReq miss latency 292system.l2c.ReadReq_avg_miss_latency::total 52130.556677 # average ReadReq miss latency 293system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6357.953329 # average UpgradeReq miss latency 294system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7569.591951 # average UpgradeReq miss latency 295system.l2c.UpgradeReq_avg_miss_latency::total 6883.501030 # average UpgradeReq miss latency 296system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7086.725664 # average SCUpgradeReq miss latency 297system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12038.216561 # average SCUpgradeReq miss latency 298system.l2c.SCUpgradeReq_avg_miss_latency::total 9337.837838 # average SCUpgradeReq miss latency 299system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.856544 # average ReadExReq miss latency 300system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52114.530881 # average ReadExReq miss latency 301system.l2c.ReadExReq_avg_miss_latency::total 52075.350086 # average ReadExReq miss latency |
| 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency | 302system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency |
| 319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency 320system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency 321system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency 322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency 323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 324system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency 325system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency 326system.l2c.demand_avg_miss_latency::total 52096.107637 # average overall miss latency | 303system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency 304system.l2c.demand_avg_miss_latency::cpu0.inst 52130.805357 # average overall miss latency 305system.l2c.demand_avg_miss_latency::cpu0.data 52032.260655 # average overall miss latency 306system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52750 # average overall miss latency 307system.l2c.demand_avg_miss_latency::cpu1.inst 52262.901945 # average overall miss latency 308system.l2c.demand_avg_miss_latency::cpu1.data 52117.173336 # average overall miss latency 309system.l2c.demand_avg_miss_latency::total 52082.965177 # average overall miss latency |
| 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency | 310system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency |
| 328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency 329system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency 330system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency 331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency 332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 333system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency 334system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency 335system.l2c.overall_avg_miss_latency::total 52096.107637 # average overall miss latency | 311system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency 312system.l2c.overall_avg_miss_latency::cpu0.inst 52130.805357 # average overall miss latency 313system.l2c.overall_avg_miss_latency::cpu0.data 52032.260655 # average overall miss latency 314system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52750 # average overall miss latency 315system.l2c.overall_avg_miss_latency::cpu1.inst 52262.901945 # average overall miss latency 316system.l2c.overall_avg_miss_latency::cpu1.data 52117.173336 # average overall miss latency 317system.l2c.overall_avg_miss_latency::total 52082.965177 # average overall miss latency |
| 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 339system.l2c.blocked::no_targets 0 # number of cycles access was blocked 340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 342system.l2c.fast_writes 0 # number of fast writes performed 343system.l2c.cache_copies 0 # number of cache copies performed | 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed |
| 344system.l2c.writebacks::writebacks 110181 # number of writebacks 345system.l2c.writebacks::total 110181 # number of writebacks | 326system.l2c.writebacks::writebacks 63941 # number of writebacks 327system.l2c.writebacks::total 63941 # number of writebacks |
| 346system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 347system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 348system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 349system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 350system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 351system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 328system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 329system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 330system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 331system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 332system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 333system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits |
| 352system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses 353system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses 354system.l2c.ReadReq_mshr_misses::cpu0.inst 7941 # number of ReadReq MSHR misses 355system.l2c.ReadReq_mshr_misses::cpu0.data 11318 # number of ReadReq MSHR misses 356system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses 357system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 5 # number of ReadReq MSHR misses 358system.l2c.ReadReq_mshr_misses::cpu1.inst 7342 # number of ReadReq MSHR misses 359system.l2c.ReadReq_mshr_misses::cpu1.data 8301 # number of ReadReq MSHR misses 360system.l2c.ReadReq_mshr_misses::total 34939 # number of ReadReq MSHR misses 361system.l2c.UpgradeReq_mshr_misses::cpu0.data 4674 # number of UpgradeReq MSHR misses 362system.l2c.UpgradeReq_mshr_misses::cpu1.data 3622 # number of UpgradeReq MSHR misses 363system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses 364system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 567 # number of SCUpgradeReq MSHR misses 365system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 452 # number of SCUpgradeReq MSHR misses 366system.l2c.SCUpgradeReq_mshr_misses::total 1019 # number of SCUpgradeReq MSHR misses 367system.l2c.ReadExReq_mshr_misses::cpu0.data 71101 # number of ReadExReq MSHR misses 368system.l2c.ReadExReq_mshr_misses::cpu1.data 76239 # number of ReadExReq MSHR misses 369system.l2c.ReadExReq_mshr_misses::total 147340 # number of ReadExReq MSHR misses 370system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses 371system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses 372system.l2c.demand_mshr_misses::cpu0.inst 7941 # number of demand (read+write) MSHR misses 373system.l2c.demand_mshr_misses::cpu0.data 82419 # number of demand (read+write) MSHR misses 374system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses 375system.l2c.demand_mshr_misses::cpu1.itb.walker 5 # number of demand (read+write) MSHR misses 376system.l2c.demand_mshr_misses::cpu1.inst 7342 # number of demand (read+write) MSHR misses 377system.l2c.demand_mshr_misses::cpu1.data 84540 # number of demand (read+write) MSHR misses 378system.l2c.demand_mshr_misses::total 182279 # number of demand (read+write) MSHR misses 379system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses 380system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses 381system.l2c.overall_mshr_misses::cpu0.inst 7941 # number of overall MSHR misses 382system.l2c.overall_mshr_misses::cpu0.data 82419 # number of overall MSHR misses 383system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses 384system.l2c.overall_mshr_misses::cpu1.itb.walker 5 # number of overall MSHR misses 385system.l2c.overall_mshr_misses::cpu1.inst 7342 # number of overall MSHR misses 386system.l2c.overall_mshr_misses::cpu1.data 84540 # number of overall MSHR misses 387system.l2c.overall_mshr_misses::total 182279 # number of overall MSHR misses 388system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles 389system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadReq MSHR miss cycles 390system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 318844000 # number of ReadReq MSHR miss cycles 391system.l2c.ReadReq_mshr_miss_latency::cpu0.data 453649000 # number of ReadReq MSHR miss cycles 392system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 724000 # number of ReadReq MSHR miss cycles 393system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 200000 # number of ReadReq MSHR miss cycles 394system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 295681000 # number of ReadReq MSHR miss cycles 395system.l2c.ReadReq_mshr_miss_latency::cpu1.data 333248000 # number of ReadReq MSHR miss cycles 396system.l2c.ReadReq_mshr_miss_latency::total 1402906000 # number of ReadReq MSHR miss cycles 397system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187154000 # number of UpgradeReq MSHR miss cycles 398system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 145115000 # number of UpgradeReq MSHR miss cycles 399system.l2c.UpgradeReq_mshr_miss_latency::total 332269000 # number of UpgradeReq MSHR miss cycles 400system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22686000 # number of SCUpgradeReq MSHR miss cycles 401system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18114000 # number of SCUpgradeReq MSHR miss cycles 402system.l2c.SCUpgradeReq_mshr_miss_latency::total 40800000 # number of SCUpgradeReq MSHR miss cycles 403system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2847286000 # number of ReadExReq MSHR miss cycles 404system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3058502000 # number of ReadExReq MSHR miss cycles 405system.l2c.ReadExReq_mshr_miss_latency::total 5905788000 # number of ReadExReq MSHR miss cycles 406system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles 407system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles 408system.l2c.demand_mshr_miss_latency::cpu0.inst 318844000 # number of demand (read+write) MSHR miss cycles 409system.l2c.demand_mshr_miss_latency::cpu0.data 3300935000 # number of demand (read+write) MSHR miss cycles 410system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 724000 # number of demand (read+write) MSHR miss cycles 411system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 200000 # number of demand (read+write) MSHR miss cycles 412system.l2c.demand_mshr_miss_latency::cpu1.inst 295681000 # number of demand (read+write) MSHR miss cycles 413system.l2c.demand_mshr_miss_latency::cpu1.data 3391750000 # number of demand (read+write) MSHR miss cycles 414system.l2c.demand_mshr_miss_latency::total 7308694000 # number of demand (read+write) MSHR miss cycles 415system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles 416system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles 417system.l2c.overall_mshr_miss_latency::cpu0.inst 318844000 # number of overall MSHR miss cycles 418system.l2c.overall_mshr_miss_latency::cpu0.data 3300935000 # number of overall MSHR miss cycles 419system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 724000 # number of overall MSHR miss cycles 420system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 200000 # number of overall MSHR miss cycles 421system.l2c.overall_mshr_miss_latency::cpu1.inst 295681000 # number of overall MSHR miss cycles 422system.l2c.overall_mshr_miss_latency::cpu1.data 3391750000 # number of overall MSHR miss cycles 423system.l2c.overall_mshr_miss_latency::total 7308694000 # number of overall MSHR miss cycles | 334system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 335system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 336system.l2c.ReadReq_mshr_misses::cpu0.inst 5748 # number of ReadReq MSHR misses 337system.l2c.ReadReq_mshr_misses::cpu0.data 7868 # number of ReadReq MSHR misses 338system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses 339system.l2c.ReadReq_mshr_misses::cpu1.inst 5038 # number of ReadReq MSHR misses 340system.l2c.ReadReq_mshr_misses::cpu1.data 3631 # number of ReadReq MSHR misses 341system.l2c.ReadReq_mshr_misses::total 22292 # number of ReadReq MSHR misses 342system.l2c.UpgradeReq_mshr_misses::cpu0.data 4671 # number of UpgradeReq MSHR misses 343system.l2c.UpgradeReq_mshr_misses::cpu1.data 3578 # number of UpgradeReq MSHR misses 344system.l2c.UpgradeReq_mshr_misses::total 8249 # number of UpgradeReq MSHR misses 345system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 565 # number of SCUpgradeReq MSHR misses 346system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 471 # number of SCUpgradeReq MSHR misses 347system.l2c.SCUpgradeReq_mshr_misses::total 1036 # number of SCUpgradeReq MSHR misses 348system.l2c.ReadExReq_mshr_misses::cpu0.data 66836 # number of ReadExReq MSHR misses 349system.l2c.ReadExReq_mshr_misses::cpu1.data 72487 # number of ReadExReq MSHR misses 350system.l2c.ReadExReq_mshr_misses::total 139323 # number of ReadExReq MSHR misses 351system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 352system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 353system.l2c.demand_mshr_misses::cpu0.inst 5748 # number of demand (read+write) MSHR misses 354system.l2c.demand_mshr_misses::cpu0.data 74704 # number of demand (read+write) MSHR misses 355system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses 356system.l2c.demand_mshr_misses::cpu1.inst 5038 # number of demand (read+write) MSHR misses 357system.l2c.demand_mshr_misses::cpu1.data 76118 # number of demand (read+write) MSHR misses 358system.l2c.demand_mshr_misses::total 161615 # number of demand (read+write) MSHR misses 359system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 360system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 361system.l2c.overall_mshr_misses::cpu0.inst 5748 # number of overall MSHR misses 362system.l2c.overall_mshr_misses::cpu0.data 74704 # number of overall MSHR misses 363system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses 364system.l2c.overall_mshr_misses::cpu1.inst 5038 # number of overall MSHR misses 365system.l2c.overall_mshr_misses::cpu1.data 76118 # number of overall MSHR misses 366system.l2c.overall_mshr_misses::total 161615 # number of overall MSHR misses 367system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles 368system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles 369system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230696000 # number of ReadReq MSHR miss cycles 370system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314934000 # number of ReadReq MSHR miss cycles 371system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 163000 # number of ReadReq MSHR miss cycles 372system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202841000 # number of ReadReq MSHR miss cycles 373system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145857000 # number of ReadReq MSHR miss cycles 374system.l2c.ReadReq_mshr_miss_latency::total 894611000 # number of ReadReq MSHR miss cycles 375system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186977000 # number of UpgradeReq MSHR miss cycles 376system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143294000 # number of UpgradeReq MSHR miss cycles 377system.l2c.UpgradeReq_mshr_miss_latency::total 330271000 # number of UpgradeReq MSHR miss cycles 378system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22610000 # number of SCUpgradeReq MSHR miss cycles 379system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18883000 # number of SCUpgradeReq MSHR miss cycles 380system.l2c.SCUpgradeReq_mshr_miss_latency::total 41493000 # number of SCUpgradeReq MSHR miss cycles 381system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2675636000 # number of ReadExReq MSHR miss cycles 382system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2907782000 # number of ReadExReq MSHR miss cycles 383system.l2c.ReadExReq_mshr_miss_latency::total 5583418000 # number of ReadExReq MSHR miss cycles 384system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles 385system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles 386system.l2c.demand_mshr_miss_latency::cpu0.inst 230696000 # number of demand (read+write) MSHR miss cycles 387system.l2c.demand_mshr_miss_latency::cpu0.data 2990570000 # number of demand (read+write) MSHR miss cycles 388system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 163000 # number of demand (read+write) MSHR miss cycles 389system.l2c.demand_mshr_miss_latency::cpu1.inst 202841000 # number of demand (read+write) MSHR miss cycles 390system.l2c.demand_mshr_miss_latency::cpu1.data 3053639000 # number of demand (read+write) MSHR miss cycles 391system.l2c.demand_mshr_miss_latency::total 6478029000 # number of demand (read+write) MSHR miss cycles 392system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles 393system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles 394system.l2c.overall_mshr_miss_latency::cpu0.inst 230696000 # number of overall MSHR miss cycles 395system.l2c.overall_mshr_miss_latency::cpu0.data 2990570000 # number of overall MSHR miss cycles 396system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 163000 # number of overall MSHR miss cycles 397system.l2c.overall_mshr_miss_latency::cpu1.inst 202841000 # number of overall MSHR miss cycles 398system.l2c.overall_mshr_miss_latency::cpu1.data 3053639000 # number of overall MSHR miss cycles 399system.l2c.overall_mshr_miss_latency::total 6478029000 # number of overall MSHR miss cycles |
| 424system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles | 400system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles |
| 425system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9316699500 # number of ReadReq MSHR uncacheable cycles | 401system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9317572500 # number of ReadReq MSHR uncacheable cycles |
| 426system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles | 402system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles |
| 427system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122238098500 # number of ReadReq MSHR uncacheable cycles 428system.l2c.ReadReq_mshr_uncacheable_latency::total 131824279000 # number of ReadReq MSHR uncacheable cycles 429system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699595000 # number of WriteReq MSHR uncacheable cycles 430system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30626242500 # number of WriteReq MSHR uncacheable cycles 431system.l2c.WriteReq_mshr_uncacheable_latency::total 31325837500 # number of WriteReq MSHR uncacheable cycles | 403system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122235998500 # number of ReadReq MSHR uncacheable cycles 404system.l2c.ReadReq_mshr_uncacheable_latency::total 131823052000 # number of ReadReq MSHR uncacheable cycles 405system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699470000 # number of WriteReq MSHR uncacheable cycles 406system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30625900500 # number of WriteReq MSHR uncacheable cycles 407system.l2c.WriteReq_mshr_uncacheable_latency::total 31325370500 # number of WriteReq MSHR uncacheable cycles |
| 432system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles | 408system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles |
| 433system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10016294500 # number of overall MSHR uncacheable cycles | 409system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10017042500 # number of overall MSHR uncacheable cycles |
| 434system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles | 410system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles |
| 435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles 436system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles 437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses 438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses 439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses 440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses 441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses 442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses 443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses 444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses 445system.l2c.ReadReq_mshr_miss_rate::total 0.028163 # mshr miss rate for ReadReq accesses 446system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses 447system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses 448system.l2c.UpgradeReq_mshr_miss_rate::total 0.826789 # mshr miss rate for UpgradeReq accesses 449system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses 450system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses 451system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710105 # mshr miss rate for SCUpgradeReq accesses 452system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses 453system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses 454system.l2c.ReadExReq_mshr_miss_rate::total 0.587311 # mshr miss rate for ReadExReq accesses 455system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses 456system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses 457system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses 458system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses 459system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses 460system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses 461system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::total 0.122213 # mshr miss rate for demand accesses 464system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses 465system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses 471system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses 472system.l2c.overall_mshr_miss_rate::total 0.122213 # mshr miss rate for overall accesses | 411system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152861899000 # number of overall MSHR uncacheable cycles 412system.l2c.overall_mshr_uncacheable_latency::total 163148422500 # number of overall MSHR uncacheable cycles 413system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for ReadReq accesses 414system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses 415system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for ReadReq accesses 416system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.037012 # mshr miss rate for ReadReq accesses 417system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses 418system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for ReadReq accesses 419system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024732 # mshr miss rate for ReadReq accesses 420system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses 421system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799555 # mshr miss rate for UpgradeReq accesses 422system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.881281 # mshr miss rate for UpgradeReq accesses 423system.l2c.UpgradeReq_mshr_miss_rate::total 0.833064 # mshr miss rate for UpgradeReq accesses 424system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725289 # mshr miss rate for SCUpgradeReq accesses 425system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817708 # mshr miss rate for SCUpgradeReq accesses 426system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764576 # mshr miss rate for SCUpgradeReq accesses 427system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541003 # mshr miss rate for ReadExReq accesses 428system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578134 # mshr miss rate for ReadExReq accesses 429system.l2c.ReadExReq_mshr_miss_rate::total 0.559705 # mshr miss rate for ReadExReq accesses 430system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for demand accesses 431system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses 432system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for demand accesses 433system.l2c.demand_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for demand accesses 434system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses 435system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for demand accesses 436system.l2c.demand_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for demand accesses 437system.l2c.demand_mshr_miss_rate::total 0.109027 # mshr miss rate for demand accesses 438system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for overall accesses 439system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses 440system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for overall accesses 441system.l2c.overall_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for overall accesses 442system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses 443system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for overall accesses 444system.l2c.overall_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for overall accesses 445system.l2c.overall_mshr_miss_rate::total 0.109027 # mshr miss rate for overall accesses |
| 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency | 446system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency 447system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency |
| 475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency 476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency 477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency 478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency 479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency 480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency 481system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531 # average ReadReq mshr miss latency 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency 483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668 # average UpgradeReq mshr miss latency 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency 486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171 # average SCUpgradeReq mshr miss latency 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency 489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239 # average ReadExReq mshr miss latency | 448system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency 449system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency 450system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency 451system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency 452system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency 453system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency 454system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency 455system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency 456system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency 457system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency 458system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency 459system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency 460system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency 461system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency 462system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency |
| 491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 463system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 464system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency 494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency 495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency 496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency 498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency 499system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency | 465system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency 466system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency 467system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 468system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency 469system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency |
| 500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency | 471system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency 472system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency |
| 502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency 503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency 504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency 505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency 506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency 507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency 508system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency | 473system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency 474system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency |
| 509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 523system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 524system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 525system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 526system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 527system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 528system.cf0.dma_write_txs 0 # Number of DMA write transactions. 529system.cpu0.dtb.inst_hits 0 # ITB inst hits 530system.cpu0.dtb.inst_misses 0 # ITB inst misses | 479system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 483system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 486system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 6 unchanged lines hidden (view full) --- 493system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 494system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 495system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 496system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 497system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 498system.cf0.dma_write_txs 0 # Number of DMA write transactions. 499system.cpu0.dtb.inst_hits 0 # ITB inst hits 500system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 531system.cpu0.dtb.read_hits 7070142 # DTB read hits 532system.cpu0.dtb.read_misses 3739 # DTB read misses 533system.cpu0.dtb.write_hits 5655287 # DTB write hits 534system.cpu0.dtb.write_misses 802 # DTB write misses | 501system.cpu0.dtb.read_hits 7070010 # DTB read hits 502system.cpu0.dtb.read_misses 3742 # DTB read misses 503system.cpu0.dtb.write_hits 5655317 # DTB write hits 504system.cpu0.dtb.write_misses 808 # DTB write misses |
| 535system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 536system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 537system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 538system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 505system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 506system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 507system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 508system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 539system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB | 509system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB |
| 540system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 510system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 541system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch | 511system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch |
| 542system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 543system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions | 512system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 513system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions |
| 544system.cpu0.dtb.read_accesses 7073881 # DTB read accesses 545system.cpu0.dtb.write_accesses 5656089 # DTB write accesses | 514system.cpu0.dtb.read_accesses 7073752 # DTB read accesses 515system.cpu0.dtb.write_accesses 5656125 # DTB write accesses |
| 546system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 516system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 547system.cpu0.dtb.hits 12725429 # DTB hits 548system.cpu0.dtb.misses 4541 # DTB misses 549system.cpu0.dtb.accesses 12729970 # DTB accesses 550system.cpu0.itb.inst_hits 29439632 # ITB inst hits | 517system.cpu0.dtb.hits 12725327 # DTB hits 518system.cpu0.dtb.misses 4550 # DTB misses 519system.cpu0.dtb.accesses 12729877 # DTB accesses 520system.cpu0.itb.inst_hits 29439174 # ITB inst hits |
| 551system.cpu0.itb.inst_misses 2205 # ITB inst misses 552system.cpu0.itb.read_hits 0 # DTB read hits 553system.cpu0.itb.read_misses 0 # DTB read misses 554system.cpu0.itb.write_hits 0 # DTB write hits 555system.cpu0.itb.write_misses 0 # DTB write misses 556system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 558system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 559system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 560system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 565system.cpu0.itb.read_accesses 0 # DTB read accesses 566system.cpu0.itb.write_accesses 0 # DTB write accesses | 521system.cpu0.itb.inst_misses 2205 # ITB inst misses 522system.cpu0.itb.read_hits 0 # DTB read hits 523system.cpu0.itb.read_misses 0 # DTB read misses 524system.cpu0.itb.write_hits 0 # DTB write hits 525system.cpu0.itb.write_misses 0 # DTB write misses 526system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 527system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 528system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 529system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 530system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 535system.cpu0.itb.read_accesses 0 # DTB read accesses 536system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 567system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses 568system.cpu0.itb.hits 29439632 # DTB hits | 537system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses 538system.cpu0.itb.hits 29439174 # DTB hits |
| 569system.cpu0.itb.misses 2205 # DTB misses | 539system.cpu0.itb.misses 2205 # DTB misses |
| 570system.cpu0.itb.accesses 29441837 # DTB accesses 571system.cpu0.numCycles 2339414086 # number of cpu cycles simulated | 540system.cpu0.itb.accesses 29441379 # DTB accesses 541system.cpu0.numCycles 2338602594 # number of cpu cycles simulated |
| 572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 542system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 543system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 574system.cpu0.committedInsts 28747266 # Number of instructions committed 575system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed 576system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses | 544system.cpu0.committedInsts 28746820 # Number of instructions committed 545system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed 546system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses |
| 577system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses | 547system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses |
| 578system.cpu0.num_func_calls 1116936 # number of times a function call or return occured 579system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls 580system.cpu0.num_int_insts 33031535 # number of integer instructions | 548system.cpu0.num_func_calls 1241704 # number of times a function call or return occured 549system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls 550system.cpu0.num_int_insts 33031249 # number of integer instructions |
| 581system.cpu0.num_fp_insts 3860 # number of float instructions | 551system.cpu0.num_fp_insts 3860 # number of float instructions |
| 582system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read 583system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written | 552system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read 553system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written |
| 584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written | 554system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 555system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written |
| 586system.cpu0.num_mem_refs 13393398 # number of memory refs 587system.cpu0.num_load_insts 7407664 # Number of load instructions 588system.cpu0.num_store_insts 5985734 # Number of store instructions 589system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles 590system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles 591system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles 592system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles | 556system.cpu0.num_mem_refs 13393278 # number of memory refs 557system.cpu0.num_load_insts 7407523 # Number of load instructions 558system.cpu0.num_store_insts 5985755 # Number of store instructions 559system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles 560system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles 561system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles 562system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles |
| 593system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 594system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed 595system.cpu0.icache.replacements 408172 # number of replacements 596system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use 597system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. 598system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. 599system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. 600system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. 601system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor 602system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy 603system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy 604system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits 605system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits 606system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits 607system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits 608system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits 609system.cpu0.icache.overall_hits::total 29030930 # number of overall hits 610system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses 611system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses 612system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses 613system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses 614system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses 615system.cpu0.icache.overall_misses::total 408685 # number of overall misses 616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles 617system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles 618system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles 619system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles 620system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles 621system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles 622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) 623system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) 624system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses 625system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses 626system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses 627system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses 628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses 629system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses 630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses 631system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses 632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses 633system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses 634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency 635system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency 636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency 637system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency 638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency 639system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency | 564system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed 565system.cpu0.icache.replacements 408143 # number of replacements 566system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use 567system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. 568system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. 569system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. 570system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor 572system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy 573system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy 574system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits 579system.cpu0.icache.overall_hits::total 29030502 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses 585system.cpu0.icache.overall_misses::total 408655 # number of overall misses 586system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles 587system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles 588system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles 589system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles 590system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles 591system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles 592system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) 593system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) 594system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses 595system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses 596system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses 597system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses 598system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses 599system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses 600system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses 601system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses 602system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses 603system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses 604system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency 605system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency 606system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency 607system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency 608system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency 609system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency |
| 640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu0.icache.fast_writes 0 # number of fast writes performed 647system.cpu0.icache.cache_copies 0 # number of cache copies performed | 610system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 613system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 614system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.cpu0.icache.fast_writes 0 # number of fast writes performed 617system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 648system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks 649system.cpu0.icache.writebacks::total 16458 # number of writebacks 650system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses 651system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses 652system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses 653system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses 654system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses 655system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses 656system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles 657system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles 658system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles 659system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles 660system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles 661system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles | 618system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks 619system.cpu0.icache.writebacks::total 20759 # number of writebacks 620system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses 621system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses 622system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses 623system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses 624system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses 625system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses 626system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # number of ReadReq MSHR miss cycles 627system.cpu0.icache.ReadReq_mshr_miss_latency::total 4737808500 # number of ReadReq MSHR miss cycles 628system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4737808500 # number of demand (read+write) MSHR miss cycles 629system.cpu0.icache.demand_mshr_miss_latency::total 4737808500 # number of demand (read+write) MSHR miss cycles 630system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4737808500 # number of overall MSHR miss cycles 631system.cpu0.icache.overall_mshr_miss_latency::total 4737808500 # number of overall MSHR miss cycles |
| 662system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 663system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 664system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 665system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles | 632system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles 633system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles 634system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles 635system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles |
| 666system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses 667system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses 668system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses 669system.cpu0.icache.demand_mshr_miss_rate::total 0.013882 # mshr miss rate for demand accesses 670system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses 671system.cpu0.icache.overall_mshr_miss_rate::total 0.013882 # mshr miss rate for overall accesses 672system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency 673system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947 # average ReadReq mshr miss latency 674system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency 675system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency 676system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency 677system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency | 636system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses 637system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses 638system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses 639system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses 640system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses 641system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses 642system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency 643system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency 644system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency 645system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency 646system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency 647system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency |
| 678system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 679system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 680system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 681system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 682system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 648system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 649system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 650system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 651system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 652system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 683system.cpu0.dcache.replacements 335831 # number of replacements 684system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use 685system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. 686system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. 687system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. | 653system.cpu0.dcache.replacements 330129 # number of replacements 654system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use 655system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. 656system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. 657system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. |
| 688system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. | 658system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. |
| 689system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor 690system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy 691system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy 692system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # number of ReadReq hits 693system.cpu0.dcache.ReadReq_hits::total 6596660 # number of ReadReq hits 694system.cpu0.dcache.WriteReq_hits::cpu0.data 5349249 # number of WriteReq hits 695system.cpu0.dcache.WriteReq_hits::total 5349249 # number of WriteReq hits 696system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147717 # number of LoadLockedReq hits 697system.cpu0.dcache.LoadLockedReq_hits::total 147717 # number of LoadLockedReq hits 698system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149695 # number of StoreCondReq hits 699system.cpu0.dcache.StoreCondReq_hits::total 149695 # number of StoreCondReq hits 700system.cpu0.dcache.demand_hits::cpu0.data 11945909 # number of demand (read+write) hits 701system.cpu0.dcache.demand_hits::total 11945909 # number of demand (read+write) hits 702system.cpu0.dcache.overall_hits::cpu0.data 11945909 # number of overall hits 703system.cpu0.dcache.overall_hits::total 11945909 # number of overall hits 704system.cpu0.dcache.ReadReq_misses::cpu0.data 231189 # number of ReadReq misses 705system.cpu0.dcache.ReadReq_misses::total 231189 # number of ReadReq misses 706system.cpu0.dcache.WriteReq_misses::cpu0.data 142616 # number of WriteReq misses 707system.cpu0.dcache.WriteReq_misses::total 142616 # number of WriteReq misses 708system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9505 # number of LoadLockedReq misses 709system.cpu0.dcache.LoadLockedReq_misses::total 9505 # number of LoadLockedReq misses 710system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses 711system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses 712system.cpu0.dcache.demand_misses::cpu0.data 373805 # number of demand (read+write) misses 713system.cpu0.dcache.demand_misses::total 373805 # number of demand (read+write) misses 714system.cpu0.dcache.overall_misses::cpu0.data 373805 # number of overall misses 715system.cpu0.dcache.overall_misses::total 373805 # number of overall misses 716system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3541904000 # number of ReadReq miss cycles 717system.cpu0.dcache.ReadReq_miss_latency::total 3541904000 # number of ReadReq miss cycles 718system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5075999000 # number of WriteReq miss cycles 719system.cpu0.dcache.WriteReq_miss_latency::total 5075999000 # number of WriteReq miss cycles 720system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104931000 # number of LoadLockedReq miss cycles 721system.cpu0.dcache.LoadLockedReq_miss_latency::total 104931000 # number of LoadLockedReq miss cycles 722system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68264000 # number of StoreCondReq miss cycles 723system.cpu0.dcache.StoreCondReq_miss_latency::total 68264000 # number of StoreCondReq miss cycles 724system.cpu0.dcache.demand_miss_latency::cpu0.data 8617903000 # number of demand (read+write) miss cycles 725system.cpu0.dcache.demand_miss_latency::total 8617903000 # number of demand (read+write) miss cycles 726system.cpu0.dcache.overall_miss_latency::cpu0.data 8617903000 # number of overall miss cycles 727system.cpu0.dcache.overall_miss_latency::total 8617903000 # number of overall miss cycles 728system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827849 # number of ReadReq accesses(hits+misses) 729system.cpu0.dcache.ReadReq_accesses::total 6827849 # number of ReadReq accesses(hits+misses) 730system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491865 # number of WriteReq accesses(hits+misses) 731system.cpu0.dcache.WriteReq_accesses::total 5491865 # number of WriteReq accesses(hits+misses) 732system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157222 # number of LoadLockedReq accesses(hits+misses) 733system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses) 734system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses) 735system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses) 736system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses 737system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses 738system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses 739system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses 740system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses 741system.cpu0.dcache.ReadReq_miss_rate::total 0.033860 # miss rate for ReadReq accesses 742system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses 743system.cpu0.dcache.WriteReq_miss_rate::total 0.025969 # miss rate for WriteReq accesses 744system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses 745system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060456 # miss rate for LoadLockedReq accesses 746system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses 747system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047493 # miss rate for StoreCondReq accesses 748system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses 749system.cpu0.dcache.demand_miss_rate::total 0.030342 # miss rate for demand accesses 750system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses 751system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses 752system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency 753system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency 754system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency 755system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency 756system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency 757system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency 758system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency 759system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency 760system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency 761system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency 762system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency 763system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency | 659system.cpu0.dcache.occ_blocks::cpu0.data 459.697251 # Average occupied blocks per requestor 660system.cpu0.dcache.occ_percent::cpu0.data 0.897846 # Average percentage of cache occupancy 661system.cpu0.dcache.occ_percent::total 0.897846 # Average percentage of cache occupancy 662system.cpu0.dcache.ReadReq_hits::cpu0.data 6600245 # number of ReadReq hits 663system.cpu0.dcache.ReadReq_hits::total 6600245 # number of ReadReq hits 664system.cpu0.dcache.WriteReq_hits::cpu0.data 5350394 # number of WriteReq hits 665system.cpu0.dcache.WriteReq_hits::total 5350394 # number of WriteReq hits 666system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147923 # number of LoadLockedReq hits 667system.cpu0.dcache.LoadLockedReq_hits::total 147923 # number of LoadLockedReq hits 668system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149677 # number of StoreCondReq hits 669system.cpu0.dcache.StoreCondReq_hits::total 149677 # number of StoreCondReq hits 670system.cpu0.dcache.demand_hits::cpu0.data 11950639 # number of demand (read+write) hits 671system.cpu0.dcache.demand_hits::total 11950639 # number of demand (read+write) hits 672system.cpu0.dcache.overall_hits::cpu0.data 11950639 # number of overall hits 673system.cpu0.dcache.overall_hits::total 11950639 # number of overall hits 674system.cpu0.dcache.ReadReq_misses::cpu0.data 227470 # number of ReadReq misses 675system.cpu0.dcache.ReadReq_misses::total 227470 # number of ReadReq misses 676system.cpu0.dcache.WriteReq_misses::cpu0.data 141496 # number of WriteReq misses 677system.cpu0.dcache.WriteReq_misses::total 141496 # number of WriteReq misses 678system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9302 # number of LoadLockedReq misses 679system.cpu0.dcache.LoadLockedReq_misses::total 9302 # number of LoadLockedReq misses 680system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses 681system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses 682system.cpu0.dcache.demand_misses::cpu0.data 368966 # number of demand (read+write) misses 683system.cpu0.dcache.demand_misses::total 368966 # number of demand (read+write) misses 684system.cpu0.dcache.overall_misses::cpu0.data 368966 # number of overall misses 685system.cpu0.dcache.overall_misses::total 368966 # number of overall misses 686system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3341792500 # number of ReadReq miss cycles 687system.cpu0.dcache.ReadReq_miss_latency::total 3341792500 # number of ReadReq miss cycles 688system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4877331500 # number of WriteReq miss cycles 689system.cpu0.dcache.WriteReq_miss_latency::total 4877331500 # number of WriteReq miss cycles 690system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98417500 # number of LoadLockedReq miss cycles 691system.cpu0.dcache.LoadLockedReq_miss_latency::total 98417500 # number of LoadLockedReq miss cycles 692system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles 693system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles 694system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles 695system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles 696system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles 697system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles 698system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) 699system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) 700system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) 701system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) 706system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses 707system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses 708system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses 709system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses 710system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses 711system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses 713system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses 714system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses 715system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses 716system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses 717system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses 718system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses 719system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses 720system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses 721system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses 722system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency 723system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency 724system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency 725system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency 726system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency 727system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency 728system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency 729system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency |
| 764system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 767system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 769system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 770system.cpu0.dcache.fast_writes 0 # number of fast writes performed 771system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu0.dcache.fast_writes 0 # number of fast writes performed 741system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 772system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks 773system.cpu0.dcache.writebacks::total 287163 # number of writebacks 774system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses 775system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses 776system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses 777system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses 778system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses 779system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses 780system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses 781system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses 782system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses 783system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses 784system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses 785system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses 786system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles 787system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles 788system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles 789system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles 790system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles 791system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles 792system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles 793system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency 824system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency 825system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency 826system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency 827system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency | 742system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks 743system.cpu0.dcache.writebacks::total 306018 # number of writebacks 744system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses 745system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses 746system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses 747system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses 748system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses 749system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses 750system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses 751system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses 752system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses 753system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses 754system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses 755system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses 756system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles 757system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles 758system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles 759system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles 760system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles 761system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles 762system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles 763system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles 764system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles 768system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles 771system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles 774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses 783system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses 784system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses 785system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency 790system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency 791system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency 792system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency 793system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency 794system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency 795system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency 796system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency 797system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency |
| 828system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 829system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 830system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 831system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 832system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 833system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 834system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 835system.cpu1.dtb.inst_hits 0 # ITB inst hits 836system.cpu1.dtb.inst_misses 0 # ITB inst misses | 798system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 799system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 800system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 801system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 802system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 803system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 804system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu1.dtb.inst_hits 0 # ITB inst hits 806system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 837system.cpu1.dtb.read_hits 8313009 # DTB read hits 838system.cpu1.dtb.read_misses 3663 # DTB read misses 839system.cpu1.dtb.write_hits 5829499 # DTB write hits 840system.cpu1.dtb.write_misses 1439 # DTB write misses | 807system.cpu1.dtb.read_hits 8311514 # DTB read hits 808system.cpu1.dtb.read_misses 3660 # DTB read misses 809system.cpu1.dtb.write_hits 5828200 # DTB write hits 810system.cpu1.dtb.write_misses 1442 # DTB write misses |
| 841system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 842system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 843system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 844system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 845system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB 846system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 811system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 812system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 813system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 814system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 815system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB 816system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 847system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch | 817system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch |
| 848system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 849system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions | 818system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 819system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions |
| 850system.cpu1.dtb.read_accesses 8316672 # DTB read accesses 851system.cpu1.dtb.write_accesses 5830938 # DTB write accesses | 820system.cpu1.dtb.read_accesses 8315174 # DTB read accesses 821system.cpu1.dtb.write_accesses 5829642 # DTB write accesses |
| 852system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 822system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 853system.cpu1.dtb.hits 14142508 # DTB hits | 823system.cpu1.dtb.hits 14139714 # DTB hits |
| 854system.cpu1.dtb.misses 5102 # DTB misses | 824system.cpu1.dtb.misses 5102 # DTB misses |
| 855system.cpu1.dtb.accesses 14147610 # DTB accesses 856system.cpu1.itb.inst_hits 32286240 # ITB inst hits | 825system.cpu1.dtb.accesses 14144816 # DTB accesses 826system.cpu1.itb.inst_hits 32283727 # ITB inst hits |
| 857system.cpu1.itb.inst_misses 2171 # ITB inst misses 858system.cpu1.itb.read_hits 0 # DTB read hits 859system.cpu1.itb.read_misses 0 # DTB read misses 860system.cpu1.itb.write_hits 0 # DTB write hits 861system.cpu1.itb.write_misses 0 # DTB write misses 862system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 863system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 864system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 865system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 866system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 867system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 868system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 869system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 870system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 871system.cpu1.itb.read_accesses 0 # DTB read accesses 872system.cpu1.itb.write_accesses 0 # DTB write accesses | 827system.cpu1.itb.inst_misses 2171 # ITB inst misses 828system.cpu1.itb.read_hits 0 # DTB read hits 829system.cpu1.itb.read_misses 0 # DTB read misses 830system.cpu1.itb.write_hits 0 # DTB write hits 831system.cpu1.itb.write_misses 0 # DTB write misses 832system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 833system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 834system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 835system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 836system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 837system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 838system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 839system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 840system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 841system.cpu1.itb.read_accesses 0 # DTB read accesses 842system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 873system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses 874system.cpu1.itb.hits 32286240 # DTB hits | 843system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses 844system.cpu1.itb.hits 32283727 # DTB hits |
| 875system.cpu1.itb.misses 2171 # DTB misses | 845system.cpu1.itb.misses 2171 # DTB misses |
| 876system.cpu1.itb.accesses 32288411 # DTB accesses 877system.cpu1.numCycles 2338003468 # number of cpu cycles simulated | 846system.cpu1.itb.accesses 32285898 # DTB accesses 847system.cpu1.numCycles 2337184534 # number of cpu cycles simulated |
| 878system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 879system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 848system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 849system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 880system.cpu1.committedInsts 31682438 # Number of instructions committed 881system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed 882system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses | 850system.cpu1.committedInsts 31679948 # Number of instructions committed 851system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed 852system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses |
| 883system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses | 853system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses |
| 884system.cpu1.num_func_calls 909270 # number of times a function call or return occured 885system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls 886system.cpu1.num_int_insts 36868206 # number of integer instructions | 854system.cpu1.num_func_calls 962114 # number of times a function call or return occured 855system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls 856system.cpu1.num_int_insts 36862651 # number of integer instructions |
| 887system.cpu1.num_fp_insts 6793 # number of float instructions | 857system.cpu1.num_fp_insts 6793 # number of float instructions |
| 888system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read 889system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written | 858system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read 859system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written |
| 890system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 891system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written | 860system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 861system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written |
| 892system.cpu1.num_mem_refs 14680299 # number of memory refs 893system.cpu1.num_load_insts 8634860 # Number of load instructions 894system.cpu1.num_store_insts 6045439 # Number of store instructions 895system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles 896system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles 897system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles 898system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles | 862system.cpu1.num_mem_refs 14677413 # number of memory refs 863system.cpu1.num_load_insts 8633313 # Number of load instructions 864system.cpu1.num_store_insts 6044100 # Number of store instructions 865system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles 866system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles 867system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles 868system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles |
| 899system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 869system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 900system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed 901system.cpu1.icache.replacements 454317 # number of replacements 902system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use 903system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. 904system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. 905system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. 906system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. 907system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor 908system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy 909system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy 910system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits 911system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits 912system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits 913system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits 914system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits 915system.cpu1.icache.overall_hits::total 31831407 # number of overall hits 916system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses 917system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses 918system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses 919system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses 920system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses 921system.cpu1.icache.overall_misses::total 454829 # number of overall misses 922system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles 923system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles 924system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles 925system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles 926system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles 927system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles 928system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) 929system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) 930system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses 931system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses 932system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses 933system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses 934system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses 935system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses 936system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses 937system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses 938system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses 939system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses 940system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency 941system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency 942system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency 943system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency 944system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency 945system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency | 870system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed 871system.cpu1.icache.replacements 454250 # number of replacements 872system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use 873system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. 874system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. 875system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. 876system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. 877system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor 878system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy 879system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy 880system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits 881system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits 882system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits 883system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits 884system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits 885system.cpu1.icache.overall_hits::total 31828961 # number of overall hits 886system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses 887system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses 888system.cpu1.icache.demand_misses::cpu1.inst 454762 # number of demand (read+write) misses 889system.cpu1.icache.demand_misses::total 454762 # number of demand (read+write) misses 890system.cpu1.icache.overall_misses::cpu1.inst 454762 # number of overall misses 891system.cpu1.icache.overall_misses::total 454762 # number of overall misses 892system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6579254500 # number of ReadReq miss cycles 893system.cpu1.icache.ReadReq_miss_latency::total 6579254500 # number of ReadReq miss cycles 894system.cpu1.icache.demand_miss_latency::cpu1.inst 6579254500 # number of demand (read+write) miss cycles 895system.cpu1.icache.demand_miss_latency::total 6579254500 # number of demand (read+write) miss cycles 896system.cpu1.icache.overall_miss_latency::cpu1.inst 6579254500 # number of overall miss cycles 897system.cpu1.icache.overall_miss_latency::total 6579254500 # number of overall miss cycles 898system.cpu1.icache.ReadReq_accesses::cpu1.inst 32283723 # number of ReadReq accesses(hits+misses) 899system.cpu1.icache.ReadReq_accesses::total 32283723 # number of ReadReq accesses(hits+misses) 900system.cpu1.icache.demand_accesses::cpu1.inst 32283723 # number of demand (read+write) accesses 901system.cpu1.icache.demand_accesses::total 32283723 # number of demand (read+write) accesses 902system.cpu1.icache.overall_accesses::cpu1.inst 32283723 # number of overall (read+write) accesses 903system.cpu1.icache.overall_accesses::total 32283723 # number of overall (read+write) accesses 904system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014086 # miss rate for ReadReq accesses 905system.cpu1.icache.ReadReq_miss_rate::total 0.014086 # miss rate for ReadReq accesses 906system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014086 # miss rate for demand accesses 907system.cpu1.icache.demand_miss_rate::total 0.014086 # miss rate for demand accesses 908system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014086 # miss rate for overall accesses 909system.cpu1.icache.overall_miss_rate::total 0.014086 # miss rate for overall accesses 910system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598 # average ReadReq miss latency 911system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency 912system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency 913system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency 914system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency 915system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency |
| 946system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 947system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 948system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 949system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 950system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 951system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 952system.cpu1.icache.fast_writes 0 # number of fast writes performed 953system.cpu1.icache.cache_copies 0 # number of cache copies performed | 916system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 917system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 918system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 921system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 922system.cpu1.icache.fast_writes 0 # number of fast writes performed 923system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 954system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks 955system.cpu1.icache.writebacks::total 19149 # number of writebacks 956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses 957system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses 958system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses 959system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses 960system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses 961system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses 962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles 963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles 964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles 965system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles 966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles 967system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles | 924system.cpu1.icache.writebacks::writebacks 23283 # number of writebacks 925system.cpu1.icache.writebacks::total 23283 # number of writebacks 926system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454762 # number of ReadReq MSHR misses 927system.cpu1.icache.ReadReq_mshr_misses::total 454762 # number of ReadReq MSHR misses 928system.cpu1.icache.demand_mshr_misses::cpu1.inst 454762 # number of demand (read+write) MSHR misses 929system.cpu1.icache.demand_mshr_misses::total 454762 # number of demand (read+write) MSHR misses 930system.cpu1.icache.overall_mshr_misses::cpu1.inst 454762 # number of overall MSHR misses 931system.cpu1.icache.overall_mshr_misses::total 454762 # number of overall MSHR misses 932system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5213754000 # number of ReadReq MSHR miss cycles 933system.cpu1.icache.ReadReq_mshr_miss_latency::total 5213754000 # number of ReadReq MSHR miss cycles 934system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5213754000 # number of demand (read+write) MSHR miss cycles 935system.cpu1.icache.demand_mshr_miss_latency::total 5213754000 # number of demand (read+write) MSHR miss cycles 936system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5213754000 # number of overall MSHR miss cycles 937system.cpu1.icache.overall_mshr_miss_latency::total 5213754000 # number of overall MSHR miss cycles |
| 968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles | 938system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles 939system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles 940system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles 941system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles |
| 972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses 973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses 974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses 975system.cpu1.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses 976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses 977system.cpu1.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses 978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency 979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965 # average ReadReq mshr miss latency 980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency 981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency 982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency 983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency | 942system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for ReadReq accesses 943system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014086 # mshr miss rate for ReadReq accesses 944system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for demand accesses 945system.cpu1.icache.demand_mshr_miss_rate::total 0.014086 # mshr miss rate for demand accesses 946system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for overall accesses 947system.cpu1.icache.overall_mshr_miss_rate::total 0.014086 # mshr miss rate for overall accesses 948system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average ReadReq mshr miss latency 949system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11464.796971 # average ReadReq mshr miss latency 950system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency 951system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency 952system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency 953system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency |
| 984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 954system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 955system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 956system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 957system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 958system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 989system.cpu1.dcache.replacements 294642 # number of replacements 990system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use 991system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks. 992system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks. 993system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks. 994system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit. 995system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor 996system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy 997system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy 998system.cpu1.dcache.ReadReq_hits::cpu1.data 6946891 # number of ReadReq hits 999system.cpu1.dcache.ReadReq_hits::total 6946891 # number of ReadReq hits 1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4828705 # number of WriteReq hits 1001system.cpu1.dcache.WriteReq_hits::total 4828705 # number of WriteReq hits 1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81776 # number of LoadLockedReq hits 1003system.cpu1.dcache.LoadLockedReq_hits::total 81776 # number of LoadLockedReq hits 1004system.cpu1.dcache.StoreCondReq_hits::cpu1.data 83111 # number of StoreCondReq hits 1005system.cpu1.dcache.StoreCondReq_hits::total 83111 # number of StoreCondReq hits 1006system.cpu1.dcache.demand_hits::cpu1.data 11775596 # number of demand (read+write) hits 1007system.cpu1.dcache.demand_hits::total 11775596 # number of demand (read+write) hits 1008system.cpu1.dcache.overall_hits::cpu1.data 11775596 # number of overall hits 1009system.cpu1.dcache.overall_hits::total 11775596 # number of overall hits 1010system.cpu1.dcache.ReadReq_misses::cpu1.data 172105 # number of ReadReq misses 1011system.cpu1.dcache.ReadReq_misses::total 172105 # number of ReadReq misses 1012system.cpu1.dcache.WriteReq_misses::cpu1.data 150416 # number of WriteReq misses 1013system.cpu1.dcache.WriteReq_misses::total 150416 # number of WriteReq misses 1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11123 # number of LoadLockedReq misses 1015system.cpu1.dcache.LoadLockedReq_misses::total 11123 # number of LoadLockedReq misses 1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9715 # number of StoreCondReq misses 1017system.cpu1.dcache.StoreCondReq_misses::total 9715 # number of StoreCondReq misses 1018system.cpu1.dcache.demand_misses::cpu1.data 322521 # number of demand (read+write) misses 1019system.cpu1.dcache.demand_misses::total 322521 # number of demand (read+write) misses 1020system.cpu1.dcache.overall_misses::cpu1.data 322521 # number of overall misses 1021system.cpu1.dcache.overall_misses::total 322521 # number of overall misses 1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2496186500 # number of ReadReq miss cycles 1023system.cpu1.dcache.ReadReq_miss_latency::total 2496186500 # number of ReadReq miss cycles 1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5287724000 # number of WriteReq miss cycles 1025system.cpu1.dcache.WriteReq_miss_latency::total 5287724000 # number of WriteReq miss cycles 1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124574500 # number of LoadLockedReq miss cycles 1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 124574500 # number of LoadLockedReq miss cycles 1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 73632000 # number of StoreCondReq miss cycles 1029system.cpu1.dcache.StoreCondReq_miss_latency::total 73632000 # number of StoreCondReq miss cycles 1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7783910500 # number of demand (read+write) miss cycles 1031system.cpu1.dcache.demand_miss_latency::total 7783910500 # number of demand (read+write) miss cycles 1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7783910500 # number of overall miss cycles 1033system.cpu1.dcache.overall_miss_latency::total 7783910500 # number of overall miss cycles 1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118996 # number of ReadReq accesses(hits+misses) 1035system.cpu1.dcache.ReadReq_accesses::total 7118996 # number of ReadReq accesses(hits+misses) 1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979121 # number of WriteReq accesses(hits+misses) 1037system.cpu1.dcache.WriteReq_accesses::total 4979121 # number of WriteReq accesses(hits+misses) 1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92899 # number of LoadLockedReq accesses(hits+misses) 1039system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses) 1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses) 1041system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses) 1042system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses 1043system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses 1044system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses 1045system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses 1046system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses 1047system.cpu1.dcache.ReadReq_miss_rate::total 0.024175 # miss rate for ReadReq accesses 1048system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses 1049system.cpu1.dcache.WriteReq_miss_rate::total 0.030209 # miss rate for WriteReq accesses 1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses 1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119732 # miss rate for LoadLockedReq accesses 1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses 1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104658 # miss rate for StoreCondReq accesses 1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses 1055system.cpu1.dcache.demand_miss_rate::total 0.026659 # miss rate for demand accesses 1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses 1057system.cpu1.dcache.overall_miss_rate::total 0.026659 # miss rate for overall accesses 1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency 1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110 # average ReadReq miss latency 1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency 1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575 # average WriteReq miss latency 1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency 1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298 # average LoadLockedReq miss latency 1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency 1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7579.207411 # average StoreCondReq miss latency 1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency 1067system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035 # average overall miss latency 1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency 1069system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035 # average overall miss latency | 959system.cpu1.dcache.replacements 292077 # number of replacements 960system.cpu1.dcache.tagsinuse 472.260521 # Cycle average of tags in use 961system.cpu1.dcache.total_refs 11962886 # Total number of references to valid blocks. 962system.cpu1.dcache.sampled_refs 292453 # Sample count of references to valid blocks. 963system.cpu1.dcache.avg_refs 40.905328 # Average number of references to valid blocks. 964system.cpu1.dcache.warmup_cycle 83467733000 # Cycle when the warmup percentage was hit. 965system.cpu1.dcache.occ_blocks::cpu1.data 472.260521 # Average occupied blocks per requestor 966system.cpu1.dcache.occ_percent::cpu1.data 0.922384 # Average percentage of cache occupancy 967system.cpu1.dcache.occ_percent::total 0.922384 # Average percentage of cache occupancy 968system.cpu1.dcache.ReadReq_hits::cpu1.data 6946947 # number of ReadReq hits 969system.cpu1.dcache.ReadReq_hits::total 6946947 # number of ReadReq hits 970system.cpu1.dcache.WriteReq_hits::cpu1.data 4827784 # number of WriteReq hits 971system.cpu1.dcache.WriteReq_hits::total 4827784 # number of WriteReq hits 972system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81815 # number of LoadLockedReq hits 973system.cpu1.dcache.LoadLockedReq_hits::total 81815 # number of LoadLockedReq hits 974system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82770 # number of StoreCondReq hits 975system.cpu1.dcache.StoreCondReq_hits::total 82770 # number of StoreCondReq hits 976system.cpu1.dcache.demand_hits::cpu1.data 11774731 # number of demand (read+write) hits 977system.cpu1.dcache.demand_hits::total 11774731 # number of demand (read+write) hits 978system.cpu1.dcache.overall_hits::cpu1.data 11774731 # number of overall hits 979system.cpu1.dcache.overall_hits::total 11774731 # number of overall hits 980system.cpu1.dcache.ReadReq_misses::cpu1.data 170577 # number of ReadReq misses 981system.cpu1.dcache.ReadReq_misses::total 170577 # number of ReadReq misses 982system.cpu1.dcache.WriteReq_misses::cpu1.data 150060 # number of WriteReq misses 983system.cpu1.dcache.WriteReq_misses::total 150060 # number of WriteReq misses 984system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11061 # number of LoadLockedReq misses 985system.cpu1.dcache.LoadLockedReq_misses::total 11061 # number of LoadLockedReq misses 986system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10037 # number of StoreCondReq misses 987system.cpu1.dcache.StoreCondReq_misses::total 10037 # number of StoreCondReq misses 988system.cpu1.dcache.demand_misses::cpu1.data 320637 # number of demand (read+write) misses 989system.cpu1.dcache.demand_misses::total 320637 # number of demand (read+write) misses 990system.cpu1.dcache.overall_misses::cpu1.data 320637 # number of overall misses 991system.cpu1.dcache.overall_misses::total 320637 # number of overall misses 992system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2293338000 # number of ReadReq miss cycles 993system.cpu1.dcache.ReadReq_miss_latency::total 2293338000 # number of ReadReq miss cycles 994system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5119779000 # number of WriteReq miss cycles 995system.cpu1.dcache.WriteReq_miss_latency::total 5119779000 # number of WriteReq miss cycles 996system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102150000 # number of LoadLockedReq miss cycles 997system.cpu1.dcache.LoadLockedReq_miss_latency::total 102150000 # number of LoadLockedReq miss cycles 998system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 75382000 # number of StoreCondReq miss cycles 999system.cpu1.dcache.StoreCondReq_miss_latency::total 75382000 # number of StoreCondReq miss cycles 1000system.cpu1.dcache.demand_miss_latency::cpu1.data 7413117000 # number of demand (read+write) miss cycles 1001system.cpu1.dcache.demand_miss_latency::total 7413117000 # number of demand (read+write) miss cycles 1002system.cpu1.dcache.overall_miss_latency::cpu1.data 7413117000 # number of overall miss cycles 1003system.cpu1.dcache.overall_miss_latency::total 7413117000 # number of overall miss cycles 1004system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117524 # number of ReadReq accesses(hits+misses) 1005system.cpu1.dcache.ReadReq_accesses::total 7117524 # number of ReadReq accesses(hits+misses) 1006system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977844 # number of WriteReq accesses(hits+misses) 1007system.cpu1.dcache.WriteReq_accesses::total 4977844 # number of WriteReq accesses(hits+misses) 1008system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92876 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu1.dcache.LoadLockedReq_accesses::total 92876 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92807 # number of StoreCondReq accesses(hits+misses) 1011system.cpu1.dcache.StoreCondReq_accesses::total 92807 # number of StoreCondReq accesses(hits+misses) 1012system.cpu1.dcache.demand_accesses::cpu1.data 12095368 # number of demand (read+write) accesses 1013system.cpu1.dcache.demand_accesses::total 12095368 # number of demand (read+write) accesses 1014system.cpu1.dcache.overall_accesses::cpu1.data 12095368 # number of overall (read+write) accesses 1015system.cpu1.dcache.overall_accesses::total 12095368 # number of overall (read+write) accesses 1016system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023966 # miss rate for ReadReq accesses 1017system.cpu1.dcache.ReadReq_miss_rate::total 0.023966 # miss rate for ReadReq accesses 1018system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030146 # miss rate for WriteReq accesses 1019system.cpu1.dcache.WriteReq_miss_rate::total 0.030146 # miss rate for WriteReq accesses 1020system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119094 # miss rate for LoadLockedReq accesses 1021system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119094 # miss rate for LoadLockedReq accesses 1022system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108149 # miss rate for StoreCondReq accesses 1023system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108149 # miss rate for StoreCondReq accesses 1024system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026509 # miss rate for demand accesses 1025system.cpu1.dcache.demand_miss_rate::total 0.026509 # miss rate for demand accesses 1026system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026509 # miss rate for overall accesses 1027system.cpu1.dcache.overall_miss_rate::total 0.026509 # miss rate for overall accesses 1028system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006 # average ReadReq miss latency 1029system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006 # average ReadReq miss latency 1030system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715 # average WriteReq miss latency 1031system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715 # average WriteReq miss latency 1032system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9235.150529 # average LoadLockedReq miss latency 1033system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9235.150529 # average LoadLockedReq miss latency 1034system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7510.411478 # average StoreCondReq miss latency 1035system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7510.411478 # average StoreCondReq miss latency 1036system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency 1037system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440 # average overall miss latency 1038system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency 1039system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440 # average overall miss latency |
| 1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1040system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1041system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1042system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1043system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1044system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1045system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1046system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1047system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1078system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks 1079system.cpu1.dcache.writebacks::total 254584 # number of writebacks 1080system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses 1081system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses 1082system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses 1083system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses 1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses 1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses 1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses 1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses 1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses 1089system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses 1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses 1091system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses 1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles 1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles 1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles 1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles 1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles 1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles 1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles 1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles 1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles 1101system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles 1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles 1103system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles 1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles 1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles 1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles 1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles 1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles 1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles 1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses 1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses 1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses 1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses 1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses 1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses 1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses 1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses 1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses 1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses 1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses 1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses 1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency 1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency 1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency 1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency 1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency 1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency 1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency 1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency 1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency 1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency 1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency 1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency | 1048system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks 1049system.cpu1.dcache.writebacks::total 265856 # number of writebacks 1050system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses 1051system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses 1052system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses 1053system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses 1054system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses 1055system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses 1056system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses 1057system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses 1058system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses 1059system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses 1060system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses 1061system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses 1062system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles 1063system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles 1064system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles 1065system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles 1066system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles 1067system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles 1068system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles 1069system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles 1070system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1071system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1072system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles 1073system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles 1074system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles 1075system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles 1076system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles 1077system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles 1078system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles 1079system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles 1080system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles 1081system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles 1082system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses 1083system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses 1084system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses 1085system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses 1086system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses 1087system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses 1088system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses 1089system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses 1090system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses 1091system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses 1092system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses 1093system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses 1094system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency 1095system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency 1096system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency 1097system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency 1098system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency 1099system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency 1100system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency 1101system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency 1102system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1103system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1104system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency 1105system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency 1106system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency 1107system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency |
| 1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.iocache.fast_writes 0 # number of fast writes performed 1154system.iocache.cache_copies 0 # number of cache copies performed | 1108system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1109system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1110system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1111system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1112system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1113system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1114system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1115system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1121system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1122system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1123system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1124system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1125system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1126system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1127system.iocache.fast_writes 0 # number of fast writes performed 1128system.iocache.cache_copies 0 # number of cache copies performed |
| 1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles 1156system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles 1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles 1158system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles | 1129system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles 1130system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles 1131system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles 1132system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles |
| 1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1164 1165---------- End Simulation Statistics ---------- | 1133system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1134system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1135system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1136system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1137system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1138 1139---------- End Simulation Statistics ---------- |