| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.669611 # Number of seconds simulated 4sim_ticks 2669611225000 # Number of ticks simulated 5final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.669611 # Number of seconds simulated 4sim_ticks 2669611225000 # Number of ticks simulated 5final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 887100 # Simulator instruction rate (inst/s) 8host_op_rate 1134851 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38636092154 # Simulator tick rate (ticks/s) 10host_mem_usage 379132 # Number of bytes of host memory used 11host_seconds 69.10 # Real time elapsed on the host | 7host_inst_rate 280373 # Simulator instruction rate (inst/s) 8host_op_rate 358676 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12211141498 # Simulator tick rate (ticks/s) 10host_mem_usage 385748 # Number of bytes of host memory used 11host_seconds 218.62 # Real time elapsed on the host |
| 12sim_insts 61295282 # Number of instructions simulated 13sim_ops 78413979 # Number of ops (including micro ops) simulated | 12sim_insts 61295282 # Number of instructions simulated 13sim_ops 78413979 # Number of ops (including micro ops) simulated |
| 14system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s) | |
| 23system.physmem.bytes_read 134334820 # Number of bytes read from this memory 24system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory 25system.physmem.bytes_written 10194256 # Number of bytes written to this memory 26system.physmem.num_reads 15523876 # Number of read requests responded to by this memory 27system.physmem.num_writes 869239 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read 134334820 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10194256 # Number of bytes written to this memory 17system.physmem.num_reads 15523876 # Number of read requests responded to by this memory 18system.physmem.num_writes 869239 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s) |
| 24system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s) |
|
| 33system.l2c.replacements 127749 # number of replacements 34system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use 35system.l2c.total_refs 1540413 # Total number of references to valid blocks. 36system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. 37system.l2c.avg_refs 9.801684 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor --- 221 unchanged lines hidden (view full) --- 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 33system.l2c.replacements 127749 # number of replacements 34system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use 35system.l2c.total_refs 1540413 # Total number of references to valid blocks. 36system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. 37system.l2c.avg_refs 9.801684 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor --- 221 unchanged lines hidden (view full) --- 262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency 263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency 264system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency 265system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency 266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 269system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 270system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed 274system.l2c.writebacks::writebacks 111955 # number of writebacks 275system.l2c.writebacks::total 111955 # number of writebacks 276system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 277system.l2c.ReadReq_mshr_hits::cpu0.data 8 # number of ReadReq MSHR hits 278system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 279system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits --- 268 unchanged lines hidden (view full) --- 548system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses 549system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency 550system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency 551system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency 552system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 272system.l2c.fast_writes 0 # number of fast writes performed 273system.l2c.cache_copies 0 # number of cache copies performed 274system.l2c.writebacks::writebacks 111955 # number of writebacks 275system.l2c.writebacks::total 111955 # number of writebacks 276system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 277system.l2c.ReadReq_mshr_hits::cpu0.data 8 # number of ReadReq MSHR hits 278system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 279system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits --- 268 unchanged lines hidden (view full) --- 548system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses 549system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency 550system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency 551system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency 552system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 556system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 557system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 556system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 558system.cpu0.icache.fast_writes 0 # number of fast writes performed 559system.cpu0.icache.cache_copies 0 # number of cache copies performed 560system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks 561system.cpu0.icache.writebacks::total 12960 # number of writebacks 562system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380584 # number of ReadReq MSHR misses 563system.cpu0.icache.ReadReq_mshr_misses::total 380584 # number of ReadReq MSHR misses 564system.cpu0.icache.demand_mshr_misses::cpu0.inst 380584 # number of demand (read+write) MSHR misses 565system.cpu0.icache.demand_mshr_misses::total 380584 # number of demand (read+write) MSHR misses --- 86 unchanged lines hidden (view full) --- 652system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency 653system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency 654system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency 655system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency 656system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 558system.cpu0.icache.fast_writes 0 # number of fast writes performed 559system.cpu0.icache.cache_copies 0 # number of cache copies performed 560system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks 561system.cpu0.icache.writebacks::total 12960 # number of writebacks 562system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380584 # number of ReadReq MSHR misses 563system.cpu0.icache.ReadReq_mshr_misses::total 380584 # number of ReadReq MSHR misses 564system.cpu0.icache.demand_mshr_misses::cpu0.inst 380584 # number of demand (read+write) MSHR misses 565system.cpu0.icache.demand_mshr_misses::total 380584 # number of demand (read+write) MSHR misses --- 86 unchanged lines hidden (view full) --- 652system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency 653system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency 654system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency 655system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency 656system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 660system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 661system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 660system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 662system.cpu0.dcache.fast_writes 0 # number of fast writes performed 663system.cpu0.dcache.cache_copies 0 # number of cache copies performed 664system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks 665system.cpu0.dcache.writebacks::total 294891 # number of writebacks 666system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses 667system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses 668system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses 669system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses --- 146 unchanged lines hidden (view full) --- 816system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses 817system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency 818system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency 819system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency 820system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 821system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 822system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 823system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 662system.cpu0.dcache.fast_writes 0 # number of fast writes performed 663system.cpu0.dcache.cache_copies 0 # number of cache copies performed 664system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks 665system.cpu0.dcache.writebacks::total 294891 # number of writebacks 666system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses 667system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses 668system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses 669system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses --- 146 unchanged lines hidden (view full) --- 816system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses 817system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency 818system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency 819system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency 820system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 821system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 822system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 823system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 824system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 825system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 824system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 825system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 826system.cpu1.icache.fast_writes 0 # number of fast writes performed 827system.cpu1.icache.cache_copies 0 # number of cache copies performed 828system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks 829system.cpu1.icache.writebacks::total 27998 # number of writebacks 830system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses 831system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses 832system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses 833system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses --- 86 unchanged lines hidden (view full) --- 920system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.421476 # average LoadLockedReq miss latency 921system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency 922system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency 923system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency 924system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 925system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 926system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 927system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 826system.cpu1.icache.fast_writes 0 # number of fast writes performed 827system.cpu1.icache.cache_copies 0 # number of cache copies performed 828system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks 829system.cpu1.icache.writebacks::total 27998 # number of writebacks 830system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses 831system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses 832system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses 833system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses --- 86 unchanged lines hidden (view full) --- 920system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.421476 # average LoadLockedReq miss latency 921system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency 922system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency 923system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency 924system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 925system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 926system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 927system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 928system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 929system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 928system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 929system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 930system.cpu1.dcache.fast_writes 0 # number of fast writes performed 931system.cpu1.dcache.cache_copies 0 # number of cache copies performed 932system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks 933system.cpu1.dcache.writebacks::total 253551 # number of writebacks 934system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses 935system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses 936system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses 937system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses --- 38 unchanged lines hidden (view full) --- 976system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 977system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 978system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 979system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 980system.iocache.replacements 0 # number of replacements 981system.iocache.tagsinuse 0 # Cycle average of tags in use 982system.iocache.total_refs 0 # Total number of references to valid blocks. 983system.iocache.sampled_refs 0 # Sample count of references to valid blocks. | 930system.cpu1.dcache.fast_writes 0 # number of fast writes performed 931system.cpu1.dcache.cache_copies 0 # number of cache copies performed 932system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks 933system.cpu1.dcache.writebacks::total 253551 # number of writebacks 934system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses 935system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses 936system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses 937system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses --- 38 unchanged lines hidden (view full) --- 976system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 977system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 978system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 979system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 980system.iocache.replacements 0 # number of replacements 981system.iocache.tagsinuse 0 # Cycle average of tags in use 982system.iocache.total_refs 0 # Total number of references to valid blocks. 983system.iocache.sampled_refs 0 # Sample count of references to valid blocks. |
| 984system.iocache.avg_refs no_value # Average number of references to valid blocks. | 984system.iocache.avg_refs nan # Average number of references to valid blocks. |
| 985system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 986system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 985system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 986system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 990system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 991system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 990system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 991system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 992system.iocache.fast_writes 0 # number of fast writes performed 993system.iocache.cache_copies 0 # number of cache copies performed 994system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles 995system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles 996system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles 997system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles 998system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 999system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1000system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1001 1002---------- End Simulation Statistics ---------- | 992system.iocache.fast_writes 0 # number of fast writes performed 993system.iocache.cache_copies 0 # number of cache copies performed 994system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles 995system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles 996system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles 997system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles 998system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 999system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1000system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1001 1002---------- End Simulation Statistics ---------- |