Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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stats.txt (11754:c209cb86278a)	stats.txt (11957:90bb43dfc028)
1 2---------- Begin Simulation Statistics ----------	1 2---------- Begin Simulation Statistics ----------
3sim_seconds 2.870996 # Number of seconds simulated 4sim_ticks 2870995800500 # Number of ticks simulated 5final_tick 2870995800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1013503 # Simulator instruction rate (inst/s) 8host_op_rate 1225877 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22160332076 # Simulator tick rate (ticks/s) 10host_mem_usage 622032 # Number of bytes of host memory used 11host_seconds 129.56 # Real time elapsed on the host 12sim_insts 131304972 # Number of instructions simulated 13sim_ops 158819278 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1181796 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1294372 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8555136 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 152212 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 573844 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 414464 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12173424 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 1181796 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 152212 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 1334008 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8754752 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 34system.physmem.bytes_written::total 8772316 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 26919 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 20744 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 133674 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 2533 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 8987 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 6476 # Number of read requests responded to by this memory 44system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 199358 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 136793 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 49system.physmem.num_writes::total 141184 # Number of write requests responded to by this memory 50system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 411633 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 450844 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 2979850 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 53017 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 199876 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 144362 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::total 4240140 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu0.inst 411633 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::cpu1.inst 53017 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::total 464650 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_write::writebacks 3049378 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::total 3055496 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_total::writebacks 3049378 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 411633 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 456948 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 2979850 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 53017 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 199890 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 144362 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::total 7295636 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.readReqs 199358 # Number of read requests accepted 81system.physmem.writeReqs 141184 # Number of write requests accepted 82system.physmem.readBursts 199358 # Number of DRAM read bursts, including those serviced by the write queue 83system.physmem.writeBursts 141184 # Number of DRAM write bursts, including those merged in the write queue 84system.physmem.bytesReadDRAM 12748800 # Total number of bytes read from DRAM 85system.physmem.bytesReadWrQ 10112 # Total number of bytes read from write queue 86system.physmem.bytesWritten 8785280 # Total number of bytes written to DRAM 87system.physmem.bytesReadSys 12173424 # Total read bytes from the system interface side 88system.physmem.bytesWrittenSys 8772316 # Total written bytes from the system interface side 89system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by the write queue 90system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 91system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 92system.physmem.perBankRdBursts::0 11937 # Per bank write bursts 93system.physmem.perBankRdBursts::1 11961 # Per bank write bursts 94system.physmem.perBankRdBursts::2 12063 # Per bank write bursts 95system.physmem.perBankRdBursts::3 12015 # Per bank write bursts 96system.physmem.perBankRdBursts::4 20362 # Per bank write bursts 97system.physmem.perBankRdBursts::5 11984 # Per bank write bursts 98system.physmem.perBankRdBursts::6 12067 # Per bank write bursts 99system.physmem.perBankRdBursts::7 12160 # Per bank write bursts 100system.physmem.perBankRdBursts::8 12406 # Per bank write bursts 101system.physmem.perBankRdBursts::9 12763 # Per bank write bursts 102system.physmem.perBankRdBursts::10 11654 # Per bank write bursts 103system.physmem.perBankRdBursts::11 11199 # Per bank write bursts 104system.physmem.perBankRdBursts::12 11763 # Per bank write bursts 105system.physmem.perBankRdBursts::13 11689 # Per bank write bursts 106system.physmem.perBankRdBursts::14 11766 # Per bank write bursts 107system.physmem.perBankRdBursts::15 11411 # Per bank write bursts 108system.physmem.perBankWrBursts::0 8587 # Per bank write bursts 109system.physmem.perBankWrBursts::1 8807 # Per bank write bursts 110system.physmem.perBankWrBursts::2 8988 # Per bank write bursts 111system.physmem.perBankWrBursts::3 8742 # Per bank write bursts 112system.physmem.perBankWrBursts::4 8269 # Per bank write bursts 113system.physmem.perBankWrBursts::5 8555 # Per bank write bursts 114system.physmem.perBankWrBursts::6 8883 # Per bank write bursts 115system.physmem.perBankWrBursts::7 8651 # Per bank write bursts 116system.physmem.perBankWrBursts::8 8881 # Per bank write bursts 117system.physmem.perBankWrBursts::9 9204 # Per bank write bursts 118system.physmem.perBankWrBursts::10 8442 # Per bank write bursts 119system.physmem.perBankWrBursts::11 8330 # Per bank write bursts 120system.physmem.perBankWrBursts::12 8611 # Per bank write bursts 121system.physmem.perBankWrBursts::13 8076 # Per bank write bursts 122system.physmem.perBankWrBursts::14 8388 # Per bank write bursts 123system.physmem.perBankWrBursts::15 7856 # Per bank write bursts 124system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 125system.physmem.numWrRetry 86 # Number of times write queue was full causing retry 126system.physmem.totGap 2870994769000 # Total gap between requests 127system.physmem.readPktSize::0 0 # Read request sizes (log2) 128system.physmem.readPktSize::1 0 # Read request sizes (log2) 129system.physmem.readPktSize::2 9732 # Read request sizes (log2) 130system.physmem.readPktSize::3 28 # Read request sizes (log2) 131system.physmem.readPktSize::4 0 # Read request sizes (log2) 132system.physmem.readPktSize::5 0 # Read request sizes (log2) 133system.physmem.readPktSize::6 189598 # Read request sizes (log2) 134system.physmem.writePktSize::0 0 # Write request sizes (log2) 135system.physmem.writePktSize::1 0 # Write request sizes (log2) 136system.physmem.writePktSize::2 4391 # Write request sizes (log2) 137system.physmem.writePktSize::3 0 # Write request sizes (log2) 138system.physmem.writePktSize::4 0 # Write request sizes (log2) 139system.physmem.writePktSize::5 0 # Write request sizes (log2) 140system.physmem.writePktSize::6 136793 # Write request sizes (log2) 141system.physmem.rdQLenPdf::0 136138 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::1 17236 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::2 10604 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::3 8747 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::4 7299 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::5 5883 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::6 5032 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::7 4260 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::8 3698 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::9 128 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::11 51 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 173system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::15 2554 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::16 3487 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::17 4394 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::18 5386 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::19 6479 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::20 6593 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::23 8490 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::24 8347 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::25 9668 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::26 9980 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::27 8490 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::28 8119 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::29 8411 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::30 9434 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::31 7894 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::32 7591 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::33 637 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::35 414 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::36 292 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::38 248 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::39 218 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::44 252 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::45 243 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::46 237 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::47 193 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::49 181 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::51 166 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::53 162 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::54 225 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::57 221 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::59 250 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::61 135 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::62 104 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::63 244 # What write queue length does an incoming req see 237system.physmem.bytesPerActivate::samples 85519 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::mean 251.803880 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::gmean 143.212865 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::stdev 307.683468 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::0-127 42851 50.11% 50.11% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::128-255 18042 21.10% 71.20% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::256-383 6336 7.41% 78.61% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::384-511 3652 4.27% 82.88% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::512-639 2667 3.12% 86.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::640-767 1677 1.96% 87.96% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::768-895 875 1.02% 88.99% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::896-1023 945 1.11% 90.09% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1024-1151 8474 9.91% 100.00% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::total 85519 # Bytes accessed per row activation 251system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::mean 29.315232 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::stdev 564.685462 # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes 258system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::mean 20.201619 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::gmean 18.574221 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::stdev 13.473858 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::16-19 5740 84.47% 84.47% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::20-23 356 5.24% 89.71% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::24-27 65 0.96% 90.67% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::28-31 46 0.68% 91.35% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-35 271 3.99% 95.33% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::36-39 21 0.31% 95.64% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::40-43 19 0.28% 95.92% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::44-47 18 0.26% 96.19% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::48-51 11 0.16% 96.35% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::52-55 7 0.10% 96.45% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::56-59 2 0.03% 96.48% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::60-63 7 0.10% 96.59% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::64-67 153 2.25% 98.84% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::68-71 7 0.10% 98.94% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::72-75 9 0.13% 99.07% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::76-79 5 0.07% 99.15% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::80-83 7 0.10% 99.25% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::84-87 2 0.03% 99.28% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::88-91 1 0.01% 99.29% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::96-99 3 0.04% 99.34% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::100-103 3 0.04% 99.38% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::104-107 1 0.01% 99.40% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::108-111 4 0.06% 99.46% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::112-115 2 0.03% 99.48% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::120-123 3 0.04% 99.53% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::124-127 2 0.03% 99.56% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::128-131 10 0.15% 99.71% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::132-135 1 0.01% 99.72% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::144-147 2 0.03% 99.82% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::152-155 1 0.01% 99.84% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::156-159 1 0.01% 99.85% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::160-163 3 0.04% 99.90% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::176-179 2 0.03% 99.96% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::192-195 2 0.03% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads 301system.physmem.totQLat 9377591483 # Total ticks spent queuing 302system.physmem.totMemAccLat 13112591483 # Total ticks spent from burst creation until serviced by the DRAM 303system.physmem.totBusLat 996000000 # Total ticks spent in databus transfers 304system.physmem.avgQLat 47076.26 # Average queueing delay per DRAM burst 305system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 306system.physmem.avgMemAccLat 65826.26 # Average memory access latency per DRAM burst 307system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s 308system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s 309system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s 310system.physmem.avgWrBWSys 3.06 # Average system write bandwidth in MiByte/s 311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 312system.physmem.busUtil 0.06 # Data bus utilization in percentage 313system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 314system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 315system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 316system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing 317system.physmem.readRowHits 166242 # Number of row buffer hits during reads 318system.physmem.writeRowHits 84708 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 83.45 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes 321system.physmem.avgGap 8430662.79 # Average gap between requests 322system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined 323system.physmem_0.actEnergy 309183420 # Energy for activate commands per rank (pJ) 324system.physmem_0.preEnergy 164331090 # Energy for precharge commands per rank (pJ) 325system.physmem_0.readEnergy 746479860 # Energy for read commands per rank (pJ) 326system.physmem_0.writeEnergy 362696040 # Energy for write commands per rank (pJ) 327system.physmem_0.refreshEnergy 6139024320.000001 # Energy for refresh commands per rank (pJ) 328system.physmem_0.actBackEnergy 5630456580 # Energy for active background per rank (pJ) 329system.physmem_0.preBackEnergy 369226560 # Energy for precharge background per rank (pJ) 330system.physmem_0.actPowerDownEnergy 11487380430 # Energy for active power-down per rank (pJ) 331system.physmem_0.prePowerDownEnergy 9121751040 # Energy for precharge power-down per rank (pJ) 332system.physmem_0.selfRefreshEnergy 675280298985 # Energy for self refresh per rank (pJ) 333system.physmem_0.totalEnergy 709613489745 # Total energy per rank (pJ) 334system.physmem_0.averagePower 247.166328 # Core power per rank (mW) 335system.physmem_0.totalIdleTime 2857680941179 # Total Idle time Per DRAM Rank 336system.physmem_0.memoryStateTime::IDLE 688127950 # Time in different power states 337system.physmem_0.memoryStateTime::REF 2609960000 # Time in different power states 338system.physmem_0.memoryStateTime::SREF 2808734663750 # Time in different power states 339system.physmem_0.memoryStateTime::PRE_PDN 23754548081 # Time in different power states 340system.physmem_0.memoryStateTime::ACT 10016707371 # Time in different power states 341system.physmem_0.memoryStateTime::ACT_PDN 25191793348 # Time in different power states 342system.physmem_1.actEnergy 301429380 # Energy for activate commands per rank (pJ) 343system.physmem_1.preEnergy 160213515 # Energy for precharge commands per rank (pJ) 344system.physmem_1.readEnergy 675808140 # Energy for read commands per rank (pJ) 345system.physmem_1.writeEnergy 353853360 # Energy for write commands per rank (pJ) 346system.physmem_1.refreshEnergy 6242283840.000001 # Energy for refresh commands per rank (pJ) 347system.physmem_1.actBackEnergy 5675698050 # Energy for active background per rank (pJ) 348system.physmem_1.preBackEnergy 365488800 # Energy for precharge background per rank (pJ) 349system.physmem_1.actPowerDownEnergy 11403357870 # Energy for active power-down per rank (pJ) 350system.physmem_1.prePowerDownEnergy 9537644640 # Energy for precharge power-down per rank (pJ) 351system.physmem_1.selfRefreshEnergy 675067441050 # Energy for self refresh per rank (pJ) 352system.physmem_1.totalEnergy 709786212765 # Total energy per rank (pJ) 353system.physmem_1.averagePower 247.226489 # Core power per rank (mW) 354system.physmem_1.totalIdleTime 2857340478310 # Total Idle time Per DRAM Rank 355system.physmem_1.memoryStateTime::IDLE 678311229 # Time in different power states 356system.physmem_1.memoryStateTime::REF 2653946000 # Time in different power states 357system.physmem_1.memoryStateTime::SREF 2807745675250 # Time in different power states 358system.physmem_1.memoryStateTime::PRE_PDN 24837614861 # Time in different power states 359system.physmem_1.memoryStateTime::ACT 10072973461 # Time in different power states 360system.physmem_1.memoryStateTime::ACT_PDN 25007279699 # Time in different power states 361system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 362system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 363system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 365system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 366system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 367system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 368system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 369system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 370system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 371system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 380system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 381system.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 382system.bridge.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 383system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 384system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 385system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 386system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 387system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 388system.cf0.dma_write_txs 631 # Number of DMA write transactions. 389system.cpu_clk_domain.clock 500 # Clock period in ticks 390system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 400system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 401system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 402system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 403system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 404system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 420system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 421system.cpu0.dtb.walker.walks 7823 # Table walker walks requested 422system.cpu0.dtb.walker.walksShort 7823 # Table walker walks initiated with short descriptors 423system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1468 # Level at which table walker walks with short descriptors terminate 424system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6355 # Level at which table walker walks with short descriptors terminate 425system.cpu0.dtb.walker.walkWaitTime::samples 7823 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::total 7823 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkCompletionTime::samples 6429 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::mean 12550.163322 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::gmean 11491.858959 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::stdev 6296.322703 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::0-16383 5867 91.26% 91.26% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::16384-32767 463 7.20% 98.46% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::32768-49151 86 1.34% 99.80% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.12% 99.92% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::total 6429 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walkPageSizes::4K 5000 77.77% 77.77% # Table walker page sizes translated 444system.cpu0.dtb.walker.walkPageSizes::1M 1429 22.23% 100.00% # Table walker page sizes translated 445system.cpu0.dtb.walker.walkPageSizes::total 6429 # Table walker page sizes translated 446system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin::total 14252 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.inst_hits 0 # ITB inst hits 454system.cpu0.dtb.inst_misses 0 # ITB inst misses 455system.cpu0.dtb.read_hits 25081905 # DTB read hits 456system.cpu0.dtb.read_misses 6707 # DTB read misses 457system.cpu0.dtb.write_hits 18693539 # DTB write hits 458system.cpu0.dtb.write_misses 1116 # DTB write misses 459system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 460system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 461system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 462system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 463system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB 464system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu0.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch 466system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 468system.cpu0.dtb.read_accesses 25088612 # DTB read accesses 469system.cpu0.dtb.write_accesses 18694655 # DTB write accesses 470system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 471system.cpu0.dtb.hits 43775444 # DTB hits 472system.cpu0.dtb.misses 7823 # DTB misses 473system.cpu0.dtb.accesses 43783267 # DTB accesses 474system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 475system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 484system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 485system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 486system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 487system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 488system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 492system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 493system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 494system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 495system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 496system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 498system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 499system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 500system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 501system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 502system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 503system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 504system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 505system.cpu0.itb.walker.walks 3349 # Table walker walks requested 506system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 507system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 508system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 509system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 510system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 511system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 512system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::mean 12879.339906 # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::gmean 12002.998619 # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::stdev 5903.446394 # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::0-8191 363 15.56% 15.56% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::8192-16383 1682 72.10% 87.66% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::16384-24575 212 9.09% 96.74% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.59% 98.33% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.54% 99.87% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution 526system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution 527system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution 528system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated 529system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated 530system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated 531system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 535system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst 536system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst 537system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst 538system.cpu0.itb.inst_hits 118659015 # ITB inst hits 539system.cpu0.itb.inst_misses 3349 # ITB inst misses 540system.cpu0.itb.read_hits 0 # DTB read hits 541system.cpu0.itb.read_misses 0 # DTB read misses 542system.cpu0.itb.write_hits 0 # DTB write hits 543system.cpu0.itb.write_misses 0 # DTB write misses 544system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 545system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 546system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 547system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 548system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB 549system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 550system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 551system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 552system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 553system.cpu0.itb.read_accesses 0 # DTB read accesses 554system.cpu0.itb.write_accesses 0 # DTB write accesses 555system.cpu0.itb.inst_accesses 118662364 # ITB inst accesses 556system.cpu0.itb.hits 118659015 # DTB hits 557system.cpu0.itb.misses 3349 # DTB misses 558system.cpu0.itb.accesses 118662364 # DTB accesses 559system.cpu0.numPwrStateTransitions 3724 # Number of power state transitions 560system.cpu0.pwrStateClkGateDist::samples 1862 # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::mean 1466902343.272825 # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::stdev 23730658455.603134 # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% # Distribution of time spent in the clock gated state 565system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 566system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state 567system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 568system.cpu0.pwrStateClkGateDist::max_value 499963373360 # Distribution of time spent in the clock gated state 569system.cpu0.pwrStateClkGateDist::total 1862 # Distribution of time spent in the clock gated state 570system.cpu0.pwrStateResidencyTicks::ON 139623637326 # Cumulative time (in ticks) in various power states 571system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731372163174 # Cumulative time (in ticks) in various power states 572system.cpu0.numCycles 5741991601 # number of cpu cycles simulated 573system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 574system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 575system.cpu0.kern.inst.arm 0 # number of arm instructions executed 576system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed 577system.cpu0.committedInsts 114996919 # Number of instructions committed 578system.cpu0.committedOps 138962993 # Number of ops (including micro ops) committed 579system.cpu0.num_int_alu_accesses 122999157 # Number of integer alu accesses 580system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 581system.cpu0.num_func_calls 12659267 # number of times a function call or return occured 582system.cpu0.num_conditional_control_insts 15643522 # number of instructions that are conditional controls 583system.cpu0.num_int_insts 122999157 # number of integer instructions 584system.cpu0.num_fp_insts 9755 # number of float instructions 585system.cpu0.num_int_register_reads 226444380 # number of times the integer registers were read 586system.cpu0.num_int_register_writes 85465434 # number of times the integer registers were written 587system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 588system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 589system.cpu0.num_cc_register_reads 503448381 # number of times the CC registers were read 590system.cpu0.num_cc_register_writes 52091583 # number of times the CC registers were written 591system.cpu0.num_mem_refs 44908198 # number of memory refs 592system.cpu0.num_load_insts 25331105 # Number of load instructions 593system.cpu0.num_store_insts 19577093 # Number of store instructions 594system.cpu0.num_idle_cycles 5462744326.346097 # Number of idle cycles 595system.cpu0.num_busy_cycles 279247274.653903 # Number of busy cycles 596system.cpu0.not_idle_fraction 0.048632 # Percentage of non-idle cycles 597system.cpu0.idle_fraction 0.951368 # Percentage of idle cycles 598system.cpu0.Branches 29039529 # Number of branches fetched 599system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 600system.cpu0.op_class::IntAlu 97695313 68.45% 68.45% # Class of executed instruction 601system.cpu0.op_class::IntMult 108459 0.08% 68.53% # Class of executed instruction 602system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction 603system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction 604system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction 605system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction 606system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction 607system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction 608system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction 609system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction 610system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction 611system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction 612system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction 613system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction 614system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction 615system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction 616system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction 617system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction 618system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction 619system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction 620system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction 621system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction 622system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction 623system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction 624system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction 625system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction 626system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction 627system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% # Class of executed instruction 628system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 629system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 630system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 631system.cpu0.op_class::MemRead 25328849 17.75% 86.28% # Class of executed instruction 632system.cpu0.op_class::MemWrite 19569598 13.71% 99.99% # Class of executed instruction 633system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction 634system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction 635system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 636system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 637system.cpu0.op_class::total 142722234 # Class of executed instruction 638system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 639system.cpu0.dcache.tags.replacements 690121 # number of replacements 640system.cpu0.dcache.tags.tagsinuse 498.373175 # Cycle average of tags in use 641system.cpu0.dcache.tags.total_refs 42907120 # Total number of references to valid blocks. 642system.cpu0.dcache.tags.sampled_refs 690633 # Sample count of references to valid blocks. 643system.cpu0.dcache.tags.avg_refs 62.127237 # Average number of references to valid blocks. 644system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit. 645system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.373175 # Average occupied blocks per requestor 646system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973385 # Average percentage of cache occupancy 647system.cpu0.dcache.tags.occ_percent::total 0.973385 # Average percentage of cache occupancy 648system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 649system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 650system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 651system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id 652system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 653system.cpu0.dcache.tags.tag_accesses 88185256 # Number of tag accesses 654system.cpu0.dcache.tags.data_accesses 88185256 # Number of data accesses 655system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 656system.cpu0.dcache.ReadReq_hits::cpu0.data 23824030 # number of ReadReq hits 657system.cpu0.dcache.ReadReq_hits::total 23824030 # number of ReadReq hits 658system.cpu0.dcache.WriteReq_hits::cpu0.data 17964029 # number of WriteReq hits 659system.cpu0.dcache.WriteReq_hits::total 17964029 # number of WriteReq hits 660system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318863 # number of SoftPFReq hits 661system.cpu0.dcache.SoftPFReq_hits::total 318863 # number of SoftPFReq hits 662system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364525 # number of LoadLockedReq hits 663system.cpu0.dcache.LoadLockedReq_hits::total 364525 # number of LoadLockedReq hits 664system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361510 # number of StoreCondReq hits 665system.cpu0.dcache.StoreCondReq_hits::total 361510 # number of StoreCondReq hits 666system.cpu0.dcache.demand_hits::cpu0.data 41788059 # number of demand (read+write) hits 667system.cpu0.dcache.demand_hits::total 41788059 # number of demand (read+write) hits 668system.cpu0.dcache.overall_hits::cpu0.data 42106922 # number of overall hits 669system.cpu0.dcache.overall_hits::total 42106922 # number of overall hits 670system.cpu0.dcache.ReadReq_misses::cpu0.data 394827 # number of ReadReq misses 671system.cpu0.dcache.ReadReq_misses::total 394827 # number of ReadReq misses 672system.cpu0.dcache.WriteReq_misses::cpu0.data 324085 # number of WriteReq misses 673system.cpu0.dcache.WriteReq_misses::total 324085 # number of WriteReq misses 674system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127008 # number of SoftPFReq misses 675system.cpu0.dcache.SoftPFReq_misses::total 127008 # number of SoftPFReq misses 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21435 # number of LoadLockedReq misses 677system.cpu0.dcache.LoadLockedReq_misses::total 21435 # number of LoadLockedReq misses 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19554 # number of StoreCondReq misses 679system.cpu0.dcache.StoreCondReq_misses::total 19554 # number of StoreCondReq misses 680system.cpu0.dcache.demand_misses::cpu0.data 718912 # number of demand (read+write) misses 681system.cpu0.dcache.demand_misses::total 718912 # number of demand (read+write) misses 682system.cpu0.dcache.overall_misses::cpu0.data 845920 # number of overall misses 683system.cpu0.dcache.overall_misses::total 845920 # number of overall misses 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5517390500 # number of ReadReq miss cycles 685system.cpu0.dcache.ReadReq_miss_latency::total 5517390500 # number of ReadReq miss cycles 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6298218500 # number of WriteReq miss cycles 687system.cpu0.dcache.WriteReq_miss_latency::total 6298218500 # number of WriteReq miss cycles 688system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337010500 # number of LoadLockedReq miss cycles 689system.cpu0.dcache.LoadLockedReq_miss_latency::total 337010500 # number of LoadLockedReq miss cycles 690system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 458737500 # number of StoreCondReq miss cycles 691system.cpu0.dcache.StoreCondReq_miss_latency::total 458737500 # number of StoreCondReq miss cycles 692system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1113000 # number of StoreCondFailReq miss cycles 693system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1113000 # number of StoreCondFailReq miss cycles 694system.cpu0.dcache.demand_miss_latency::cpu0.data 11815609000 # number of demand (read+write) miss cycles 695system.cpu0.dcache.demand_miss_latency::total 11815609000 # number of demand (read+write) miss cycles 696system.cpu0.dcache.overall_miss_latency::cpu0.data 11815609000 # number of overall miss cycles 697system.cpu0.dcache.overall_miss_latency::total 11815609000 # number of overall miss cycles 698system.cpu0.dcache.ReadReq_accesses::cpu0.data 24218857 # number of ReadReq accesses(hits+misses) 699system.cpu0.dcache.ReadReq_accesses::total 24218857 # number of ReadReq accesses(hits+misses) 700system.cpu0.dcache.WriteReq_accesses::cpu0.data 18288114 # number of WriteReq accesses(hits+misses) 701system.cpu0.dcache.WriteReq_accesses::total 18288114 # number of WriteReq accesses(hits+misses) 702system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445871 # number of SoftPFReq accesses(hits+misses) 703system.cpu0.dcache.SoftPFReq_accesses::total 445871 # number of SoftPFReq accesses(hits+misses) 704system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385960 # number of LoadLockedReq accesses(hits+misses) 705system.cpu0.dcache.LoadLockedReq_accesses::total 385960 # number of LoadLockedReq accesses(hits+misses) 706system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381064 # number of StoreCondReq accesses(hits+misses) 707system.cpu0.dcache.StoreCondReq_accesses::total 381064 # number of StoreCondReq accesses(hits+misses) 708system.cpu0.dcache.demand_accesses::cpu0.data 42506971 # number of demand (read+write) accesses 709system.cpu0.dcache.demand_accesses::total 42506971 # number of demand (read+write) accesses 710system.cpu0.dcache.overall_accesses::cpu0.data 42952842 # number of overall (read+write) accesses 711system.cpu0.dcache.overall_accesses::total 42952842 # number of overall (read+write) accesses 712system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016302 # miss rate for ReadReq accesses 713system.cpu0.dcache.ReadReq_miss_rate::total 0.016302 # miss rate for ReadReq accesses 714system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017721 # miss rate for WriteReq accesses 715system.cpu0.dcache.WriteReq_miss_rate::total 0.017721 # miss rate for WriteReq accesses 716system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284854 # miss rate for SoftPFReq accesses 717system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284854 # miss rate for SoftPFReq accesses 718system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055537 # miss rate for LoadLockedReq accesses 719system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055537 # miss rate for LoadLockedReq accesses 720system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051314 # miss rate for StoreCondReq accesses 721system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051314 # miss rate for StoreCondReq accesses 722system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016913 # miss rate for demand accesses 723system.cpu0.dcache.demand_miss_rate::total 0.016913 # miss rate for demand accesses 724system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019694 # miss rate for overall accesses 725system.cpu0.dcache.overall_miss_rate::total 0.019694 # miss rate for overall accesses 726system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13974.197560 # average ReadReq miss latency 727system.cpu0.dcache.ReadReq_avg_miss_latency::total 13974.197560 # average ReadReq miss latency 728system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19433.847602 # average WriteReq miss latency 729system.cpu0.dcache.WriteReq_avg_miss_latency::total 19433.847602 # average WriteReq miss latency 730system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15722.439935 # average LoadLockedReq miss latency 731system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15722.439935 # average LoadLockedReq miss latency 732system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23460.033753 # average StoreCondReq miss latency 733system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23460.033753 # average StoreCondReq miss latency 734system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 735system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 736system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16435.403777 # average overall miss latency 737system.cpu0.dcache.demand_avg_miss_latency::total 16435.403777 # average overall miss latency 738system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13967.761727 # average overall miss latency 739system.cpu0.dcache.overall_avg_miss_latency::total 13967.761727 # average overall miss latency 740system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 741system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 742system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 743system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 744system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 745system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu0.dcache.writebacks::writebacks 690121 # number of writebacks 747system.cpu0.dcache.writebacks::total 690121 # number of writebacks 748system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25200 # number of ReadReq MSHR hits 749system.cpu0.dcache.ReadReq_mshr_hits::total 25200 # number of ReadReq MSHR hits 750system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15056 # number of LoadLockedReq MSHR hits 751system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15056 # number of LoadLockedReq MSHR hits 752system.cpu0.dcache.demand_mshr_hits::cpu0.data 25200 # number of demand (read+write) MSHR hits 753system.cpu0.dcache.demand_mshr_hits::total 25200 # number of demand (read+write) MSHR hits 754system.cpu0.dcache.overall_mshr_hits::cpu0.data 25200 # number of overall MSHR hits 755system.cpu0.dcache.overall_mshr_hits::total 25200 # number of overall MSHR hits 756system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369627 # number of ReadReq MSHR misses 757system.cpu0.dcache.ReadReq_mshr_misses::total 369627 # number of ReadReq MSHR misses 758system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324085 # number of WriteReq MSHR misses 759system.cpu0.dcache.WriteReq_mshr_misses::total 324085 # number of WriteReq MSHR misses 760system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100010 # number of SoftPFReq MSHR misses 761system.cpu0.dcache.SoftPFReq_mshr_misses::total 100010 # number of SoftPFReq MSHR misses 762system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6379 # number of LoadLockedReq MSHR misses 763system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6379 # number of LoadLockedReq MSHR misses 764system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19554 # number of StoreCondReq MSHR misses 765system.cpu0.dcache.StoreCondReq_mshr_misses::total 19554 # number of StoreCondReq MSHR misses 766system.cpu0.dcache.demand_mshr_misses::cpu0.data 693712 # number of demand (read+write) MSHR misses 767system.cpu0.dcache.demand_mshr_misses::total 693712 # number of demand (read+write) MSHR misses 768system.cpu0.dcache.overall_mshr_misses::cpu0.data 793722 # number of overall MSHR misses 769system.cpu0.dcache.overall_mshr_misses::total 793722 # number of overall MSHR misses 770system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable 771system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31768 # number of ReadReq MSHR uncacheable 772system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable 773system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable 774system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses 775system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60214 # number of overall MSHR uncacheable misses 776system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4739955500 # number of ReadReq MSHR miss cycles 777system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739955500 # number of ReadReq MSHR miss cycles 778system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5974133500 # number of WriteReq MSHR miss cycles 779system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5974133500 # number of WriteReq MSHR miss cycles 780system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1650418500 # number of SoftPFReq MSHR miss cycles 781system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1650418500 # number of SoftPFReq MSHR miss cycles 782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101003000 # number of LoadLockedReq MSHR miss cycles 783system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101003000 # number of LoadLockedReq MSHR miss cycles 784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439215500 # number of StoreCondReq MSHR miss cycles 785system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439215500 # number of StoreCondReq MSHR miss cycles 786system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1081000 # number of StoreCondFailReq MSHR miss cycles 787system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1081000 # number of StoreCondFailReq MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10714089000 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.demand_mshr_miss_latency::total 10714089000 # number of demand (read+write) MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12364507500 # number of overall MSHR miss cycles 791system.cpu0.dcache.overall_mshr_miss_latency::total 12364507500 # number of overall MSHR miss cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631169500 # number of ReadReq MSHR uncacheable cycles 793system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631169500 # number of ReadReq MSHR uncacheable cycles 794system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631169500 # number of overall MSHR uncacheable cycles 795system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631169500 # number of overall MSHR uncacheable cycles 796system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015262 # mshr miss rate for ReadReq accesses 797system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015262 # mshr miss rate for ReadReq accesses 798system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017721 # mshr miss rate for WriteReq accesses 799system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017721 # mshr miss rate for WriteReq accesses 800system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224303 # mshr miss rate for SoftPFReq accesses 801system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224303 # mshr miss rate for SoftPFReq accesses 802system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016528 # mshr miss rate for LoadLockedReq accesses 803system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016528 # mshr miss rate for LoadLockedReq accesses 804system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051314 # mshr miss rate for StoreCondReq accesses 805system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051314 # mshr miss rate for StoreCondReq accesses 806system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016320 # mshr miss rate for demand accesses 807system.cpu0.dcache.demand_mshr_miss_rate::total 0.016320 # mshr miss rate for demand accesses 808system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018479 # mshr miss rate for overall accesses 809system.cpu0.dcache.overall_mshr_miss_rate::total 0.018479 # mshr miss rate for overall accesses 810system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12823.618134 # average ReadReq mshr miss latency 811system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12823.618134 # average ReadReq mshr miss latency 812system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18433.847602 # average WriteReq mshr miss latency 813system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18433.847602 # average WriteReq mshr miss latency 814system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16502.534747 # average SoftPFReq mshr miss latency 815system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16502.534747 # average SoftPFReq mshr miss latency 816system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15833.672989 # average LoadLockedReq mshr miss latency 817system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15833.672989 # average LoadLockedReq mshr miss latency 818system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22461.670246 # average StoreCondReq mshr miss latency 819system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22461.670246 # average StoreCondReq mshr miss latency 820system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 821system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 822system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15444.577865 # average overall mshr miss latency 823system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15444.577865 # average overall mshr miss latency 824system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15577.881802 # average overall mshr miss latency 825system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15577.881802 # average overall mshr miss latency 826system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208737.392974 # average ReadReq mshr uncacheable latency 827system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208737.392974 # average ReadReq mshr uncacheable latency 828system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110126.706414 # average overall mshr uncacheable latency 829system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110126.706414 # average overall mshr uncacheable latency 830system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 831system.cpu0.icache.tags.replacements 1095423 # number of replacements 832system.cpu0.icache.tags.tagsinuse 511.436912 # Cycle average of tags in use 833system.cpu0.icache.tags.total_refs 117563071 # Total number of references to valid blocks. 834system.cpu0.icache.tags.sampled_refs 1095935 # Sample count of references to valid blocks. 835system.cpu0.icache.tags.avg_refs 107.271938 # Average number of references to valid blocks. 836system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit. 837system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436912 # Average occupied blocks per requestor 838system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy 839system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy 840system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 841system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 842system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 843system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 844system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 845system.cpu0.icache.tags.tag_accesses 238413974 # Number of tag accesses 846system.cpu0.icache.tags.data_accesses 238413974 # Number of data accesses 847system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 848system.cpu0.icache.ReadReq_hits::cpu0.inst 117563071 # number of ReadReq hits 849system.cpu0.icache.ReadReq_hits::total 117563071 # number of ReadReq hits 850system.cpu0.icache.demand_hits::cpu0.inst 117563071 # number of demand (read+write) hits 851system.cpu0.icache.demand_hits::total 117563071 # number of demand (read+write) hits 852system.cpu0.icache.overall_hits::cpu0.inst 117563071 # number of overall hits 853system.cpu0.icache.overall_hits::total 117563071 # number of overall hits 854system.cpu0.icache.ReadReq_misses::cpu0.inst 1095944 # number of ReadReq misses 855system.cpu0.icache.ReadReq_misses::total 1095944 # number of ReadReq misses 856system.cpu0.icache.demand_misses::cpu0.inst 1095944 # number of demand (read+write) misses 857system.cpu0.icache.demand_misses::total 1095944 # number of demand (read+write) misses 858system.cpu0.icache.overall_misses::cpu0.inst 1095944 # number of overall misses 859system.cpu0.icache.overall_misses::total 1095944 # number of overall misses 860system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11846969000 # number of ReadReq miss cycles 861system.cpu0.icache.ReadReq_miss_latency::total 11846969000 # number of ReadReq miss cycles 862system.cpu0.icache.demand_miss_latency::cpu0.inst 11846969000 # number of demand (read+write) miss cycles 863system.cpu0.icache.demand_miss_latency::total 11846969000 # number of demand (read+write) miss cycles 864system.cpu0.icache.overall_miss_latency::cpu0.inst 11846969000 # number of overall miss cycles 865system.cpu0.icache.overall_miss_latency::total 11846969000 # number of overall miss cycles 866system.cpu0.icache.ReadReq_accesses::cpu0.inst 118659015 # number of ReadReq accesses(hits+misses) 867system.cpu0.icache.ReadReq_accesses::total 118659015 # number of ReadReq accesses(hits+misses) 868system.cpu0.icache.demand_accesses::cpu0.inst 118659015 # number of demand (read+write) accesses 869system.cpu0.icache.demand_accesses::total 118659015 # number of demand (read+write) accesses 870system.cpu0.icache.overall_accesses::cpu0.inst 118659015 # number of overall (read+write) accesses 871system.cpu0.icache.overall_accesses::total 118659015 # number of overall (read+write) accesses 872system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009236 # miss rate for ReadReq accesses 873system.cpu0.icache.ReadReq_miss_rate::total 0.009236 # miss rate for ReadReq accesses 874system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009236 # miss rate for demand accesses 875system.cpu0.icache.demand_miss_rate::total 0.009236 # miss rate for demand accesses 876system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009236 # miss rate for overall accesses 877system.cpu0.icache.overall_miss_rate::total 0.009236 # miss rate for overall accesses 878system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10809.830612 # average ReadReq miss latency 879system.cpu0.icache.ReadReq_avg_miss_latency::total 10809.830612 # average ReadReq miss latency 880system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency 881system.cpu0.icache.demand_avg_miss_latency::total 10809.830612 # average overall miss latency 882system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency 883system.cpu0.icache.overall_avg_miss_latency::total 10809.830612 # average overall miss latency 884system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 885system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 886system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 887system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 888system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 889system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 890system.cpu0.icache.writebacks::writebacks 1095423 # number of writebacks 891system.cpu0.icache.writebacks::total 1095423 # number of writebacks 892system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1095944 # number of ReadReq MSHR misses 893system.cpu0.icache.ReadReq_mshr_misses::total 1095944 # number of ReadReq MSHR misses 894system.cpu0.icache.demand_mshr_misses::cpu0.inst 1095944 # number of demand (read+write) MSHR misses 895system.cpu0.icache.demand_mshr_misses::total 1095944 # number of demand (read+write) MSHR misses 896system.cpu0.icache.overall_mshr_misses::cpu0.inst 1095944 # number of overall MSHR misses 897system.cpu0.icache.overall_mshr_misses::total 1095944 # number of overall MSHR misses 898system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 899system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 900system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 901system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 902system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11298997000 # number of ReadReq MSHR miss cycles 903system.cpu0.icache.ReadReq_mshr_miss_latency::total 11298997000 # number of ReadReq MSHR miss cycles 904system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11298997000 # number of demand (read+write) MSHR miss cycles 905system.cpu0.icache.demand_mshr_miss_latency::total 11298997000 # number of demand (read+write) MSHR miss cycles 906system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11298997000 # number of overall MSHR miss cycles 907system.cpu0.icache.overall_mshr_miss_latency::total 11298997000 # number of overall MSHR miss cycles 908system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles 909system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles 910system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles 911system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles 912system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for ReadReq accesses 913system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009236 # mshr miss rate for ReadReq accesses 914system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for demand accesses 915system.cpu0.icache.demand_mshr_miss_rate::total 0.009236 # mshr miss rate for demand accesses 916system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for overall accesses 917system.cpu0.icache.overall_mshr_miss_rate::total 0.009236 # mshr miss rate for overall accesses 918system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average ReadReq mshr miss latency 919system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10309.830612 # average ReadReq mshr miss latency 920system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency 921system.cpu0.icache.demand_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency 922system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency 923system.cpu0.icache.overall_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency 924system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency 925system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency 926system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency 927system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency 928system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 929system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843455 # number of hwpf issued 930system.cpu0.l2cache.prefetcher.pfIdentified 1843489 # number of prefetch candidates identified 931system.cpu0.l2cache.prefetcher.pfBufferHit 30 # number of redundant prefetches already in prefetch queue 932system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 933system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 934system.cpu0.l2cache.prefetcher.pfSpanPage 237167 # number of prefetches not generated due to page crossing 935system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 936system.cpu0.l2cache.tags.replacements 260392 # number of replacements 937system.cpu0.l2cache.tags.tagsinuse 15616.554479 # Cycle average of tags in use 938system.cpu0.l2cache.tags.total_refs 1673878 # Total number of references to valid blocks. 939system.cpu0.l2cache.tags.sampled_refs 276011 # Sample count of references to valid blocks. 940system.cpu0.l2cache.tags.avg_refs 6.064534 # Average number of references to valid blocks. 941system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 942system.cpu0.l2cache.tags.occ_blocks::writebacks 14458.510897 # Average occupied blocks per requestor 943system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.380966 # Average occupied blocks per requestor 944system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135465 # Average occupied blocks per requestor 945system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1156.527151 # Average occupied blocks per requestor 946system.cpu0.l2cache.tags.occ_percent::writebacks 0.882477 # Average percentage of cache occupancy 947system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy 948system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 949system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070589 # Average percentage of cache occupancy 950system.cpu0.l2cache.tags.occ_percent::total 0.953159 # Average percentage of cache occupancy 951system.cpu0.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id 952system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 953system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15300 # Occupied blocks per task id 954system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 955system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id 956system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 129 # Occupied blocks per task id 957system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 150 # Occupied blocks per task id 958system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 959system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id 962system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6046 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6216 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2035 # Occupied blocks per task id 965system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id 966system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 967system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933838 # Percentage of cache occupancy per task id 968system.cpu0.l2cache.tags.tag_accesses 60952812 # Number of tag accesses 969system.cpu0.l2cache.tags.data_accesses 60952812 # Number of data accesses 970system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 971system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9949 # number of ReadReq hits 972system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4513 # number of ReadReq hits 973system.cpu0.l2cache.ReadReq_hits::total 14462 # number of ReadReq hits 974system.cpu0.l2cache.WritebackDirty_hits::writebacks 474087 # number of WritebackDirty hits 975system.cpu0.l2cache.WritebackDirty_hits::total 474087 # number of WritebackDirty hits 976system.cpu0.l2cache.WritebackClean_hits::writebacks 1283679 # number of WritebackClean hits 977system.cpu0.l2cache.WritebackClean_hits::total 1283679 # number of WritebackClean hits 978system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226501 # number of ReadExReq hits 979system.cpu0.l2cache.ReadExReq_hits::total 226501 # number of ReadExReq hits 980system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1033387 # number of ReadCleanReq hits 981system.cpu0.l2cache.ReadCleanReq_hits::total 1033387 # number of ReadCleanReq hits 982system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 374984 # number of ReadSharedReq hits 983system.cpu0.l2cache.ReadSharedReq_hits::total 374984 # number of ReadSharedReq hits 984system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9949 # number of demand (read+write) hits 985system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4513 # number of demand (read+write) hits 986system.cpu0.l2cache.demand_hits::cpu0.inst 1033387 # number of demand (read+write) hits 987system.cpu0.l2cache.demand_hits::cpu0.data 601485 # number of demand (read+write) hits 988system.cpu0.l2cache.demand_hits::total 1649334 # number of demand (read+write) hits 989system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9949 # number of overall hits 990system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4513 # number of overall hits 991system.cpu0.l2cache.overall_hits::cpu0.inst 1033387 # number of overall hits 992system.cpu0.l2cache.overall_hits::cpu0.data 601485 # number of overall hits 993system.cpu0.l2cache.overall_hits::total 1649334 # number of overall hits 994system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 333 # number of ReadReq misses 995system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 154 # number of ReadReq misses 996system.cpu0.l2cache.ReadReq_misses::total 487 # number of ReadReq misses 997system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54609 # number of UpgradeReq misses 998system.cpu0.l2cache.UpgradeReq_misses::total 54609 # number of UpgradeReq misses 999system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19552 # number of SCUpgradeReq misses 1000system.cpu0.l2cache.SCUpgradeReq_misses::total 19552 # number of SCUpgradeReq misses 1001system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1002system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1003system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42975 # number of ReadExReq misses 1004system.cpu0.l2cache.ReadExReq_misses::total 42975 # number of ReadExReq misses 1005system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62557 # number of ReadCleanReq misses 1006system.cpu0.l2cache.ReadCleanReq_misses::total 62557 # number of ReadCleanReq misses 1007system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101032 # number of ReadSharedReq misses 1008system.cpu0.l2cache.ReadSharedReq_misses::total 101032 # number of ReadSharedReq misses 1009system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 333 # number of demand (read+write) misses 1010system.cpu0.l2cache.demand_misses::cpu0.itb.walker 154 # number of demand (read+write) misses 1011system.cpu0.l2cache.demand_misses::cpu0.inst 62557 # number of demand (read+write) misses 1012system.cpu0.l2cache.demand_misses::cpu0.data 144007 # number of demand (read+write) misses 1013system.cpu0.l2cache.demand_misses::total 207051 # number of demand (read+write) misses 1014system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 333 # number of overall misses 1015system.cpu0.l2cache.overall_misses::cpu0.itb.walker 154 # number of overall misses 1016system.cpu0.l2cache.overall_misses::cpu0.inst 62557 # number of overall misses 1017system.cpu0.l2cache.overall_misses::cpu0.data 144007 # number of overall misses 1018system.cpu0.l2cache.overall_misses::total 207051 # number of overall misses 1019system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8868000 # number of ReadReq miss cycles 1020system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618500 # number of ReadReq miss cycles 1021system.cpu0.l2cache.ReadReq_miss_latency::total 12486500 # number of ReadReq miss cycles 1022system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 29801000 # number of UpgradeReq miss cycles 1023system.cpu0.l2cache.UpgradeReq_miss_latency::total 29801000 # number of UpgradeReq miss cycles 1024system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8716000 # number of SCUpgradeReq miss cycles 1025system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8716000 # number of SCUpgradeReq miss cycles 1026system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1032499 # number of SCUpgradeFailReq miss cycles 1027system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1032499 # number of SCUpgradeFailReq miss cycles 1028system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2749345500 # number of ReadExReq miss cycles 1029system.cpu0.l2cache.ReadExReq_miss_latency::total 2749345500 # number of ReadExReq miss cycles 1030system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3431495000 # number of ReadCleanReq miss cycles 1031system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3431495000 # number of ReadCleanReq miss cycles 1032system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3333037000 # number of ReadSharedReq miss cycles 1033system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3333037000 # number of ReadSharedReq miss cycles 1034system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8868000 # number of demand (read+write) miss cycles 1035system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618500 # number of demand (read+write) miss cycles 1036system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3431495000 # number of demand (read+write) miss cycles 1037system.cpu0.l2cache.demand_miss_latency::cpu0.data 6082382500 # number of demand (read+write) miss cycles 1038system.cpu0.l2cache.demand_miss_latency::total 9526364000 # number of demand (read+write) miss cycles 1039system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8868000 # number of overall miss cycles 1040system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618500 # number of overall miss cycles 1041system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3431495000 # number of overall miss cycles 1042system.cpu0.l2cache.overall_miss_latency::cpu0.data 6082382500 # number of overall miss cycles 1043system.cpu0.l2cache.overall_miss_latency::total 9526364000 # number of overall miss cycles 1044system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10282 # number of ReadReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4667 # number of ReadReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadReq_accesses::total 14949 # number of ReadReq accesses(hits+misses) 1047system.cpu0.l2cache.WritebackDirty_accesses::writebacks 474087 # number of WritebackDirty accesses(hits+misses) 1048system.cpu0.l2cache.WritebackDirty_accesses::total 474087 # number of WritebackDirty accesses(hits+misses) 1049system.cpu0.l2cache.WritebackClean_accesses::writebacks 1283679 # number of WritebackClean accesses(hits+misses) 1050system.cpu0.l2cache.WritebackClean_accesses::total 1283679 # number of WritebackClean accesses(hits+misses) 1051system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54609 # number of UpgradeReq accesses(hits+misses) 1052system.cpu0.l2cache.UpgradeReq_accesses::total 54609 # number of UpgradeReq accesses(hits+misses) 1053system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19552 # number of SCUpgradeReq accesses(hits+misses) 1054system.cpu0.l2cache.SCUpgradeReq_accesses::total 19552 # number of SCUpgradeReq accesses(hits+misses) 1055system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1056system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1057system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269476 # number of ReadExReq accesses(hits+misses) 1058system.cpu0.l2cache.ReadExReq_accesses::total 269476 # number of ReadExReq accesses(hits+misses) 1059system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1095944 # number of ReadCleanReq accesses(hits+misses) 1060system.cpu0.l2cache.ReadCleanReq_accesses::total 1095944 # number of ReadCleanReq accesses(hits+misses) 1061system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476016 # number of ReadSharedReq accesses(hits+misses) 1062system.cpu0.l2cache.ReadSharedReq_accesses::total 476016 # number of ReadSharedReq accesses(hits+misses) 1063system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10282 # number of demand (read+write) accesses 1064system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4667 # number of demand (read+write) accesses 1065system.cpu0.l2cache.demand_accesses::cpu0.inst 1095944 # number of demand (read+write) accesses 1066system.cpu0.l2cache.demand_accesses::cpu0.data 745492 # number of demand (read+write) accesses 1067system.cpu0.l2cache.demand_accesses::total 1856385 # number of demand (read+write) accesses 1068system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10282 # number of overall (read+write) accesses 1069system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4667 # number of overall (read+write) accesses 1070system.cpu0.l2cache.overall_accesses::cpu0.inst 1095944 # number of overall (read+write) accesses 1071system.cpu0.l2cache.overall_accesses::cpu0.data 745492 # number of overall (read+write) accesses 1072system.cpu0.l2cache.overall_accesses::total 1856385 # number of overall (read+write) accesses 1073system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for ReadReq accesses 1074system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032998 # miss rate for ReadReq accesses 1075system.cpu0.l2cache.ReadReq_miss_rate::total 0.032577 # miss rate for ReadReq accesses 1076system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1077system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1078system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1079system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1080system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1081system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1082system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159476 # miss rate for ReadExReq accesses 1083system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159476 # miss rate for ReadExReq accesses 1084system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.057080 # miss rate for ReadCleanReq accesses 1085system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.057080 # miss rate for ReadCleanReq accesses 1086system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212245 # miss rate for ReadSharedReq accesses 1087system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212245 # miss rate for ReadSharedReq accesses 1088system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for demand accesses 1089system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032998 # miss rate for demand accesses 1090system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057080 # miss rate for demand accesses 1091system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193170 # miss rate for demand accesses 1092system.cpu0.l2cache.demand_miss_rate::total 0.111535 # miss rate for demand accesses 1093system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for overall accesses 1094system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032998 # miss rate for overall accesses 1095system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057080 # miss rate for overall accesses 1096system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193170 # miss rate for overall accesses 1097system.cpu0.l2cache.overall_miss_rate::total 0.111535 # miss rate for overall accesses 1098system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average ReadReq miss latency 1099system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23496.753247 # average ReadReq miss latency 1100system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25639.630390 # average ReadReq miss latency 1101system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 545.715908 # average UpgradeReq miss latency 1102system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 545.715908 # average UpgradeReq miss latency 1103system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 445.785597 # average SCUpgradeReq miss latency 1104system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 445.785597 # average SCUpgradeReq miss latency 1105system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 516249.500000 # average SCUpgradeFailReq miss latency 1106system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 516249.500000 # average SCUpgradeFailReq miss latency 1107system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63975.462478 # average ReadExReq miss latency 1108system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63975.462478 # average ReadExReq miss latency 1109system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54853.893249 # average ReadCleanReq miss latency 1110system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54853.893249 # average ReadCleanReq miss latency 1111system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32989.914087 # average ReadSharedReq miss latency 1112system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32989.914087 # average ReadSharedReq miss latency 1113system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency 1114system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency 1115system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency 1116system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency 1117system.cpu0.l2cache.demand_avg_miss_latency::total 46009.746391 # average overall miss latency 1118system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency 1119system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency 1120system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency 1121system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency 1122system.cpu0.l2cache.overall_avg_miss_latency::total 46009.746391 # average overall miss latency 1123system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1124system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1125system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1126system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1127system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1128system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1129system.cpu0.l2cache.unused_prefetches 10486 # number of HardPF blocks evicted w/o reference 1130system.cpu0.l2cache.writebacks::writebacks 227470 # number of writebacks 1131system.cpu0.l2cache.writebacks::total 227470 # number of writebacks 1132system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1575 # number of ReadExReq MSHR hits 1133system.cpu0.l2cache.ReadExReq_mshr_hits::total 1575 # number of ReadExReq MSHR hits 1134system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits 1135system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1605 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.demand_mshr_hits::total 1605 # number of demand (read+write) MSHR hits 1138system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1605 # number of overall MSHR hits 1139system.cpu0.l2cache.overall_mshr_hits::total 1605 # number of overall MSHR hits 1140system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 333 # number of ReadReq MSHR misses 1141system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 154 # number of ReadReq MSHR misses 1142system.cpu0.l2cache.ReadReq_mshr_misses::total 487 # number of ReadReq MSHR misses 1143system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of HardPFReq MSHR misses 1144system.cpu0.l2cache.HardPFReq_mshr_misses::total 261736 # number of HardPFReq MSHR misses 1145system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54609 # number of UpgradeReq MSHR misses 1146system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54609 # number of UpgradeReq MSHR misses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19552 # number of SCUpgradeReq MSHR misses 1148system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19552 # number of SCUpgradeReq MSHR misses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1150system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1151system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41400 # number of ReadExReq MSHR misses 1152system.cpu0.l2cache.ReadExReq_mshr_misses::total 41400 # number of ReadExReq MSHR misses 1153system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62557 # number of ReadCleanReq MSHR misses 1154system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62557 # number of ReadCleanReq MSHR misses 1155system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses 1156system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses 1157system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 333 # number of demand (read+write) MSHR misses 1158system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 154 # number of demand (read+write) MSHR misses 1159system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62557 # number of demand (read+write) MSHR misses 1160system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142402 # number of demand (read+write) MSHR misses 1161system.cpu0.l2cache.demand_mshr_misses::total 205446 # number of demand (read+write) MSHR misses 1162system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 333 # number of overall MSHR misses 1163system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 154 # number of overall MSHR misses 1164system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62557 # number of overall MSHR misses 1165system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142402 # number of overall MSHR misses 1166system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of overall MSHR misses 1167system.cpu0.l2cache.overall_mshr_misses::total 467182 # number of overall MSHR misses 1168system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1169system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable 1170system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40790 # number of ReadReq MSHR uncacheable 1171system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable 1172system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable 1173system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1174system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses 1175system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69236 # number of overall MSHR uncacheable misses 1176system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of ReadReq MSHR miss cycles 1177system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2694500 # number of ReadReq MSHR miss cycles 1178system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9564500 # number of ReadReq MSHR miss cycles 1179system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of HardPFReq MSHR miss cycles 1180system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16748653122 # number of HardPFReq MSHR miss cycles 1181system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 936375500 # number of UpgradeReq MSHR miss cycles 1182system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 936375500 # number of UpgradeReq MSHR miss cycles 1183system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292739000 # number of SCUpgradeReq MSHR miss cycles 1184system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292739000 # number of SCUpgradeReq MSHR miss cycles 1185system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 840499 # number of SCUpgradeFailReq MSHR miss cycles 1186system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 840499 # number of SCUpgradeFailReq MSHR miss cycles 1187system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2221757000 # number of ReadExReq MSHR miss cycles 1188system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2221757000 # number of ReadExReq MSHR miss cycles 1189system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3056153000 # number of ReadCleanReq MSHR miss cycles 1190system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3056153000 # number of ReadCleanReq MSHR miss cycles 1191system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2721461500 # number of ReadSharedReq MSHR miss cycles 1192system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2721461500 # number of ReadSharedReq MSHR miss cycles 1193system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of demand (read+write) MSHR miss cycles 1194system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2694500 # number of demand (read+write) MSHR miss cycles 1195system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3056153000 # number of demand (read+write) MSHR miss cycles 1196system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4943218500 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.l2cache.demand_mshr_miss_latency::total 8008936000 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of overall MSHR miss cycles 1199system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2694500 # number of overall MSHR miss cycles 1200system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3056153000 # number of overall MSHR miss cycles 1201system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4943218500 # number of overall MSHR miss cycles 1202system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of overall MSHR miss cycles 1203system.cpu0.l2cache.overall_mshr_miss_latency::total 24757589122 # number of overall MSHR miss cycles 1204system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles 1205system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6376615000 # number of ReadReq MSHR uncacheable cycles 1206system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172255500 # number of ReadReq MSHR uncacheable cycles 1207system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles 1208system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6376615000 # number of overall MSHR uncacheable cycles 1209system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172255500 # number of overall MSHR uncacheable cycles 1210system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for ReadReq accesses 1211system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for ReadReq accesses 1212system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032577 # mshr miss rate for ReadReq accesses 1213system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1214system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1215system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1216system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1217system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1218system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1219system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1220system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1221system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153631 # mshr miss rate for ReadExReq accesses 1222system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153631 # mshr miss rate for ReadExReq accesses 1223system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for ReadCleanReq accesses 1224system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.057080 # mshr miss rate for ReadCleanReq accesses 1225system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212182 # mshr miss rate for ReadSharedReq accesses 1226system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212182 # mshr miss rate for ReadSharedReq accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for demand accesses 1230system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for demand accesses 1231system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110670 # mshr miss rate for demand accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for overall accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for overall accesses 1235system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for overall accesses 1236system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1237system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251662 # mshr miss rate for overall accesses 1238system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average ReadReq mshr miss latency 1239system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average ReadReq mshr miss latency 1240system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19639.630390 # average ReadReq mshr miss latency 1241system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average HardPFReq mshr miss latency 1242system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63990.636068 # average HardPFReq mshr miss latency 1243system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17146.908019 # average UpgradeReq mshr miss latency 1244system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17146.908019 # average UpgradeReq mshr miss latency 1245system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14972.330196 # average SCUpgradeReq mshr miss latency 1246system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.330196 # average SCUpgradeReq mshr miss latency 1247system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 420249.500000 # average SCUpgradeFailReq mshr miss latency 1248system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 420249.500000 # average SCUpgradeFailReq mshr miss latency 1249system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53665.628019 # average ReadExReq mshr miss latency 1250system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53665.628019 # average ReadExReq mshr miss latency 1251system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average ReadCleanReq mshr miss latency 1252system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48853.893249 # average ReadCleanReq mshr miss latency 1253system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26944.629809 # average ReadSharedReq mshr miss latency 1254system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26944.629809 # average ReadSharedReq mshr miss latency 1255system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency 1256system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency 1257system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency 1258system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency 1259system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38983.168326 # average overall mshr miss latency 1260system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency 1261system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency 1263system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency 1264system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average overall mshr miss latency 1265system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52993.456773 # average overall mshr miss latency 1266system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency 1267system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200724.471166 # average ReadReq mshr uncacheable latency 1268system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175833.672469 # average ReadReq mshr uncacheable latency 1269system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency 1270system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105899.209486 # average overall mshr uncacheable latency 1271system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.419204 # average overall mshr uncacheable latency 1272system.cpu0.toL2Bus.snoop_filter.tot_requests 3713043 # Total number of requests made to the snoop filter. 1273system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871637 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1274system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27791 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1275system.cpu0.toL2Bus.snoop_filter.tot_snoops 210694 # Total number of snoops made to the snoop filter. 1276system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1277system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1647 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1278system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1279system.cpu0.toL2Bus.trans_dist::ReadReq 61395 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::ReadResp 1681090 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::WriteReq 28446 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::WriteResp 28446 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::WritebackDirty 701864 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::WritebackClean 1311457 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::CleanEvict 80209 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::HardPFReq 307976 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::UpgradeReq 86960 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41708 # Transaction distribution 1290system.cpu0.toL2Bus.trans_dist::UpgradeResp 111633 # Transaction distribution 1291system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::ReadExReq 288540 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::ReadExResp 285048 # Transaction distribution 1295system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095944 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562349 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 # Transaction distribution 1299system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3305355 # Packet count per connected master and slave (bytes) 1300system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550756 # Packet count per connected master and slave (bytes) 1301system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11066 # Packet count per connected master and slave (bytes) 1302system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24460 # Packet count per connected master and slave (bytes) 1303system.cpu0.toL2Bus.pkt_count::total 5891637 # Packet count per connected master and slave (bytes) 1304system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140283576 # Cumulative packet size per connected master and slave (bytes) 1305system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96129280 # Cumulative packet size per connected master and slave (bytes) 1306system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18668 # Cumulative packet size per connected master and slave (bytes) 1307system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41128 # Cumulative packet size per connected master and slave (bytes) 1308system.cpu0.toL2Bus.pkt_size::total 236472652 # Cumulative packet size per connected master and slave (bytes) 1309system.cpu0.toL2Bus.snoops 885693 # Total snoops (count) 1310system.cpu0.toL2Bus.snoopTraffic 18656572 # Total snoop traffic (bytes) 1311system.cpu0.toL2Bus.snoop_fanout::samples 2784580 # Request fanout histogram 1312system.cpu0.toL2Bus.snoop_fanout::mean 0.090516 # Request fanout histogram 1313system.cpu0.toL2Bus.snoop_fanout::stdev 0.288973 # Request fanout histogram 1314system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1315system.cpu0.toL2Bus.snoop_fanout::0 2534179 91.01% 91.01% # Request fanout histogram 1316system.cpu0.toL2Bus.snoop_fanout::1 248754 8.93% 99.94% # Request fanout histogram 1317system.cpu0.toL2Bus.snoop_fanout::2 1647 0.06% 100.00% # Request fanout histogram 1318system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1319system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1320system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1321system.cpu0.toL2Bus.snoop_fanout::total 2784580 # Request fanout histogram 1322system.cpu0.toL2Bus.reqLayer0.occupancy 3695245998 # Layer occupancy (ticks) 1323system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1324system.cpu0.toL2Bus.snoopLayer0.occupancy 113887546 # Layer occupancy (ticks) 1325system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1326system.cpu0.toL2Bus.respLayer0.occupancy 1652938000 # Layer occupancy (ticks) 1327system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1328system.cpu0.toL2Bus.respLayer1.occupancy 1201348488 # Layer occupancy (ticks) 1329system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1330system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1331system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1332system.cpu0.toL2Bus.respLayer3.occupancy 14180994 # Layer occupancy (ticks) 1333system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1342system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1343system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1344system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1345system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1346system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1347system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1348system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1349system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1350system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1351system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1352system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1353system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1354system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1355system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1356system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1357system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1358system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1359system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1360system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1361system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1362system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1363system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1364system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1365system.cpu1.dtb.walker.walks 3368 # Table walker walks requested 1366system.cpu1.dtb.walker.walksShort 3368 # Table walker walks initiated with short descriptors 1367system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate 1368system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate 1369system.cpu1.dtb.walker.walkWaitTime::samples 3368 # Table walker wait (enqueue to first request) latency 1370system.cpu1.dtb.walker.walkWaitTime::0 3368 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1371system.cpu1.dtb.walker.walkWaitTime::total 3368 # Table walker wait (enqueue to first request) latency 1372system.cpu1.dtb.walker.walkCompletionTime::samples 2598 # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::mean 12496.920708 # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::gmean 11544.208502 # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::stdev 5669.313441 # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::0-8191 611 23.52% 23.52% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 64.32% 87.84% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 8.85% 96.69% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::24576-32767 69 2.66% 99.35% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::32768-40959 10 0.38% 99.73% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.85% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::total 2598 # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution 1387system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution 1388system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution 1389system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.56% 74.56% # Table walker page sizes translated 1390system.cpu1.dtb.walker.walkPageSizes::1M 661 25.44% 100.00% # Table walker page sizes translated 1391system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated 1392system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3368 # Table walker requests started/completed, data/inst 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3368 # Table walker requests started/completed, data/inst 1395system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.walker.walkRequestOrigin::total 5966 # Table walker requests started/completed, data/inst 1399system.cpu1.dtb.inst_hits 0 # ITB inst hits 1400system.cpu1.dtb.inst_misses 0 # ITB inst misses 1401system.cpu1.dtb.read_hits 3952331 # DTB read hits 1402system.cpu1.dtb.read_misses 2852 # DTB read misses 1403system.cpu1.dtb.write_hits 3427850 # DTB write hits 1404system.cpu1.dtb.write_misses 516 # DTB write misses 1405system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1406system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1407system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1408system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1409system.cpu1.dtb.flush_entries 1975 # Number of entries that have been flushed from TLB 1410system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1411system.cpu1.dtb.prefetch_faults 341 # Number of TLB faults due to prefetch 1412system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dtb.read_accesses 3955183 # DTB read accesses 1415system.cpu1.dtb.write_accesses 3428366 # DTB write accesses 1416system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dtb.hits 7380181 # DTB hits 1418system.cpu1.dtb.misses 3368 # DTB misses 1419system.cpu1.dtb.accesses 7383549 # DTB accesses 1420system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1429system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1430system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1431system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1432system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1433system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1434system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1435system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1436system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1437system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1438system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1439system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1440system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1441system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1442system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1443system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1444system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1445system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1446system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1447system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1448system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1449system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1450system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1451system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1452system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1453system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1454system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1455system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1456system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1457system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1458system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::mean 12746.160795 # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::gmean 11849.716682 # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::stdev 5651.710937 # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.36% 15.36% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::8192-12287 628 56.73% 72.09% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::12288-16383 162 14.63% 86.72% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.43% 91.15% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::20480-24575 38 3.43% 94.58% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::24576-28671 32 2.89% 97.47% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.01% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::32768-36863 4 0.36% 99.37% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution 1477system.cpu1.itb.walker.walksPending::total -1938367828 # Table walker pending requests distribution 1478system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1479system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1480system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1487system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1488system.cpu1.itb.inst_hits 16663369 # ITB inst hits 1489system.cpu1.itb.inst_misses 1746 # ITB inst misses 1490system.cpu1.itb.read_hits 0 # DTB read hits 1491system.cpu1.itb.read_misses 0 # DTB read misses 1492system.cpu1.itb.write_hits 0 # DTB write hits 1493system.cpu1.itb.write_misses 0 # DTB write misses 1494system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1495system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1496system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1497system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1498system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB 1499system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1500system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1501system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1502system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1503system.cpu1.itb.read_accesses 0 # DTB read accesses 1504system.cpu1.itb.write_accesses 0 # DTB write accesses 1505system.cpu1.itb.inst_accesses 16665115 # ITB inst accesses 1506system.cpu1.itb.hits 16663369 # DTB hits 1507system.cpu1.itb.misses 1746 # DTB misses 1508system.cpu1.itb.accesses 16665115 # DTB accesses 1509system.cpu1.numPwrStateTransitions 5435 # Number of power state transitions 1510system.cpu1.pwrStateClkGateDist::samples 2718 # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::mean 1046549937.704562 # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::stdev 25917662670.452511 # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::underflows 1945 71.56% 71.56% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::1000-5e+10 767 28.22% 99.78% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state 1522system.cpu1.pwrStateClkGateDist::total 2718 # Distribution of time spent in the clock gated state 1523system.cpu1.pwrStateResidencyTicks::ON 26473069819 # Cumulative time (in ticks) in various power states 1524system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844522730681 # Cumulative time (in ticks) in various power states 1525system.cpu1.numCycles 5741059879 # number of cpu cycles simulated 1526system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1527system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1528system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1529system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed 1530system.cpu1.committedInsts 16308053 # Number of instructions committed 1531system.cpu1.committedOps 19856285 # Number of ops (including micro ops) committed 1532system.cpu1.num_int_alu_accesses 17888019 # Number of integer alu accesses 1533system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 1534system.cpu1.num_func_calls 1028859 # number of times a function call or return occured 1535system.cpu1.num_conditional_control_insts 1844250 # number of instructions that are conditional controls 1536system.cpu1.num_int_insts 17888019 # number of integer instructions 1537system.cpu1.num_fp_insts 1792 # number of float instructions 1538system.cpu1.num_int_register_reads 32444258 # number of times the integer registers were read 1539system.cpu1.num_int_register_writes 12537466 # number of times the integer registers were written 1540system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 1541system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1542system.cpu1.num_cc_register_reads 72543530 # number of times the CC registers were read 1543system.cpu1.num_cc_register_writes 6508973 # number of times the CC registers were written 1544system.cpu1.num_mem_refs 7613771 # number of memory refs 1545system.cpu1.num_load_insts 4063495 # Number of load instructions 1546system.cpu1.num_store_insts 3550276 # Number of store instructions 1547system.cpu1.num_idle_cycles 5688122330.646462 # Number of idle cycles 1548system.cpu1.num_busy_cycles 52937548.353538 # Number of busy cycles 1549system.cpu1.not_idle_fraction 0.009221 # Percentage of non-idle cycles 1550system.cpu1.idle_fraction 0.990779 # Percentage of idle cycles 1551system.cpu1.Branches 2952894 # Number of branches fetched 1552system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1553system.cpu1.op_class::IntAlu 12563541 62.17% 62.17% # Class of executed instruction 1554system.cpu1.op_class::IntMult 26310 0.13% 62.30% # Class of executed instruction 1555system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction 1556system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction 1557system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction 1558system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction 1559system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction 1560system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% # Class of executed instruction 1561system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction 1562system.cpu1.op_class::FloatMisc 0 0.00% 62.30% # Class of executed instruction 1563system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction 1564system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction 1565system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction 1566system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction 1567system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction 1568system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction 1569system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction 1570system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction 1571system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction 1572system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction 1573system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction 1574system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction 1575system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction 1576system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction 1577system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction 1578system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction 1579system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction 1580system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.32% # Class of executed instruction 1581system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction 1582system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction 1583system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction 1584system.cpu1.op_class::MemRead 4062979 20.11% 82.43% # Class of executed instruction 1585system.cpu1.op_class::MemWrite 3549000 17.56% 99.99% # Class of executed instruction 1586system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction 1587system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction 1588system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1589system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1590system.cpu1.op_class::total 20206967 # Class of executed instruction 1591system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1592system.cpu1.dcache.tags.replacements 187241 # number of replacements 1593system.cpu1.dcache.tags.tagsinuse 470.165247 # Cycle average of tags in use 1594system.cpu1.dcache.tags.total_refs 7113602 # Total number of references to valid blocks. 1595system.cpu1.dcache.tags.sampled_refs 187604 # Sample count of references to valid blocks. 1596system.cpu1.dcache.tags.avg_refs 37.918179 # Average number of references to valid blocks. 1597system.cpu1.dcache.tags.warmup_cycle 128171950500 # Cycle when the warmup percentage was hit. 1598system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.165247 # Average occupied blocks per requestor 1599system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918291 # Average percentage of cache occupancy 1600system.cpu1.dcache.tags.occ_percent::total 0.918291 # Average percentage of cache occupancy 1601system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id 1602system.cpu1.dcache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id 1603system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id 1604system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id 1605system.cpu1.dcache.tags.tag_accesses 14979376 # Number of tag accesses 1606system.cpu1.dcache.tags.data_accesses 14979376 # Number of data accesses 1607system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1608system.cpu1.dcache.ReadReq_hits::cpu1.data 3640649 # number of ReadReq hits 1609system.cpu1.dcache.ReadReq_hits::total 3640649 # number of ReadReq hits 1610system.cpu1.dcache.WriteReq_hits::cpu1.data 3239316 # number of WriteReq hits 1611system.cpu1.dcache.WriteReq_hits::total 3239316 # number of WriteReq hits 1612system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49005 # number of SoftPFReq hits 1613system.cpu1.dcache.SoftPFReq_hits::total 49005 # number of SoftPFReq hits 1614system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78940 # number of LoadLockedReq hits 1615system.cpu1.dcache.LoadLockedReq_hits::total 78940 # number of LoadLockedReq hits 1616system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70837 # number of StoreCondReq hits 1617system.cpu1.dcache.StoreCondReq_hits::total 70837 # number of StoreCondReq hits 1618system.cpu1.dcache.demand_hits::cpu1.data 6879965 # number of demand (read+write) hits 1619system.cpu1.dcache.demand_hits::total 6879965 # number of demand (read+write) hits 1620system.cpu1.dcache.overall_hits::cpu1.data 6928970 # number of overall hits 1621system.cpu1.dcache.overall_hits::total 6928970 # number of overall hits 1622system.cpu1.dcache.ReadReq_misses::cpu1.data 133578 # number of ReadReq misses 1623system.cpu1.dcache.ReadReq_misses::total 133578 # number of ReadReq misses 1624system.cpu1.dcache.WriteReq_misses::cpu1.data 91863 # number of WriteReq misses 1625system.cpu1.dcache.WriteReq_misses::total 91863 # number of WriteReq misses 1626system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30193 # number of SoftPFReq misses 1627system.cpu1.dcache.SoftPFReq_misses::total 30193 # number of SoftPFReq misses 1628system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16916 # number of LoadLockedReq misses 1629system.cpu1.dcache.LoadLockedReq_misses::total 16916 # number of LoadLockedReq misses 1630system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23207 # number of StoreCondReq misses 1631system.cpu1.dcache.StoreCondReq_misses::total 23207 # number of StoreCondReq misses 1632system.cpu1.dcache.demand_misses::cpu1.data 225441 # number of demand (read+write) misses 1633system.cpu1.dcache.demand_misses::total 225441 # number of demand (read+write) misses 1634system.cpu1.dcache.overall_misses::cpu1.data 255634 # number of overall misses 1635system.cpu1.dcache.overall_misses::total 255634 # number of overall misses 1636system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2045952000 # number of ReadReq miss cycles 1637system.cpu1.dcache.ReadReq_miss_latency::total 2045952000 # number of ReadReq miss cycles 1638system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2531885000 # number of WriteReq miss cycles 1639system.cpu1.dcache.WriteReq_miss_latency::total 2531885000 # number of WriteReq miss cycles 1640system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322352500 # number of LoadLockedReq miss cycles 1641system.cpu1.dcache.LoadLockedReq_miss_latency::total 322352500 # number of LoadLockedReq miss cycles 1642system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544400500 # number of StoreCondReq miss cycles 1643system.cpu1.dcache.StoreCondReq_miss_latency::total 544400500 # number of StoreCondReq miss cycles 1644system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2036500 # number of StoreCondFailReq miss cycles 1645system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2036500 # number of StoreCondFailReq miss cycles 1646system.cpu1.dcache.demand_miss_latency::cpu1.data 4577837000 # number of demand (read+write) miss cycles 1647system.cpu1.dcache.demand_miss_latency::total 4577837000 # number of demand (read+write) miss cycles 1648system.cpu1.dcache.overall_miss_latency::cpu1.data 4577837000 # number of overall miss cycles 1649system.cpu1.dcache.overall_miss_latency::total 4577837000 # number of overall miss cycles 1650system.cpu1.dcache.ReadReq_accesses::cpu1.data 3774227 # number of ReadReq accesses(hits+misses) 1651system.cpu1.dcache.ReadReq_accesses::total 3774227 # number of ReadReq accesses(hits+misses) 1652system.cpu1.dcache.WriteReq_accesses::cpu1.data 3331179 # number of WriteReq accesses(hits+misses) 1653system.cpu1.dcache.WriteReq_accesses::total 3331179 # number of WriteReq accesses(hits+misses) 1654system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79198 # number of SoftPFReq accesses(hits+misses) 1655system.cpu1.dcache.SoftPFReq_accesses::total 79198 # number of SoftPFReq accesses(hits+misses) 1656system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95856 # number of LoadLockedReq accesses(hits+misses) 1657system.cpu1.dcache.LoadLockedReq_accesses::total 95856 # number of LoadLockedReq accesses(hits+misses) 1658system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94044 # number of StoreCondReq accesses(hits+misses) 1659system.cpu1.dcache.StoreCondReq_accesses::total 94044 # number of StoreCondReq accesses(hits+misses) 1660system.cpu1.dcache.demand_accesses::cpu1.data 7105406 # number of demand (read+write) accesses 1661system.cpu1.dcache.demand_accesses::total 7105406 # number of demand (read+write) accesses 1662system.cpu1.dcache.overall_accesses::cpu1.data 7184604 # number of overall (read+write) accesses 1663system.cpu1.dcache.overall_accesses::total 7184604 # number of overall (read+write) accesses 1664system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035392 # miss rate for ReadReq accesses 1665system.cpu1.dcache.ReadReq_miss_rate::total 0.035392 # miss rate for ReadReq accesses 1666system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027577 # miss rate for WriteReq accesses 1667system.cpu1.dcache.WriteReq_miss_rate::total 0.027577 # miss rate for WriteReq accesses 1668system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381234 # miss rate for SoftPFReq accesses 1669system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381234 # miss rate for SoftPFReq accesses 1670system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176473 # miss rate for LoadLockedReq accesses 1671system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176473 # miss rate for LoadLockedReq accesses 1672system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246767 # miss rate for StoreCondReq accesses 1673system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246767 # miss rate for StoreCondReq accesses 1674system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031728 # miss rate for demand accesses 1675system.cpu1.dcache.demand_miss_rate::total 0.031728 # miss rate for demand accesses 1676system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses 1677system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses 1678system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15316.534160 # average ReadReq miss latency 1679system.cpu1.dcache.ReadReq_avg_miss_latency::total 15316.534160 # average ReadReq miss latency 1680system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27561.531846 # average WriteReq miss latency 1681system.cpu1.dcache.WriteReq_avg_miss_latency::total 27561.531846 # average WriteReq miss latency 1682system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19056.071175 # average LoadLockedReq miss latency 1683system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19056.071175 # average LoadLockedReq miss latency 1684system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23458.460809 # average StoreCondReq miss latency 1685system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23458.460809 # average StoreCondReq miss latency 1686system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1687system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1688system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20306.142184 # average overall miss latency 1689system.cpu1.dcache.demand_avg_miss_latency::total 20306.142184 # average overall miss latency 1690system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17907.778308 # average overall miss latency 1691system.cpu1.dcache.overall_avg_miss_latency::total 17907.778308 # average overall miss latency 1692system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1693system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1694system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1695system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1696system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1697system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1698system.cpu1.dcache.writebacks::writebacks 187241 # number of writebacks 1699system.cpu1.dcache.writebacks::total 187241 # number of writebacks 1700system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 248 # number of ReadReq MSHR hits 1701system.cpu1.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits 1702system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11947 # number of LoadLockedReq MSHR hits 1703system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11947 # number of LoadLockedReq MSHR hits 1704system.cpu1.dcache.demand_mshr_hits::cpu1.data 248 # number of demand (read+write) MSHR hits 1705system.cpu1.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 1706system.cpu1.dcache.overall_mshr_hits::cpu1.data 248 # number of overall MSHR hits 1707system.cpu1.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits 1708system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133330 # number of ReadReq MSHR misses 1709system.cpu1.dcache.ReadReq_mshr_misses::total 133330 # number of ReadReq MSHR misses 1710system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91863 # number of WriteReq MSHR misses 1711system.cpu1.dcache.WriteReq_mshr_misses::total 91863 # number of WriteReq MSHR misses 1712system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29503 # number of SoftPFReq MSHR misses 1713system.cpu1.dcache.SoftPFReq_mshr_misses::total 29503 # number of SoftPFReq MSHR misses 1714system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4969 # number of LoadLockedReq MSHR misses 1715system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4969 # number of LoadLockedReq MSHR misses 1716system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23207 # number of StoreCondReq MSHR misses 1717system.cpu1.dcache.StoreCondReq_mshr_misses::total 23207 # number of StoreCondReq MSHR misses 1718system.cpu1.dcache.demand_mshr_misses::cpu1.data 225193 # number of demand (read+write) MSHR misses 1719system.cpu1.dcache.demand_mshr_misses::total 225193 # number of demand (read+write) MSHR misses 1720system.cpu1.dcache.overall_mshr_misses::cpu1.data 254696 # number of overall MSHR misses 1721system.cpu1.dcache.overall_mshr_misses::total 254696 # number of overall MSHR misses 1722system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable 1723system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3077 # number of ReadReq MSHR uncacheable 1724system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable 1725system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable 1726system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses 1727system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5509 # number of overall MSHR uncacheable misses 1728system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901282500 # number of ReadReq MSHR miss cycles 1729system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901282500 # number of ReadReq MSHR miss cycles 1730system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2440022000 # number of WriteReq MSHR miss cycles 1731system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2440022000 # number of WriteReq MSHR miss cycles 1732system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 505317500 # number of SoftPFReq MSHR miss cycles 1733system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 505317500 # number of SoftPFReq MSHR miss cycles 1734system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91175500 # number of LoadLockedReq MSHR miss cycles 1735system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91175500 # number of LoadLockedReq MSHR miss cycles 1736system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521240500 # number of StoreCondReq MSHR miss cycles 1737system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521240500 # number of StoreCondReq MSHR miss cycles 1738system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1989500 # number of StoreCondFailReq MSHR miss cycles 1739system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1989500 # number of StoreCondFailReq MSHR miss cycles 1740system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4341304500 # number of demand (read+write) MSHR miss cycles 1741system.cpu1.dcache.demand_mshr_miss_latency::total 4341304500 # number of demand (read+write) MSHR miss cycles 1742system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846622000 # number of overall MSHR miss cycles 1743system.cpu1.dcache.overall_mshr_miss_latency::total 4846622000 # number of overall MSHR miss cycles 1744system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442663500 # number of ReadReq MSHR uncacheable cycles 1745system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442663500 # number of ReadReq MSHR uncacheable cycles 1746system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442663500 # number of overall MSHR uncacheable cycles 1747system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442663500 # number of overall MSHR uncacheable cycles 1748system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035326 # mshr miss rate for ReadReq accesses 1749system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035326 # mshr miss rate for ReadReq accesses 1750system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027577 # mshr miss rate for WriteReq accesses 1751system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027577 # mshr miss rate for WriteReq accesses 1752system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372522 # mshr miss rate for SoftPFReq accesses 1753system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372522 # mshr miss rate for SoftPFReq accesses 1754system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051838 # mshr miss rate for LoadLockedReq accesses 1755system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051838 # mshr miss rate for LoadLockedReq accesses 1756system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246767 # mshr miss rate for StoreCondReq accesses 1757system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246767 # mshr miss rate for StoreCondReq accesses 1758system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031693 # mshr miss rate for demand accesses 1759system.cpu1.dcache.demand_mshr_miss_rate::total 0.031693 # mshr miss rate for demand accesses 1760system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035450 # mshr miss rate for overall accesses 1761system.cpu1.dcache.overall_mshr_miss_rate::total 0.035450 # mshr miss rate for overall accesses 1762system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14259.975249 # average ReadReq mshr miss latency 1763system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14259.975249 # average ReadReq mshr miss latency 1764system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26561.531846 # average WriteReq mshr miss latency 1765system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26561.531846 # average WriteReq mshr miss latency 1766system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17127.664983 # average SoftPFReq mshr miss latency 1767system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17127.664983 # average SoftPFReq mshr miss latency 1768system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18348.862950 # average LoadLockedReq mshr miss latency 1769system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18348.862950 # average LoadLockedReq mshr miss latency 1770system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22460.486060 # average StoreCondReq mshr miss latency 1771system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22460.486060 # average StoreCondReq mshr miss latency 1772system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1773system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1774system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19278.150298 # average overall mshr miss latency 1775system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19278.150298 # average overall mshr miss latency 1776system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19029.046393 # average overall mshr miss latency 1777system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19029.046393 # average overall mshr miss latency 1778system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143862.040949 # average ReadReq mshr uncacheable latency 1779system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143862.040949 # average ReadReq mshr uncacheable latency 1780system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80352.786350 # average overall mshr uncacheable latency 1781system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80352.786350 # average overall mshr uncacheable latency 1782system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1783system.cpu1.icache.tags.replacements 503470 # number of replacements 1784system.cpu1.icache.tags.tagsinuse 498.455555 # Cycle average of tags in use 1785system.cpu1.icache.tags.total_refs 16159382 # Total number of references to valid blocks. 1786system.cpu1.icache.tags.sampled_refs 503982 # Sample count of references to valid blocks. 1787system.cpu1.icache.tags.avg_refs 32.063411 # Average number of references to valid blocks. 1788system.cpu1.icache.tags.warmup_cycle 85409649000 # Cycle when the warmup percentage was hit. 1789system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455555 # Average occupied blocks per requestor 1790system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546 # Average percentage of cache occupancy 1791system.cpu1.icache.tags.occ_percent::total 0.973546 # Average percentage of cache occupancy 1792system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1793system.cpu1.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id 1794system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id 1795system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id 1796system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1797system.cpu1.icache.tags.tag_accesses 33830710 # Number of tag accesses 1798system.cpu1.icache.tags.data_accesses 33830710 # Number of data accesses 1799system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1800system.cpu1.icache.ReadReq_hits::cpu1.inst 16159382 # number of ReadReq hits 1801system.cpu1.icache.ReadReq_hits::total 16159382 # number of ReadReq hits 1802system.cpu1.icache.demand_hits::cpu1.inst 16159382 # number of demand (read+write) hits 1803system.cpu1.icache.demand_hits::total 16159382 # number of demand (read+write) hits 1804system.cpu1.icache.overall_hits::cpu1.inst 16159382 # number of overall hits 1805system.cpu1.icache.overall_hits::total 16159382 # number of overall hits 1806system.cpu1.icache.ReadReq_misses::cpu1.inst 503982 # number of ReadReq misses 1807system.cpu1.icache.ReadReq_misses::total 503982 # number of ReadReq misses 1808system.cpu1.icache.demand_misses::cpu1.inst 503982 # number of demand (read+write) misses 1809system.cpu1.icache.demand_misses::total 503982 # number of demand (read+write) misses 1810system.cpu1.icache.overall_misses::cpu1.inst 503982 # number of overall misses 1811system.cpu1.icache.overall_misses::total 503982 # number of overall misses 1812system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4760681000 # number of ReadReq miss cycles 1813system.cpu1.icache.ReadReq_miss_latency::total 4760681000 # number of ReadReq miss cycles 1814system.cpu1.icache.demand_miss_latency::cpu1.inst 4760681000 # number of demand (read+write) miss cycles 1815system.cpu1.icache.demand_miss_latency::total 4760681000 # number of demand (read+write) miss cycles 1816system.cpu1.icache.overall_miss_latency::cpu1.inst 4760681000 # number of overall miss cycles 1817system.cpu1.icache.overall_miss_latency::total 4760681000 # number of overall miss cycles 1818system.cpu1.icache.ReadReq_accesses::cpu1.inst 16663364 # number of ReadReq accesses(hits+misses) 1819system.cpu1.icache.ReadReq_accesses::total 16663364 # number of ReadReq accesses(hits+misses) 1820system.cpu1.icache.demand_accesses::cpu1.inst 16663364 # number of demand (read+write) accesses 1821system.cpu1.icache.demand_accesses::total 16663364 # number of demand (read+write) accesses 1822system.cpu1.icache.overall_accesses::cpu1.inst 16663364 # number of overall (read+write) accesses 1823system.cpu1.icache.overall_accesses::total 16663364 # number of overall (read+write) accesses 1824system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030245 # miss rate for ReadReq accesses 1825system.cpu1.icache.ReadReq_miss_rate::total 0.030245 # miss rate for ReadReq accesses 1826system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030245 # miss rate for demand accesses 1827system.cpu1.icache.demand_miss_rate::total 0.030245 # miss rate for demand accesses 1828system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030245 # miss rate for overall accesses 1829system.cpu1.icache.overall_miss_rate::total 0.030245 # miss rate for overall accesses 1830system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9446.132997 # average ReadReq miss latency 1831system.cpu1.icache.ReadReq_avg_miss_latency::total 9446.132997 # average ReadReq miss latency 1832system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency 1833system.cpu1.icache.demand_avg_miss_latency::total 9446.132997 # average overall miss latency 1834system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency 1835system.cpu1.icache.overall_avg_miss_latency::total 9446.132997 # average overall miss latency 1836system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1837system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1838system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1839system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1840system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1841system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1842system.cpu1.icache.writebacks::writebacks 503470 # number of writebacks 1843system.cpu1.icache.writebacks::total 503470 # number of writebacks 1844system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503982 # number of ReadReq MSHR misses 1845system.cpu1.icache.ReadReq_mshr_misses::total 503982 # number of ReadReq MSHR misses 1846system.cpu1.icache.demand_mshr_misses::cpu1.inst 503982 # number of demand (read+write) MSHR misses 1847system.cpu1.icache.demand_mshr_misses::total 503982 # number of demand (read+write) MSHR misses 1848system.cpu1.icache.overall_mshr_misses::cpu1.inst 503982 # number of overall MSHR misses 1849system.cpu1.icache.overall_mshr_misses::total 503982 # number of overall MSHR misses 1850system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1851system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1852system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1853system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1854system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4508690000 # number of ReadReq MSHR miss cycles 1855system.cpu1.icache.ReadReq_mshr_miss_latency::total 4508690000 # number of ReadReq MSHR miss cycles 1856system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4508690000 # number of demand (read+write) MSHR miss cycles 1857system.cpu1.icache.demand_mshr_miss_latency::total 4508690000 # number of demand (read+write) MSHR miss cycles 1858system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4508690000 # number of overall MSHR miss cycles 1859system.cpu1.icache.overall_mshr_miss_latency::total 4508690000 # number of overall MSHR miss cycles 1860system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles 1861system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles 1862system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles 1863system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles 1864system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for ReadReq accesses 1865system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030245 # mshr miss rate for ReadReq accesses 1866system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for demand accesses 1867system.cpu1.icache.demand_mshr_miss_rate::total 0.030245 # mshr miss rate for demand accesses 1868system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for overall accesses 1869system.cpu1.icache.overall_mshr_miss_rate::total 0.030245 # mshr miss rate for overall accesses 1870system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average ReadReq mshr miss latency 1871system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8946.132997 # average ReadReq mshr miss latency 1872system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency 1873system.cpu1.icache.demand_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency 1874system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency 1875system.cpu1.icache.overall_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency 1876system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency 1877system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency 1878system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency 1879system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency 1880system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1881system.cpu1.l2cache.prefetcher.num_hwpf_issued 202393 # number of hwpf issued 1882system.cpu1.l2cache.prefetcher.pfIdentified 202393 # number of prefetch candidates identified 1883system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1884system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1885system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1886system.cpu1.l2cache.prefetcher.pfSpanPage 60767 # number of prefetches not generated due to page crossing 1887system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1888system.cpu1.l2cache.tags.replacements 44084 # number of replacements 1889system.cpu1.l2cache.tags.tagsinuse 14674.344516 # Cycle average of tags in use 1890system.cpu1.l2cache.tags.total_refs 603056 # Total number of references to valid blocks. 1891system.cpu1.l2cache.tags.sampled_refs 58488 # Sample count of references to valid blocks. 1892system.cpu1.l2cache.tags.avg_refs 10.310765 # Average number of references to valid blocks. 1893system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1894system.cpu1.l2cache.tags.occ_blocks::writebacks 14288.601821 # Average occupied blocks per requestor 1895system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.272921 # Average occupied blocks per requestor 1896system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.058859 # Average occupied blocks per requestor 1897system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.410915 # Average occupied blocks per requestor 1898system.cpu1.l2cache.tags.occ_percent::writebacks 0.872107 # Average percentage of cache occupancy 1899system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy 1900system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy 1901system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023279 # Average percentage of cache occupancy 1902system.cpu1.l2cache.tags.occ_percent::total 0.895651 # Average percentage of cache occupancy 1903system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id 1904system.cpu1.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1905system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14077 # Occupied blocks per task id 1906system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id 1907system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id 1908system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 292 # Occupied blocks per task id 1909system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1910system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1911system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 892 # Occupied blocks per task id 1912system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2699 # Occupied blocks per task id 1913system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10486 # Occupied blocks per task id 1914system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id 1915system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id 1916system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.859192 # Percentage of cache occupancy per task id 1917system.cpu1.l2cache.tags.tag_accesses 24261935 # Number of tag accesses 1918system.cpu1.l2cache.tags.data_accesses 24261935 # Number of data accesses 1919system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 1920system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3748 # number of ReadReq hits 1921system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1963 # number of ReadReq hits 1922system.cpu1.l2cache.ReadReq_hits::total 5711 # number of ReadReq hits 1923system.cpu1.l2cache.WritebackDirty_hits::writebacks 114339 # number of WritebackDirty hits 1924system.cpu1.l2cache.WritebackDirty_hits::total 114339 # number of WritebackDirty hits 1925system.cpu1.l2cache.WritebackClean_hits::writebacks 565289 # number of WritebackClean hits 1926system.cpu1.l2cache.WritebackClean_hits::total 565289 # number of WritebackClean hits 1927system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27869 # number of ReadExReq hits 1928system.cpu1.l2cache.ReadExReq_hits::total 27869 # number of ReadExReq hits 1929system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 482614 # number of ReadCleanReq hits 1930system.cpu1.l2cache.ReadCleanReq_hits::total 482614 # number of ReadCleanReq hits 1931system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98302 # number of ReadSharedReq hits 1932system.cpu1.l2cache.ReadSharedReq_hits::total 98302 # number of ReadSharedReq hits 1933system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3748 # number of demand (read+write) hits 1934system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1963 # number of demand (read+write) hits 1935system.cpu1.l2cache.demand_hits::cpu1.inst 482614 # number of demand (read+write) hits 1936system.cpu1.l2cache.demand_hits::cpu1.data 126171 # number of demand (read+write) hits 1937system.cpu1.l2cache.demand_hits::total 614496 # number of demand (read+write) hits 1938system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3748 # number of overall hits 1939system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1963 # number of overall hits 1940system.cpu1.l2cache.overall_hits::cpu1.inst 482614 # number of overall hits 1941system.cpu1.l2cache.overall_hits::cpu1.data 126171 # number of overall hits 1942system.cpu1.l2cache.overall_hits::total 614496 # number of overall hits 1943system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 433 # number of ReadReq misses 1944system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 316 # number of ReadReq misses 1945system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses 1946system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29344 # number of UpgradeReq misses 1947system.cpu1.l2cache.UpgradeReq_misses::total 29344 # number of UpgradeReq misses 1948system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23201 # number of SCUpgradeReq misses 1949system.cpu1.l2cache.SCUpgradeReq_misses::total 23201 # number of SCUpgradeReq misses 1950system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 1951system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1952system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34650 # number of ReadExReq misses 1953system.cpu1.l2cache.ReadExReq_misses::total 34650 # number of ReadExReq misses 1954system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21368 # number of ReadCleanReq misses 1955system.cpu1.l2cache.ReadCleanReq_misses::total 21368 # number of ReadCleanReq misses 1956system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69500 # number of ReadSharedReq misses 1957system.cpu1.l2cache.ReadSharedReq_misses::total 69500 # number of ReadSharedReq misses 1958system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 433 # number of demand (read+write) misses 1959system.cpu1.l2cache.demand_misses::cpu1.itb.walker 316 # number of demand (read+write) misses 1960system.cpu1.l2cache.demand_misses::cpu1.inst 21368 # number of demand (read+write) misses 1961system.cpu1.l2cache.demand_misses::cpu1.data 104150 # number of demand (read+write) misses 1962system.cpu1.l2cache.demand_misses::total 126267 # number of demand (read+write) misses 1963system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 433 # number of overall misses 1964system.cpu1.l2cache.overall_misses::cpu1.itb.walker 316 # number of overall misses 1965system.cpu1.l2cache.overall_misses::cpu1.inst 21368 # number of overall misses 1966system.cpu1.l2cache.overall_misses::cpu1.data 104150 # number of overall misses 1967system.cpu1.l2cache.overall_misses::total 126267 # number of overall misses 1968system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8916500 # number of ReadReq miss cycles 1969system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6346000 # number of ReadReq miss cycles 1970system.cpu1.l2cache.ReadReq_miss_latency::total 15262500 # number of ReadReq miss cycles 1971system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14232000 # number of UpgradeReq miss cycles 1972system.cpu1.l2cache.UpgradeReq_miss_latency::total 14232000 # number of UpgradeReq miss cycles 1973system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17729000 # number of SCUpgradeReq miss cycles 1974system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17729000 # number of SCUpgradeReq miss cycles 1975system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1919000 # number of SCUpgradeFailReq miss cycles 1976system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1919000 # number of SCUpgradeFailReq miss cycles 1977system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1493005000 # number of ReadExReq miss cycles 1978system.cpu1.l2cache.ReadExReq_miss_latency::total 1493005000 # number of ReadExReq miss cycles 1979system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 842821500 # number of ReadCleanReq miss cycles 1980system.cpu1.l2cache.ReadCleanReq_miss_latency::total 842821500 # number of ReadCleanReq miss cycles 1981system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1603059500 # number of ReadSharedReq miss cycles 1982system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1603059500 # number of ReadSharedReq miss cycles 1983system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8916500 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6346000 # number of demand (read+write) miss cycles 1985system.cpu1.l2cache.demand_miss_latency::cpu1.inst 842821500 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.demand_miss_latency::cpu1.data 3096064500 # number of demand (read+write) miss cycles 1987system.cpu1.l2cache.demand_miss_latency::total 3954148500 # number of demand (read+write) miss cycles 1988system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8916500 # number of overall miss cycles 1989system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6346000 # number of overall miss cycles 1990system.cpu1.l2cache.overall_miss_latency::cpu1.inst 842821500 # number of overall miss cycles 1991system.cpu1.l2cache.overall_miss_latency::cpu1.data 3096064500 # number of overall miss cycles 1992system.cpu1.l2cache.overall_miss_latency::total 3954148500 # number of overall miss cycles 1993system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4181 # number of ReadReq accesses(hits+misses) 1994system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2279 # number of ReadReq accesses(hits+misses) 1995system.cpu1.l2cache.ReadReq_accesses::total 6460 # number of ReadReq accesses(hits+misses) 1996system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114339 # number of WritebackDirty accesses(hits+misses) 1997system.cpu1.l2cache.WritebackDirty_accesses::total 114339 # number of WritebackDirty accesses(hits+misses) 1998system.cpu1.l2cache.WritebackClean_accesses::writebacks 565289 # number of WritebackClean accesses(hits+misses) 1999system.cpu1.l2cache.WritebackClean_accesses::total 565289 # number of WritebackClean accesses(hits+misses) 2000system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29344 # number of UpgradeReq accesses(hits+misses) 2001system.cpu1.l2cache.UpgradeReq_accesses::total 29344 # number of UpgradeReq accesses(hits+misses) 2002system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23201 # number of SCUpgradeReq accesses(hits+misses) 2003system.cpu1.l2cache.SCUpgradeReq_accesses::total 23201 # number of SCUpgradeReq accesses(hits+misses) 2004system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 2005system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 2006system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62519 # number of ReadExReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadExReq_accesses::total 62519 # number of ReadExReq accesses(hits+misses) 2008system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 503982 # number of ReadCleanReq accesses(hits+misses) 2009system.cpu1.l2cache.ReadCleanReq_accesses::total 503982 # number of ReadCleanReq accesses(hits+misses) 2010system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167802 # number of ReadSharedReq accesses(hits+misses) 2011system.cpu1.l2cache.ReadSharedReq_accesses::total 167802 # number of ReadSharedReq accesses(hits+misses) 2012system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4181 # number of demand (read+write) accesses 2013system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2279 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::cpu1.inst 503982 # number of demand (read+write) accesses 2015system.cpu1.l2cache.demand_accesses::cpu1.data 230321 # number of demand (read+write) accesses 2016system.cpu1.l2cache.demand_accesses::total 740763 # number of demand (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4181 # number of overall (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2279 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::cpu1.inst 503982 # number of overall (read+write) accesses 2020system.cpu1.l2cache.overall_accesses::cpu1.data 230321 # number of overall (read+write) accesses 2021system.cpu1.l2cache.overall_accesses::total 740763 # number of overall (read+write) accesses 2022system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for ReadReq accesses 2023system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138657 # miss rate for ReadReq accesses 2024system.cpu1.l2cache.ReadReq_miss_rate::total 0.115944 # miss rate for ReadReq accesses 2025system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2026system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2028system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2029system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2031system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554232 # miss rate for ReadExReq accesses 2032system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554232 # miss rate for ReadExReq accesses 2033system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042398 # miss rate for ReadCleanReq accesses 2034system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042398 # miss rate for ReadCleanReq accesses 2035system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414179 # miss rate for ReadSharedReq accesses 2036system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414179 # miss rate for ReadSharedReq accesses 2037system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for demand accesses 2038system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138657 # miss rate for demand accesses 2039system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042398 # miss rate for demand accesses 2040system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452195 # miss rate for demand accesses 2041system.cpu1.l2cache.demand_miss_rate::total 0.170455 # miss rate for demand accesses 2042system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for overall accesses 2043system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138657 # miss rate for overall accesses 2044system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042398 # miss rate for overall accesses 2045system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452195 # miss rate for overall accesses 2046system.cpu1.l2cache.overall_miss_rate::total 0.170455 # miss rate for overall accesses 2047system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average ReadReq miss latency 2048system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20082.278481 # average ReadReq miss latency 2049system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20377.169559 # average ReadReq miss latency 2050system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 485.005453 # average UpgradeReq miss latency 2051system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 485.005453 # average UpgradeReq miss latency 2052system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 764.148097 # average SCUpgradeReq miss latency 2053system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 764.148097 # average SCUpgradeReq miss latency 2054system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 319833.333333 # average SCUpgradeFailReq miss latency 2055system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 319833.333333 # average SCUpgradeFailReq miss latency 2056system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43088.167388 # average ReadExReq miss latency 2057system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43088.167388 # average ReadExReq miss latency 2058system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39443.162673 # average ReadCleanReq miss latency 2059system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39443.162673 # average ReadCleanReq miss latency 2060system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23065.604317 # average ReadSharedReq miss latency 2061system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23065.604317 # average ReadSharedReq miss latency 2062system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency 2063system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency 2064system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency 2065system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency 2066system.cpu1.l2cache.demand_avg_miss_latency::total 31315.771342 # average overall miss latency 2067system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency 2068system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency 2069system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency 2070system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency 2071system.cpu1.l2cache.overall_avg_miss_latency::total 31315.771342 # average overall miss latency 2072system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2073system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2074system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2075system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2076system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2077system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2078system.cpu1.l2cache.unused_prefetches 850 # number of HardPF blocks evicted w/o reference 2079system.cpu1.l2cache.writebacks::writebacks 33278 # number of writebacks 2080system.cpu1.l2cache.writebacks::total 33278 # number of writebacks 2081system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 91 # number of ReadExReq MSHR hits 2082system.cpu1.l2cache.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits 2083system.cpu1.l2cache.demand_mshr_hits::cpu1.data 91 # number of demand (read+write) MSHR hits 2084system.cpu1.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 2085system.cpu1.l2cache.overall_mshr_hits::cpu1.data 91 # number of overall MSHR hits 2086system.cpu1.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits 2087system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 433 # number of ReadReq MSHR misses 2088system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 316 # number of ReadReq MSHR misses 2089system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses 2090system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of HardPFReq MSHR misses 2091system.cpu1.l2cache.HardPFReq_mshr_misses::total 26693 # number of HardPFReq MSHR misses 2092system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29344 # number of UpgradeReq MSHR misses 2093system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29344 # number of UpgradeReq MSHR misses 2094system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23201 # number of SCUpgradeReq MSHR misses 2095system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23201 # number of SCUpgradeReq MSHR misses 2096system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 2097system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 2098system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34559 # number of ReadExReq MSHR misses 2099system.cpu1.l2cache.ReadExReq_mshr_misses::total 34559 # number of ReadExReq MSHR misses 2100system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21368 # number of ReadCleanReq MSHR misses 2101system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21368 # number of ReadCleanReq MSHR misses 2102system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69500 # number of ReadSharedReq MSHR misses 2103system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69500 # number of ReadSharedReq MSHR misses 2104system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 433 # number of demand (read+write) MSHR misses 2105system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 316 # number of demand (read+write) MSHR misses 2106system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21368 # number of demand (read+write) MSHR misses 2107system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104059 # number of demand (read+write) MSHR misses 2108system.cpu1.l2cache.demand_mshr_misses::total 126176 # number of demand (read+write) MSHR misses 2109system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 433 # number of overall MSHR misses 2110system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 316 # number of overall MSHR misses 2111system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21368 # number of overall MSHR misses 2112system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104059 # number of overall MSHR misses 2113system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of overall MSHR misses 2114system.cpu1.l2cache.overall_mshr_misses::total 152869 # number of overall MSHR misses 2115system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2116system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable 2117system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3254 # number of ReadReq MSHR uncacheable 2118system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable 2119system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable 2120system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2121system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses 2122system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5686 # number of overall MSHR uncacheable misses 2123system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of ReadReq MSHR miss cycles 2124system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4450000 # number of ReadReq MSHR miss cycles 2125system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10768500 # number of ReadReq MSHR miss cycles 2126system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of HardPFReq MSHR miss cycles 2127system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 957745966 # number of HardPFReq MSHR miss cycles 2128system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 449306000 # number of UpgradeReq MSHR miss cycles 2129system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 449306000 # number of UpgradeReq MSHR miss cycles 2130system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347204000 # number of SCUpgradeReq MSHR miss cycles 2131system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347204000 # number of SCUpgradeReq MSHR miss cycles 2132system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1637000 # number of SCUpgradeFailReq MSHR miss cycles 2133system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1637000 # number of SCUpgradeFailReq MSHR miss cycles 2134system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1274798000 # number of ReadExReq MSHR miss cycles 2135system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1274798000 # number of ReadExReq MSHR miss cycles 2136system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 714613500 # number of ReadCleanReq MSHR miss cycles 2137system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 714613500 # number of ReadCleanReq MSHR miss cycles 2138system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1186059500 # number of ReadSharedReq MSHR miss cycles 2139system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1186059500 # number of ReadSharedReq MSHR miss cycles 2140system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of demand (read+write) MSHR miss cycles 2141system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4450000 # number of demand (read+write) MSHR miss cycles 2142system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 714613500 # number of demand (read+write) MSHR miss cycles 2143system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2460857500 # number of demand (read+write) MSHR miss cycles 2144system.cpu1.l2cache.demand_mshr_miss_latency::total 3186239500 # number of demand (read+write) MSHR miss cycles 2145system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of overall MSHR miss cycles 2146system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4450000 # number of overall MSHR miss cycles 2147system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 714613500 # number of overall MSHR miss cycles 2148system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2460857500 # number of overall MSHR miss cycles 2149system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of overall MSHR miss cycles 2150system.cpu1.l2cache.overall_mshr_miss_latency::total 4143985466 # number of overall MSHR miss cycles 2151system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 # number of ReadReq MSHR uncacheable cycles 2152system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417705000 # number of ReadReq MSHR uncacheable cycles 2153system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433446000 # number of ReadReq MSHR uncacheable cycles 2154system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 # number of overall MSHR uncacheable cycles 2155system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417705000 # number of overall MSHR uncacheable cycles 2156system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433446000 # number of overall MSHR uncacheable cycles 2157system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for ReadReq accesses 2158system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for ReadReq accesses 2159system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115944 # mshr miss rate for ReadReq accesses 2160system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2161system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2162system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2163system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2164system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2165system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2166system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2167system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2168system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552776 # mshr miss rate for ReadExReq accesses 2169system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552776 # mshr miss rate for ReadExReq accesses 2170system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for ReadCleanReq accesses 2171system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042398 # mshr miss rate for ReadCleanReq accesses 2172system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414179 # mshr miss rate for ReadSharedReq accesses 2173system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414179 # mshr miss rate for ReadSharedReq accesses 2174system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for demand accesses 2175system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for demand accesses 2176system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for demand accesses 2177system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for demand accesses 2178system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170332 # mshr miss rate for demand accesses 2179system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for overall accesses 2180system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for overall accesses 2181system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for overall accesses 2182system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for overall accesses 2183system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2184system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206367 # mshr miss rate for overall accesses 2185system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average ReadReq mshr miss latency 2186system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average ReadReq mshr miss latency 2187system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14377.169559 # average ReadReq mshr miss latency 2188system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average HardPFReq mshr miss latency 2189system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35880.042183 # average HardPFReq mshr miss latency 2190system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15311.682116 # average UpgradeReq mshr miss latency 2191system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15311.682116 # average UpgradeReq mshr miss latency 2192system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.044610 # average SCUpgradeReq mshr miss latency 2193system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.044610 # average SCUpgradeReq mshr miss latency 2194system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 272833.333333 # average SCUpgradeFailReq mshr miss latency 2195system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 272833.333333 # average SCUpgradeFailReq mshr miss latency 2196system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36887.583553 # average ReadExReq mshr miss latency 2197system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36887.583553 # average ReadExReq mshr miss latency 2198system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average ReadCleanReq mshr miss latency 2199system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33443.162673 # average ReadCleanReq mshr miss latency 2200system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17065.604317 # average ReadSharedReq mshr miss latency 2201system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17065.604317 # average ReadSharedReq mshr miss latency 2202system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency 2203system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency 2204system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency 2205system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency 2206system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25252.341967 # average overall mshr miss latency 2207system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency 2208system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency 2209system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency 2210system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency 2211system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average overall mshr miss latency 2212system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27108.082515 # average overall mshr miss latency 2213system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency 2214system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135750.731232 # average ReadReq mshr uncacheable latency 2215system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133204.056546 # average ReadReq mshr uncacheable latency 2216system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency 2217system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75822.290797 # average overall mshr uncacheable latency 2218system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76230.390433 # average overall mshr uncacheable latency 2219system.cpu1.toL2Bus.snoop_filter.tot_requests 1483973 # Total number of requests made to the snoop filter. 2220system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749706 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2221system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2222system.cpu1.toL2Bus.snoop_filter.tot_snoops 112750 # Total number of snoops made to the snoop filter. 2223system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2224system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2225system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2226system.cpu1.toL2Bus.trans_dist::ReadReq 12645 # Transaction distribution 2227system.cpu1.toL2Bus.trans_dist::ReadResp 721727 # Transaction distribution 2228system.cpu1.toL2Bus.trans_dist::WriteReq 2432 # Transaction distribution 2229system.cpu1.toL2Bus.trans_dist::WriteResp 2432 # Transaction distribution 2230system.cpu1.toL2Bus.trans_dist::WritebackDirty 148874 # Transaction distribution 2231system.cpu1.toL2Bus.trans_dist::WritebackClean 576372 # Transaction distribution 2232system.cpu1.toL2Bus.trans_dist::CleanEvict 28336 # Transaction distribution 2233system.cpu1.toL2Bus.trans_dist::HardPFReq 31823 # Transaction distribution 2234system.cpu1.toL2Bus.trans_dist::UpgradeReq 70615 # Transaction distribution 2235system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40952 # Transaction distribution 2236system.cpu1.toL2Bus.trans_dist::UpgradeResp 85036 # Transaction distribution 2237system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution 2238system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution 2239system.cpu1.toL2Bus.trans_dist::ReadExReq 69693 # Transaction distribution 2240system.cpu1.toL2Bus.trans_dist::ReadExResp 67178 # Transaction distribution 2241system.cpu1.toL2Bus.trans_dist::ReadCleanReq 503982 # Transaction distribution 2242system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263487 # Transaction distribution 2243system.cpu1.toL2Bus.trans_dist::InvalidateReq 292 # Transaction distribution 2244system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511788 # Packet count per connected master and slave (bytes) 2245system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838524 # Packet count per connected master and slave (bytes) 2246system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5603 # Packet count per connected master and slave (bytes) 2247system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10248 # Packet count per connected master and slave (bytes) 2248system.cpu1.toL2Bus.pkt_count::total 2366163 # Packet count per connected master and slave (bytes) 2249system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64477636 # Cumulative packet size per connected master and slave (bytes) 2250system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29432570 # Cumulative packet size per connected master and slave (bytes) 2251system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9116 # Cumulative packet size per connected master and slave (bytes) 2252system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16724 # Cumulative packet size per connected master and slave (bytes) 2253system.cpu1.toL2Bus.pkt_size::total 93936046 # Cumulative packet size per connected master and slave (bytes) 2254system.cpu1.toL2Bus.snoops 334351 # Total snoops (count) 2255system.cpu1.toL2Bus.snoopTraffic 4909260 # Total snoop traffic (bytes) 2256system.cpu1.toL2Bus.snoop_fanout::samples 1058830 # Request fanout histogram 2257system.cpu1.toL2Bus.snoop_fanout::mean 0.130816 # Request fanout histogram 2258system.cpu1.toL2Bus.snoop_fanout::stdev 0.359612 # Request fanout histogram 2259system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2260system.cpu1.toL2Bus.snoop_fanout::0 928586 87.70% 87.70% # Request fanout histogram 2261system.cpu1.toL2Bus.snoop_fanout::1 121976 11.52% 99.22% # Request fanout histogram 2262system.cpu1.toL2Bus.snoop_fanout::2 8268 0.78% 100.00% # Request fanout histogram 2263system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2264system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2265system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2266system.cpu1.toL2Bus.snoop_fanout::total 1058830 # Request fanout histogram 2267system.cpu1.toL2Bus.reqLayer0.occupancy 1438248000 # Layer occupancy (ticks) 2268system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2269system.cpu1.toL2Bus.snoopLayer0.occupancy 79282585 # Layer occupancy (ticks) 2270system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2271system.cpu1.toL2Bus.respLayer0.occupancy 756150000 # Layer occupancy (ticks) 2272system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2273system.cpu1.toL2Bus.respLayer1.occupancy 376097000 # Layer occupancy (ticks) 2274system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2275system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2276system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2277system.cpu1.toL2Bus.respLayer3.occupancy 6067998 # Layer occupancy (ticks) 2278system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2279system.iobus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2280system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2281system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2282system.iobus.trans_dist::WriteReq 59423 # Transaction distribution 2283system.iobus.trans_dist::WriteResp 59423 # Transaction distribution 2284system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) 2285system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2287system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2288system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2289system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2290system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2291system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2292system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2293system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2294system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2298system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2299system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2300system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2301system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2302system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2303system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) 2304system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2305system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2306system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) 2307system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) 2308system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2310system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2311system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2312system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2313system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2314system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2315system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2316system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2317system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2321system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2322system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2323system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2324system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2325system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2326system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) 2327system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2328system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2329system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) 2330system.iobus.reqLayer0.occupancy 48604000 # Layer occupancy (ticks) 2331system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2332system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) 2333system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2334system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 2335system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2336system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) 2337system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2338system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) 2339system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2340system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) 2341system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2342system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks) 2343system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2344system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) 2345system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2346system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 2347system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2348system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 2349system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2350system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 2351system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer16.occupancy 46500 # Layer occupancy (ticks) 2353system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 2355system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) 2357system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2359system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2361system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) 2363system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer23.occupancy 6201500 # Layer occupancy (ticks) 2365system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer24.occupancy 32041500 # Layer occupancy (ticks) 2367system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer25.occupancy 187869528 # Layer occupancy (ticks) 2369system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2370system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) 2371system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2372system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2373system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2374system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2375system.iocache.tags.replacements 36445 # number of replacements 2376system.iocache.tags.tagsinuse 14.382505 # Cycle average of tags in use 2377system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2378system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2379system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2380system.iocache.tags.warmup_cycle 290037968000 # Cycle when the warmup percentage was hit. 2381system.iocache.tags.occ_blocks::realview.ide 14.382505 # Average occupied blocks per requestor 2382system.iocache.tags.occ_percent::realview.ide 0.898907 # Average percentage of cache occupancy 2383system.iocache.tags.occ_percent::total 0.898907 # Average percentage of cache occupancy 2384system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2385system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2386system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2387system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2388system.iocache.tags.data_accesses 328311 # Number of data accesses 2389system.iocache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2390system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2391system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2392system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2393system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2394system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2395system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2396system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2397system.iocache.overall_misses::total 36479 # number of overall misses 2398system.iocache.ReadReq_miss_latency::realview.ide 41042377 # number of ReadReq miss cycles 2399system.iocache.ReadReq_miss_latency::total 41042377 # number of ReadReq miss cycles 2400system.iocache.WriteLineReq_miss_latency::realview.ide 4379492151 # number of WriteLineReq miss cycles 2401system.iocache.WriteLineReq_miss_latency::total 4379492151 # number of WriteLineReq miss cycles 2402system.iocache.demand_miss_latency::realview.ide 4420534528 # number of demand (read+write) miss cycles 2403system.iocache.demand_miss_latency::total 4420534528 # number of demand (read+write) miss cycles 2404system.iocache.overall_miss_latency::realview.ide 4420534528 # number of overall miss cycles 2405system.iocache.overall_miss_latency::total 4420534528 # number of overall miss cycles 2406system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2407system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2408system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2409system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2410system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2411system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2412system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2413system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2414system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2415system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2416system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2417system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2418system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2419system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2420system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2421system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2422system.iocache.ReadReq_avg_miss_latency::realview.ide 160950.498039 # average ReadReq miss latency 2423system.iocache.ReadReq_avg_miss_latency::total 160950.498039 # average ReadReq miss latency 2424system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120900.291271 # average WriteLineReq miss latency 2425system.iocache.WriteLineReq_avg_miss_latency::total 120900.291271 # average WriteLineReq miss latency 2426system.iocache.demand_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency 2427system.iocache.demand_avg_miss_latency::total 121180.255161 # average overall miss latency 2428system.iocache.overall_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency 2429system.iocache.overall_avg_miss_latency::total 121180.255161 # average overall miss latency 2430system.iocache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked 2431system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2432system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked 2433system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2434system.iocache.avg_blocked_cycles::no_mshrs 33.111111 # average number of cycles each access was blocked 2435system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2436system.iocache.writebacks::writebacks 36190 # number of writebacks 2437system.iocache.writebacks::total 36190 # number of writebacks 2438system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2439system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2440system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2441system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2442system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2443system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2444system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2445system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2446system.iocache.ReadReq_mshr_miss_latency::realview.ide 28292377 # number of ReadReq MSHR miss cycles 2447system.iocache.ReadReq_mshr_miss_latency::total 28292377 # number of ReadReq MSHR miss cycles 2448system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2566405842 # number of WriteLineReq MSHR miss cycles 2449system.iocache.WriteLineReq_mshr_miss_latency::total 2566405842 # number of WriteLineReq MSHR miss cycles 2450system.iocache.demand_mshr_miss_latency::realview.ide 2594698219 # number of demand (read+write) MSHR miss cycles 2451system.iocache.demand_mshr_miss_latency::total 2594698219 # number of demand (read+write) MSHR miss cycles 2452system.iocache.overall_mshr_miss_latency::realview.ide 2594698219 # number of overall MSHR miss cycles 2453system.iocache.overall_mshr_miss_latency::total 2594698219 # number of overall MSHR miss cycles 2454system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2455system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2456system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2457system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2458system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2459system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2460system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2461system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2462system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110950.498039 # average ReadReq mshr miss latency 2463system.iocache.ReadReq_avg_mshr_miss_latency::total 110950.498039 # average ReadReq mshr miss latency 2464system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70848.217811 # average WriteLineReq mshr miss latency 2465system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70848.217811 # average WriteLineReq mshr miss latency 2466system.iocache.demand_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency 2467system.iocache.demand_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency 2468system.iocache.overall_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency 2469system.iocache.overall_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency 2470system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2471system.l2c.tags.replacements 137345 # number of replacements 2472system.l2c.tags.tagsinuse 65074.392349 # Cycle average of tags in use 2473system.l2c.tags.total_refs 526935 # Total number of references to valid blocks. 2474system.l2c.tags.sampled_refs 202695 # Sample count of references to valid blocks. 2475system.l2c.tags.avg_refs 2.599645 # Average number of references to valid blocks. 2476system.l2c.tags.warmup_cycle 103119965000 # Cycle when the warmup percentage was hit. 2477system.l2c.tags.occ_blocks::writebacks 6537.248776 # Average occupied blocks per requestor 2478system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009779 # Average occupied blocks per requestor 2479system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050987 # Average occupied blocks per requestor 2480system.l2c.tags.occ_blocks::cpu0.inst 7065.227850 # Average occupied blocks per requestor 2481system.l2c.tags.occ_blocks::cpu0.data 6920.254188 # Average occupied blocks per requestor 2482system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.581661 # Average occupied blocks per requestor 2483system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844 # Average occupied blocks per requestor 2484system.l2c.tags.occ_blocks::cpu1.inst 1513.426266 # Average occupied blocks per requestor 2485system.l2c.tags.occ_blocks::cpu1.data 3159.258777 # Average occupied blocks per requestor 2486system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2388.379223 # Average occupied blocks per requestor 2487system.l2c.tags.occ_percent::writebacks 0.099751 # Average percentage of cache occupancy 2488system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy 2489system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2490system.l2c.tags.occ_percent::cpu0.inst 0.107807 # Average percentage of cache occupancy 2491system.l2c.tags.occ_percent::cpu0.data 0.105595 # Average percentage of cache occupancy 2492system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571985 # Average percentage of cache occupancy 2493system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 2494system.l2c.tags.occ_percent::cpu1.inst 0.023093 # Average percentage of cache occupancy 2495system.l2c.tags.occ_percent::cpu1.data 0.048206 # Average percentage of cache occupancy 2496system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036444 # Average percentage of cache occupancy 2497system.l2c.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy 2498system.l2c.tags.occ_task_id_blocks::1022 34308 # Occupied blocks per task id 2499system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 2500system.l2c.tags.occ_task_id_blocks::1024 31034 # Occupied blocks per task id 2501system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2502system.l2c.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id 2503system.l2c.tags.age_task_id_blocks_1022::3 4715 # Occupied blocks per task id 2504system.l2c.tags.age_task_id_blocks_1022::4 29456 # Occupied blocks per task id 2505system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 2506system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2507system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 2508system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 2509system.l2c.tags.age_task_id_blocks_1024::3 1168 # Occupied blocks per task id 2510system.l2c.tags.age_task_id_blocks_1024::4 29797 # Occupied blocks per task id 2511system.l2c.tags.occ_task_id_percent::1022 0.523499 # Percentage of cache occupancy per task id 2512system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 2513system.l2c.tags.occ_task_id_percent::1024 0.473541 # Percentage of cache occupancy per task id 2514system.l2c.tags.tag_accesses 6118121 # Number of tag accesses 2515system.l2c.tags.data_accesses 6118121 # Number of data accesses 2516system.l2c.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2517system.l2c.WritebackDirty_hits::writebacks 260748 # number of WritebackDirty hits 2518system.l2c.WritebackDirty_hits::total 260748 # number of WritebackDirty hits 2519system.l2c.UpgradeReq_hits::cpu0.data 39886 # number of UpgradeReq hits 2520system.l2c.UpgradeReq_hits::cpu1.data 4893 # number of UpgradeReq hits 2521system.l2c.UpgradeReq_hits::total 44779 # number of UpgradeReq hits 2522system.l2c.SCUpgradeReq_hits::cpu0.data 2390 # number of SCUpgradeReq hits 2523system.l2c.SCUpgradeReq_hits::cpu1.data 2219 # number of SCUpgradeReq hits 2524system.l2c.SCUpgradeReq_hits::total 4609 # number of SCUpgradeReq hits 2525system.l2c.ReadExReq_hits::cpu0.data 3995 # number of ReadExReq hits 2526system.l2c.ReadExReq_hits::cpu1.data 1504 # number of ReadExReq hits 2527system.l2c.ReadExReq_hits::total 5499 # number of ReadExReq hits 2528system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 159 # number of ReadSharedReq hits 2529system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits 2530system.l2c.ReadSharedReq_hits::cpu0.inst 44649 # number of ReadSharedReq hits 2531system.l2c.ReadSharedReq_hits::cpu0.data 52745 # number of ReadSharedReq hits 2532system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45897 # number of ReadSharedReq hits 2533system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits 2534system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 # number of ReadSharedReq hits 2535system.l2c.ReadSharedReq_hits::cpu1.inst 18994 # number of ReadSharedReq hits 2536system.l2c.ReadSharedReq_hits::cpu1.data 11024 # number of ReadSharedReq hits 2537system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5470 # number of ReadSharedReq hits 2538system.l2c.ReadSharedReq_hits::total 179087 # number of ReadSharedReq hits 2539system.l2c.demand_hits::cpu0.dtb.walker 159 # number of demand (read+write) hits 2540system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits 2541system.l2c.demand_hits::cpu0.inst 44649 # number of demand (read+write) hits 2542system.l2c.demand_hits::cpu0.data 56740 # number of demand (read+write) hits 2543system.l2c.demand_hits::cpu0.l2cache.prefetcher 45897 # number of demand (read+write) hits 2544system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits 2545system.l2c.demand_hits::cpu1.itb.walker 28 # number of demand (read+write) hits 2546system.l2c.demand_hits::cpu1.inst 18994 # number of demand (read+write) hits 2547system.l2c.demand_hits::cpu1.data 12528 # number of demand (read+write) hits 2548system.l2c.demand_hits::cpu1.l2cache.prefetcher 5470 # number of demand (read+write) hits 2549system.l2c.demand_hits::total 184586 # number of demand (read+write) hits 2550system.l2c.overall_hits::cpu0.dtb.walker 159 # number of overall hits 2551system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits 2552system.l2c.overall_hits::cpu0.inst 44649 # number of overall hits 2553system.l2c.overall_hits::cpu0.data 56740 # number of overall hits 2554system.l2c.overall_hits::cpu0.l2cache.prefetcher 45897 # number of overall hits 2555system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits 2556system.l2c.overall_hits::cpu1.itb.walker 28 # number of overall hits 2557system.l2c.overall_hits::cpu1.inst 18994 # number of overall hits 2558system.l2c.overall_hits::cpu1.data 12528 # number of overall hits 2559system.l2c.overall_hits::cpu1.l2cache.prefetcher 5470 # number of overall hits 2560system.l2c.overall_hits::total 184586 # number of overall hits 2561system.l2c.UpgradeReq_misses::cpu0.data 631 # number of UpgradeReq misses 2562system.l2c.UpgradeReq_misses::cpu1.data 289 # number of UpgradeReq misses 2563system.l2c.UpgradeReq_misses::total 920 # number of UpgradeReq misses 2564system.l2c.SCUpgradeReq_misses::cpu0.data 83 # number of SCUpgradeReq misses 2565system.l2c.SCUpgradeReq_misses::cpu1.data 96 # number of SCUpgradeReq misses 2566system.l2c.SCUpgradeReq_misses::total 179 # number of SCUpgradeReq misses 2567system.l2c.ReadExReq_misses::cpu0.data 11301 # number of ReadExReq misses 2568system.l2c.ReadExReq_misses::cpu1.data 8030 # number of ReadExReq misses 2569system.l2c.ReadExReq_misses::total 19331 # number of ReadExReq misses 2570system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 2571system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2572system.l2c.ReadSharedReq_misses::cpu0.inst 17908 # number of ReadSharedReq misses 2573system.l2c.ReadSharedReq_misses::cpu0.data 9085 # number of ReadSharedReq misses 2574system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq misses 2575system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses 2576system.l2c.ReadSharedReq_misses::cpu1.inst 2374 # number of ReadSharedReq misses 2577system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses 2578system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq misses 2579system.l2c.ReadSharedReq_misses::total 170639 # number of ReadSharedReq misses 2580system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2581system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2582system.l2c.demand_misses::cpu0.inst 17908 # number of demand (read+write) misses 2583system.l2c.demand_misses::cpu0.data 20386 # number of demand (read+write) misses 2584system.l2c.demand_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) misses 2585system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 2586system.l2c.demand_misses::cpu1.inst 2374 # number of demand (read+write) misses 2587system.l2c.demand_misses::cpu1.data 8972 # number of demand (read+write) misses 2588system.l2c.demand_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) misses 2589system.l2c.demand_misses::total 189970 # number of demand (read+write) misses 2590system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2591system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2592system.l2c.overall_misses::cpu0.inst 17908 # number of overall misses 2593system.l2c.overall_misses::cpu0.data 20386 # number of overall misses 2594system.l2c.overall_misses::cpu0.l2cache.prefetcher 133844 # number of overall misses 2595system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 2596system.l2c.overall_misses::cpu1.inst 2374 # number of overall misses 2597system.l2c.overall_misses::cpu1.data 8972 # number of overall misses 2598system.l2c.overall_misses::cpu1.l2cache.prefetcher 6476 # number of overall misses 2599system.l2c.overall_misses::total 189970 # number of overall misses 2600system.l2c.UpgradeReq_miss_latency::cpu0.data 10365500 # number of UpgradeReq miss cycles 2601system.l2c.UpgradeReq_miss_latency::cpu1.data 935500 # number of UpgradeReq miss cycles 2602system.l2c.UpgradeReq_miss_latency::total 11301000 # number of UpgradeReq miss cycles 2603system.l2c.SCUpgradeReq_miss_latency::cpu0.data 563000 # number of SCUpgradeReq miss cycles 2604system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162500 # number of SCUpgradeReq miss cycles 2605system.l2c.SCUpgradeReq_miss_latency::total 725500 # number of SCUpgradeReq miss cycles 2606system.l2c.ReadExReq_miss_latency::cpu0.data 1654925500 # number of ReadExReq miss cycles 2607system.l2c.ReadExReq_miss_latency::cpu1.data 828235000 # number of ReadExReq miss cycles 2608system.l2c.ReadExReq_miss_latency::total 2483160500 # number of ReadExReq miss cycles 2609system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1167000 # number of ReadSharedReq miss cycles 2610system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 185500 # number of ReadSharedReq miss cycles 2611system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949681500 # number of ReadSharedReq miss cycles 2612system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106313500 # number of ReadSharedReq miss cycles 2613system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of ReadSharedReq miss cycles 2614system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 90000 # number of ReadSharedReq miss cycles 2615system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261013000 # number of ReadSharedReq miss cycles 2616system.l2c.ReadSharedReq_miss_latency::cpu1.data 123092000 # number of ReadSharedReq miss cycles 2617system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of ReadSharedReq miss cycles 2618system.l2c.ReadSharedReq_miss_latency::total 20215818501 # number of ReadSharedReq miss cycles 2619system.l2c.demand_miss_latency::cpu0.dtb.walker 1167000 # number of demand (read+write) miss cycles 2620system.l2c.demand_miss_latency::cpu0.itb.walker 185500 # number of demand (read+write) miss cycles 2621system.l2c.demand_miss_latency::cpu0.inst 1949681500 # number of demand (read+write) miss cycles 2622system.l2c.demand_miss_latency::cpu0.data 2761239000 # number of demand (read+write) miss cycles 2623system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of demand (read+write) miss cycles 2624system.l2c.demand_miss_latency::cpu1.dtb.walker 90000 # number of demand (read+write) miss cycles 2625system.l2c.demand_miss_latency::cpu1.inst 261013000 # number of demand (read+write) miss cycles 2626system.l2c.demand_miss_latency::cpu1.data 951327000 # number of demand (read+write) miss cycles 2627system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of demand (read+write) miss cycles 2628system.l2c.demand_miss_latency::total 22698979001 # number of demand (read+write) miss cycles 2629system.l2c.overall_miss_latency::cpu0.dtb.walker 1167000 # number of overall miss cycles 2630system.l2c.overall_miss_latency::cpu0.itb.walker 185500 # number of overall miss cycles 2631system.l2c.overall_miss_latency::cpu0.inst 1949681500 # number of overall miss cycles 2632system.l2c.overall_miss_latency::cpu0.data 2761239000 # number of overall miss cycles 2633system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of overall miss cycles 2634system.l2c.overall_miss_latency::cpu1.dtb.walker 90000 # number of overall miss cycles 2635system.l2c.overall_miss_latency::cpu1.inst 261013000 # number of overall miss cycles 2636system.l2c.overall_miss_latency::cpu1.data 951327000 # number of overall miss cycles 2637system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of overall miss cycles 2638system.l2c.overall_miss_latency::total 22698979001 # number of overall miss cycles 2639system.l2c.WritebackDirty_accesses::writebacks 260748 # number of WritebackDirty accesses(hits+misses) 2640system.l2c.WritebackDirty_accesses::total 260748 # number of WritebackDirty accesses(hits+misses) 2641system.l2c.UpgradeReq_accesses::cpu0.data 40517 # number of UpgradeReq accesses(hits+misses) 2642system.l2c.UpgradeReq_accesses::cpu1.data 5182 # number of UpgradeReq accesses(hits+misses) 2643system.l2c.UpgradeReq_accesses::total 45699 # number of UpgradeReq accesses(hits+misses) 2644system.l2c.SCUpgradeReq_accesses::cpu0.data 2473 # number of SCUpgradeReq accesses(hits+misses) 2645system.l2c.SCUpgradeReq_accesses::cpu1.data 2315 # number of SCUpgradeReq accesses(hits+misses) 2646system.l2c.SCUpgradeReq_accesses::total 4788 # number of SCUpgradeReq accesses(hits+misses) 2647system.l2c.ReadExReq_accesses::cpu0.data 15296 # number of ReadExReq accesses(hits+misses) 2648system.l2c.ReadExReq_accesses::cpu1.data 9534 # number of ReadExReq accesses(hits+misses) 2649system.l2c.ReadExReq_accesses::total 24830 # number of ReadExReq accesses(hits+misses) 2650system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 166 # number of ReadSharedReq accesses(hits+misses) 2651system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 77 # number of ReadSharedReq accesses(hits+misses) 2652system.l2c.ReadSharedReq_accesses::cpu0.inst 62557 # number of ReadSharedReq accesses(hits+misses) 2653system.l2c.ReadSharedReq_accesses::cpu0.data 61830 # number of ReadSharedReq accesses(hits+misses) 2654system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179741 # number of ReadSharedReq accesses(hits+misses) 2655system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 47 # number of ReadSharedReq accesses(hits+misses) 2656system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 28 # number of ReadSharedReq accesses(hits+misses) 2657system.l2c.ReadSharedReq_accesses::cpu1.inst 21368 # number of ReadSharedReq accesses(hits+misses) 2658system.l2c.ReadSharedReq_accesses::cpu1.data 11966 # number of ReadSharedReq accesses(hits+misses) 2659system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11946 # number of ReadSharedReq accesses(hits+misses) 2660system.l2c.ReadSharedReq_accesses::total 349726 # number of ReadSharedReq accesses(hits+misses) 2661system.l2c.demand_accesses::cpu0.dtb.walker 166 # number of demand (read+write) accesses 2662system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses 2663system.l2c.demand_accesses::cpu0.inst 62557 # number of demand (read+write) accesses 2664system.l2c.demand_accesses::cpu0.data 77126 # number of demand (read+write) accesses 2665system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179741 # number of demand (read+write) accesses 2666system.l2c.demand_accesses::cpu1.dtb.walker 47 # number of demand (read+write) accesses 2667system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses 2668system.l2c.demand_accesses::cpu1.inst 21368 # number of demand (read+write) accesses 2669system.l2c.demand_accesses::cpu1.data 21500 # number of demand (read+write) accesses 2670system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11946 # number of demand (read+write) accesses 2671system.l2c.demand_accesses::total 374556 # number of demand (read+write) accesses 2672system.l2c.overall_accesses::cpu0.dtb.walker 166 # number of overall (read+write) accesses 2673system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses 2674system.l2c.overall_accesses::cpu0.inst 62557 # number of overall (read+write) accesses 2675system.l2c.overall_accesses::cpu0.data 77126 # number of overall (read+write) accesses 2676system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179741 # number of overall (read+write) accesses 2677system.l2c.overall_accesses::cpu1.dtb.walker 47 # number of overall (read+write) accesses 2678system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses 2679system.l2c.overall_accesses::cpu1.inst 21368 # number of overall (read+write) accesses 2680system.l2c.overall_accesses::cpu1.data 21500 # number of overall (read+write) accesses 2681system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11946 # number of overall (read+write) accesses 2682system.l2c.overall_accesses::total 374556 # number of overall (read+write) accesses 2683system.l2c.UpgradeReq_miss_rate::cpu0.data 0.015574 # miss rate for UpgradeReq accesses 2684system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055770 # miss rate for UpgradeReq accesses 2685system.l2c.UpgradeReq_miss_rate::total 0.020132 # miss rate for UpgradeReq accesses 2686system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033562 # miss rate for SCUpgradeReq accesses 2687system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.041469 # miss rate for SCUpgradeReq accesses 2688system.l2c.SCUpgradeReq_miss_rate::total 0.037385 # miss rate for SCUpgradeReq accesses 2689system.l2c.ReadExReq_miss_rate::cpu0.data 0.738821 # miss rate for ReadExReq accesses 2690system.l2c.ReadExReq_miss_rate::cpu1.data 0.842249 # miss rate for ReadExReq accesses 2691system.l2c.ReadExReq_miss_rate::total 0.778534 # miss rate for ReadExReq accesses 2692system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for ReadSharedReq accesses 2693system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadSharedReq accesses 2694system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.286267 # miss rate for ReadSharedReq accesses 2695system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146935 # miss rate for ReadSharedReq accesses 2696system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for ReadSharedReq accesses 2697system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for ReadSharedReq accesses 2698system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111101 # miss rate for ReadSharedReq accesses 2699system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078723 # miss rate for ReadSharedReq accesses 2700system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for ReadSharedReq accesses 2701system.l2c.ReadSharedReq_miss_rate::total 0.487922 # miss rate for ReadSharedReq accesses 2702system.l2c.demand_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for demand accesses 2703system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses 2704system.l2c.demand_miss_rate::cpu0.inst 0.286267 # miss rate for demand accesses 2705system.l2c.demand_miss_rate::cpu0.data 0.264321 # miss rate for demand accesses 2706system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for demand accesses 2707system.l2c.demand_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for demand accesses 2708system.l2c.demand_miss_rate::cpu1.inst 0.111101 # miss rate for demand accesses 2709system.l2c.demand_miss_rate::cpu1.data 0.417302 # miss rate for demand accesses 2710system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for demand accesses 2711system.l2c.demand_miss_rate::total 0.507187 # miss rate for demand accesses 2712system.l2c.overall_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for overall accesses 2713system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses 2714system.l2c.overall_miss_rate::cpu0.inst 0.286267 # miss rate for overall accesses 2715system.l2c.overall_miss_rate::cpu0.data 0.264321 # miss rate for overall accesses 2716system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for overall accesses 2717system.l2c.overall_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for overall accesses 2718system.l2c.overall_miss_rate::cpu1.inst 0.111101 # miss rate for overall accesses 2719system.l2c.overall_miss_rate::cpu1.data 0.417302 # miss rate for overall accesses 2720system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for overall accesses 2721system.l2c.overall_miss_rate::total 0.507187 # miss rate for overall accesses 2722system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16427.099842 # average UpgradeReq miss latency 2723system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3237.024221 # average UpgradeReq miss latency 2724system.l2c.UpgradeReq_avg_miss_latency::total 12283.695652 # average UpgradeReq miss latency 2725system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6783.132530 # average SCUpgradeReq miss latency 2726system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1692.708333 # average SCUpgradeReq miss latency 2727system.l2c.SCUpgradeReq_avg_miss_latency::total 4053.072626 # average SCUpgradeReq miss latency 2728system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146440.624723 # average ReadExReq miss latency 2729system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103142.590286 # average ReadExReq miss latency 2730system.l2c.ReadExReq_avg_miss_latency::total 128454.839377 # average ReadExReq miss latency 2731system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average ReadSharedReq miss latency 2732system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92750 # average ReadSharedReq miss latency 2733system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 108872.096270 # average ReadSharedReq miss latency 2734system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121773.637865 # average ReadSharedReq miss latency 2735system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average ReadSharedReq miss latency 2736system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90000 # average ReadSharedReq miss latency 2737system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109946.503791 # average ReadSharedReq miss latency 2738system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130670.912951 # average ReadSharedReq miss latency 2739system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average ReadSharedReq miss latency 2740system.l2c.ReadSharedReq_avg_miss_latency::total 118471.266832 # average ReadSharedReq miss latency 2741system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency 2742system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency 2743system.l2c.demand_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency 2744system.l2c.demand_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency 2745system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency 2746system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency 2747system.l2c.demand_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency 2748system.l2c.demand_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency 2749system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency 2750system.l2c.demand_avg_miss_latency::total 119487.176928 # average overall miss latency 2751system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency 2752system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency 2753system.l2c.overall_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency 2754system.l2c.overall_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency 2755system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency 2756system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency 2757system.l2c.overall_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency 2758system.l2c.overall_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency 2759system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency 2760system.l2c.overall_avg_miss_latency::total 119487.176928 # average overall miss latency 2761system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2762system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2763system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2764system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2765system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2766system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2767system.l2c.writebacks::writebacks 100603 # number of writebacks 2768system.l2c.writebacks::total 100603 # number of writebacks 2769system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits 2770system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 # number of ReadSharedReq MSHR hits 2771system.l2c.ReadSharedReq_mshr_hits::total 10 # number of ReadSharedReq MSHR hits 2772system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 2773system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 2774system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits 2775system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 2776system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 2777system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits 2778system.l2c.CleanEvict_mshr_misses::writebacks 3738 # number of CleanEvict MSHR misses 2779system.l2c.CleanEvict_mshr_misses::total 3738 # number of CleanEvict MSHR misses 2780system.l2c.UpgradeReq_mshr_misses::cpu0.data 631 # number of UpgradeReq MSHR misses 2781system.l2c.UpgradeReq_mshr_misses::cpu1.data 289 # number of UpgradeReq MSHR misses 2782system.l2c.UpgradeReq_mshr_misses::total 920 # number of UpgradeReq MSHR misses 2783system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 83 # number of SCUpgradeReq MSHR misses 2784system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 96 # number of SCUpgradeReq MSHR misses 2785system.l2c.SCUpgradeReq_mshr_misses::total 179 # number of SCUpgradeReq MSHR misses 2786system.l2c.ReadExReq_mshr_misses::cpu0.data 11301 # number of ReadExReq MSHR misses 2787system.l2c.ReadExReq_mshr_misses::cpu1.data 8030 # number of ReadExReq MSHR misses 2788system.l2c.ReadExReq_mshr_misses::total 19331 # number of ReadExReq MSHR misses 2789system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses 2790system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2791system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17904 # number of ReadSharedReq MSHR misses 2792system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9085 # number of ReadSharedReq MSHR misses 2793system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq MSHR misses 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2194500 # number of SCUpgradeReq MSHR miss cycles 2836system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2340500 # number of SCUpgradeReq MSHR miss cycles 2837system.l2c.SCUpgradeReq_mshr_miss_latency::total 4535000 # number of SCUpgradeReq MSHR miss cycles 2838system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1541915500 # number of ReadExReq MSHR miss cycles 2839system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 747935000 # number of ReadExReq MSHR miss cycles 2840system.l2c.ReadExReq_mshr_miss_latency::total 2289850500 # number of ReadExReq MSHR miss cycles 2841system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of ReadSharedReq MSHR miss cycles 2842system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 165500 # number of ReadSharedReq MSHR miss cycles 2843system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770529000 # number of ReadSharedReq MSHR miss cycles 2844system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015463500 # number of ReadSharedReq MSHR miss cycles 2845system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of ReadSharedReq MSHR miss cycles 2846system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 80000 # number of ReadSharedReq MSHR miss cycles 2847system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 236880000 # number of ReadSharedReq MSHR miss cycles 2848system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 113671002 # number of ReadSharedReq MSHR miss cycles 2849system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of ReadSharedReq MSHR miss cycles 2850system.l2c.ReadSharedReq_mshr_miss_latency::total 18508956015 # number of ReadSharedReq MSHR miss cycles 2851system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of demand (read+write) MSHR miss cycles 2852system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165500 # number of demand (read+write) MSHR miss cycles 2853system.l2c.demand_mshr_miss_latency::cpu0.inst 1770529000 # number of demand (read+write) MSHR miss cycles 2854system.l2c.demand_mshr_miss_latency::cpu0.data 2557379000 # number of demand (read+write) MSHR miss cycles 2855system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of demand (read+write) MSHR miss cycles 2856system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 80000 # number of demand (read+write) MSHR miss cycles 2857system.l2c.demand_mshr_miss_latency::cpu1.inst 236880000 # number of demand (read+write) MSHR miss cycles 2858system.l2c.demand_mshr_miss_latency::cpu1.data 861606002 # number of demand (read+write) MSHR miss cycles 2859system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of demand (read+write) MSHR miss cycles 2860system.l2c.demand_mshr_miss_latency::total 20798806515 # number of demand (read+write) MSHR miss cycles 2861system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of overall MSHR miss cycles 2862system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165500 # number of overall MSHR miss cycles 2863system.l2c.overall_mshr_miss_latency::cpu0.inst 1770529000 # number of overall MSHR miss cycles 2864system.l2c.overall_mshr_miss_latency::cpu0.data 2557379000 # number of overall MSHR miss cycles 2865system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of overall MSHR miss cycles 2866system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 80000 # number of overall MSHR miss cycles 2867system.l2c.overall_mshr_miss_latency::cpu1.inst 236880000 # number of overall MSHR miss cycles 2868system.l2c.overall_mshr_miss_latency::cpu1.data 861606002 # number of overall MSHR miss cycles 2869system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of overall MSHR miss cycles 2870system.l2c.overall_mshr_miss_latency::total 20798806515 # number of overall MSHR miss cycles 2871system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles 2872system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5804773000 # number of ReadReq MSHR uncacheable cycles 2873system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 # number of ReadReq MSHR uncacheable cycles 2874system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362314500 # number of ReadReq MSHR uncacheable cycles 2875system.l2c.ReadReq_mshr_uncacheable_latency::total 6812886500 # number of ReadReq MSHR uncacheable cycles 2876system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles 2877system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5804773000 # number of overall MSHR uncacheable cycles 2878system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 # number of overall MSHR uncacheable cycles 2879system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362314500 # number of overall MSHR uncacheable cycles 2880system.l2c.overall_mshr_uncacheable_latency::total 6812886500 # number of overall MSHR uncacheable cycles 2881system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2882system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2883system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015574 # mshr miss rate for UpgradeReq accesses 2884system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055770 # mshr miss rate for UpgradeReq accesses 2885system.l2c.UpgradeReq_mshr_miss_rate::total 0.020132 # mshr miss rate for UpgradeReq accesses 2886system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033562 # mshr miss rate for SCUpgradeReq accesses 2887system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.041469 # mshr miss rate for SCUpgradeReq accesses 2888system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037385 # mshr miss rate for SCUpgradeReq accesses 2889system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.738821 # mshr miss rate for ReadExReq accesses 2890system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842249 # mshr miss rate for ReadExReq accesses 2891system.l2c.ReadExReq_mshr_miss_rate::total 0.778534 # mshr miss rate for ReadExReq accesses 2892system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for ReadSharedReq accesses 2893system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for ReadSharedReq accesses 2894system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for ReadSharedReq accesses 2895system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146935 # mshr miss rate for ReadSharedReq accesses 2896system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for ReadSharedReq accesses 2897system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses 2898system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for ReadSharedReq accesses 2899system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078723 # mshr miss rate for ReadSharedReq accesses 2900system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for ReadSharedReq accesses 2901system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487893 # mshr miss rate for ReadSharedReq accesses 2902system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for demand accesses 2903system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for demand accesses 2904system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for demand accesses 2905system.l2c.demand_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for demand accesses 2906system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for demand accesses 2907system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for demand accesses 2908system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for demand accesses 2909system.l2c.demand_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for demand accesses 2910system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for demand accesses 2911system.l2c.demand_mshr_miss_rate::total 0.507160 # mshr miss rate for demand accesses 2912system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for overall accesses 2913system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for overall accesses 2914system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for overall accesses 2915system.l2c.overall_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for overall accesses 2916system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for overall accesses 2917system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for overall accesses 2918system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for overall accesses 2919system.l2c.overall_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for overall accesses 2920system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for overall accesses 2921system.l2c.overall_mshr_miss_rate::total 0.507160 # mshr miss rate for overall accesses 2922system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23352.614897 # average UpgradeReq mshr miss latency 2923system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21818.339100 # average UpgradeReq mshr miss latency 2924system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22870.652174 # average UpgradeReq mshr miss latency 2925system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26439.759036 # average SCUpgradeReq mshr miss latency 2926system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24380.208333 # average SCUpgradeReq mshr miss latency 2927system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25335.195531 # average SCUpgradeReq mshr miss latency 2928system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136440.624723 # average ReadExReq mshr miss latency 2929system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93142.590286 # average ReadExReq mshr miss latency 2930system.l2c.ReadExReq_avg_mshr_miss_latency::total 118454.839377 # average ReadExReq mshr miss latency 2931system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average ReadSharedReq mshr miss latency 2932system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average ReadSharedReq mshr miss latency 2933system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average ReadSharedReq mshr miss latency 2934system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111773.637865 # average ReadSharedReq mshr miss latency 2935system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average ReadSharedReq mshr miss latency 2936system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average ReadSharedReq mshr miss latency 2937system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average ReadSharedReq mshr miss latency 2938system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120669.853503 # average ReadSharedReq mshr miss latency 2939system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average ReadSharedReq mshr miss latency 2940system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108474.854890 # average ReadSharedReq mshr miss latency 2941system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency 2942system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency 2943system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency 2944system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency 2945system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency 2946system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency 2947system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency 2948system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency 2949system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency 2950system.l2c.demand_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency 2951system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency 2952system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency 2953system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency 2954system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency 2955system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency 2956system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency 2957system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency 2958system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency 2959system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency 2960system.l2c.overall_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency 2961system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency 2962system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182723.904558 # average ReadReq mshr uncacheable latency 2963system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency 2964system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117864.183474 # average ReadReq mshr uncacheable latency 2965system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154694.182693 # average ReadReq mshr uncacheable latency 2966system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency 2967system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96402.381506 # average overall mshr uncacheable latency 2968system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency 2969system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65803.577915 # average overall mshr uncacheable latency 2970system.l2c.overall_avg_mshr_uncacheable_latency::total 90936.698301 # average overall mshr uncacheable latency 2971system.membus.snoop_filter.tot_requests 502698 # Total number of requests made to the snoop filter. 2972system.membus.snoop_filter.hit_single_requests 282285 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2973system.membus.snoop_filter.hit_multi_requests 634 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2974system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2975system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2976system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2977system.membus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 2978system.membus.trans_dist::ReadReq 44041 # Transaction distribution 2979system.membus.trans_dist::ReadResp 214925 # Transaction distribution 2980system.membus.trans_dist::WriteReq 30878 # Transaction distribution 2981system.membus.trans_dist::WriteResp 30878 # Transaction distribution 2982system.membus.trans_dist::WritebackDirty 136793 # Transaction distribution 2983system.membus.trans_dist::CleanEvict 16421 # Transaction distribution 2984system.membus.trans_dist::UpgradeReq 64440 # Transaction distribution 2985system.membus.trans_dist::SCUpgradeReq 38073 # Transaction distribution 2986system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 2987system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2988system.membus.trans_dist::ReadExReq 39751 # Transaction distribution 2989system.membus.trans_dist::ReadExResp 19302 # Transaction distribution 2990system.membus.trans_dist::ReadSharedReq 170884 # Transaction distribution 2991system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2992system.membus.trans_dist::InvalidateResp 4530 # Transaction distribution 2993system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 2994system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2995system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13584 # Packet count per connected master and slave (bytes) 2996system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647548 # Packet count per connected master and slave (bytes) 2997system.membus.pkt_count_system.l2c.mem_side::total 769084 # Packet count per connected master and slave (bytes) 2998system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) 2999system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) 3000system.membus.pkt_count::total 842023 # Packet count per connected master and slave (bytes) 3001system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) 3002system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 3003system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27168 # Cumulative packet size per connected master and slave (bytes) 3004system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18628620 # Cumulative packet size per connected master and slave (bytes) 3005system.membus.pkt_size_system.l2c.mem_side::total 18818654 # Cumulative packet size per connected master and slave (bytes) 3006system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 3007system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 3008system.membus.pkt_size::total 21135774 # Cumulative packet size per connected master and slave (bytes) 3009system.membus.snoops 126969 # Total snoops (count) 3010system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) 3011system.membus.snoop_fanout::samples 424292 # Request fanout histogram 3012system.membus.snoop_fanout::mean 0.012213 # Request fanout histogram 3013system.membus.snoop_fanout::stdev 0.109837 # Request fanout histogram 3014system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3015system.membus.snoop_fanout::0 419110 98.78% 98.78% # Request fanout histogram 3016system.membus.snoop_fanout::1 5182 1.22% 100.00% # Request fanout histogram 3017system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3018system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3019system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3020system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3021system.membus.snoop_fanout::total 424292 # Request fanout histogram 3022system.membus.reqLayer0.occupancy 88179000 # Layer occupancy (ticks) 3023system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3024system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 3025system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3026system.membus.reqLayer2.occupancy 11330000 # Layer occupancy (ticks) 3027system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3028system.membus.reqLayer5.occupancy 970733801 # Layer occupancy (ticks) 3029system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3030system.membus.respLayer2.occupancy 1113560532 # Layer occupancy (ticks) 3031system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3032system.membus.respLayer3.occupancy 7243389 # Layer occupancy (ticks) 3033system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3034system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3035system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3036system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3037system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3038system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3039system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3040system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3041system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3042system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3043system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3044system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3045system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3046system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3047system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3048system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3049system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3050system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3051system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3052system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3053system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3054system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3055system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3056system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3057system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3058system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3059system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3060system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3061system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3062system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3063system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3064system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3065system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3066system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3067system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3068system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3069system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3070system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3071system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3072system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3073system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3074system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3075system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3076system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3077system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3078system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3079system.realview.ethernet.droppedPackets 0 # number of packets dropped 3080system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3081system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3082system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3083system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3084system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3085system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3086system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3087system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3088system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3089system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3090system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3091system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3092system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3093system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3094system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3095system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3096system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3097system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3098system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3099system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3100system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3101system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3102system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3103system.toL2Bus.snoop_filter.tot_requests 1013922 # Total number of requests made to the snoop filter. 3104system.toL2Bus.snoop_filter.hit_single_requests 527446 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3105system.toL2Bus.snoop_filter.hit_multi_requests 187526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3106system.toL2Bus.snoop_filter.tot_snoops 29573 # Total number of snoops made to the snoop filter. 3107system.toL2Bus.snoop_filter.hit_single_snoops 28355 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3108system.toL2Bus.snoop_filter.hit_multi_snoops 1218 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3109system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states 3110system.toL2Bus.trans_dist::ReadReq 44044 # Transaction distribution 3111system.toL2Bus.trans_dist::ReadResp 511645 # Transaction distribution 3112system.toL2Bus.trans_dist::WriteReq 30878 # Transaction distribution 3113system.toL2Bus.trans_dist::WriteResp 30878 # Transaction distribution 3114system.toL2Bus.trans_dist::WritebackDirty 361351 # Transaction distribution 3115system.toL2Bus.trans_dist::CleanEvict 119836 # Transaction distribution 3116system.toL2Bus.trans_dist::UpgradeReq 109190 # Transaction distribution 3117system.toL2Bus.trans_dist::SCUpgradeReq 42682 # Transaction distribution 3118system.toL2Bus.trans_dist::UpgradeResp 151872 # Transaction distribution 3119system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution 3120system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution 3121system.toL2Bus.trans_dist::ReadExReq 50757 # Transaction distribution 3122system.toL2Bus.trans_dist::ReadExResp 50757 # Transaction distribution 3123system.toL2Bus.trans_dist::ReadSharedReq 467605 # Transaction distribution 3124system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution 3125system.toL2Bus.trans_dist::InvalidateResp 3427 # Transaction distribution 3126system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1275330 # Packet count per connected master and slave (bytes) 3127system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317115 # Packet count per connected master and slave (bytes) 3128system.toL2Bus.pkt_count::total 1592445 # Packet count per connected master and slave (bytes) 3129system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35259052 # Cumulative packet size per connected master and slave (bytes) 3130system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5662514 # Cumulative packet size per connected master and slave (bytes) 3131system.toL2Bus.pkt_size::total 40921566 # Cumulative packet size per connected master and slave (bytes) 3132system.toL2Bus.snoops 390876 # Total snoops (count) 3133system.toL2Bus.snoopTraffic 15646988 # Total snoop traffic (bytes) 3134system.toL2Bus.snoop_fanout::samples 887171 # Request fanout histogram 3135system.toL2Bus.snoop_fanout::mean 0.397282 # Request fanout histogram 3136system.toL2Bus.snoop_fanout::stdev 0.492133 # Request fanout histogram 3137system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3138system.toL2Bus.snoop_fanout::0 535932 60.41% 60.41% # Request fanout histogram 3139system.toL2Bus.snoop_fanout::1 350021 39.45% 99.86% # Request fanout histogram 3140system.toL2Bus.snoop_fanout::2 1218 0.14% 100.00% # Request fanout histogram 3141system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3142system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3143system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3144system.toL2Bus.snoop_fanout::total 887171 # Request fanout histogram 3145system.toL2Bus.reqLayer0.occupancy 894860010 # Layer occupancy (ticks) 3146system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3147system.toL2Bus.snoopLayer0.occupancy 2155585 # Layer occupancy (ticks) 3148system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3149system.toL2Bus.respLayer0.occupancy 676392933 # Layer occupancy (ticks) 3150system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3151system.toL2Bus.respLayer1.occupancy 238880542 # Layer occupancy (ticks) 3152system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)	3sim_seconds 2.871012 4sim_ticks 2871012355500 5final_tick 2871012355500 6sim_freq 1000000000000 7host_inst_rate 1070603 8host_op_rate 1294963 9host_tick_rate 23409963735 10host_mem_usage 628644 11host_seconds 122.64 12sim_insts 131299345 13sim_ops 158815094 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2871012355500 17system.physmem.bytes_read::cpu0.dtb.walker 448 18system.physmem.bytes_read::cpu0.itb.walker 128 19system.physmem.bytes_read::cpu0.inst 1181348 20system.physmem.bytes_read::cpu0.data 1294820 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8551616 22system.physmem.bytes_read::cpu1.dtb.walker 64 23system.physmem.bytes_read::cpu1.inst 152660 24system.physmem.bytes_read::cpu1.data 573908 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 413696 26system.physmem.bytes_read::realview.ide 960 27system.physmem.bytes_read::total 12169648 28system.physmem.bytes_inst_read::cpu0.inst 1181348 29system.physmem.bytes_inst_read::cpu1.inst 152660 30system.physmem.bytes_inst_read::total 1334008 31system.physmem.bytes_written::writebacks 8749184 32system.physmem.bytes_written::cpu0.data 17524 33system.physmem.bytes_written::cpu1.data 40 34system.physmem.bytes_written::total 8766748 35system.physmem.num_reads::cpu0.dtb.walker 7 36system.physmem.num_reads::cpu0.itb.walker 2 37system.physmem.num_reads::cpu0.inst 26912 38system.physmem.num_reads::cpu0.data 20751 39system.physmem.num_reads::cpu0.l2cache.prefetcher 133619 40system.physmem.num_reads::cpu1.dtb.walker 1 41system.physmem.num_reads::cpu1.inst 2540 42system.physmem.num_reads::cpu1.data 8988 43system.physmem.num_reads::cpu1.l2cache.prefetcher 6464 44system.physmem.num_reads::realview.ide 15 45system.physmem.num_reads::total 199299 46system.physmem.num_writes::writebacks 136706 47system.physmem.num_writes::cpu0.data 4381 48system.physmem.num_writes::cpu1.data 10 49system.physmem.num_writes::total 141097 50system.physmem.bw_read::cpu0.dtb.walker 156 51system.physmem.bw_read::cpu0.itb.walker 45 52system.physmem.bw_read::cpu0.inst 411474 53system.physmem.bw_read::cpu0.data 450998 54system.physmem.bw_read::cpu0.l2cache.prefetcher 2978606 55system.physmem.bw_read::cpu1.dtb.walker 22 56system.physmem.bw_read::cpu1.inst 53173 57system.physmem.bw_read::cpu1.data 199897 58system.physmem.bw_read::cpu1.l2cache.prefetcher 144094 59system.physmem.bw_read::realview.ide 334 60system.physmem.bw_read::total 4238800 61system.physmem.bw_inst_read::cpu0.inst 411474 62system.physmem.bw_inst_read::cpu1.inst 53173 63system.physmem.bw_inst_read::total 464647 64system.physmem.bw_write::writebacks 3047421 65system.physmem.bw_write::cpu0.data 6104 66system.physmem.bw_write::cpu1.data 14 67system.physmem.bw_write::total 3053539 68system.physmem.bw_total::writebacks 3047421 69system.physmem.bw_total::cpu0.dtb.walker 156 70system.physmem.bw_total::cpu0.itb.walker 45 71system.physmem.bw_total::cpu0.inst 411474 72system.physmem.bw_total::cpu0.data 457101 73system.physmem.bw_total::cpu0.l2cache.prefetcher 2978606 74system.physmem.bw_total::cpu1.dtb.walker 22 75system.physmem.bw_total::cpu1.inst 53173 76system.physmem.bw_total::cpu1.data 199911 77system.physmem.bw_total::cpu1.l2cache.prefetcher 144094 78system.physmem.bw_total::realview.ide 334 79system.physmem.bw_total::total 7292339 80system.physmem.readReqs 199299 81system.physmem.writeReqs 141097 82system.physmem.readBursts 199299 83system.physmem.writeBursts 141097 84system.physmem.bytesReadDRAM 12744832 85system.physmem.bytesReadWrQ 10304 86system.physmem.bytesWritten 8779712 87system.physmem.bytesReadSys 12169648 88system.physmem.bytesWrittenSys 8766748 89system.physmem.servicedByWrQ 161 90system.physmem.mergedWrBursts 3897 91system.physmem.neitherReadNorWriteReqs 0 92system.physmem.perBankRdBursts::0 11941 93system.physmem.perBankRdBursts::1 11941 94system.physmem.perBankRdBursts::2 12061 95system.physmem.perBankRdBursts::3 12014 96system.physmem.perBankRdBursts::4 20277 97system.physmem.perBankRdBursts::5 11993 98system.physmem.perBankRdBursts::6 12082 99system.physmem.perBankRdBursts::7 12163 100system.physmem.perBankRdBursts::8 12412 101system.physmem.perBankRdBursts::9 12768 102system.physmem.perBankRdBursts::10 11659 103system.physmem.perBankRdBursts::11 11203 104system.physmem.perBankRdBursts::12 11765 105system.physmem.perBankRdBursts::13 11689 106system.physmem.perBankRdBursts::14 11759 107system.physmem.perBankRdBursts::15 11411 108system.physmem.perBankWrBursts::0 8593 109system.physmem.perBankWrBursts::1 8809 110system.physmem.perBankWrBursts::2 8990 111system.physmem.perBankWrBursts::3 8736 112system.physmem.perBankWrBursts::4 8204 113system.physmem.perBankWrBursts::5 8547 114system.physmem.perBankWrBursts::6 8879 115system.physmem.perBankWrBursts::7 8644 116system.physmem.perBankWrBursts::8 8884 117system.physmem.perBankWrBursts::9 9196 118system.physmem.perBankWrBursts::10 8452 119system.physmem.perBankWrBursts::11 8329 120system.physmem.perBankWrBursts::12 8624 121system.physmem.perBankWrBursts::13 8076 122system.physmem.perBankWrBursts::14 8386 123system.physmem.perBankWrBursts::15 7834 124system.physmem.numRdRetry 0 125system.physmem.numWrRetry 79 126system.physmem.totGap 2871011323500 127system.physmem.readPktSize::0 0 128system.physmem.readPktSize::1 0 129system.physmem.readPktSize::2 9732 130system.physmem.readPktSize::3 28 131system.physmem.readPktSize::4 0 132system.physmem.readPktSize::5 0 133system.physmem.readPktSize::6 189539 134system.physmem.writePktSize::0 0 135system.physmem.writePktSize::1 0 136system.physmem.writePktSize::2 4391 137system.physmem.writePktSize::3 0 138system.physmem.writePktSize::4 0 139system.physmem.writePktSize::5 0 140system.physmem.writePktSize::6 136706 141system.physmem.rdQLenPdf::0 135966 142system.physmem.rdQLenPdf::1 17240 143system.physmem.rdQLenPdf::2 10602 144system.physmem.rdQLenPdf::3 8757 145system.physmem.rdQLenPdf::4 7338 146system.physmem.rdQLenPdf::5 5891 147system.physmem.rdQLenPdf::6 5065 148system.physmem.rdQLenPdf::7 4253 149system.physmem.rdQLenPdf::8 3715 150system.physmem.rdQLenPdf::9 134 151system.physmem.rdQLenPdf::10 84 152system.physmem.rdQLenPdf::11 52 153system.physmem.rdQLenPdf::12 25 154system.physmem.rdQLenPdf::13 7 155system.physmem.rdQLenPdf::14 3 156system.physmem.rdQLenPdf::15 2 157system.physmem.rdQLenPdf::16 2 158system.physmem.rdQLenPdf::17 2 159system.physmem.rdQLenPdf::18 0 160system.physmem.rdQLenPdf::19 0 161system.physmem.rdQLenPdf::20 0 162system.physmem.rdQLenPdf::21 0 163system.physmem.rdQLenPdf::22 0 164system.physmem.rdQLenPdf::23 0 165system.physmem.rdQLenPdf::24 0 166system.physmem.rdQLenPdf::25 0 167system.physmem.rdQLenPdf::26 0 168system.physmem.rdQLenPdf::27 0 169system.physmem.rdQLenPdf::28 0 170system.physmem.rdQLenPdf::29 0 171system.physmem.rdQLenPdf::30 0 172system.physmem.rdQLenPdf::31 0 173system.physmem.wrQLenPdf::0 1 174system.physmem.wrQLenPdf::1 1 175system.physmem.wrQLenPdf::2 1 176system.physmem.wrQLenPdf::3 1 177system.physmem.wrQLenPdf::4 1 178system.physmem.wrQLenPdf::5 1 179system.physmem.wrQLenPdf::6 1 180system.physmem.wrQLenPdf::7 1 181system.physmem.wrQLenPdf::8 1 182system.physmem.wrQLenPdf::9 1 183system.physmem.wrQLenPdf::10 1 184system.physmem.wrQLenPdf::11 1 185system.physmem.wrQLenPdf::12 1 186system.physmem.wrQLenPdf::13 1 187system.physmem.wrQLenPdf::14 1 188system.physmem.wrQLenPdf::15 2529 189system.physmem.wrQLenPdf::16 3481 190system.physmem.wrQLenPdf::17 4419 191system.physmem.wrQLenPdf::18 5391 192system.physmem.wrQLenPdf::19 6442 193system.physmem.wrQLenPdf::20 6509 194system.physmem.wrQLenPdf::21 7071 195system.physmem.wrQLenPdf::22 7524 196system.physmem.wrQLenPdf::23 8510 197system.physmem.wrQLenPdf::24 8349 198system.physmem.wrQLenPdf::25 9606 199system.physmem.wrQLenPdf::26 10061 200system.physmem.wrQLenPdf::27 8512 201system.physmem.wrQLenPdf::28 8112 202system.physmem.wrQLenPdf::29 8311 203system.physmem.wrQLenPdf::30 9404 204system.physmem.wrQLenPdf::31 7883 205system.physmem.wrQLenPdf::32 7638 206system.physmem.wrQLenPdf::33 727 207system.physmem.wrQLenPdf::34 448 208system.physmem.wrQLenPdf::35 388 209system.physmem.wrQLenPdf::36 335 210system.physmem.wrQLenPdf::37 256 211system.physmem.wrQLenPdf::38 272 212system.physmem.wrQLenPdf::39 265 213system.physmem.wrQLenPdf::40 225 214system.physmem.wrQLenPdf::41 178 215system.physmem.wrQLenPdf::42 199 216system.physmem.wrQLenPdf::43 179 217system.physmem.wrQLenPdf::44 202 218system.physmem.wrQLenPdf::45 241 219system.physmem.wrQLenPdf::46 234 220system.physmem.wrQLenPdf::47 176 221system.physmem.wrQLenPdf::48 183 222system.physmem.wrQLenPdf::49 185 223system.physmem.wrQLenPdf::50 199 224system.physmem.wrQLenPdf::51 165 225system.physmem.wrQLenPdf::52 205 226system.physmem.wrQLenPdf::53 189 227system.physmem.wrQLenPdf::54 159 228system.physmem.wrQLenPdf::55 158 229system.physmem.wrQLenPdf::56 255 230system.physmem.wrQLenPdf::57 220 231system.physmem.wrQLenPdf::58 143 232system.physmem.wrQLenPdf::59 244 233system.physmem.wrQLenPdf::60 209 234system.physmem.wrQLenPdf::61 180 235system.physmem.wrQLenPdf::62 157 236system.physmem.wrQLenPdf::63 257 237system.physmem.bytesPerActivate::samples 85488 238system.physmem.bytesPerActivate::mean 251.783642 239system.physmem.bytesPerActivate::gmean 143.209500 240system.physmem.bytesPerActivate::stdev 307.626161 241system.physmem.bytesPerActivate::0-127 42834 50.11% 50.11% 242system.physmem.bytesPerActivate::128-255 18033 21.09% 71.20% 243system.physmem.bytesPerActivate::256-383 6282 7.35% 78.55% 244system.physmem.bytesPerActivate::384-511 3726 4.36% 82.91% 245system.physmem.bytesPerActivate::512-639 2666 3.12% 86.02% 246system.physmem.bytesPerActivate::640-767 1646 1.93% 87.95% 247system.physmem.bytesPerActivate::768-895 883 1.03% 88.98% 248system.physmem.bytesPerActivate::896-1023 975 1.14% 90.12% 249system.physmem.bytesPerActivate::1024-1151 8443 9.88% 100.00% 250system.physmem.bytesPerActivate::total 85488 251system.physmem.rdPerTurnAround::samples 6782 252system.physmem.rdPerTurnAround::mean 29.362430 253system.physmem.rdPerTurnAround::stdev 565.225219 254system.physmem.rdPerTurnAround::0-2047 6780 99.97% 99.97% 255system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% 256system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% 257system.physmem.rdPerTurnAround::total 6782 258system.physmem.wrPerTurnAround::samples 6782 259system.physmem.wrPerTurnAround::mean 20.227514 260system.physmem.wrPerTurnAround::gmean 18.570606 261system.physmem.wrPerTurnAround::stdev 13.781277 262system.physmem.wrPerTurnAround::16-19 5756 84.87% 84.87% 263system.physmem.wrPerTurnAround::20-23 321 4.73% 89.60% 264system.physmem.wrPerTurnAround::24-27 54 0.80% 90.40% 265system.physmem.wrPerTurnAround::28-31 63 0.93% 91.33% 266system.physmem.wrPerTurnAround::32-35 275 4.05% 95.38% 267system.physmem.wrPerTurnAround::36-39 22 0.32% 95.71% 268system.physmem.wrPerTurnAround::40-43 19 0.28% 95.99% 269system.physmem.wrPerTurnAround::44-47 12 0.18% 96.17% 270system.physmem.wrPerTurnAround::48-51 17 0.25% 96.42% 271system.physmem.wrPerTurnAround::52-55 2 0.03% 96.45% 272system.physmem.wrPerTurnAround::56-59 1 0.01% 96.46% 273system.physmem.wrPerTurnAround::60-63 11 0.16% 96.62% 274system.physmem.wrPerTurnAround::64-67 152 2.24% 98.86% 275system.physmem.wrPerTurnAround::68-71 7 0.10% 98.97% 276system.physmem.wrPerTurnAround::72-75 10 0.15% 99.12% 277system.physmem.wrPerTurnAround::76-79 5 0.07% 99.19% 278system.physmem.wrPerTurnAround::80-83 2 0.03% 99.22% 279system.physmem.wrPerTurnAround::84-87 1 0.01% 99.23% 280system.physmem.wrPerTurnAround::88-91 1 0.01% 99.25% 281system.physmem.wrPerTurnAround::92-95 2 0.03% 99.28% 282system.physmem.wrPerTurnAround::96-99 3 0.04% 99.32% 283system.physmem.wrPerTurnAround::100-103 2 0.03% 99.35% 284system.physmem.wrPerTurnAround::104-107 1 0.01% 99.37% 285system.physmem.wrPerTurnAround::108-111 5 0.07% 99.44% 286system.physmem.wrPerTurnAround::112-115 2 0.03% 99.47% 287system.physmem.wrPerTurnAround::120-123 1 0.01% 99.48% 288system.physmem.wrPerTurnAround::124-127 2 0.03% 99.51% 289system.physmem.wrPerTurnAround::128-131 8 0.12% 99.63% 290system.physmem.wrPerTurnAround::132-135 3 0.04% 99.68% 291system.physmem.wrPerTurnAround::136-139 5 0.07% 99.75% 292system.physmem.wrPerTurnAround::144-147 2 0.03% 99.78% 293system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% 294system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% 295system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% 296system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% 297system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% 298system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% 299system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% 300system.physmem.wrPerTurnAround::total 6782 301system.physmem.totQLat 9440334255 302system.physmem.totMemAccLat 13174171755 303system.physmem.totBusLat 995690000 304system.physmem.avgQLat 47405.99 305system.physmem.avgBusLat 5000.00 306system.physmem.avgMemAccLat 66155.99 307system.physmem.avgRdBW 4.44 308system.physmem.avgWrBW 3.06 309system.physmem.avgRdBWSys 4.24 310system.physmem.avgWrBWSys 3.05 311system.physmem.peakBW 12800.00 312system.physmem.busUtil 0.06 313system.physmem.busUtilRead 0.03 314system.physmem.busUtilWrite 0.02 315system.physmem.avgRdQLen 1.05 316system.physmem.avgWrQLen 22.72 317system.physmem.readRowHits 166173 318system.physmem.writeRowHits 84659 319system.physmem.readRowHitRate 83.45 320system.physmem.writeRowHitRate 61.70 321system.physmem.avgGap 8434327.44 322system.physmem.pageHitRate 74.58 323system.physmem_0.actEnergy 308819280 324system.physmem_0.preEnergy 164137545 325system.physmem_0.readEnergy 745930080 326system.physmem_0.writeEnergy 362278440 327system.physmem_0.refreshEnergy 6150087840.000001 328system.physmem_0.actBackEnergy 5622831690 329system.physmem_0.preBackEnergy 364043040 330system.physmem_0.actPowerDownEnergy 11524806630 331system.physmem_0.prePowerDownEnergy 9158295840 332system.physmem_0.selfRefreshEnergy 675248492655 333system.physmem_0.totalEnergy 709652557290 334system.physmem_0.averagePower 247.178510 335system.physmem_0.totalIdleTime 2857727193718 336system.physmem_0.memoryStateTime::IDLE 674787943 337system.physmem_0.memoryStateTime::REF 2614676000 338system.physmem_0.memoryStateTime::SREF 2808603815500 339system.physmem_0.memoryStateTime::PRE_PDN 23849720592 340system.physmem_0.memoryStateTime::ACT 9995633339 341system.physmem_0.memoryStateTime::ACT_PDN 25273722126 342system.physmem_1.actEnergy 301572180 343system.physmem_1.preEnergy 160289415 344system.physmem_1.readEnergy 675915240 345system.physmem_1.writeEnergy 353816820 346system.physmem_1.refreshEnergy 6255191280.000001 347system.physmem_1.actBackEnergy 5736132870 348system.physmem_1.preBackEnergy 359474400 349system.physmem_1.actPowerDownEnergy 11377384680 350system.physmem_1.prePowerDownEnergy 9560351520 351system.physmem_1.selfRefreshEnergy 675046333020 352system.physmem_1.totalEnergy 709829884665 353system.physmem_1.averagePower 247.240275 354system.physmem_1.totalIdleTime 2857311193722 355system.physmem_1.memoryStateTime::IDLE 664285239 356system.physmem_1.memoryStateTime::REF 2659412000 357system.physmem_1.memoryStateTime::SREF 2807642220500 358system.physmem_1.memoryStateTime::PRE_PDN 24896771092 359system.physmem_1.memoryStateTime::ACT 10199382539 360system.physmem_1.memoryStateTime::ACT_PDN 24950284130 361system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2871012355500 362system.realview.nvmem.bytes_read::cpu0.inst 20 363system.realview.nvmem.bytes_read::cpu1.inst 48 364system.realview.nvmem.bytes_read::total 68 365system.realview.nvmem.bytes_inst_read::cpu0.inst 20 366system.realview.nvmem.bytes_inst_read::cpu1.inst 48 367system.realview.nvmem.bytes_inst_read::total 68 368system.realview.nvmem.num_reads::cpu0.inst 5 369system.realview.nvmem.num_reads::cpu1.inst 12 370system.realview.nvmem.num_reads::total 17 371system.realview.nvmem.bw_read::cpu0.inst 7 372system.realview.nvmem.bw_read::cpu1.inst 17 373system.realview.nvmem.bw_read::total 24 374system.realview.nvmem.bw_inst_read::cpu0.inst 7 375system.realview.nvmem.bw_inst_read::cpu1.inst 17 376system.realview.nvmem.bw_inst_read::total 24 377system.realview.nvmem.bw_total::cpu0.inst 7 378system.realview.nvmem.bw_total::cpu1.inst 17 379system.realview.nvmem.bw_total::total 24 380system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2871012355500 381system.pwrStateResidencyTicks::UNDEFINED 2871012355500 382system.bridge.pwrStateResidencyTicks::UNDEFINED 2871012355500 383system.cf0.dma_read_full_pages 0 384system.cf0.dma_read_bytes 1024 385system.cf0.dma_read_txs 1 386system.cf0.dma_write_full_pages 540 387system.cf0.dma_write_bytes 2318336 388system.cf0.dma_write_txs 631 389system.cpu_clk_domain.clock 500 390system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 399system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 400system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 401system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 402system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 403system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 404system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 409system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 410system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 411system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 420system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 421system.cpu0.dtb.walker.walks 7823 422system.cpu0.dtb.walker.walksShort 7823 423system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1470 424system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6353 425system.cpu0.dtb.walker.walkWaitTime::samples 7823 426system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% 427system.cpu0.dtb.walker.walkWaitTime::total 7823 428system.cpu0.dtb.walker.walkCompletionTime::samples 6429 429system.cpu0.dtb.walker.walkCompletionTime::mean 12399.906673 430system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.406906 431system.cpu0.dtb.walker.walkCompletionTime::stdev 6039.827624 432system.cpu0.dtb.walker.walkCompletionTime::0-16383 5900 91.77% 91.77% 433system.cpu0.dtb.walker.walkCompletionTime::16384-32767 462 7.19% 98.96% 434system.cpu0.dtb.walker.walkCompletionTime::32768-49151 57 0.89% 99.84% 435system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.08% 99.92% 436system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% 437system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% 438system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% 439system.cpu0.dtb.walker.walkCompletionTime::total 6429 440system.cpu0.dtb.walker.walksPending::samples 1181300000 441system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% 442system.cpu0.dtb.walker.walksPending::total 1181300000 443system.cpu0.dtb.walker.walkPageSizes::4K 4998 77.74% 77.74% 444system.cpu0.dtb.walker.walkPageSizes::1M 1431 22.26% 100.00% 445system.cpu0.dtb.walker.walkPageSizes::total 6429 446system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 447system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 448system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 449system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 450system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 451system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 452system.cpu0.dtb.walker.walkRequestOrigin::total 14252 453system.cpu0.dtb.inst_hits 0 454system.cpu0.dtb.inst_misses 0 455system.cpu0.dtb.read_hits 25079832 456system.cpu0.dtb.read_misses 6706 457system.cpu0.dtb.write_hits 18692115 458system.cpu0.dtb.write_misses 1117 459system.cpu0.dtb.flush_tlb 66 460system.cpu0.dtb.flush_tlb_mva 917 461system.cpu0.dtb.flush_tlb_mva_asid 0 462system.cpu0.dtb.flush_tlb_asid 0 463system.cpu0.dtb.flush_entries 3388 464system.cpu0.dtb.align_faults 0 465system.cpu0.dtb.prefetch_faults 1745 466system.cpu0.dtb.domain_faults 0 467system.cpu0.dtb.perms_faults 282 468system.cpu0.dtb.read_accesses 25086538 469system.cpu0.dtb.write_accesses 18693232 470system.cpu0.dtb.inst_accesses 0 471system.cpu0.dtb.hits 43771947 472system.cpu0.dtb.misses 7823 473system.cpu0.dtb.accesses 43779770 474system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 475system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 483system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 484system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 485system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 486system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 487system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 488system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 492system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 493system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 494system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 495system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 496system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 497system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 498system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 499system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 500system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 501system.cpu0.istage2_mmu.stage2_tlb.hits 0 502system.cpu0.istage2_mmu.stage2_tlb.misses 0 503system.cpu0.istage2_mmu.stage2_tlb.accesses 0 504system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 505system.cpu0.itb.walker.walks 3349 506system.cpu0.itb.walker.walksShort 3349 507system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 508system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 509system.cpu0.itb.walker.walkWaitTime::samples 3349 510system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% 511system.cpu0.itb.walker.walkWaitTime::total 3349 512system.cpu0.itb.walker.walkCompletionTime::samples 2333 513system.cpu0.itb.walker.walkCompletionTime::mean 13009.858551 514system.cpu0.itb.walker.walkCompletionTime::gmean 12064.182996 515system.cpu0.itb.walker.walkCompletionTime::stdev 6171.150068 516system.cpu0.itb.walker.walkCompletionTime::0-8191 364 15.60% 15.60% 517system.cpu0.itb.walker.walkCompletionTime::8192-16383 1659 71.11% 86.71% 518system.cpu0.itb.walker.walkCompletionTime::16384-24575 218 9.34% 96.06% 519system.cpu0.itb.walker.walkCompletionTime::24576-32767 44 1.89% 97.94% 520system.cpu0.itb.walker.walkCompletionTime::32768-40959 45 1.93% 99.87% 521system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% 522system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% 523system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% 524system.cpu0.itb.walker.walkCompletionTime::total 2333 525system.cpu0.itb.walker.walksPending::samples 1180899500 526system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% 527system.cpu0.itb.walker.walksPending::total 1180899500 528system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% 529system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% 530system.cpu0.itb.walker.walkPageSizes::total 2333 531system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 532system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 533system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 534system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 535system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 536system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 537system.cpu0.itb.walker.walkRequestOrigin::total 5682 538system.cpu0.itb.inst_hits 118651077 539system.cpu0.itb.inst_misses 3349 540system.cpu0.itb.read_hits 0 541system.cpu0.itb.read_misses 0 542system.cpu0.itb.write_hits 0 543system.cpu0.itb.write_misses 0 544system.cpu0.itb.flush_tlb 66 545system.cpu0.itb.flush_tlb_mva 917 546system.cpu0.itb.flush_tlb_mva_asid 0 547system.cpu0.itb.flush_tlb_asid 0 548system.cpu0.itb.flush_entries 2087 549system.cpu0.itb.align_faults 0 550system.cpu0.itb.prefetch_faults 0 551system.cpu0.itb.domain_faults 0 552system.cpu0.itb.perms_faults 0 553system.cpu0.itb.read_accesses 0 554system.cpu0.itb.write_accesses 0 555system.cpu0.itb.inst_accesses 118654426 556system.cpu0.itb.hits 118651077 557system.cpu0.itb.misses 3349 558system.cpu0.itb.accesses 118654426 559system.cpu0.numPwrStateTransitions 3724 560system.cpu0.pwrStateClkGateDist::samples 1862 561system.cpu0.pwrStateClkGateDist::mean 1466914321.975295 562system.cpu0.pwrStateClkGateDist::stdev 23730695905.598595 563system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% 564system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% 565system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% 566system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% 567system.cpu0.pwrStateClkGateDist::min_value 501 568system.cpu0.pwrStateClkGateDist::max_value 499964525704 569system.cpu0.pwrStateClkGateDist::total 1862 570system.cpu0.pwrStateResidencyTicks::ON 139617887982 571system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731394467518 572system.cpu0.numCycles 5742024711 573system.cpu0.numWorkItemsStarted 0 574system.cpu0.numWorkItemsCompleted 0 575system.cpu0.kern.inst.arm 0 576system.cpu0.kern.inst.quiesce 1862 577system.cpu0.committedInsts 114989095 578system.cpu0.committedOps 138953395 579system.cpu0.num_int_alu_accesses 122990229 580system.cpu0.num_fp_alu_accesses 9755 581system.cpu0.num_func_calls 12658538 582system.cpu0.num_conditional_control_insts 15642727 583system.cpu0.num_int_insts 122990229 584system.cpu0.num_fp_insts 9755 585system.cpu0.num_int_register_reads 226428267 586system.cpu0.num_int_register_writes 85458801 587system.cpu0.num_fp_register_reads 7495 588system.cpu0.num_fp_register_writes 2264 589system.cpu0.num_cc_register_reads 503412465 590system.cpu0.num_cc_register_writes 52088929 591system.cpu0.num_mem_refs 44904529 592system.cpu0.num_load_insts 25328869 593system.cpu0.num_store_insts 19575660 594system.cpu0.num_idle_cycles 5462788935.034097 595system.cpu0.num_busy_cycles 279235775.965903 596system.cpu0.not_idle_fraction 0.048630 597system.cpu0.idle_fraction 0.951370 598system.cpu0.Branches 29038037 599system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% 600system.cpu0.op_class::IntAlu 97689121 68.45% 68.45% 601system.cpu0.op_class::IntMult 108461 0.08% 68.53% 602system.cpu0.op_class::IntDiv 0 0.00% 68.53% 603system.cpu0.op_class::FloatAdd 0 0.00% 68.53% 604system.cpu0.op_class::FloatCmp 0 0.00% 68.53% 605system.cpu0.op_class::FloatCvt 0 0.00% 68.53% 606system.cpu0.op_class::FloatMult 0 0.00% 68.53% 607system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% 608system.cpu0.op_class::FloatDiv 0 0.00% 68.53% 609system.cpu0.op_class::FloatMisc 0 0.00% 68.53% 610system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% 611system.cpu0.op_class::SimdAdd 0 0.00% 68.53% 612system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% 613system.cpu0.op_class::SimdAlu 0 0.00% 68.53% 614system.cpu0.op_class::SimdCmp 0 0.00% 68.53% 615system.cpu0.op_class::SimdCvt 0 0.00% 68.53% 616system.cpu0.op_class::SimdMisc 0 0.00% 68.53% 617system.cpu0.op_class::SimdMult 0 0.00% 68.53% 618system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% 619system.cpu0.op_class::SimdShift 0 0.00% 68.53% 620system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% 621system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% 622system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% 623system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% 624system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% 625system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% 626system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% 627system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% 628system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% 629system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% 630system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% 631system.cpu0.op_class::MemRead 25326613 17.75% 86.28% 632system.cpu0.op_class::MemWrite 19568165 13.71% 99.99% 633system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% 634system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% 635system.cpu0.op_class::IprAccess 0 0.00% 100.00% 636system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% 637system.cpu0.op_class::total 142712375 638system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 639system.cpu0.dcache.tags.replacements 689805 640system.cpu0.dcache.tags.tagsinuse 498.372694 641system.cpu0.dcache.tags.total_refs 42903858 642system.cpu0.dcache.tags.sampled_refs 690317 643system.cpu0.dcache.tags.avg_refs 62.150951 644system.cpu0.dcache.tags.warmup_cycle 1207348000 645system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.372694 646system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973384 647system.cpu0.dcache.tags.occ_percent::total 0.973384 648system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 649system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 650system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 651system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 652system.cpu0.dcache.tags.occ_task_id_percent::1024 1 653system.cpu0.dcache.tags.tag_accesses 88178135 654system.cpu0.dcache.tags.data_accesses 88178135 655system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2871012355500 656system.cpu0.dcache.ReadReq_hits::cpu0.data 23822310 657system.cpu0.dcache.ReadReq_hits::total 23822310 658system.cpu0.dcache.WriteReq_hits::cpu0.data 17962514 659system.cpu0.dcache.WriteReq_hits::total 17962514 660system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318853 661system.cpu0.dcache.SoftPFReq_hits::total 318853 662system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364520 663system.cpu0.dcache.LoadLockedReq_hits::total 364520 664system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361475 665system.cpu0.dcache.StoreCondReq_hits::total 361475 666system.cpu0.dcache.demand_hits::cpu0.data 41784824 667system.cpu0.dcache.demand_hits::total 41784824 668system.cpu0.dcache.overall_hits::cpu0.data 42103677 669system.cpu0.dcache.overall_hits::total 42103677 670system.cpu0.dcache.ReadReq_misses::cpu0.data 394535 671system.cpu0.dcache.ReadReq_misses::total 394535 672system.cpu0.dcache.WriteReq_misses::cpu0.data 324202 673system.cpu0.dcache.WriteReq_misses::total 324202 674system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126994 675system.cpu0.dcache.SoftPFReq_misses::total 126994 676system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21422 677system.cpu0.dcache.LoadLockedReq_misses::total 21422 678system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19571 679system.cpu0.dcache.StoreCondReq_misses::total 19571 680system.cpu0.dcache.demand_misses::cpu0.data 718737 681system.cpu0.dcache.demand_misses::total 718737 682system.cpu0.dcache.overall_misses::cpu0.data 845731 683system.cpu0.dcache.overall_misses::total 845731 684system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5513220000 685system.cpu0.dcache.ReadReq_miss_latency::total 5513220000 686system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6311049000 687system.cpu0.dcache.WriteReq_miss_latency::total 6311049000 688system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337488500 689system.cpu0.dcache.LoadLockedReq_miss_latency::total 337488500 690system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459190500 691system.cpu0.dcache.StoreCondReq_miss_latency::total 459190500 692system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1100000 693system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1100000 694system.cpu0.dcache.demand_miss_latency::cpu0.data 11824269000 695system.cpu0.dcache.demand_miss_latency::total 11824269000 696system.cpu0.dcache.overall_miss_latency::cpu0.data 11824269000 697system.cpu0.dcache.overall_miss_latency::total 11824269000 698system.cpu0.dcache.ReadReq_accesses::cpu0.data 24216845 699system.cpu0.dcache.ReadReq_accesses::total 24216845 700system.cpu0.dcache.WriteReq_accesses::cpu0.data 18286716 701system.cpu0.dcache.WriteReq_accesses::total 18286716 702system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445847 703system.cpu0.dcache.SoftPFReq_accesses::total 445847 704system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385942 705system.cpu0.dcache.LoadLockedReq_accesses::total 385942 706system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381046 707system.cpu0.dcache.StoreCondReq_accesses::total 381046 708system.cpu0.dcache.demand_accesses::cpu0.data 42503561 709system.cpu0.dcache.demand_accesses::total 42503561 710system.cpu0.dcache.overall_accesses::cpu0.data 42949408 711system.cpu0.dcache.overall_accesses::total 42949408 712system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016292 713system.cpu0.dcache.ReadReq_miss_rate::total 0.016292 714system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017729 715system.cpu0.dcache.WriteReq_miss_rate::total 0.017729 716system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284838 717system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284838 718system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055506 719system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055506 720system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051361 721system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051361 722system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016910 723system.cpu0.dcache.demand_miss_rate::total 0.016910 724system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019691 725system.cpu0.dcache.overall_miss_rate::total 0.019691 726system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13973.969356 727system.cpu0.dcache.ReadReq_avg_miss_latency::total 13973.969356 728system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19466.409831 729system.cpu0.dcache.WriteReq_avg_miss_latency::total 19466.409831 730system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15754.294650 731system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15754.294650 732system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.802105 733system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.802105 734system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf 735system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf 736system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16451.454426 737system.cpu0.dcache.demand_avg_miss_latency::total 16451.454426 738system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13981.122839 739system.cpu0.dcache.overall_avg_miss_latency::total 13981.122839 740system.cpu0.dcache.blocked_cycles::no_mshrs 0 741system.cpu0.dcache.blocked_cycles::no_targets 0 742system.cpu0.dcache.blocked::no_mshrs 0 743system.cpu0.dcache.blocked::no_targets 0 744system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan 745system.cpu0.dcache.avg_blocked_cycles::no_targets nan 746system.cpu0.dcache.writebacks::writebacks 689805 747system.cpu0.dcache.writebacks::total 689805 748system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25204 749system.cpu0.dcache.ReadReq_mshr_hits::total 25204 750system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15035 751system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15035 752system.cpu0.dcache.demand_mshr_hits::cpu0.data 25204 753system.cpu0.dcache.demand_mshr_hits::total 25204 754system.cpu0.dcache.overall_mshr_hits::cpu0.data 25204 755system.cpu0.dcache.overall_mshr_hits::total 25204 756system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369331 757system.cpu0.dcache.ReadReq_mshr_misses::total 369331 758system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324202 759system.cpu0.dcache.WriteReq_mshr_misses::total 324202 760system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100006 761system.cpu0.dcache.SoftPFReq_mshr_misses::total 100006 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1333system.cpu0.toL2Bus.respLayer2.utilization 0.0 1334system.cpu0.toL2Bus.respLayer3.occupancy 14180491 1335system.cpu0.toL2Bus.respLayer3.utilization 0.0 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 1339system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 1340system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 1341system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 1342system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 1343system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 1344system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 1345system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 1346system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 1347system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 1348system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 1349system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 1350system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 1351system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 1352system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 1353system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 1354system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 1355system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 1356system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 1357system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 1358system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 1359system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 1360system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 1361system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 1362system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 1363system.cpu1.dstage2_mmu.stage2_tlb.hits 0 1364system.cpu1.dstage2_mmu.stage2_tlb.misses 0 1365system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 1366system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 1367system.cpu1.dtb.walker.walks 3373 1368system.cpu1.dtb.walker.walksShort 3373 1369system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 671 1370system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2702 1371system.cpu1.dtb.walker.walkWaitTime::samples 3373 1372system.cpu1.dtb.walker.walkWaitTime::0 3373 100.00% 100.00% 1373system.cpu1.dtb.walker.walkWaitTime::total 3373 1374system.cpu1.dtb.walker.walkCompletionTime::samples 2603 1375system.cpu1.dtb.walker.walkCompletionTime::mean 12478.486362 1376system.cpu1.dtb.walker.walkCompletionTime::gmean 11546.344109 1377system.cpu1.dtb.walker.walkCompletionTime::stdev 5610.903902 1378system.cpu1.dtb.walker.walkCompletionTime::0-8191 607 23.32% 23.32% 1379system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1682 64.62% 87.94% 1380system.cpu1.dtb.walker.walkCompletionTime::16384-24575 233 8.95% 96.89% 1381system.cpu1.dtb.walker.walkCompletionTime::24576-32767 66 2.54% 99.42% 1382system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.35% 99.77% 1383system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.88% 1384system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% 1385system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% 1386system.cpu1.dtb.walker.walkCompletionTime::total 2603 1387system.cpu1.dtb.walker.walksPending::samples -1937787828 1388system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% 1389system.cpu1.dtb.walker.walksPending::total -1937787828 1390system.cpu1.dtb.walker.walkPageSizes::4K 1940 74.53% 74.53% 1391system.cpu1.dtb.walker.walkPageSizes::1M 663 25.47% 100.00% 1392system.cpu1.dtb.walker.walkPageSizes::total 2603 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3373 1394system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 1395system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3373 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2603 1397system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 1398system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2603 1399system.cpu1.dtb.walker.walkRequestOrigin::total 5976 1400system.cpu1.dtb.inst_hits 0 1401system.cpu1.dtb.inst_misses 0 1402system.cpu1.dtb.read_hits 3953610 1403system.cpu1.dtb.read_misses 2858 1404system.cpu1.dtb.write_hits 3430069 1405system.cpu1.dtb.write_misses 515 1406system.cpu1.dtb.flush_tlb 66 1407system.cpu1.dtb.flush_tlb_mva 917 1408system.cpu1.dtb.flush_tlb_mva_asid 0 1409system.cpu1.dtb.flush_tlb_asid 0 1410system.cpu1.dtb.flush_entries 1978 1411system.cpu1.dtb.align_faults 0 1412system.cpu1.dtb.prefetch_faults 342 1413system.cpu1.dtb.domain_faults 0 1414system.cpu1.dtb.perms_faults 163 1415system.cpu1.dtb.read_accesses 3956468 1416system.cpu1.dtb.write_accesses 3430584 1417system.cpu1.dtb.inst_accesses 0 1418system.cpu1.dtb.hits 7383679 1419system.cpu1.dtb.misses 3373 1420system.cpu1.dtb.accesses 7387052 1421system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 1428system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 1429system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 1430system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 1431system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 1432system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 1433system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 1434system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 1435system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 1436system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 1437system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 1438system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 1439system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 1440system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 1441system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 1442system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 1443system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 1444system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 1445system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 1446system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 1447system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 1448system.cpu1.istage2_mmu.stage2_tlb.hits 0 1449system.cpu1.istage2_mmu.stage2_tlb.misses 0 1450system.cpu1.istage2_mmu.stage2_tlb.accesses 0 1451system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 1452system.cpu1.itb.walker.walks 1746 1453system.cpu1.itb.walker.walksShort 1746 1454system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 1455system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 1456system.cpu1.itb.walker.walkWaitTime::samples 1746 1457system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% 1458system.cpu1.itb.walker.walkWaitTime::total 1746 1459system.cpu1.itb.walker.walkCompletionTime::samples 1107 1460system.cpu1.itb.walker.walkCompletionTime::mean 12838.301716 1461system.cpu1.itb.walker.walkCompletionTime::gmean 11944.354322 1462system.cpu1.itb.walker.walkCompletionTime::stdev 5752.116994 1463system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.54% 14.54% 1464system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 72.18% 1465system.cpu1.itb.walker.walkCompletionTime::12288-16383 160 14.45% 86.63% 1466system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 90.97% 1467system.cpu1.itb.walker.walkCompletionTime::20480-24575 40 3.61% 94.58% 1468system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.62% 97.20% 1469system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.64% 1470system.cpu1.itb.walker.walkCompletionTime::32768-36863 6 0.54% 99.19% 1471system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% 1472system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% 1473system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% 1474system.cpu1.itb.walker.walkCompletionTime::total 1107 1475system.cpu1.itb.walker.walksPending::samples -1938367828 1476system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% 1477system.cpu1.itb.walker.walksPending::total -1938367828 1478system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% 1479system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% 1480system.cpu1.itb.walker.walkPageSizes::total 1107 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 1482system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 1483system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 1485system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 1486system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 1487system.cpu1.itb.walker.walkRequestOrigin::total 2853 1488system.cpu1.itb.inst_hits 16665543 1489system.cpu1.itb.inst_misses 1746 1490system.cpu1.itb.read_hits 0 1491system.cpu1.itb.read_misses 0 1492system.cpu1.itb.write_hits 0 1493system.cpu1.itb.write_misses 0 1494system.cpu1.itb.flush_tlb 66 1495system.cpu1.itb.flush_tlb_mva 917 1496system.cpu1.itb.flush_tlb_mva_asid 0 1497system.cpu1.itb.flush_tlb_asid 0 1498system.cpu1.itb.flush_entries 1084 1499system.cpu1.itb.align_faults 0 1500system.cpu1.itb.prefetch_faults 0 1501system.cpu1.itb.domain_faults 0 1502system.cpu1.itb.perms_faults 0 1503system.cpu1.itb.read_accesses 0 1504system.cpu1.itb.write_accesses 0 1505system.cpu1.itb.inst_accesses 16667289 1506system.cpu1.itb.hits 16665543 1507system.cpu1.itb.misses 1746 1508system.cpu1.itb.accesses 16667289 1509system.cpu1.numPwrStateTransitions 5457 1510system.cpu1.pwrStateClkGateDist::samples 2729 1511system.cpu1.pwrStateClkGateDist::mean 1042331816.440454 1512system.cpu1.pwrStateClkGateDist::stdev 25865412745.750839 1513system.cpu1.pwrStateClkGateDist::underflows 1950 71.45% 71.45% 1514system.cpu1.pwrStateClkGateDist::1000-5e+10 773 28.33% 99.78% 1515system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% 1516system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% 1517system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% 1518system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% 1519system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% 1520system.cpu1.pwrStateClkGateDist::min_value 501 1521system.cpu1.pwrStateClkGateDist::max_value 929980418584 1522system.cpu1.pwrStateClkGateDist::total 2729 1523system.cpu1.pwrStateResidencyTicks::ON 26488828434 1524system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844523527066 1525system.cpu1.numCycles 5741091540 1526system.cpu1.numWorkItemsStarted 0 1527system.cpu1.numWorkItemsCompleted 0 1528system.cpu1.kern.inst.arm 0 1529system.cpu1.kern.inst.quiesce 2729 1530system.cpu1.committedInsts 16310250 1531system.cpu1.committedOps 19861699 1532system.cpu1.num_int_alu_accesses 17893275 1533system.cpu1.num_fp_alu_accesses 1792 1534system.cpu1.num_func_calls 1028889 1535system.cpu1.num_conditional_control_insts 1844355 1536system.cpu1.num_int_insts 17893275 1537system.cpu1.num_fp_insts 1792 1538system.cpu1.num_int_register_reads 32455374 1539system.cpu1.num_int_register_writes 12541370 1540system.cpu1.num_fp_register_reads 1276 1541system.cpu1.num_fp_register_writes 516 1542system.cpu1.num_cc_register_reads 72563559 1543system.cpu1.num_cc_register_writes 6509295 1544system.cpu1.num_mem_refs 7617254 1545system.cpu1.num_load_insts 4064765 1546system.cpu1.num_store_insts 3552489 1547system.cpu1.num_idle_cycles 5688122492.849936 1548system.cpu1.num_busy_cycles 52969047.150064 1549system.cpu1.not_idle_fraction 0.009226 1550system.cpu1.idle_fraction 0.990774 1551system.cpu1.Branches 2953035 1552system.cpu1.op_class::No_OpClass 66 0.00% 0.00% 1553system.cpu1.op_class::IntAlu 12565444 62.17% 62.17% 1554system.cpu1.op_class::IntMult 26315 0.13% 62.30% 1555system.cpu1.op_class::IntDiv 0 0.00% 62.30% 1556system.cpu1.op_class::FloatAdd 0 0.00% 62.30% 1557system.cpu1.op_class::FloatCmp 0 0.00% 62.30% 1558system.cpu1.op_class::FloatCvt 0 0.00% 62.30% 1559system.cpu1.op_class::FloatMult 0 0.00% 62.30% 1560system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% 1561system.cpu1.op_class::FloatDiv 0 0.00% 62.30% 1562system.cpu1.op_class::FloatMisc 0 0.00% 62.30% 1563system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% 1564system.cpu1.op_class::SimdAdd 0 0.00% 62.30% 1565system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% 1566system.cpu1.op_class::SimdAlu 0 0.00% 62.30% 1567system.cpu1.op_class::SimdCmp 0 0.00% 62.30% 1568system.cpu1.op_class::SimdCvt 0 0.00% 62.30% 1569system.cpu1.op_class::SimdMisc 0 0.00% 62.30% 1570system.cpu1.op_class::SimdMult 0 0.00% 62.30% 1571system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% 1572system.cpu1.op_class::SimdShift 0 0.00% 62.30% 1573system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% 1574system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% 1575system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% 1576system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% 1577system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% 1578system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% 1579system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% 1580system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.31% 1581system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% 1582system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% 1583system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% 1584system.cpu1.op_class::MemRead 4064249 20.11% 82.42% 1585system.cpu1.op_class::MemWrite 3551213 17.57% 99.99% 1586system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% 1587system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% 1588system.cpu1.op_class::IprAccess 0 0.00% 100.00% 1589system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% 1590system.cpu1.op_class::total 20212358 1591system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 1592system.cpu1.dcache.tags.replacements 187431 1593system.cpu1.dcache.tags.tagsinuse 470.676841 1594system.cpu1.dcache.tags.total_refs 7112504 1595system.cpu1.dcache.tags.sampled_refs 187790 1596system.cpu1.dcache.tags.avg_refs 37.874775 1597system.cpu1.dcache.tags.warmup_cycle 128171950500 1598system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.676841 1599system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919291 1600system.cpu1.dcache.tags.occ_percent::total 0.919291 1601system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 1602system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 1603system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 1604system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 1605system.cpu1.dcache.tags.tag_accesses 14986603 1606system.cpu1.dcache.tags.data_accesses 14986603 1607system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2871012355500 1608system.cpu1.dcache.ReadReq_hits::cpu1.data 3641806 1609system.cpu1.dcache.ReadReq_hits::total 3641806 1610system.cpu1.dcache.WriteReq_hits::cpu1.data 3241391 1611system.cpu1.dcache.WriteReq_hits::total 3241391 1612system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49016 1613system.cpu1.dcache.SoftPFReq_hits::total 49016 1614system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78939 1615system.cpu1.dcache.LoadLockedReq_hits::total 78939 1616system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70838 1617system.cpu1.dcache.StoreCondReq_hits::total 70838 1618system.cpu1.dcache.demand_hits::cpu1.data 6883197 1619system.cpu1.dcache.demand_hits::total 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2529system.l2c.ReadSharedReq_hits::cpu0.inst 44443 2530system.l2c.ReadSharedReq_hits::cpu0.data 52813 2531system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45878 2532system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 45 2533system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 2534system.l2c.ReadSharedReq_hits::cpu1.inst 19063 2535system.l2c.ReadSharedReq_hits::cpu1.data 11032 2536system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5457 2537system.l2c.ReadSharedReq_hits::total 178998 2538system.l2c.demand_hits::cpu0.dtb.walker 137 2539system.l2c.demand_hits::cpu0.itb.walker 102 2540system.l2c.demand_hits::cpu0.inst 44443 2541system.l2c.demand_hits::cpu0.data 56748 2542system.l2c.demand_hits::cpu0.l2cache.prefetcher 45878 2543system.l2c.demand_hits::cpu1.dtb.walker 45 2544system.l2c.demand_hits::cpu1.itb.walker 28 2545system.l2c.demand_hits::cpu1.inst 19063 2546system.l2c.demand_hits::cpu1.data 12528 2547system.l2c.demand_hits::cpu1.l2cache.prefetcher 5457 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2972system.l2c.overall_avg_mshr_uncacheable_latency::total 90935.033982 2973system.membus.snoop_filter.tot_requests 502622 2974system.membus.snoop_filter.hit_single_requests 282245 2975system.membus.snoop_filter.hit_multi_requests 635 2976system.membus.snoop_filter.tot_snoops 0 2977system.membus.snoop_filter.hit_single_snoops 0 2978system.membus.snoop_filter.hit_multi_snoops 0 2979system.membus.pwrStateResidencyTicks::UNDEFINED 2871012355500 2980system.membus.trans_dist::ReadReq 44023 2981system.membus.trans_dist::ReadResp 214836 2982system.membus.trans_dist::WriteReq 30870 2983system.membus.trans_dist::WriteResp 30870 2984system.membus.trans_dist::WritebackDirty 136706 2985system.membus.trans_dist::CleanEvict 16434 2986system.membus.trans_dist::UpgradeReq 64435 2987system.membus.trans_dist::SCUpgradeReq 38119 2988system.membus.trans_dist::UpgradeResp 17 2989system.membus.trans_dist::SCUpgradeFailReq 1 2990system.membus.trans_dist::ReadExReq 39786 2991system.membus.trans_dist::ReadExResp 19314 2992system.membus.trans_dist::ReadSharedReq 170813 2993system.membus.trans_dist::InvalidateReq 36224 2994system.membus.trans_dist::InvalidateResp 4530 2995system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107898 2996system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 2997system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13552 2998system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647420 2999system.membus.pkt_count_system.l2c.mem_side::total 768904 3000system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 3001system.membus.pkt_count_system.iocache.mem_side::total 72939 3002system.membus.pkt_count::total 841843 3003system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162788 3004system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 3005system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27104 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3062system.realview.ethernet.coalescedRxOk nan 3063system.realview.ethernet.totalRxOk 0 3064system.realview.ethernet.postedRxDesc 0 3065system.realview.ethernet.coalescedRxDesc nan 3066system.realview.ethernet.totalRxDesc 0 3067system.realview.ethernet.postedTxOk 0 3068system.realview.ethernet.coalescedTxOk nan 3069system.realview.ethernet.totalTxOk 0 3070system.realview.ethernet.postedTxIdle 0 3071system.realview.ethernet.coalescedTxIdle nan 3072system.realview.ethernet.totalTxIdle 0 3073system.realview.ethernet.postedTxDesc 0 3074system.realview.ethernet.coalescedTxDesc nan 3075system.realview.ethernet.totalTxDesc 0 3076system.realview.ethernet.postedRxOrn 0 3077system.realview.ethernet.coalescedRxOrn nan 3078system.realview.ethernet.totalRxOrn 0 3079system.realview.ethernet.coalescedTotal nan 3080system.realview.ethernet.postedInterrupts 0 3081system.realview.ethernet.droppedPackets 0 3082system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2871012355500 3083system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2871012355500 3084system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2871012355500 3085system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2871012355500 3086system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3087system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3088system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2871012355500 3089system.realview.mcc.osc_clcd.clock 42105 3090system.realview.mcc.osc_mcc.clock 20000 3091system.realview.mcc.osc_peripheral.clock 41667 3092system.realview.mcc.osc_system_bus.clock 41667 3093system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3094system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2871012355500 3095system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3096system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2871012355500 3097system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2871012355500 3098system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2871012355500 3099system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3100system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3101system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3102system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3103system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2871012355500 3104system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 3105system.toL2Bus.snoop_filter.tot_requests 1013756 3106system.toL2Bus.snoop_filter.hit_single_requests 527510 3107system.toL2Bus.snoop_filter.hit_multi_requests 187290 3108system.toL2Bus.snoop_filter.tot_snoops 29674 3109system.toL2Bus.snoop_filter.hit_single_snoops 28443 3110system.toL2Bus.snoop_filter.hit_multi_snoops 1231 3111system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500 3112system.toL2Bus.trans_dist::ReadReq 44026 3113system.toL2Bus.trans_dist::ReadResp 511611 3114system.toL2Bus.trans_dist::WriteReq 30870 3115system.toL2Bus.trans_dist::WriteResp 30870 3116system.toL2Bus.trans_dist::WritebackDirty 361082 3117system.toL2Bus.trans_dist::CleanEvict 119910 3118system.toL2Bus.trans_dist::UpgradeReq 109230 3119system.toL2Bus.trans_dist::SCUpgradeReq 42710 3120system.toL2Bus.trans_dist::UpgradeResp 151940 3121system.toL2Bus.trans_dist::SCUpgradeFailReq 77 3122system.toL2Bus.trans_dist::UpgradeFailResp 77 3123system.toL2Bus.trans_dist::ReadExReq 50740 3124system.toL2Bus.trans_dist::ReadExResp 50740 3125system.toL2Bus.trans_dist::ReadSharedReq 467589 3126system.toL2Bus.trans_dist::InvalidateReq 4574 3127system.toL2Bus.trans_dist::InvalidateResp 3436 3128system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1274602 3129system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317408 3130system.toL2Bus.pkt_count::total 1592010 3131system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35235610 3132system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5660730 3133system.toL2Bus.pkt_size::total 40896340 3134system.toL2Bus.snoops 391148 3135system.toL2Bus.snoopTraffic 15652684 3136system.toL2Bus.snoop_fanout::samples 887182 3137system.toL2Bus.snoop_fanout::mean 0.397329 3138system.toL2Bus.snoop_fanout::stdev 0.492173 3139system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% 3140system.toL2Bus.snoop_fanout::0 535910 60.41% 60.41% 3141system.toL2Bus.snoop_fanout::1 350041 39.46% 99.86% 3142system.toL2Bus.snoop_fanout::2 1231 0.14% 100.00% 3143system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% 3144system.toL2Bus.snoop_fanout::min_value 0 3145system.toL2Bus.snoop_fanout::max_value 2 3146system.toL2Bus.snoop_fanout::total 887182 3147system.toL2Bus.reqLayer0.occupancy 894578674 3148system.toL2Bus.reqLayer0.utilization 0.0 3149system.toL2Bus.snoopLayer0.occupancy 2158873 3150system.toL2Bus.snoopLayer0.utilization 0.0 3151system.toL2Bus.respLayer0.occupancy 676162622 3152system.toL2Bus.respLayer0.utilization 0.0 3153system.toL2Bus.respLayer1.occupancy 239095357 3154system.toL2Bus.respLayer1.utilization 0.0
3153 3154---------- End Simulation Statistics ----------	3155 3156---------- End Simulation Statistics ----------