| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 932940 # Simulator instruction rate (inst/s) 8host_op_rate 1128445 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20351712140 # Simulator tick rate (ticks/s) 10host_mem_usage 661084 # Number of bytes of host memory used 11host_seconds 141.01 # Real time elapsed on the host | 7host_inst_rate 540600 # Simulator instruction rate (inst/s) 8host_op_rate 653886 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11792964574 # Simulator tick rate (ticks/s) 10host_mem_usage 618088 # Number of bytes of host memory used 11host_seconds 243.35 # Real time elapsed on the host |
| 12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory --- 415 unchanged lines hidden (view full) --- 435system.cpu0.dtb.read_hits 25156508 # DTB read hits 436system.cpu0.dtb.read_misses 6829 # DTB read misses 437system.cpu0.dtb.write_hits 18749941 # DTB write hits 438system.cpu0.dtb.write_misses 1114 # DTB write misses 439system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 440system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 441system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory --- 415 unchanged lines hidden (view full) --- 435system.cpu0.dtb.read_hits 25156508 # DTB read hits 436system.cpu0.dtb.read_misses 6829 # DTB read misses 437system.cpu0.dtb.write_hits 18749941 # DTB write hits 438system.cpu0.dtb.write_misses 1114 # DTB write misses 439system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 440system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 441system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 443system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB | 443system.cpu0.dtb.flush_entries 3392 # Number of entries that have been flushed from TLB |
| 444system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch 446system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 448system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 449system.cpu0.dtb.write_accesses 18751055 # DTB write accesses 450system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu0.dtb.hits 43906449 # DTB hits --- 69 unchanged lines hidden (view full) --- 521system.cpu0.itb.read_hits 0 # DTB read hits 522system.cpu0.itb.read_misses 0 # DTB read misses 523system.cpu0.itb.write_hits 0 # DTB write hits 524system.cpu0.itb.write_misses 0 # DTB write misses 525system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 526system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 527system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 528system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 444system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch 446system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 448system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 449system.cpu0.dtb.write_accesses 18751055 # DTB write accesses 450system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu0.dtb.hits 43906449 # DTB hits --- 69 unchanged lines hidden (view full) --- 521system.cpu0.itb.read_hits 0 # DTB read hits 522system.cpu0.itb.read_misses 0 # DTB read misses 523system.cpu0.itb.write_hits 0 # DTB write hits 524system.cpu0.itb.write_misses 0 # DTB write misses 525system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 526system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 527system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 528system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 529system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB | 529system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB |
| 530system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 531system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 532system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 533system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 534system.cpu0.itb.read_accesses 0 # DTB read accesses 535system.cpu0.itb.write_accesses 0 # DTB write accesses 536system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses 537system.cpu0.itb.hits 119016789 # DTB hits --- 840 unchanged lines hidden (view full) --- 1378system.cpu1.dtb.read_hits 3941258 # DTB read hits 1379system.cpu1.dtb.read_misses 2845 # DTB read misses 1380system.cpu1.dtb.write_hits 3419362 # DTB write hits 1381system.cpu1.dtb.write_misses 507 # DTB write misses 1382system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1383system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1384system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1385system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 530system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 531system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 532system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 533system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 534system.cpu0.itb.read_accesses 0 # DTB read accesses 535system.cpu0.itb.write_accesses 0 # DTB write accesses 536system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses 537system.cpu0.itb.hits 119016789 # DTB hits --- 840 unchanged lines hidden (view full) --- 1378system.cpu1.dtb.read_hits 3941258 # DTB read hits 1379system.cpu1.dtb.read_misses 2845 # DTB read misses 1380system.cpu1.dtb.write_hits 3419362 # DTB write hits 1381system.cpu1.dtb.write_misses 507 # DTB write misses 1382system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1383system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1384system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1385system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1386system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB | 1386system.cpu1.dtb.flush_entries 1980 # Number of entries that have been flushed from TLB |
| 1387system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1388system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch 1389system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1390system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1391system.cpu1.dtb.read_accesses 3944103 # DTB read accesses 1392system.cpu1.dtb.write_accesses 3419869 # DTB write accesses 1393system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1394system.cpu1.dtb.hits 7360620 # DTB hits --- 72 unchanged lines hidden (view full) --- 1467system.cpu1.itb.read_hits 0 # DTB read hits 1468system.cpu1.itb.read_misses 0 # DTB read misses 1469system.cpu1.itb.write_hits 0 # DTB write hits 1470system.cpu1.itb.write_misses 0 # DTB write misses 1471system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1472system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1473system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1474system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1387system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1388system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch 1389system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1390system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1391system.cpu1.dtb.read_accesses 3944103 # DTB read accesses 1392system.cpu1.dtb.write_accesses 3419869 # DTB write accesses 1393system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1394system.cpu1.dtb.hits 7360620 # DTB hits --- 72 unchanged lines hidden (view full) --- 1467system.cpu1.itb.read_hits 0 # DTB read hits 1468system.cpu1.itb.read_misses 0 # DTB read misses 1469system.cpu1.itb.write_hits 0 # DTB write hits 1470system.cpu1.itb.write_misses 0 # DTB write misses 1471system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1472system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1473system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1474system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1475system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB | 1475system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB |
| 1476system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1477system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1478system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1479system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1480system.cpu1.itb.read_accesses 0 # DTB read accesses 1481system.cpu1.itb.write_accesses 0 # DTB write accesses 1482system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses 1483system.cpu1.itb.hits 16556610 # DTB hits --- 1612 unchanged lines hidden --- | 1476system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1477system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1478system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1479system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1480system.cpu1.itb.read_accesses 0 # DTB read accesses 1481system.cpu1.itb.write_accesses 0 # DTB write accesses 1482system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses 1483system.cpu1.itb.hits 16556610 # DTB hits --- 1612 unchanged lines hidden --- |