| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1069345 # Simulator instruction rate (inst/s) 8host_op_rate 1293434 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23327334867 # Simulator tick rate (ticks/s) 10host_mem_usage 660408 # Number of bytes of host memory used 11host_seconds 123.02 # Real time elapsed on the host | 7host_inst_rate 932940 # Simulator instruction rate (inst/s) 8host_op_rate 1128445 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20351712140 # Simulator tick rate (ticks/s) 10host_mem_usage 661084 # Number of bytes of host memory used 11host_seconds 141.01 # Real time elapsed on the host |
| 12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory --- 307 unchanged lines hidden (view full) --- 331system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) 332system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) 333system.physmem_1.averagePower 669.487743 # Core power per rank (mW) 334system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states 335system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states 336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 337system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states 338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory --- 307 unchanged lines hidden (view full) --- 332system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) 333system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) 334system.physmem_1.averagePower 669.487743 # Core power per rank (mW) 335system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states 336system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states 337system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 338system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states 339system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 340system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 339system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 345system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 346system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 347system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 348system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 349system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) | 341system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 347system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 350system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) |
| 359system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 360system.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 361system.bridge.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 357system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 358system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 359system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 360system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 361system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 362system.cf0.dma_write_txs 631 # Number of DMA write transactions. 363system.cpu_clk_domain.clock 500 # Clock period in ticks | 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. 368system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 369system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 364system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 385system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 399system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 393system.cpu0.dtb.walker.walks 7943 # Table walker walks requested 394system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors 395system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate 396system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate 397system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency 398system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency 399system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency 400system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency --- 38 unchanged lines hidden (view full) --- 439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 440system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 441system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 442system.cpu0.dtb.write_accesses 18751055 # DTB write accesses 443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 444system.cpu0.dtb.hits 43906449 # DTB hits 445system.cpu0.dtb.misses 7943 # DTB misses 446system.cpu0.dtb.accesses 43914392 # DTB accesses | 400system.cpu0.dtb.walker.walks 7943 # Table walker walks requested 401system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors 402system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate 403system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate 404system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency --- 38 unchanged lines hidden (view full) --- 446system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 448system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 449system.cpu0.dtb.write_accesses 18751055 # DTB write accesses 450system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu0.dtb.hits 43906449 # DTB hits 452system.cpu0.dtb.misses 7943 # DTB misses 453system.cpu0.dtb.accesses 43914392 # DTB accesses |
| 454system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 468system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 470system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 471system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 472system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 473system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 474system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 475system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 455system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 476system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 484system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 476system.cpu0.itb.walker.walks 3349 # Table walker walks requested 477system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 478system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 479system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 480system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 481system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 482system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 483system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 523system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 524system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 525system.cpu0.itb.read_accesses 0 # DTB read accesses 526system.cpu0.itb.write_accesses 0 # DTB write accesses 527system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses 528system.cpu0.itb.hits 119016789 # DTB hits 529system.cpu0.itb.misses 3349 # DTB misses 530system.cpu0.itb.accesses 119020138 # DTB accesses | 485system.cpu0.itb.walker.walks 3349 # Table walker walks requested 486system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 487system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 488system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 489system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 490system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 532system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 533system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 534system.cpu0.itb.read_accesses 0 # DTB read accesses 535system.cpu0.itb.write_accesses 0 # DTB write accesses 536system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses 537system.cpu0.itb.hits 119016789 # DTB hits 538system.cpu0.itb.misses 3349 # DTB misses 539system.cpu0.itb.accesses 119020138 # DTB accesses |
| 540system.cpu0.numPwrStateTransitions 3732 # Number of power state transitions 541system.cpu0.pwrStateClkGateDist::samples 1866 # Distribution of time spent in the clock gated state 542system.cpu0.pwrStateClkGateDist::mean 1464105256.698285 # Distribution of time spent in the clock gated state 543system.cpu0.pwrStateClkGateDist::stdev 23703834177.511120 # Distribution of time spent in the clock gated state 544system.cpu0.pwrStateClkGateDist::underflows 1075 57.61% 57.61% # Distribution of time spent in the clock gated state 545system.cpu0.pwrStateClkGateDist::1000-5e+10 786 42.12% 99.73% # Distribution of time spent in the clock gated state 546system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 547system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state 548system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 549system.cpu0.pwrStateClkGateDist::max_value 499964077872 # Distribution of time spent in the clock gated state 550system.cpu0.pwrStateClkGateDist::total 1866 # Distribution of time spent in the clock gated state 551system.cpu0.pwrStateResidencyTicks::ON 137768561001 # Cumulative time (in ticks) in various power states 552system.cpu0.pwrStateResidencyTicks::CLK_GATED 2732020408999 # Cumulative time (in ticks) in various power states |
|
| 531system.cpu0.numCycles 5739577940 # number of cpu cycles simulated 532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 534system.cpu0.kern.inst.arm 0 # number of arm instructions executed 535system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed 536system.cpu0.committedInsts 115352405 # Number of instructions committed 537system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed 538system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 585system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 586system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 588system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction 589system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction 590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 592system.cpu0.op_class::total 143145074 # Class of executed instruction | 553system.cpu0.numCycles 5739577940 # number of cpu cycles simulated 554system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 555system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 556system.cpu0.kern.inst.arm 0 # number of arm instructions executed 557system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed 558system.cpu0.committedInsts 115352405 # Number of instructions committed 559system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed 560system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 607system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 608system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 609system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 610system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction 611system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction 612system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 613system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 614system.cpu0.op_class::total 143145074 # Class of executed instruction |
| 615system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 593system.cpu0.dcache.tags.replacements 692159 # number of replacements 594system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use 595system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. 596system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. 597system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. 598system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. 599system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor 600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy 601system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 607system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses 608system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses | 616system.cpu0.dcache.tags.replacements 692159 # number of replacements 617system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use 618system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. 619system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. 620system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. 621system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. 622system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor 623system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy 624system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy 625system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 626system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 627system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 628system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 629system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 630system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses 631system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses |
| 632system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 609system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits 610system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits 611system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits 612system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits 613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits 614system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits 615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits 616system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits --- 158 unchanged lines hidden (view full) --- 775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency 776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency 777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency 778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency 780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency 781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency 782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency | 633system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits 634system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits 635system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits 636system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits 637system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits 638system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits 639system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits 640system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits --- 158 unchanged lines hidden (view full) --- 799system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency 800system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency 801system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency 802system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency 803system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency 804system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency 806system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency |
| 807system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 783system.cpu0.icache.tags.replacements 1103881 # number of replacements 784system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use 785system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. 786system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. 787system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks. 788system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. 789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor 790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy 791system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy 792system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 793system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 794system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 795system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 796system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 797system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses 798system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses | 808system.cpu0.icache.tags.replacements 1103881 # number of replacements 809system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use 810system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. 811system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. 812system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks. 813system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. 814system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor 815system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy 816system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy 817system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 818system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 819system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 820system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 821system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 822system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses 823system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses |
| 824system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 799system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits 804system.cpu0.icache.overall_hits::total 117912387 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 872system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 874system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency 876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency 877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency 878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency | 825system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits 826system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits 827system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits 828system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits 829system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits 830system.cpu0.icache.overall_hits::total 117912387 # number of overall hits 831system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses 832system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 897system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 898system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 899system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 900system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 901system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency 902system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency 903system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency 904system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency |
| 905system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued 880system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified 881system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue 882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 884system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing | 906system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued 907system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified 908system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue 909system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 910system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 911system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing |
| 912system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 885system.cpu0.l2cache.tags.replacements 266444 # number of replacements 886system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use 887system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. 888system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. 889system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. 890system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 891system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor 892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor --- 18 unchanged lines hidden (view full) --- 911system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id 914system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id 915system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 916system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id 917system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses 918system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses | 913system.cpu0.l2cache.tags.replacements 266444 # number of replacements 914system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use 915system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. 916system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. 917system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. 918system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 919system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor 920system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor --- 18 unchanged lines hidden (view full) --- 939system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id 942system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id 943system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 944system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id 945system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses 946system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses |
| 947system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 919system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits 920system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits 921system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits 922system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits 923system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits 924system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits 925system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits 926system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits --- 291 unchanged lines hidden (view full) --- 1218system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency 1219system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency 1220system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. 1221system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1222system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1223system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. 1224system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1225system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 948system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits 949system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits 950system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits 951system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits 952system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits 953system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits 954system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits 955system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits --- 291 unchanged lines hidden (view full) --- 1247system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency 1248system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency 1249system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. 1250system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1251system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1252system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. 1253system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1254system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1255system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1226system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution 1227system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution 1228system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution 1229system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution 1230system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution 1231system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution 1232system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution 1233system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 1270system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) 1271system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1272system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) 1273system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1274system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1275system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1276system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) 1277system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1256system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution 1257system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution 1258system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution 1259system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution 1260system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution 1261system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution 1262system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution 1263system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 1300system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) 1301system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1302system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) 1303system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1304system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1305system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1306system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) 1307system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1308system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1278system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1279system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1280system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1281system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1282system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1283system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1284system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1285system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1299system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1300system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1301system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1302system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1303system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1304system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1305system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1306system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1309system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1310system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1311system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1312system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1313system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1314system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1315system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1316system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1330system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1331system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1332system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1333system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1334system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1335system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1336system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1337system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1338system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1307system.cpu1.dtb.walker.walks 3352 # Table walker walks requested 1308system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors 1309system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate 1310system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate 1311system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency 1312system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1313system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency 1314system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency --- 42 unchanged lines hidden (view full) --- 1357system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1358system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1359system.cpu1.dtb.read_accesses 3944103 # DTB read accesses 1360system.cpu1.dtb.write_accesses 3419869 # DTB write accesses 1361system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1362system.cpu1.dtb.hits 7360620 # DTB hits 1363system.cpu1.dtb.misses 3352 # DTB misses 1364system.cpu1.dtb.accesses 7363972 # DTB accesses | 1339system.cpu1.dtb.walker.walks 3352 # Table walker walks requested 1340system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors 1341system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate 1342system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate 1343system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency 1344system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1345system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency 1346system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency --- 42 unchanged lines hidden (view full) --- 1389system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1390system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1391system.cpu1.dtb.read_accesses 3944103 # DTB read accesses 1392system.cpu1.dtb.write_accesses 3419869 # DTB write accesses 1393system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1394system.cpu1.dtb.hits 7360620 # DTB hits 1395system.cpu1.dtb.misses 3352 # DTB misses 1396system.cpu1.dtb.accesses 7363972 # DTB accesses |
| 1397system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1365system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1366system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1367system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1368system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1369system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1386system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1387system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1388system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1389system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1390system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1391system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1392system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1393system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1398system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1399system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1400system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1401system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1402system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1404system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1405system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1419system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1420system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1421system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1422system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1423system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1424system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1425system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1426system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1427system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1394system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1395system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1396system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1397system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1398system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1399system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1400system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1401system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency --- 42 unchanged lines hidden (view full) --- 1444system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1445system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1446system.cpu1.itb.read_accesses 0 # DTB read accesses 1447system.cpu1.itb.write_accesses 0 # DTB write accesses 1448system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses 1449system.cpu1.itb.hits 16556610 # DTB hits 1450system.cpu1.itb.misses 1746 # DTB misses 1451system.cpu1.itb.accesses 16558356 # DTB accesses | 1428system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1429system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1430system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1431system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1432system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1433system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1434system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1435system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency --- 42 unchanged lines hidden (view full) --- 1478system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1479system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1480system.cpu1.itb.read_accesses 0 # DTB read accesses 1481system.cpu1.itb.write_accesses 0 # DTB write accesses 1482system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses 1483system.cpu1.itb.hits 16556610 # DTB hits 1484system.cpu1.itb.misses 1746 # DTB misses 1485system.cpu1.itb.accesses 16558356 # DTB accesses |
| 1486system.cpu1.numPwrStateTransitions 5511 # Number of power state transitions 1487system.cpu1.pwrStateClkGateDist::samples 2756 # Distribution of time spent in the clock gated state 1488system.cpu1.pwrStateClkGateDist::mean 1031898407.856313 # Distribution of time spent in the clock gated state 1489system.cpu1.pwrStateClkGateDist::stdev 25737040202.524998 # Distribution of time spent in the clock gated state 1490system.cpu1.pwrStateClkGateDist::underflows 1964 71.26% 71.26% # Distribution of time spent in the clock gated state 1491system.cpu1.pwrStateClkGateDist::1000-5e+10 786 28.52% 99.78% # Distribution of time spent in the clock gated state 1492system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1493system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1494system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1495system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1496system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1497system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1498system.cpu1.pwrStateClkGateDist::max_value 929980631528 # Distribution of time spent in the clock gated state 1499system.cpu1.pwrStateClkGateDist::total 2756 # Distribution of time spent in the clock gated state 1500system.cpu1.pwrStateResidencyTicks::ON 25876957948 # Cumulative time (in ticks) in various power states 1501system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843912012052 # Cumulative time (in ticks) in various power states |
|
| 1452system.cpu1.numCycles 5738649789 # number of cpu cycles simulated 1453system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1454system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1455system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1456system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed 1457system.cpu1.committedInsts 16201169 # Number of instructions committed 1458system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed 1459system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 1506system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction 1507system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction 1508system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction 1509system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction 1510system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction 1511system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1512system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1513system.cpu1.op_class::total 20092250 # Class of executed instruction | 1502system.cpu1.numCycles 5738649789 # number of cpu cycles simulated 1503system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1504system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1505system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1506system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed 1507system.cpu1.committedInsts 16201169 # Number of instructions committed 1508system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed 1509system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 1556system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction 1557system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction 1558system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction 1559system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction 1560system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction 1561system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1562system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1563system.cpu1.op_class::total 20092250 # Class of executed instruction |
| 1564system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1514system.cpu1.dcache.tags.replacements 186389 # number of replacements 1515system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use 1516system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. 1517system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. 1518system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. 1519system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. 1520system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor 1521system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy 1522system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy 1523system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 1524system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id 1525system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id 1526system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 1527system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses 1528system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses | 1565system.cpu1.dcache.tags.replacements 186389 # number of replacements 1566system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use 1567system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. 1568system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. 1569system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. 1570system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. 1571system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor 1572system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy 1573system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy 1574system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 1575system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id 1576system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id 1577system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 1578system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses 1579system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses |
| 1580system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1529system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits 1530system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits 1531system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits 1532system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits 1533system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits 1534system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits 1535system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits 1536system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits --- 158 unchanged lines hidden (view full) --- 1695system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency 1696system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency 1697system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency 1698system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency 1699system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency 1700system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency 1701system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency 1702system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency | 1581system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits 1582system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits 1583system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits 1584system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits 1585system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits 1586system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits 1587system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits 1588system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits --- 158 unchanged lines hidden (view full) --- 1747system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency 1748system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency 1749system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency 1750system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency 1751system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency 1752system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency 1753system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency 1754system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency |
| 1755system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1703system.cpu1.icache.tags.replacements 505464 # number of replacements 1704system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use 1705system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. 1706system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. 1707system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. 1708system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. 1709system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor 1710system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy 1711system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy 1712system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1713system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1714system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id 1715system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1716system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1717system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses 1718system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses | 1756system.cpu1.icache.tags.replacements 505464 # number of replacements 1757system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use 1758system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. 1759system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. 1760system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. 1761system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. 1762system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor 1763system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy 1764system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy 1765system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1766system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1767system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id 1768system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1769system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1770system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses 1771system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses |
| 1772system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1719system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits 1720system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits 1721system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits 1722system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits 1723system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits 1724system.cpu1.icache.overall_hits::total 16050629 # number of overall hits 1725system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses 1726system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1791system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1792system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1793system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1794system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1795system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency 1796system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency 1797system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency 1798system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency | 1773system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits 1774system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits 1775system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits 1776system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits 1777system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits 1778system.cpu1.icache.overall_hits::total 16050629 # number of overall hits 1779system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses 1780system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1845system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1846system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1847system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1848system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1849system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency 1850system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency 1851system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency 1852system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency |
| 1853system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1799system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued 1800system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified 1801system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1802system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1803system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1804system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing | 1854system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued 1855system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified 1856system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1857system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1858system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1859system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing |
| 1860system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1805system.cpu1.l2cache.tags.replacements 44688 # number of replacements 1806system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use 1807system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. 1808system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. 1809system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. 1810system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1811system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor 1812system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor --- 14 unchanged lines hidden (view full) --- 1827system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1828system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id 1829system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id 1830system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id 1831system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1832system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id 1833system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses 1834system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses | 1861system.cpu1.l2cache.tags.replacements 44688 # number of replacements 1862system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use 1863system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. 1864system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. 1865system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. 1866system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1867system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor 1868system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor --- 14 unchanged lines hidden (view full) --- 1883system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1884system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id 1885system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id 1886system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id 1887system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1888system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id 1889system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses 1890system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses |
| 1891system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 1835system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits 1836system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits 1837system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits 1838system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits 1839system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits 1840system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits 1841system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits 1842system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits --- 289 unchanged lines hidden (view full) --- 2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency 2133system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency 2134system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. 2135system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2136system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2137system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. 2138system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2139system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1892system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits 1893system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits 1894system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits 1895system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits 1896system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits 1897system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits 1898system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits 1899system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits --- 289 unchanged lines hidden (view full) --- 2189system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency 2190system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency 2191system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. 2192system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2193system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2194system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. 2195system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2196system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2197system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2140system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution 2141system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution 2142system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution 2143system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution 2144system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution 2145system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution 2146system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution 2147system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 2184system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) 2185system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2186system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) 2187system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2188system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2189system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2190system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) 2191system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2198system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution 2199system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution 2200system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution 2201system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution 2202system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution 2203system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution 2204system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution 2205system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 2242system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) 2243system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2244system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) 2245system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2246system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2247system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2248system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) 2249system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2250system.iobus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2192system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2193system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2194system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2195system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2196system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2197system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2198system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2199system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 2278system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) 2279system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2280system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) 2281system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2282system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2283system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2284system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2285system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2251system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2252system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2253system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2254system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2255system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2256system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2257system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2258system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 2337system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) 2338system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2339system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) 2340system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2341system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2342system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2343system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2344system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2345system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2286system.iocache.tags.replacements 36445 # number of replacements 2287system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use 2288system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2289system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2290system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2291system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. 2292system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor 2293system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy 2294system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy 2295system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2296system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2297system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2298system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2299system.iocache.tags.data_accesses 328311 # Number of data accesses | 2346system.iocache.tags.replacements 36445 # number of replacements 2347system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use 2348system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2349system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2350system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2351system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. 2352system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor 2353system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy 2354system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy 2355system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2356system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2357system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2358system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2359system.iocache.tags.data_accesses 328311 # Number of data accesses |
| 2360system.iocache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2300system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2301system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2302system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2303system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2304system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2305system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2306system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2307system.iocache.overall_misses::total 36479 # number of overall misses --- 64 unchanged lines hidden (view full) --- 2372system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency 2373system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency 2374system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency 2375system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency 2376system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2377system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency 2378system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2379system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency | 2361system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2362system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2363system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2364system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2365system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2366system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2367system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2368system.iocache.overall_misses::total 36479 # number of overall misses --- 64 unchanged lines hidden (view full) --- 2433system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency 2434system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency 2435system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency 2436system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency 2437system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2438system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency 2439system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2440system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency |
| 2441system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2380system.l2c.tags.replacements 126308 # number of replacements 2381system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use 2382system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. 2383system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. 2384system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. 2385system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2386system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor 2387system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 2415system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id 2416system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id 2417system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id 2418system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id 2419system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2420system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id 2421system.l2c.tags.tag_accesses 5890164 # Number of tag accesses 2422system.l2c.tags.data_accesses 5890164 # Number of data accesses | 2442system.l2c.tags.replacements 126308 # number of replacements 2443system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use 2444system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. 2445system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. 2446system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. 2447system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2448system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor 2449system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 2477system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id 2478system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id 2479system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id 2480system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id 2481system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2482system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id 2483system.l2c.tags.tag_accesses 5890164 # Number of tag accesses 2484system.l2c.tags.data_accesses 5890164 # Number of data accesses |
| 2485system.l2c.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2423system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits 2424system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits 2425system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits 2426system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits 2427system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits 2428system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits 2429system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits 2430system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits --- 420 unchanged lines hidden (view full) --- 2851system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency 2852system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency 2853system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. 2854system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2855system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2856system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2857system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2858system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2486system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits 2487system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits 2488system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits 2489system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits 2490system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits 2491system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits 2492system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits 2493system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits --- 420 unchanged lines hidden (view full) --- 2914system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency 2915system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency 2916system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. 2917system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2918system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2919system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2920system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2921system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2922system.membus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2859system.membus.trans_dist::ReadReq 44083 # Transaction distribution 2860system.membus.trans_dist::ReadResp 213856 # Transaction distribution 2861system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2862system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2863system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution 2864system.membus.trans_dist::CleanEvict 15700 # Transaction distribution 2865system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution 2866system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 2905system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) 2906system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2907system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) 2908system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2909system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) 2910system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2911system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) 2912system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 2923system.membus.trans_dist::ReadReq 44083 # Transaction distribution 2924system.membus.trans_dist::ReadResp 213856 # Transaction distribution 2925system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2926system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2927system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution 2928system.membus.trans_dist::CleanEvict 15700 # Transaction distribution 2929system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution 2930system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 2969system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) 2970system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2971system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) 2972system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2973system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) 2974system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2975system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) 2976system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2977system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2978system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2979system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2980system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2981system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2982system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2983system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2913system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2914system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2915system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2916system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2917system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2918system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 2984system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2985system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2986system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2987system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2988system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2989system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 2990system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2991system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2919system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2920system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2921system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2922system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2923system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2924system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2925system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2926system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 2942system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2943system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2944system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2945system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2946system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2947system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2948system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2949system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2992system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2993system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2994system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2995system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2996system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2997system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2998system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2999system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 3015system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3016system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3017system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3018system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3019system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3020system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3021system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3022system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3023system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3024system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3025system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3026system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3027system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3028system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3029system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2950system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 2951system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 2952system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 2953system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3030system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3031system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3032system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3033system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3034system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3035system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3036system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3037system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3038system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3039system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3040system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3041system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3042system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3043system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3044system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3045system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2954system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. 2955system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2956system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2957system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. 2958system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2959system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3046system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. 3047system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3048system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3049system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. 3050system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3051system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3052system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states |
|
| 2960system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution 2961system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution 2962system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 2963system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 2964system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution 2965system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution 2966system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution 2967system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution --- 35 unchanged lines hidden --- | 3053system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution 3054system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution 3055system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 3056system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 3057system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution 3058system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution 3059system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution 3060system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution --- 35 unchanged lines hidden --- |