| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 543935 # Simulator instruction rate (inst/s) 8host_op_rate 657921 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11865725522 # Simulator tick rate (ticks/s) 10host_mem_usage 611884 # Number of bytes of host memory used 11host_seconds 241.86 # Real time elapsed on the host 12sim_insts 131553572 # Number of instructions simulated 13sim_ops 159121620 # Number of ops (including micro ops) simulated | 7host_inst_rate 480288 # Simulator instruction rate (inst/s) 8host_op_rate 580935 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10477281069 # Simulator tick rate (ticks/s) 10host_mem_usage 611892 # Number of bytes of host memory used 11host_seconds 273.91 # Real time elapsed on the host 12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory --- 259 unchanged lines hidden (view full) --- 281system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory --- 259 unchanged lines hidden (view full) --- 281system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads |
| 289system.physmem.totQLat 4572923146 # Total ticks spent queuing 290system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM | 289system.physmem.totQLat 4572903146 # Total ticks spent queuing 290system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM |
| 291system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers | 291system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers |
| 292system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst | 292system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst |
| 293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 294system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst | 294system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst |
| 295system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 296system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s 297system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 298system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s 299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 300system.physmem.busUtil 0.06 # Data bus utilization in percentage 301system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 308system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes 309system.physmem.avgGap 8495676.27 # Average gap between requests 310system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined 311system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) 312system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) 313system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) 314system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) 315system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) | 295system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 296system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s 297system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 298system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s 299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 300system.physmem.busUtil 0.06 # Data bus utilization in percentage 301system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 308system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes 309system.physmem.avgGap 8495676.27 # Average gap between requests 310system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined 311system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) 312system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) 313system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) 314system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) 315system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) |
| 316system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ) 317system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ) 318system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ) | 316system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ) 317system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ) 318system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ) |
| 319system.physmem_0.averagePower 669.573415 # Core power per rank (mW) | 319system.physmem_0.averagePower 669.573415 # Core power per rank (mW) |
| 320system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states | 320system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states |
| 321system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states 322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 321system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states 322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 323system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states | 323system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states |
| 324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) 326system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) 327system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) 328system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) 329system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) | 324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) 326system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) 327system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) 328system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) 329system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) |
| 330system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ) 331system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ) 332system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ) | 330system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ) 331system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) 332system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) |
| 333system.physmem_1.averagePower 669.487743 # Core power per rank (mW) | 333system.physmem_1.averagePower 669.487743 # Core power per rank (mW) |
| 334system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states | 334system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states |
| 335system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states 336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 335system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states 336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 337system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states | 337system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states |
| 338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 339system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 345system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory --- 74 unchanged lines hidden (view full) --- 420system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst 422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst 423system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 424system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst 425system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst 426system.cpu0.dtb.inst_hits 0 # ITB inst hits 427system.cpu0.dtb.inst_misses 0 # ITB inst misses | 338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 339system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 345system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory --- 74 unchanged lines hidden (view full) --- 420system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst 422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst 423system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 424system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst 425system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst 426system.cpu0.dtb.inst_hits 0 # ITB inst hits 427system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 428system.cpu0.dtb.read_hits 25156507 # DTB read hits | 428system.cpu0.dtb.read_hits 25156508 # DTB read hits |
| 429system.cpu0.dtb.read_misses 6829 # DTB read misses | 429system.cpu0.dtb.read_misses 6829 # DTB read misses |
| 430system.cpu0.dtb.write_hits 18749940 # DTB write hits | 430system.cpu0.dtb.write_hits 18749941 # DTB write hits |
| 431system.cpu0.dtb.write_misses 1114 # DTB write misses 432system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 433system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 434system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 435system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 436system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB 437system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 438system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch 439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 440system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 431system.cpu0.dtb.write_misses 1114 # DTB write misses 432system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 433system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 434system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 435system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 436system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB 437system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 438system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch 439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 440system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 441system.cpu0.dtb.read_accesses 25163336 # DTB read accesses 442system.cpu0.dtb.write_accesses 18751054 # DTB write accesses | 441system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 442system.cpu0.dtb.write_accesses 18751055 # DTB write accesses |
| 443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 444system.cpu0.dtb.hits 43906447 # DTB hits | 444system.cpu0.dtb.hits 43906449 # DTB hits |
| 445system.cpu0.dtb.misses 7943 # DTB misses | 445system.cpu0.dtb.misses 7943 # DTB misses |
| 446system.cpu0.dtb.accesses 43914390 # DTB accesses | 446system.cpu0.dtb.accesses 43914392 # DTB accesses |
| 447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 73 unchanged lines hidden (view full) --- 528system.cpu0.itb.hits 119016789 # DTB hits 529system.cpu0.itb.misses 3349 # DTB misses 530system.cpu0.itb.accesses 119020138 # DTB accesses 531system.cpu0.numCycles 5739577940 # number of cpu cycles simulated 532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 534system.cpu0.kern.inst.arm 0 # number of arm instructions executed 535system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed | 447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 73 unchanged lines hidden (view full) --- 528system.cpu0.itb.hits 119016789 # DTB hits 529system.cpu0.itb.misses 3349 # DTB misses 530system.cpu0.itb.accesses 119020138 # DTB accesses 531system.cpu0.numCycles 5739577940 # number of cpu cycles simulated 532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 534system.cpu0.kern.inst.arm 0 # number of arm instructions executed 535system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed |
| 536system.cpu0.committedInsts 115352403 # Number of instructions committed 537system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed | 536system.cpu0.committedInsts 115352405 # Number of instructions committed 537system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed |
| 538system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses 539system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses 540system.cpu0.num_func_calls 12675179 # number of times a function call or return occured 541system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls 542system.cpu0.num_int_insts 123360698 # number of integer instructions 543system.cpu0.num_fp_insts 9756 # number of float instructions | 538system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses 539system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses 540system.cpu0.num_func_calls 12675179 # number of times a function call or return occured 541system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls 542system.cpu0.num_int_insts 123360698 # number of integer instructions 543system.cpu0.num_fp_insts 9756 # number of float instructions |
| 544system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read 545system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written | 544system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read 545system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written |
| 546system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read 547system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 546system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read 547system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 548system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read | 548system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read |
| 549system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written 550system.cpu0.num_mem_refs 45042977 # number of memory refs 551system.cpu0.num_load_insts 25408336 # Number of load instructions 552system.cpu0.num_store_insts 19634641 # Number of store instructions 553system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles 554system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles 555system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles 556system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles --- 30 unchanged lines hidden (view full) --- 587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 588system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction 589system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction 590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 592system.cpu0.op_class::total 143145074 # Class of executed instruction 593system.cpu0.dcache.tags.replacements 692159 # number of replacements 594system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use | 549system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written 550system.cpu0.num_mem_refs 45042977 # number of memory refs 551system.cpu0.num_load_insts 25408336 # Number of load instructions 552system.cpu0.num_store_insts 19634641 # Number of store instructions 553system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles 554system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles 555system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles 556system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles --- 30 unchanged lines hidden (view full) --- 587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 588system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction 589system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction 590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 592system.cpu0.op_class::total 143145074 # Class of executed instruction 593system.cpu0.dcache.tags.replacements 692159 # number of replacements 594system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use |
| 595system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks. | 595system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. |
| 596system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. | 596system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. |
| 597system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks. | 597system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. |
| 598system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. 599system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor 600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy 601system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 598system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. 599system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor 600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy 601system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy 602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 607system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses 608system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses 609system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits 610system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits 611system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits 612system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits | 607system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses 608system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses 609system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits 610system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits 611system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits 612system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits |
| 613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits 614system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits 615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits 616system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits 617system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits 618system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits | 613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits 614system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits 615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits 616system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits 617system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits 618system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits |
| 619system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits 620system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits 621system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits 622system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits | 619system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits 620system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits 621system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits 622system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits |
| 623system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses 624system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses 625system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses 626system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses 627system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses 628system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses 629system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses 630system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses 631system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses 632system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses 633system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses 634system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses 635system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses 636system.cpu0.dcache.overall_misses::total 848828 # number of overall misses | 623system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses 624system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses 625system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses 626system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses 627system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses 628system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses 629system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses 630system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses 631system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses 632system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses 633system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses 634system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses 635system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses 636system.cpu0.dcache.overall_misses::total 848828 # number of overall misses |
| 637system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles 638system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles | 637system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles 638system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles |
| 639system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles 640system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles 641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles 642system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles 643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles 644system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles | 639system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles 640system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles 641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles 642system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles 643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles 644system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles |
| 647system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles 648system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles 649system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles 650system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles 651system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses) 652system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses) | 647system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles 648system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles 649system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles 650system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles 651system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses) 652system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses) |
| 655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) 656system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) 658system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) 659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) 660system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) | 655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) 656system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) 658system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) 659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) 660system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) |
| 661system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses 662system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses 663system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses 664system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses | 661system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses 662system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses 663system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses 664system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses |
| 665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses 666system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses 667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses 668system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses 669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses 670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses 671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses 672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses 673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses 674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses 675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses 676system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses 677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses 678system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses | 665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses 666system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses 667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses 668system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses 669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses 670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses 671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses 672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses 673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses 674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses 675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses 676system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses 677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses 678system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses |
| 679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency 680system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency | 679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency 680system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency |
| 681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency 682system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency 683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency 684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency 685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency 686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency 687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency 682system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency 683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency 684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency 685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency 686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency 687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency 690system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency 691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency 692system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency | 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency 690system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency 691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency 692system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency |
| 693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks 700system.cpu0.dcache.writebacks::total 692159 # number of writebacks --- 20 unchanged lines hidden (view full) --- 721system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses 722system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses 723system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 724system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable 725system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 726system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 727system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 728system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses | 693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks 700system.cpu0.dcache.writebacks::total 692159 # number of writebacks --- 20 unchanged lines hidden (view full) --- 721system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses 722system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses 723system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 724system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable 725system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 726system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 727system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 728system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses |
| 729system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles 730system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles | 729system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles 730system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles |
| 731system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles 732system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles 733system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles 734system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles 735system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles 736system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles 737system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles 738system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles 739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles 740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles | 731system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles 732system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles 733system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles 734system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles 735system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles 736system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles 737system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles 738system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles 739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles 740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles |
| 741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles 742system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles 743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles 744system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles | 741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles 742system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles 743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles 744system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles |
| 745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles 746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles 747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles 748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles 749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses 750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses 751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses 752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses 753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses 754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses 755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses 756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses 757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses 758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses 759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses 760system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses 761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses 762system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses | 745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles 746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles 747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles 748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles 749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses 750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses 751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses 752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses 753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses 754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses 755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses 756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses 757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses 758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses 759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses 760system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses 761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses 762system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses |
| 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency 764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency | 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency 764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency |
| 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency 766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency 767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency 768system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency 769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency 770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency 771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency 772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency 773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency 766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency 767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency 768system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency 769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency 770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency 771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency 772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency 773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency 776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency 777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency 778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency | 775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency 776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency 777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency 778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency |
| 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency 780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency 781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency 782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency 783system.cpu0.icache.tags.replacements 1103881 # number of replacements 784system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use 785system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. 786system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. --- 185 unchanged lines hidden (view full) --- 972system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles 973system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles 974system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles 975system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles 976system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles 977system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles 978system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles 979system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles | 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency 780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency 781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency 782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency 783system.cpu0.icache.tags.replacements 1103881 # number of replacements 784system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use 785system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. 786system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. --- 185 unchanged lines hidden (view full) --- 972system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles 973system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles 974system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles 975system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles 976system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles 977system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles 978system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles 979system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles |
| 980system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles 981system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles | 980system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles 981system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles |
| 982system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles 983system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles 984system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles | 982system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles 983system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles 984system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles |
| 985system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles 986system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles | 985system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles 986system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles |
| 987system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles 988system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles 989system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles | 987system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles 988system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles 989system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles |
| 990system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles 991system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles | 990system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles 991system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles |
| 992system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) 993system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) 994system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) 995system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses) 996system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses) 997system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses) 998system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses) 999system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses) --- 51 unchanged lines hidden (view full) --- 1051system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency 1052system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency 1053system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency 1054system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency 1055system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency 1056system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency 1057system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency 1058system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency | 992system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) 993system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) 994system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) 995system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses) 996system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses) 997system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses) 998system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses) 999system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses) --- 51 unchanged lines hidden (view full) --- 1051system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency 1052system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency 1053system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency 1054system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency 1055system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency 1056system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency 1057system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency 1058system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency |
| 1059system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency 1060system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency | 1059system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency 1060system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency |
| 1061system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1062system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1063system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency | 1061system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1062system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1063system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency |
| 1064system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency 1065system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency | 1064system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency 1065system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency |
| 1066system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1067system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1068system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency | 1066system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1067system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1068system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency |
| 1069system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency 1070system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency | 1069system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency 1070system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency |
| 1071system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1072system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1073system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1074system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1075system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1076system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1077system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference 1078system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks --- 40 unchanged lines hidden (view full) --- 1119system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 1120system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 1121system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1122system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 1123system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses 1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles 1125system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles 1126system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles | 1071system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1072system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1073system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1074system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1075system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1076system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1077system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference 1078system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks --- 40 unchanged lines hidden (view full) --- 1119system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 1120system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 1121system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1122system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 1123system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses 1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles 1125system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles 1126system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles |
| 1127system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles 1128system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles | 1127system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles 1128system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles |
| 1129system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles 1130system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles 1131system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles 1132system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles 1133system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1134system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1135system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles 1136system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles 1137system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles 1138system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles | 1129system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles 1130system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles 1131system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles 1132system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles 1133system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1134system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1135system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles 1136system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles 1137system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles 1138system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles |
| 1139system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles 1140system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles | 1139system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles 1140system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles |
| 1141system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles 1143system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles | 1141system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles 1142system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles 1143system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles |
| 1144system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles 1145system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles | 1144system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles 1145system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles |
| 1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles 1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles 1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles | 1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles 1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles 1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles |
| 1149system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles 1150system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles 1151system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles | 1149system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles 1150system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles 1151system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles |
| 1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles 1153system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles 1154system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles 1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles 1156system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles 1157system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles 1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses 1159system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses --- 21 unchanged lines hidden (view full) --- 1181system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses 1182system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses 1183system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses 1184system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1185system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses 1186system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency 1187system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency 1188system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency | 1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles 1153system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles 1154system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles 1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles 1156system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles 1157system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles 1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses 1159system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses --- 21 unchanged lines hidden (view full) --- 1181system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses 1182system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses 1183system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses 1184system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1185system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses 1186system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency 1187system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency 1188system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency |
| 1189system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency 1190system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency | 1189system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency 1190system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency |
| 1191system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency 1192system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency 1193system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency 1194system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency 1195system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency 1196system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency 1197system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency 1198system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency 1199system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency 1200system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency | 1191system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency 1192system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency 1193system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency 1194system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency 1195system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency 1196system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency 1197system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency 1198system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency 1199system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency 1200system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency |
| 1201system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency 1202system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency | 1201system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency 1202system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency |
| 1203system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1204system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1205system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency | 1203system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1204system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1205system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency |
| 1206system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency 1207system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency | 1206system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency 1207system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency |
| 1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1210system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency | 1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1210system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency |
| 1211system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency 1212system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency 1213system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency | 1211system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency 1212system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency 1213system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency |
| 1214system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency 1215system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency 1216system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency 1217system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency 1218system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency 1219system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency 1220system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. 1221system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. --- 1285 unchanged lines hidden (view full) --- 2507system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles 2508system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles 2509system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles 2510system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles 2511system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles 2512system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles 2513system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles 2514system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles | 1214system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency 1215system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency 1216system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency 1217system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency 1218system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency 1219system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency 1220system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. 1221system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. --- 1285 unchanged lines hidden (view full) --- 2507system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles 2508system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles 2509system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles 2510system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles 2511system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles 2512system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles 2513system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles 2514system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles |
| 2515system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles 2516system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles | 2515system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles 2516system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles |
| 2517system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles 2518system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles 2519system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles | 2517system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles 2518system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles 2519system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles |
| 2520system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles | 2520system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles |
| 2521system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles 2522system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles 2523system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles | 2521system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles 2522system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles 2523system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles |
| 2524system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles 2525system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles | 2524system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles 2525system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles |
| 2526system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles 2527system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles 2528system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles | 2526system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles 2527system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles 2528system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles |
| 2529system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles | 2529system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles |
| 2530system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles 2531system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles 2532system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles | 2530system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles 2531system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles 2532system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles |
| 2533system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles 2534system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles | 2533system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles 2534system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles |
| 2535system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles 2536system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles 2537system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles | 2535system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles 2536system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles 2537system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles |
| 2538system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles | 2538system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles |
| 2539system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) 2540system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) 2541system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) 2542system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses) 2543system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses) 2544system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses) 2545system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses) 2546system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses) --- 76 unchanged lines hidden (view full) --- 2623system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency 2624system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency 2625system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency 2626system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency 2627system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency 2628system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency 2629system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency 2630system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency | 2539system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) 2540system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) 2541system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) 2542system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses) 2543system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses) 2544system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses) 2545system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses) 2546system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses) --- 76 unchanged lines hidden (view full) --- 2623system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency 2624system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency 2625system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency 2626system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency 2627system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency 2628system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency 2629system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency 2630system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency |
| 2631system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency 2632system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency | 2631system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency 2632system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency |
| 2633system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency 2634system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency 2635system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency | 2633system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency 2634system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency 2635system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency |
| 2636system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency | 2636system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency |
| 2637system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2638system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2639system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency | 2637system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2638system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2639system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency |
| 2640system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency 2641system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency | 2640system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency 2641system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency |
| 2642system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2643system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2644system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency | 2642system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2643system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2644system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency |
| 2645system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency | 2645system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency |
| 2646system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2647system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2648system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency | 2646system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2647system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2648system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency |
| 2649system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency 2650system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency | 2649system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency 2650system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency |
| 2651system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2652system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2653system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency | 2651system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2652system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2653system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency |
| 2654system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency | 2654system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency |
| 2655system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2656system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2657system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2658system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2659system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2660system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2661system.l2c.writebacks::writebacks 98955 # number of writebacks 2662system.l2c.writebacks::total 98955 # number of writebacks --- 64 unchanged lines hidden (view full) --- 2727system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32976000 # number of SCUpgradeReq MSHR miss cycles 2728system.l2c.SCUpgradeReq_mshr_miss_latency::total 46969000 # number of SCUpgradeReq MSHR miss cycles 2729system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973980500 # number of ReadExReq MSHR miss cycles 2730system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581545000 # number of ReadExReq MSHR miss cycles 2731system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 # number of ReadExReq MSHR miss cycles 2732system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles 2733system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles 2734system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles | 2655system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2656system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2657system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2658system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2659system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2660system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2661system.l2c.writebacks::writebacks 98955 # number of writebacks 2662system.l2c.writebacks::total 98955 # number of writebacks --- 64 unchanged lines hidden (view full) --- 2727system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32976000 # number of SCUpgradeReq MSHR miss cycles 2728system.l2c.SCUpgradeReq_mshr_miss_latency::total 46969000 # number of SCUpgradeReq MSHR miss cycles 2729system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973980500 # number of ReadExReq MSHR miss cycles 2730system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581545000 # number of ReadExReq MSHR miss cycles 2731system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 # number of ReadExReq MSHR miss cycles 2732system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles 2733system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles 2734system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles |
| 2735system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles 2736system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of ReadSharedReq MSHR miss cycles | 2735system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles 2736system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles |
| 2737system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles 2738system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles 2739system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles | 2737system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles 2738system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles 2739system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles |
| 2740system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles | 2740system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles |
| 2741system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles 2742system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles 2743system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles | 2741system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles 2742system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles 2743system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles |
| 2744system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles 2745system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles | 2744system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles 2745system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles |
| 2746system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles 2747system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles 2748system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles | 2746system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles 2747system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles 2748system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles |
| 2749system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles | 2749system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles |
| 2750system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles 2751system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles 2752system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles | 2750system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles 2751system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles 2752system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles |
| 2753system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles 2754system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles | 2753system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles 2754system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles |
| 2755system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles 2756system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles 2757system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles | 2755system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles 2756system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles 2757system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles |
| 2758system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles | 2758system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles |
| 2759system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles 2760system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles 2761system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles 2762system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles 2763system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles 2764system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles 2765system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles 2766system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles --- 44 unchanged lines hidden (view full) --- 2811system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency 2812system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency 2813system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency 2814system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency 2815system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency 2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency 2817system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency 2818system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency | 2759system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles 2760system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles 2761system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles 2762system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles 2763system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles 2764system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles 2765system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles 2766system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles --- 44 unchanged lines hidden (view full) --- 2811system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency 2812system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency 2813system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency 2814system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency 2815system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency 2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency 2817system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency 2818system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency |
| 2819system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency 2820system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency | 2819system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency 2820system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency |
| 2821system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency 2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency 2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency | 2821system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency 2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency 2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency |
| 2824system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency | 2824system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency |
| 2825system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2826system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2827system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency | 2825system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2826system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2827system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency |
| 2828system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency 2829system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency | 2828system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency 2829system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency |
| 2830system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2831system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2832system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency | 2830system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2831system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2832system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency |
| 2833system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency | 2833system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency |
| 2834system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2835system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2836system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency | 2834system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2835system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2836system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency |
| 2837system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency 2838system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency | 2837system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency 2838system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency |
| 2839system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2840system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2841system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency | 2839system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2840system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2841system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency |
| 2842system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency | 2842system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency |
| 2843system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency 2844system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency 2845system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency 2846system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency 2847system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency 2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency 2849system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency 2850system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency --- 152 unchanged lines hidden --- | 2843system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency 2844system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency 2845system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency 2846system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency 2847system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency 2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency 2849system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency 2850system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency --- 152 unchanged lines hidden --- |