| stats.txt (11014:863d314f6356) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.868749 # Number of seconds simulated 4sim_ticks 2868748596000 # Number of ticks simulated 5final_tick 2868748596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.871120 # Number of seconds simulated 4sim_ticks 2871119862000 # Number of ticks simulated 5final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 740337 # Simulator instruction rate (inst/s) 8host_op_rate 895502 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16150564794 # Simulator tick rate (ticks/s) 10host_mem_usage 599396 # Number of bytes of host memory used 11host_seconds 177.63 # Real time elapsed on the host 12sim_insts 131502488 # Number of instructions simulated 13sim_ops 159063828 # Number of ops (including micro ops) simulated | 7host_inst_rate 654504 # Simulator instruction rate (inst/s) 8host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14285860596 # Simulator tick rate (ticks/s) 10host_mem_usage 653456 # Number of bytes of host memory used 11host_seconds 200.98 # Real time elapsed on the host 12sim_insts 131539806 # Number of instructions simulated 13sim_ops 159111212 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1184036 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1278116 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8584576 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 111060 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 568976 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 412800 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 25system.physmem.bytes_read::total 12141100 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 1184036 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 111060 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 1295096 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 8715904 # Number of bytes written to this memory | 25system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory |
| 30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::total 8733468 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory | 32system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory 33system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.inst 26954 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 20490 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 134134 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 1890 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 8910 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 6450 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory |
| 41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::total 198852 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 136186 # Number of write requests responded to by this memory | 42system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory |
| 44system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 44system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::total 140577 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory 47system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu0.inst 412736 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 445531 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 2992446 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 38714 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 198336 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 143895 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 4232194 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 412736 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 38714 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 451450 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 3038225 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_write::total 3044348 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 3038225 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) |
| 67system.physmem.bw_total::cpu0.inst 412736 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 451639 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 2992446 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 38714 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 198350 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 143895 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 7276541 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 198852 # Number of read requests accepted 76system.physmem.writeReqs 140577 # Number of write requests accepted 77system.physmem.readBursts 198852 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 140577 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 12717568 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue 81system.physmem.bytesWritten 8745536 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 12141100 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 8733468 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue | 67system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 196438 # Number of read requests accepted 76system.physmem.writeReqs 139355 # Number of write requests accepted 77system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue 81system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue |
| 85system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one | 85system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one |
| 86system.physmem.neitherReadNorWriteReqs 48892 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 12039 # Per bank write bursts 88system.physmem.perBankRdBursts::1 11932 # Per bank write bursts 89system.physmem.perBankRdBursts::2 12219 # Per bank write bursts 90system.physmem.perBankRdBursts::3 12193 # Per bank write bursts 91system.physmem.perBankRdBursts::4 20606 # Per bank write bursts 92system.physmem.perBankRdBursts::5 12429 # Per bank write bursts 93system.physmem.perBankRdBursts::6 12151 # Per bank write bursts 94system.physmem.perBankRdBursts::7 12313 # Per bank write bursts 95system.physmem.perBankRdBursts::8 12521 # Per bank write bursts 96system.physmem.perBankRdBursts::9 12643 # Per bank write bursts 97system.physmem.perBankRdBursts::10 11981 # Per bank write bursts 98system.physmem.perBankRdBursts::11 11107 # Per bank write bursts 99system.physmem.perBankRdBursts::12 11212 # Per bank write bursts 100system.physmem.perBankRdBursts::13 11639 # Per bank write bursts 101system.physmem.perBankRdBursts::14 10708 # Per bank write bursts 102system.physmem.perBankRdBursts::15 11019 # Per bank write bursts 103system.physmem.perBankWrBursts::0 8788 # Per bank write bursts 104system.physmem.perBankWrBursts::1 8813 # Per bank write bursts 105system.physmem.perBankWrBursts::2 9145 # Per bank write bursts 106system.physmem.perBankWrBursts::3 8891 # Per bank write bursts 107system.physmem.perBankWrBursts::4 8356 # Per bank write bursts 108system.physmem.perBankWrBursts::5 8969 # Per bank write bursts 109system.physmem.perBankWrBursts::6 8864 # Per bank write bursts 110system.physmem.perBankWrBursts::7 8722 # Per bank write bursts 111system.physmem.perBankWrBursts::8 9036 # Per bank write bursts 112system.physmem.perBankWrBursts::9 9148 # Per bank write bursts 113system.physmem.perBankWrBursts::10 8611 # Per bank write bursts 114system.physmem.perBankWrBursts::11 8177 # Per bank write bursts 115system.physmem.perBankWrBursts::12 8063 # Per bank write bursts 116system.physmem.perBankWrBursts::13 7981 # Per bank write bursts 117system.physmem.perBankWrBursts::14 7509 # Per bank write bursts 118system.physmem.perBankWrBursts::15 7576 # Per bank write bursts | 86system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 11406 # Per bank write bursts 88system.physmem.perBankRdBursts::1 11655 # Per bank write bursts 89system.physmem.perBankRdBursts::2 11752 # Per bank write bursts 90system.physmem.perBankRdBursts::3 11575 # Per bank write bursts 91system.physmem.perBankRdBursts::4 20585 # Per bank write bursts 92system.physmem.perBankRdBursts::5 12467 # Per bank write bursts 93system.physmem.perBankRdBursts::6 12095 # Per bank write bursts 94system.physmem.perBankRdBursts::7 12222 # Per bank write bursts 95system.physmem.perBankRdBursts::8 12044 # Per bank write bursts 96system.physmem.perBankRdBursts::9 12120 # Per bank write bursts 97system.physmem.perBankRdBursts::10 11627 # Per bank write bursts 98system.physmem.perBankRdBursts::11 11103 # Per bank write bursts 99system.physmem.perBankRdBursts::12 11588 # Per bank write bursts 100system.physmem.perBankRdBursts::13 11719 # Per bank write bursts 101system.physmem.perBankRdBursts::14 10853 # Per bank write bursts 102system.physmem.perBankRdBursts::15 11470 # Per bank write bursts 103system.physmem.perBankWrBursts::0 8250 # Per bank write bursts 104system.physmem.perBankWrBursts::1 8603 # Per bank write bursts 105system.physmem.perBankWrBursts::2 8782 # Per bank write bursts 106system.physmem.perBankWrBursts::3 8359 # Per bank write bursts 107system.physmem.perBankWrBursts::4 8401 # Per bank write bursts 108system.physmem.perBankWrBursts::5 9093 # Per bank write bursts 109system.physmem.perBankWrBursts::6 8866 # Per bank write bursts 110system.physmem.perBankWrBursts::7 8828 # Per bank write bursts 111system.physmem.perBankWrBursts::8 8708 # Per bank write bursts 112system.physmem.perBankWrBursts::9 8716 # Per bank write bursts 113system.physmem.perBankWrBursts::10 8411 # Per bank write bursts 114system.physmem.perBankWrBursts::11 8212 # Per bank write bursts 115system.physmem.perBankWrBursts::12 8400 # Per bank write bursts 116system.physmem.perBankWrBursts::13 8108 # Per bank write bursts 117system.physmem.perBankWrBursts::14 7766 # Per bank write bursts 118system.physmem.perBankWrBursts::15 7939 # Per bank write bursts |
| 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 120system.physmem.numWrRetry 39 # Number of times write queue was full causing retry 121system.physmem.totGap 2868748135500 # Total gap between requests | 120system.physmem.numWrRetry 25 # Number of times write queue was full causing retry 121system.physmem.totGap 2871119474000 # Total gap between requests |
| 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 9731 # Read request sizes (log2) 125system.physmem.readPktSize::3 28 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) | 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 9731 # Read request sizes (log2) 125system.physmem.readPktSize::3 28 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 128system.physmem.readPktSize::6 189093 # Read request sizes (log2) | 128system.physmem.readPktSize::6 186679 # Read request sizes (log2) |
| 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 4391 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) | 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 4391 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 135system.physmem.writePktSize::6 136186 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 138565 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 16001 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 10431 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 8838 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 7035 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 5529 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 4705 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 3918 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 3439 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 73 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see | 135system.physmem.writePktSize::6 134964 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see |
| 153system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see | 153system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see |
| 154system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see | 154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::15 2660 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 3121 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 5889 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 6298 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 6719 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 6977 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 8373 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 9929 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 9268 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 9147 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 8525 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 8846 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 10151 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 8179 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 7567 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 7217 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 252 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 245 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 148 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 160 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 144 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 60 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 133 # What write queue length does an incoming req see 232system.physmem.bytesPerActivate::samples 88033 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 243.806754 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 138.095781 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 304.392225 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 45989 52.24% 52.24% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 18103 20.56% 72.80% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 5912 6.72% 79.52% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 3673 4.17% 83.69% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 2470 2.81% 86.50% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 1565 1.78% 88.28% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 995 1.13% 89.41% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 958 1.09% 90.49% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 8368 9.51% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 88033 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 29.243709 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 545.811163 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 20.110228 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 18.616765 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 12.492638 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-19 5748 84.59% 84.59% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::20-23 291 4.28% 88.87% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::24-27 178 2.62% 91.49% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::28-31 60 0.88% 92.38% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-35 79 1.16% 93.54% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::36-39 156 2.30% 95.84% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::40-43 28 0.41% 96.25% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::44-47 7 0.10% 96.35% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::48-51 12 0.18% 96.53% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::52-55 7 0.10% 96.63% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::56-59 9 0.13% 96.76% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::60-63 7 0.10% 96.87% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-67 161 2.37% 99.23% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::68-71 3 0.04% 99.28% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::72-75 4 0.06% 99.34% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::76-79 11 0.16% 99.50% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::80-83 3 0.04% 99.54% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::92-95 2 0.03% 99.59% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::116-119 1 0.01% 99.62% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::124-127 3 0.04% 99.66% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::140-143 1 0.01% 99.84% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::164-167 4 0.06% 99.90% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::172-175 1 0.01% 99.91% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::176-179 5 0.07% 99.99% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads 286system.physmem.totQLat 4722732900 # Total ticks spent queuing 287system.physmem.totMemAccLat 8448582900 # Total ticks spent from burst creation until serviced by the DRAM 288system.physmem.totBusLat 993560000 # Total ticks spent in databus transfers 289system.physmem.avgQLat 23766.72 # Average queueing delay per DRAM burst | 183system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see 232system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads 289system.physmem.totQLat 4505900396 # Total ticks spent queuing 290system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM 291system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers 292system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst |
| 290system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 291system.physmem.avgMemAccLat 42516.72 # Average memory access latency per DRAM burst 292system.physmem.avgRdBW 4.43 # Average DRAM read bandwidth in MiByte/s 293system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 294system.physmem.avgRdBWSys 4.23 # Average system read bandwidth in MiByte/s 295system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s | 294system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst 295system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s 296system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s 297system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s 298system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s |
| 296system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 297system.physmem.busUtil 0.06 # Data bus utilization in percentage 298system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 299system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 300system.physmem.busUtil 0.06 # Data bus utilization in percentage 301system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 300system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing 301system.physmem.avgWrQLen 22.76 # Average write queue length when enqueuing 302system.physmem.readRowHits 166188 # Number of row buffer hits during reads 303system.physmem.writeRowHits 81139 # Number of row buffer hits during writes 304system.physmem.readRowHitRate 83.63 # Row buffer hit rate for reads 305system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes 306system.physmem.avgGap 8451688.38 # Average gap between requests 307system.physmem.pageHitRate 73.74 # Row buffer hit rate, read and write combined 308system.physmem_0.actEnergy 346580640 # Energy for activate commands per rank (pJ) 309system.physmem_0.preEnergy 189106500 # Energy for precharge commands per rank (pJ) 310system.physmem_0.readEnergy 825871800 # Energy for read commands per rank (pJ) 311system.physmem_0.writeEnergy 457151040 # Energy for write commands per rank (pJ) 312system.physmem_0.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) 313system.physmem_0.actBackEnergy 84248156880 # Energy for active background per rank (pJ) 314system.physmem_0.preBackEnergy 1647343810500 # Energy for precharge background per rank (pJ) 315system.physmem_0.totalEnergy 1920782998080 # Total energy per rank (pJ) 316system.physmem_0.averagePower 669.555658 # Core power per rank (mW) 317system.physmem_0.memoryStateTime::IDLE 2740372132788 # Time in different power states 318system.physmem_0.memoryStateTime::REF 95793620000 # Time in different power states | 303system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 304system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing 305system.physmem.readRowHits 163849 # Number of row buffer hits during reads 306system.physmem.writeRowHits 80221 # Number of row buffer hits during writes 307system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads 308system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes 309system.physmem.avgGap 8550266.01 # Average gap between requests 310system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined 311system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) 312system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) 313system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) 314system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) 315system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) 316system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) 317system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) 318system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) 319system.physmem_0.averagePower 669.601510 # Core power per rank (mW) 320system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states 321system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states |
| 319system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 320system.physmem_0.memoryStateTime::ACT 32582747712 # Time in different power states | 323system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states |
| 321system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 322system.physmem_1.actEnergy 318948840 # Energy for activate commands per rank (pJ) 323system.physmem_1.preEnergy 174029625 # Energy for precharge commands per rank (pJ) 324system.physmem_1.readEnergy 724074000 # Energy for read commands per rank (pJ) 325system.physmem_1.writeEnergy 428334480 # Energy for write commands per rank (pJ) 326system.physmem_1.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) 327system.physmem_1.actBackEnergy 83576818575 # Energy for active background per rank (pJ) 328system.physmem_1.preBackEnergy 1647932703750 # Energy for precharge background per rank (pJ) 329system.physmem_1.totalEnergy 1920527229990 # Total energy per rank (pJ) 330system.physmem_1.averagePower 669.466501 # Core power per rank (mW) 331system.physmem_1.memoryStateTime::IDLE 2741353761866 # Time in different power states 332system.physmem_1.memoryStateTime::REF 95793620000 # Time in different power states | 325system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) 326system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) 327system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) 328system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) 329system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) 330system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) 331system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) 332system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) 333system.physmem_1.averagePower 669.513716 # Core power per rank (mW) 334system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states 335system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states |
| 333system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 334system.physmem_1.memoryStateTime::ACT 31595469384 # Time in different power states | 337system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states |
| 335system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 337system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 338system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 339system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 340system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 341system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 342system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory --- 39 unchanged lines hidden (view full) --- 382system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 383system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 384system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 385system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 386system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 387system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 388system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 389system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 339system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 340system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 342system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 345system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory --- 39 unchanged lines hidden (view full) --- 385system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 390system.cpu0.dtb.walker.walks 7824 # Table walker walks requested 391system.cpu0.dtb.walker.walksShort 7824 # Table walker walks initiated with short descriptors 392system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1442 # Level at which table walker walks with short descriptors terminate 393system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6382 # Level at which table walker walks with short descriptors terminate 394system.cpu0.dtb.walker.walkWaitTime::samples 7824 # Table walker wait (enqueue to first request) latency 395system.cpu0.dtb.walker.walkWaitTime::0 7824 100.00% 100.00% # Table walker wait (enqueue to first request) latency 396system.cpu0.dtb.walker.walkWaitTime::total 7824 # Table walker wait (enqueue to first request) latency 397system.cpu0.dtb.walker.walkCompletionTime::samples 6430 # Table walker service (enqueue to completion) latency 398system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401 # Table walker service (enqueue to completion) latency 399system.cpu0.dtb.walker.walkCompletionTime::gmean 9252.413387 # Table walker service (enqueue to completion) latency 400system.cpu0.dtb.walker.walkCompletionTime::stdev 6597.669693 # Table walker service (enqueue to completion) latency 401system.cpu0.dtb.walker.walkCompletionTime::0-32767 6417 99.80% 99.80% # Table walker service (enqueue to completion) latency 402system.cpu0.dtb.walker.walkCompletionTime::32768-65535 7 0.11% 99.91% # Table walker service (enqueue to completion) latency 403system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency 404system.cpu0.dtb.walker.walkCompletionTime::98304-131071 3 0.05% 99.98% # Table walker service (enqueue to completion) latency | 393system.cpu0.dtb.walker.walks 5019 # Table walker walks requested 394system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors 395system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate 396system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate 397system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency 398system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency 399system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency 400system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency 401system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency 402system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency 403system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency 404system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency 405system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency 406system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency |
| 405system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency | 407system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency |
| 406system.cpu0.dtb.walker.walkCompletionTime::total 6430 # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution 408system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution 409system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution 410system.cpu0.dtb.walker.walkPageSizes::4K 5027 78.18% 78.18% # Table walker page sizes translated 411system.cpu0.dtb.walker.walkPageSizes::1M 1403 21.82% 100.00% # Table walker page sizes translated 412system.cpu0.dtb.walker.walkPageSizes::total 6430 # Table walker page sizes translated 413system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7824 # Table walker requests started/completed, data/inst | 408system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution 410system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution 411system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution 412system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated 413system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated 414system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated 415system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst |
| 414system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 416system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 415system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst 416system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6430 # Table walker requests started/completed, data/inst | 417system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst 418system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst |
| 417system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 419system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 418system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6430 # Table walker requests started/completed, data/inst 419system.cpu0.dtb.walker.walkRequestOrigin::total 14254 # Table walker requests started/completed, data/inst | 420system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst |
| 420system.cpu0.dtb.inst_hits 0 # ITB inst hits 421system.cpu0.dtb.inst_misses 0 # ITB inst misses | 422system.cpu0.dtb.inst_hits 0 # ITB inst hits 423system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 422system.cpu0.dtb.read_hits 25236580 # DTB read hits 423system.cpu0.dtb.read_misses 6707 # DTB read misses 424system.cpu0.dtb.write_hits 18793560 # DTB write hits 425system.cpu0.dtb.write_misses 1117 # DTB write misses | 424system.cpu0.dtb.read_hits 23515104 # DTB read hits 425system.cpu0.dtb.read_misses 4346 # DTB read misses 426system.cpu0.dtb.write_hits 17278792 # DTB write hits 427system.cpu0.dtb.write_misses 673 # DTB write misses |
| 426system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 427system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 428system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 428system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 429system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 430system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 431system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 430system.cpu0.dtb.flush_entries 3444 # Number of entries that have been flushed from TLB | 432system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB |
| 431system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 433system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 432system.cpu0.dtb.prefetch_faults 1747 # Number of TLB faults due to prefetch | 434system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch |
| 433system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 435system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 434system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 435system.cpu0.dtb.read_accesses 25243287 # DTB read accesses 436system.cpu0.dtb.write_accesses 18794677 # DTB write accesses | 436system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions 437system.cpu0.dtb.read_accesses 23519450 # DTB read accesses 438system.cpu0.dtb.write_accesses 17279465 # DTB write accesses |
| 437system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 439system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 438system.cpu0.dtb.hits 44030140 # DTB hits 439system.cpu0.dtb.misses 7824 # DTB misses 440system.cpu0.dtb.accesses 44037964 # DTB accesses | 440system.cpu0.dtb.hits 40793896 # DTB hits 441system.cpu0.dtb.misses 5019 # DTB misses 442system.cpu0.dtb.accesses 40798915 # DTB accesses |
| 441system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 442system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 443system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 445system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 446system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 462system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 443system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 444system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 445system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 446system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 447system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 464system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 465system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 466system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 467system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 468system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 469system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 470system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 471system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 470system.cpu0.itb.walker.walks 3348 # Table walker walks requested 471system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors 472system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate 473system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 474system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency 475system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 476system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency 477system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency 478system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786 # Table walker service (enqueue to completion) latency 479system.cpu0.itb.walker.walkCompletionTime::gmean 9465.333686 # Table walker service (enqueue to completion) latency 480system.cpu0.itb.walker.walkCompletionTime::stdev 5846.917058 # Table walker service (enqueue to completion) latency 481system.cpu0.itb.walker.walkCompletionTime::0-8191 920 39.45% 39.45% # Table walker service (enqueue to completion) latency 482system.cpu0.itb.walker.walkCompletionTime::8192-16383 1284 55.06% 94.51% # Table walker service (enqueue to completion) latency 483system.cpu0.itb.walker.walkCompletionTime::16384-24575 84 3.60% 98.11% # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 99.57% # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::32768-40959 8 0.34% 99.91% # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution 490system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution 491system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution 492system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated 493system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated 494system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated | 472system.cpu0.itb.walker.walks 2305 # Table walker walks requested 473system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors 474system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate 475system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate 476system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency 477system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency 478system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency 479system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency 480system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency 481system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency 482system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency 483system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution 490system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution 491system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution 492system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated 493system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated 494system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated |
| 495system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 495system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 496system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst 497system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst | 496system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst 497system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst |
| 498system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 498system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 499system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst 500system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst 501system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst 502system.cpu0.itb.inst_hits 119342617 # ITB inst hits 503system.cpu0.itb.inst_misses 3348 # ITB inst misses | 499system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst 500system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst 501system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst 502system.cpu0.itb.inst_hits 111711640 # ITB inst hits 503system.cpu0.itb.inst_misses 2305 # ITB inst misses |
| 504system.cpu0.itb.read_hits 0 # DTB read hits 505system.cpu0.itb.read_misses 0 # DTB read misses 506system.cpu0.itb.write_hits 0 # DTB write hits 507system.cpu0.itb.write_misses 0 # DTB write misses 508system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 509system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 510system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 511system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 504system.cpu0.itb.read_hits 0 # DTB read hits 505system.cpu0.itb.read_misses 0 # DTB read misses 506system.cpu0.itb.write_hits 0 # DTB write hits 507system.cpu0.itb.write_misses 0 # DTB write misses 508system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 509system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 510system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 511system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 512system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB | 512system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB |
| 513system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 514system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 515system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 516system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 517system.cpu0.itb.read_accesses 0 # DTB read accesses 518system.cpu0.itb.write_accesses 0 # DTB write accesses | 513system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 514system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 515system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 516system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 517system.cpu0.itb.read_accesses 0 # DTB read accesses 518system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 519system.cpu0.itb.inst_accesses 119345965 # ITB inst accesses 520system.cpu0.itb.hits 119342617 # DTB hits 521system.cpu0.itb.misses 3348 # DTB misses 522system.cpu0.itb.accesses 119345965 # DTB accesses 523system.cpu0.numCycles 5737497192 # number of cpu cycles simulated | 519system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses 520system.cpu0.itb.hits 111711640 # DTB hits 521system.cpu0.itb.misses 2305 # DTB misses 522system.cpu0.itb.accesses 111713945 # DTB accesses 523system.cpu0.numCycles 5741309822 # number of cpu cycles simulated |
| 524system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 525system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 524system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 525system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 526system.cpu0.committedInsts 115654281 # Number of instructions committed 527system.cpu0.committedOps 139770289 # Number of ops (including micro ops) committed 528system.cpu0.num_int_alu_accesses 123734710 # Number of integer alu accesses 529system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses 530system.cpu0.num_func_calls 12768418 # number of times a function call or return occured 531system.cpu0.num_conditional_control_insts 15718242 # number of instructions that are conditional controls 532system.cpu0.num_int_insts 123734710 # number of integer instructions 533system.cpu0.num_fp_insts 9820 # number of float instructions 534system.cpu0.num_int_register_reads 227859200 # number of times the integer registers were read 535system.cpu0.num_int_register_writes 85998639 # number of times the integer registers were written 536system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read 537system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 538system.cpu0.num_cc_register_reads 506429091 # number of times the CC registers were read 539system.cpu0.num_cc_register_writes 52352971 # number of times the CC registers were written 540system.cpu0.num_mem_refs 45168124 # number of memory refs 541system.cpu0.num_load_insts 25488908 # Number of load instructions 542system.cpu0.num_store_insts 19679216 # Number of store instructions 543system.cpu0.num_idle_cycles 5463941135.084096 # Number of idle cycles 544system.cpu0.num_busy_cycles 273556056.915905 # Number of busy cycles 545system.cpu0.not_idle_fraction 0.047679 # Percentage of non-idle cycles 546system.cpu0.idle_fraction 0.952321 # Percentage of idle cycles 547system.cpu0.Branches 29223626 # Number of branches fetched 548system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 549system.cpu0.op_class::IntAlu 98271812 68.45% 68.45% # Class of executed instruction 550system.cpu0.op_class::IntMult 109732 0.08% 68.53% # Class of executed instruction 551system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction 552system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction 553system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction 554system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction 555system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction 556system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction 557system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction 558system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction 559system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction 560system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction 561system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction 562system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction 563system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction 564system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction 565system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction 566system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction 567system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction 568system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction 569system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction 570system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction 571system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction 572system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction 573system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction 574system.cpu0.op_class::SimdFloatMisc 8207 0.01% 68.54% # Class of executed instruction 575system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction 576system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction 577system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction 578system.cpu0.op_class::MemRead 25488908 17.75% 86.29% # Class of executed instruction 579system.cpu0.op_class::MemWrite 19679216 13.71% 100.00% # Class of executed instruction | 526system.cpu0.committedInsts 108455216 # Number of instructions committed 527system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed 528system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses 529system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses 530system.cpu0.num_func_calls 12371356 # number of times a function call or return occured 531system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls 532system.cpu0.num_int_insts 115934267 # number of integer instructions 533system.cpu0.num_fp_insts 4495 # number of float instructions 534system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read 535system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written 536system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read 537system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 538system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read 539system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written 540system.cpu0.num_mem_refs 41877995 # number of memory refs 541system.cpu0.num_load_insts 23749275 # Number of load instructions 542system.cpu0.num_store_insts 18128720 # Number of store instructions 543system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles 544system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles 545system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles 546system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles 547system.cpu0.Branches 27818534 # Number of branches fetched 548system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction 549system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction 550system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction 551system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction 552system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction 553system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction 554system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction 555system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction 556system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction 557system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction 558system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction 559system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction 560system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction 561system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction 562system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction 563system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction 564system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction 565system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction 566system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction 567system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction 568system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction 569system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction 570system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction 571system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction 572system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction 573system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction 574system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction 575system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction 576system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction 577system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction 578system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction 579system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction |
| 580system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 581system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 580system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 581system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 582system.cpu0.op_class::total 143560148 # Class of executed instruction | 582system.cpu0.op_class::total 134599461 # Class of executed instruction |
| 583system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 583system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 584system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed 585system.cpu0.dcache.tags.replacements 696532 # number of replacements 586system.cpu0.dcache.tags.tagsinuse 491.305468 # Cycle average of tags in use 587system.cpu0.dcache.tags.total_refs 43154174 # Total number of references to valid blocks. 588system.cpu0.dcache.tags.sampled_refs 697044 # Sample count of references to valid blocks. 589system.cpu0.dcache.tags.avg_refs 61.910258 # Average number of references to valid blocks. 590system.cpu0.dcache.tags.warmup_cycle 1135377000 # Cycle when the warmup percentage was hit. 591system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.305468 # Average occupied blocks per requestor 592system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959581 # Average percentage of cache occupancy 593system.cpu0.dcache.tags.occ_percent::total 0.959581 # Average percentage of cache occupancy 594system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 596system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 597system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id 598system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 599system.cpu0.dcache.tags.tag_accesses 88699037 # Number of tag accesses 600system.cpu0.dcache.tags.data_accesses 88699037 # Number of data accesses 601system.cpu0.dcache.ReadReq_hits::cpu0.data 23972048 # number of ReadReq hits 602system.cpu0.dcache.ReadReq_hits::total 23972048 # number of ReadReq hits 603system.cpu0.dcache.WriteReq_hits::cpu0.data 18061887 # number of WriteReq hits 604system.cpu0.dcache.WriteReq_hits::total 18061887 # number of WriteReq hits 605system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318120 # number of SoftPFReq hits 606system.cpu0.dcache.SoftPFReq_hits::total 318120 # number of SoftPFReq hits 607system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365603 # number of LoadLockedReq hits 608system.cpu0.dcache.LoadLockedReq_hits::total 365603 # number of LoadLockedReq hits 609system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362648 # number of StoreCondReq hits 610system.cpu0.dcache.StoreCondReq_hits::total 362648 # number of StoreCondReq hits 611system.cpu0.dcache.demand_hits::cpu0.data 42033935 # number of demand (read+write) hits 612system.cpu0.dcache.demand_hits::total 42033935 # number of demand (read+write) hits 613system.cpu0.dcache.overall_hits::cpu0.data 42352055 # number of overall hits 614system.cpu0.dcache.overall_hits::total 42352055 # number of overall hits 615system.cpu0.dcache.ReadReq_misses::cpu0.data 398676 # number of ReadReq misses 616system.cpu0.dcache.ReadReq_misses::total 398676 # number of ReadReq misses 617system.cpu0.dcache.WriteReq_misses::cpu0.data 324664 # number of WriteReq misses 618system.cpu0.dcache.WriteReq_misses::total 324664 # number of WriteReq misses 619system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128643 # number of SoftPFReq misses 620system.cpu0.dcache.SoftPFReq_misses::total 128643 # number of SoftPFReq misses 621system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21706 # number of LoadLockedReq misses 622system.cpu0.dcache.LoadLockedReq_misses::total 21706 # number of LoadLockedReq misses 623system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19707 # number of StoreCondReq misses 624system.cpu0.dcache.StoreCondReq_misses::total 19707 # number of StoreCondReq misses 625system.cpu0.dcache.demand_misses::cpu0.data 723340 # number of demand (read+write) misses 626system.cpu0.dcache.demand_misses::total 723340 # number of demand (read+write) misses 627system.cpu0.dcache.overall_misses::cpu0.data 851983 # number of overall misses 628system.cpu0.dcache.overall_misses::total 851983 # number of overall misses 629system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5067389500 # number of ReadReq miss cycles 630system.cpu0.dcache.ReadReq_miss_latency::total 5067389500 # number of ReadReq miss cycles 631system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5162627000 # number of WriteReq miss cycles 632system.cpu0.dcache.WriteReq_miss_latency::total 5162627000 # number of WriteReq miss cycles 633system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330228000 # number of LoadLockedReq miss cycles 634system.cpu0.dcache.LoadLockedReq_miss_latency::total 330228000 # number of LoadLockedReq miss cycles 635system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435506500 # number of StoreCondReq miss cycles 636system.cpu0.dcache.StoreCondReq_miss_latency::total 435506500 # number of StoreCondReq miss cycles 637system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1585500 # number of StoreCondFailReq miss cycles 638system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1585500 # number of StoreCondFailReq miss cycles 639system.cpu0.dcache.demand_miss_latency::cpu0.data 10230016500 # number of demand (read+write) miss cycles 640system.cpu0.dcache.demand_miss_latency::total 10230016500 # number of demand (read+write) miss cycles 641system.cpu0.dcache.overall_miss_latency::cpu0.data 10230016500 # number of overall miss cycles 642system.cpu0.dcache.overall_miss_latency::total 10230016500 # number of overall miss cycles 643system.cpu0.dcache.ReadReq_accesses::cpu0.data 24370724 # number of ReadReq accesses(hits+misses) 644system.cpu0.dcache.ReadReq_accesses::total 24370724 # number of ReadReq accesses(hits+misses) 645system.cpu0.dcache.WriteReq_accesses::cpu0.data 18386551 # number of WriteReq accesses(hits+misses) 646system.cpu0.dcache.WriteReq_accesses::total 18386551 # number of WriteReq accesses(hits+misses) 647system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446763 # number of SoftPFReq accesses(hits+misses) 648system.cpu0.dcache.SoftPFReq_accesses::total 446763 # number of SoftPFReq accesses(hits+misses) 649system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387309 # number of LoadLockedReq accesses(hits+misses) 650system.cpu0.dcache.LoadLockedReq_accesses::total 387309 # number of LoadLockedReq accesses(hits+misses) 651system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382355 # number of StoreCondReq accesses(hits+misses) 652system.cpu0.dcache.StoreCondReq_accesses::total 382355 # number of StoreCondReq accesses(hits+misses) 653system.cpu0.dcache.demand_accesses::cpu0.data 42757275 # number of demand (read+write) accesses 654system.cpu0.dcache.demand_accesses::total 42757275 # number of demand (read+write) accesses 655system.cpu0.dcache.overall_accesses::cpu0.data 43204038 # number of overall (read+write) accesses 656system.cpu0.dcache.overall_accesses::total 43204038 # number of overall (read+write) accesses 657system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses 658system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses 659system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017658 # miss rate for WriteReq accesses 660system.cpu0.dcache.WriteReq_miss_rate::total 0.017658 # miss rate for WriteReq accesses 661system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287945 # miss rate for SoftPFReq accesses 662system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287945 # miss rate for SoftPFReq accesses 663system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056043 # miss rate for LoadLockedReq accesses 664system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056043 # miss rate for LoadLockedReq accesses 665system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051541 # miss rate for StoreCondReq accesses 666system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051541 # miss rate for StoreCondReq accesses 667system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016917 # miss rate for demand accesses 668system.cpu0.dcache.demand_miss_rate::total 0.016917 # miss rate for demand accesses 669system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019720 # miss rate for overall accesses 670system.cpu0.dcache.overall_miss_rate::total 0.019720 # miss rate for overall accesses 671system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656 # average ReadReq miss latency 672system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656 # average ReadReq miss latency 673system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802 # average WriteReq miss latency 674system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802 # average WriteReq miss latency 675system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639 # average LoadLockedReq miss latency 676system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639 # average LoadLockedReq miss latency 677system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22099.076470 # average StoreCondReq miss latency 678system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22099.076470 # average StoreCondReq miss latency | 584system.cpu0.kern.inst.quiesce 1796 # number of quiesce instructions executed 585system.cpu0.dcache.tags.replacements 588364 # number of replacements 586system.cpu0.dcache.tags.tagsinuse 493.639030 # Cycle average of tags in use 587system.cpu0.dcache.tags.total_refs 40011095 # Total number of references to valid blocks. 588system.cpu0.dcache.tags.sampled_refs 588715 # Sample count of references to valid blocks. 589system.cpu0.dcache.tags.avg_refs 67.963437 # Average number of references to valid blocks. 590system.cpu0.dcache.tags.warmup_cycle 1836356000 # Cycle when the warmup percentage was hit. 591system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.639030 # Average occupied blocks per requestor 592system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964139 # Average percentage of cache occupancy 593system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy 594system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id 596system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id 597system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id 598system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses 599system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses 600system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits 601system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits 602system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits 603system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits 604system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits 605system.cpu0.dcache.SoftPFReq_hits::total 300494 # number of SoftPFReq hits 606system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 340955 # number of LoadLockedReq hits 607system.cpu0.dcache.LoadLockedReq_hits::total 340955 # number of LoadLockedReq hits 608system.cpu0.dcache.StoreCondReq_hits::cpu0.data 337105 # number of StoreCondReq hits 609system.cpu0.dcache.StoreCondReq_hits::total 337105 # number of StoreCondReq hits 610system.cpu0.dcache.demand_hits::cpu0.data 38976372 # number of demand (read+write) hits 611system.cpu0.dcache.demand_hits::total 38976372 # number of demand (read+write) hits 612system.cpu0.dcache.overall_hits::cpu0.data 39276866 # number of overall hits 613system.cpu0.dcache.overall_hits::total 39276866 # number of overall hits 614system.cpu0.dcache.ReadReq_misses::cpu0.data 340778 # number of ReadReq misses 615system.cpu0.dcache.ReadReq_misses::total 340778 # number of ReadReq misses 616system.cpu0.dcache.WriteReq_misses::cpu0.data 289444 # number of WriteReq misses 617system.cpu0.dcache.WriteReq_misses::total 289444 # number of WriteReq misses 618system.cpu0.dcache.SoftPFReq_misses::cpu0.data 113643 # number of SoftPFReq misses 619system.cpu0.dcache.SoftPFReq_misses::total 113643 # number of SoftPFReq misses 620system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20322 # number of LoadLockedReq misses 621system.cpu0.dcache.LoadLockedReq_misses::total 20322 # number of LoadLockedReq misses 622system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19364 # number of StoreCondReq misses 623system.cpu0.dcache.StoreCondReq_misses::total 19364 # number of StoreCondReq misses 624system.cpu0.dcache.demand_misses::cpu0.data 630222 # number of demand (read+write) misses 625system.cpu0.dcache.demand_misses::total 630222 # number of demand (read+write) misses 626system.cpu0.dcache.overall_misses::cpu0.data 743865 # number of overall misses 627system.cpu0.dcache.overall_misses::total 743865 # number of overall misses 628system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4892226500 # number of ReadReq miss cycles 629system.cpu0.dcache.ReadReq_miss_latency::total 4892226500 # number of ReadReq miss cycles 630system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5708519500 # number of WriteReq miss cycles 631system.cpu0.dcache.WriteReq_miss_latency::total 5708519500 # number of WriteReq miss cycles 632system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329935000 # number of LoadLockedReq miss cycles 633system.cpu0.dcache.LoadLockedReq_miss_latency::total 329935000 # number of LoadLockedReq miss cycles 634system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454112500 # number of StoreCondReq miss cycles 635system.cpu0.dcache.StoreCondReq_miss_latency::total 454112500 # number of StoreCondReq miss cycles 636system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1575000 # number of StoreCondFailReq miss cycles 637system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1575000 # number of StoreCondFailReq miss cycles 638system.cpu0.dcache.demand_miss_latency::cpu0.data 10600746000 # number of demand (read+write) miss cycles 639system.cpu0.dcache.demand_miss_latency::total 10600746000 # number of demand (read+write) miss cycles 640system.cpu0.dcache.overall_miss_latency::cpu0.data 10600746000 # number of overall miss cycles 641system.cpu0.dcache.overall_miss_latency::total 10600746000 # number of overall miss cycles 642system.cpu0.dcache.ReadReq_accesses::cpu0.data 22708506 # number of ReadReq accesses(hits+misses) 643system.cpu0.dcache.ReadReq_accesses::total 22708506 # number of ReadReq accesses(hits+misses) 644system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898088 # number of WriteReq accesses(hits+misses) 645system.cpu0.dcache.WriteReq_accesses::total 16898088 # number of WriteReq accesses(hits+misses) 646system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 414137 # number of SoftPFReq accesses(hits+misses) 647system.cpu0.dcache.SoftPFReq_accesses::total 414137 # number of SoftPFReq accesses(hits+misses) 648system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 361277 # number of LoadLockedReq accesses(hits+misses) 649system.cpu0.dcache.LoadLockedReq_accesses::total 361277 # number of LoadLockedReq accesses(hits+misses) 650system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 356469 # number of StoreCondReq accesses(hits+misses) 651system.cpu0.dcache.StoreCondReq_accesses::total 356469 # number of StoreCondReq accesses(hits+misses) 652system.cpu0.dcache.demand_accesses::cpu0.data 39606594 # number of demand (read+write) accesses 653system.cpu0.dcache.demand_accesses::total 39606594 # number of demand (read+write) accesses 654system.cpu0.dcache.overall_accesses::cpu0.data 40020731 # number of overall (read+write) accesses 655system.cpu0.dcache.overall_accesses::total 40020731 # number of overall (read+write) accesses 656system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015007 # miss rate for ReadReq accesses 657system.cpu0.dcache.ReadReq_miss_rate::total 0.015007 # miss rate for ReadReq accesses 658system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017129 # miss rate for WriteReq accesses 659system.cpu0.dcache.WriteReq_miss_rate::total 0.017129 # miss rate for WriteReq accesses 660system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.274409 # miss rate for SoftPFReq accesses 661system.cpu0.dcache.SoftPFReq_miss_rate::total 0.274409 # miss rate for SoftPFReq accesses 662system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056250 # miss rate for LoadLockedReq accesses 663system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056250 # miss rate for LoadLockedReq accesses 664system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054322 # miss rate for StoreCondReq accesses 665system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054322 # miss rate for StoreCondReq accesses 666system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015912 # miss rate for demand accesses 667system.cpu0.dcache.demand_miss_rate::total 0.015912 # miss rate for demand accesses 668system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018587 # miss rate for overall accesses 669system.cpu0.dcache.overall_miss_rate::total 0.018587 # miss rate for overall accesses 670system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14356.051447 # average ReadReq miss latency 671system.cpu0.dcache.ReadReq_avg_miss_latency::total 14356.051447 # average ReadReq miss latency 672system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19722.362530 # average WriteReq miss latency 673system.cpu0.dcache.WriteReq_avg_miss_latency::total 19722.362530 # average WriteReq miss latency 674system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16235.360693 # average LoadLockedReq miss latency 675system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16235.360693 # average LoadLockedReq miss latency 676system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23451.378847 # average StoreCondReq miss latency 677system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23451.378847 # average StoreCondReq miss latency |
| 679system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 680system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 678system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 679system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 681system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14142.749606 # average overall miss latency 682system.cpu0.dcache.demand_avg_miss_latency::total 14142.749606 # average overall miss latency 683system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12007.301202 # average overall miss latency 684system.cpu0.dcache.overall_avg_miss_latency::total 12007.301202 # average overall miss latency | 680system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16820.653674 # average overall miss latency 681system.cpu0.dcache.demand_avg_miss_latency::total 16820.653674 # average overall miss latency 682system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14250.900365 # average overall miss latency 683system.cpu0.dcache.overall_avg_miss_latency::total 14250.900365 # average overall miss latency |
| 685system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 686system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 687system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 688system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 689system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 690system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 691system.cpu0.dcache.fast_writes 0 # number of fast writes performed 692system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 684system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 685system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 686system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 687system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 688system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 689system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 690system.cpu0.dcache.fast_writes 0 # number of fast writes performed 691system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 693system.cpu0.dcache.writebacks::writebacks 508357 # number of writebacks 694system.cpu0.dcache.writebacks::total 508357 # number of writebacks 695system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25412 # number of ReadReq MSHR hits 696system.cpu0.dcache.ReadReq_mshr_hits::total 25412 # number of ReadReq MSHR hits 697system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15099 # number of LoadLockedReq MSHR hits 698system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15099 # number of LoadLockedReq MSHR hits 699system.cpu0.dcache.demand_mshr_hits::cpu0.data 25412 # number of demand (read+write) MSHR hits 700system.cpu0.dcache.demand_mshr_hits::total 25412 # number of demand (read+write) MSHR hits 701system.cpu0.dcache.overall_mshr_hits::cpu0.data 25412 # number of overall MSHR hits 702system.cpu0.dcache.overall_mshr_hits::total 25412 # number of overall MSHR hits 703system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373264 # number of ReadReq MSHR misses 704system.cpu0.dcache.ReadReq_mshr_misses::total 373264 # number of ReadReq MSHR misses 705system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324664 # number of WriteReq MSHR misses 706system.cpu0.dcache.WriteReq_mshr_misses::total 324664 # number of WriteReq MSHR misses 707system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101205 # number of SoftPFReq MSHR misses 708system.cpu0.dcache.SoftPFReq_mshr_misses::total 101205 # number of SoftPFReq MSHR misses 709system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6607 # number of LoadLockedReq MSHR misses 710system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6607 # number of LoadLockedReq MSHR misses 711system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19707 # number of StoreCondReq MSHR misses 712system.cpu0.dcache.StoreCondReq_mshr_misses::total 19707 # number of StoreCondReq MSHR misses 713system.cpu0.dcache.demand_mshr_misses::cpu0.data 697928 # number of demand (read+write) MSHR misses 714system.cpu0.dcache.demand_mshr_misses::total 697928 # number of demand (read+write) MSHR misses 715system.cpu0.dcache.overall_mshr_misses::cpu0.data 799133 # number of overall MSHR misses 716system.cpu0.dcache.overall_mshr_misses::total 799133 # number of overall MSHR misses 717system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable 718system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32335 # number of ReadReq MSHR uncacheable 719system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28719 # number of WriteReq MSHR uncacheable 720system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28719 # number of WriteReq MSHR uncacheable 721system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses 722system.cpu0.dcache.overall_mshr_uncacheable_misses::total 61054 # number of overall MSHR uncacheable misses 723system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4299217000 # number of ReadReq MSHR miss cycles 724system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4299217000 # number of ReadReq MSHR miss cycles 725system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4837963000 # number of WriteReq MSHR miss cycles 726system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4837963000 # number of WriteReq MSHR miss cycles 727system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1611370000 # number of SoftPFReq MSHR miss cycles 728system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1611370000 # number of SoftPFReq MSHR miss cycles 729system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100016000 # number of LoadLockedReq MSHR miss cycles 730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100016000 # number of LoadLockedReq MSHR miss cycles 731system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 415846500 # number of StoreCondReq MSHR miss cycles 732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 415846500 # number of StoreCondReq MSHR miss cycles 733system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1538500 # number of StoreCondFailReq MSHR miss cycles 734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1538500 # number of StoreCondFailReq MSHR miss cycles 735system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9137180000 # number of demand (read+write) MSHR miss cycles 736system.cpu0.dcache.demand_mshr_miss_latency::total 9137180000 # number of demand (read+write) MSHR miss cycles 737system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10748550000 # number of overall MSHR miss cycles 738system.cpu0.dcache.overall_mshr_miss_latency::total 10748550000 # number of overall MSHR miss cycles 739system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6362298500 # number of ReadReq MSHR uncacheable cycles 740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6362298500 # number of ReadReq MSHR uncacheable cycles 741system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4936759500 # number of WriteReq MSHR uncacheable cycles 742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4936759500 # number of WriteReq MSHR uncacheable cycles 743system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11299058000 # number of overall MSHR uncacheable cycles 744system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11299058000 # number of overall MSHR uncacheable cycles 745system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015316 # mshr miss rate for ReadReq accesses 746system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015316 # mshr miss rate for ReadReq accesses 747system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017658 # mshr miss rate for WriteReq accesses 748system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017658 # mshr miss rate for WriteReq accesses 749system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226530 # mshr miss rate for SoftPFReq accesses 750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226530 # mshr miss rate for SoftPFReq accesses 751system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017059 # mshr miss rate for LoadLockedReq accesses 752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017059 # mshr miss rate for LoadLockedReq accesses 753system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051541 # mshr miss rate for StoreCondReq accesses 754system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051541 # mshr miss rate for StoreCondReq accesses 755system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016323 # mshr miss rate for demand accesses 756system.cpu0.dcache.demand_mshr_miss_rate::total 0.016323 # mshr miss rate for demand accesses 757system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses 758system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses 759system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11517.898860 # average ReadReq mshr miss latency 760system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11517.898860 # average ReadReq mshr miss latency 761system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14901.445802 # average WriteReq mshr miss latency 762system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14901.445802 # average WriteReq mshr miss latency 763system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15921.841806 # average SoftPFReq mshr miss latency 764system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15921.841806 # average SoftPFReq mshr miss latency 765system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15137.884062 # average LoadLockedReq mshr miss latency 766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15137.884062 # average LoadLockedReq mshr miss latency 767system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21101.461410 # average StoreCondReq mshr miss latency 768system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21101.461410 # average StoreCondReq mshr miss latency | 692system.cpu0.dcache.writebacks::writebacks 443107 # number of writebacks 693system.cpu0.dcache.writebacks::total 443107 # number of writebacks 694system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25234 # number of ReadReq MSHR hits 695system.cpu0.dcache.ReadReq_mshr_hits::total 25234 # number of ReadReq MSHR hits 696system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits 697system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 698system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14124 # number of LoadLockedReq MSHR hits 699system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14124 # number of LoadLockedReq MSHR hits 700system.cpu0.dcache.demand_mshr_hits::cpu0.data 25235 # number of demand (read+write) MSHR hits 701system.cpu0.dcache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits 702system.cpu0.dcache.overall_mshr_hits::cpu0.data 25235 # number of overall MSHR hits 703system.cpu0.dcache.overall_mshr_hits::total 25235 # number of overall MSHR hits 704system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 315544 # number of ReadReq MSHR misses 705system.cpu0.dcache.ReadReq_mshr_misses::total 315544 # number of ReadReq MSHR misses 706system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289443 # number of WriteReq MSHR misses 707system.cpu0.dcache.WriteReq_mshr_misses::total 289443 # number of WriteReq MSHR misses 708system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 86831 # number of SoftPFReq MSHR misses 709system.cpu0.dcache.SoftPFReq_mshr_misses::total 86831 # number of SoftPFReq MSHR misses 710system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6198 # number of LoadLockedReq MSHR misses 711system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6198 # number of LoadLockedReq MSHR misses 712system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19364 # number of StoreCondReq MSHR misses 713system.cpu0.dcache.StoreCondReq_mshr_misses::total 19364 # number of StoreCondReq MSHR misses 714system.cpu0.dcache.demand_mshr_misses::cpu0.data 604987 # number of demand (read+write) MSHR misses 715system.cpu0.dcache.demand_mshr_misses::total 604987 # number of demand (read+write) MSHR misses 716system.cpu0.dcache.overall_mshr_misses::cpu0.data 691818 # number of overall MSHR misses 717system.cpu0.dcache.overall_mshr_misses::total 691818 # number of overall MSHR misses 718system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable 719system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31738 # number of ReadReq MSHR uncacheable 720system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable 721system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28393 # number of WriteReq MSHR uncacheable 722system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses 723system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60131 # number of overall MSHR uncacheable misses 724system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4148741500 # number of ReadReq MSHR miss cycles 725system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4148741500 # number of ReadReq MSHR miss cycles 726system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5419061500 # number of WriteReq MSHR miss cycles 727system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5419061500 # number of WriteReq MSHR miss cycles 728system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1553984000 # number of SoftPFReq MSHR miss cycles 729system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1553984000 # number of SoftPFReq MSHR miss cycles 730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101488000 # number of LoadLockedReq MSHR miss cycles 731system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101488000 # number of LoadLockedReq MSHR miss cycles 732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434796500 # number of StoreCondReq MSHR miss cycles 733system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 434796500 # number of StoreCondReq MSHR miss cycles 734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1527000 # number of StoreCondFailReq MSHR miss cycles 735system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1527000 # number of StoreCondFailReq MSHR miss cycles 736system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9567803000 # number of demand (read+write) MSHR miss cycles 737system.cpu0.dcache.demand_mshr_miss_latency::total 9567803000 # number of demand (read+write) MSHR miss cycles 738system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11121787000 # number of overall MSHR miss cycles 739system.cpu0.dcache.overall_mshr_miss_latency::total 11121787000 # number of overall MSHR miss cycles 740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6274722500 # number of ReadReq MSHR uncacheable cycles 741system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6274722500 # number of ReadReq MSHR uncacheable cycles 742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086196500 # number of WriteReq MSHR uncacheable cycles 743system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086196500 # number of WriteReq MSHR uncacheable cycles 744system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11360919000 # number of overall MSHR uncacheable cycles 745system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11360919000 # number of overall MSHR uncacheable cycles 746system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013895 # mshr miss rate for ReadReq accesses 747system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013895 # mshr miss rate for ReadReq accesses 748system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017129 # mshr miss rate for WriteReq accesses 749system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017129 # mshr miss rate for WriteReq accesses 750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.209667 # mshr miss rate for SoftPFReq accesses 751system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.209667 # mshr miss rate for SoftPFReq accesses 752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017156 # mshr miss rate for LoadLockedReq accesses 753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017156 # mshr miss rate for LoadLockedReq accesses 754system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054322 # mshr miss rate for StoreCondReq accesses 755system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054322 # mshr miss rate for StoreCondReq accesses 756system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015275 # mshr miss rate for demand accesses 757system.cpu0.dcache.demand_mshr_miss_rate::total 0.015275 # mshr miss rate for demand accesses 758system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017286 # mshr miss rate for overall accesses 759system.cpu0.dcache.overall_mshr_miss_rate::total 0.017286 # mshr miss rate for overall accesses 760system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719 # average ReadReq mshr miss latency 761system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719 # average ReadReq mshr miss latency 762system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845 # average WriteReq mshr miss latency 763system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845 # average WriteReq mshr miss latency 764system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency 765system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency 766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency 767system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency 768system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency 769system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency |
| 769system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 771system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 771system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210 # average overall mshr miss latency 772system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210 # average overall mshr miss latency 773system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224 # average overall mshr miss latency 774system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224 # average overall mshr miss latency 775system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187 # average ReadReq mshr uncacheable latency 776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187 # average ReadReq mshr uncacheable latency 777system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582 # average WriteReq mshr uncacheable latency 778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171898.725582 # average WriteReq mshr uncacheable latency 779system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185066.629541 # average overall mshr uncacheable latency 780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 185066.629541 # average overall mshr uncacheable latency | 772system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15814.890237 # average overall mshr miss latency 773system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15814.890237 # average overall mshr miss latency 774system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16076.174659 # average overall mshr miss latency 775system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16076.174659 # average overall mshr miss latency 776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197703.777806 # average ReadReq mshr uncacheable latency 777system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 197703.777806 # average ReadReq mshr uncacheable latency 778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency 779system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency 780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency 781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency |
| 781system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 782system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 782system.cpu0.icache.tags.replacements 1105972 # number of replacements 783system.cpu0.icache.tags.tagsinuse 511.454897 # Cycle average of tags in use 784system.cpu0.icache.tags.total_refs 118236124 # Total number of references to valid blocks. 785system.cpu0.icache.tags.sampled_refs 1106484 # Sample count of references to valid blocks. 786system.cpu0.icache.tags.avg_refs 106.857509 # Average number of references to valid blocks. 787system.cpu0.icache.tags.warmup_cycle 13516114000 # Cycle when the warmup percentage was hit. 788system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454897 # Average occupied blocks per requestor 789system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998935 # Average percentage of cache occupancy 790system.cpu0.icache.tags.occ_percent::total 0.998935 # Average percentage of cache occupancy | 783system.cpu0.icache.tags.replacements 987035 # number of replacements 784system.cpu0.icache.tags.tagsinuse 511.323984 # Cycle average of tags in use 785system.cpu0.icache.tags.total_refs 110724084 # Total number of references to valid blocks. 786system.cpu0.icache.tags.sampled_refs 987547 # Sample count of references to valid blocks. 787system.cpu0.icache.tags.avg_refs 112.120318 # Average number of references to valid blocks. 788system.cpu0.icache.tags.warmup_cycle 14346160000 # Cycle when the warmup percentage was hit. 789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.323984 # Average occupied blocks per requestor 790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998680 # Average percentage of cache occupancy 791system.cpu0.icache.tags.occ_percent::total 0.998680 # Average percentage of cache occupancy |
| 791system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 792system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 792system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 793system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 794system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id | 793system.cpu0.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id 794system.cpu0.icache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id 795system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id |
| 795system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 796system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 796system.cpu0.icache.tags.tag_accesses 239791727 # Number of tag accesses 797system.cpu0.icache.tags.data_accesses 239791727 # Number of data accesses 798system.cpu0.icache.ReadReq_hits::cpu0.inst 118236124 # number of ReadReq hits 799system.cpu0.icache.ReadReq_hits::total 118236124 # number of ReadReq hits 800system.cpu0.icache.demand_hits::cpu0.inst 118236124 # number of demand (read+write) hits 801system.cpu0.icache.demand_hits::total 118236124 # number of demand (read+write) hits 802system.cpu0.icache.overall_hits::cpu0.inst 118236124 # number of overall hits 803system.cpu0.icache.overall_hits::total 118236124 # number of overall hits 804system.cpu0.icache.ReadReq_misses::cpu0.inst 1106493 # number of ReadReq misses 805system.cpu0.icache.ReadReq_misses::total 1106493 # number of ReadReq misses 806system.cpu0.icache.demand_misses::cpu0.inst 1106493 # number of demand (read+write) misses 807system.cpu0.icache.demand_misses::total 1106493 # number of demand (read+write) misses 808system.cpu0.icache.overall_misses::cpu0.inst 1106493 # number of overall misses 809system.cpu0.icache.overall_misses::total 1106493 # number of overall misses 810system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10938029500 # number of ReadReq miss cycles 811system.cpu0.icache.ReadReq_miss_latency::total 10938029500 # number of ReadReq miss cycles 812system.cpu0.icache.demand_miss_latency::cpu0.inst 10938029500 # number of demand (read+write) miss cycles 813system.cpu0.icache.demand_miss_latency::total 10938029500 # number of demand (read+write) miss cycles 814system.cpu0.icache.overall_miss_latency::cpu0.inst 10938029500 # number of overall miss cycles 815system.cpu0.icache.overall_miss_latency::total 10938029500 # number of overall miss cycles 816system.cpu0.icache.ReadReq_accesses::cpu0.inst 119342617 # number of ReadReq accesses(hits+misses) 817system.cpu0.icache.ReadReq_accesses::total 119342617 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.demand_accesses::cpu0.inst 119342617 # number of demand (read+write) accesses 819system.cpu0.icache.demand_accesses::total 119342617 # number of demand (read+write) accesses 820system.cpu0.icache.overall_accesses::cpu0.inst 119342617 # number of overall (read+write) accesses 821system.cpu0.icache.overall_accesses::total 119342617 # number of overall (read+write) accesses 822system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009272 # miss rate for ReadReq accesses 823system.cpu0.icache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses 824system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009272 # miss rate for demand accesses 825system.cpu0.icache.demand_miss_rate::total 0.009272 # miss rate for demand accesses 826system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009272 # miss rate for overall accesses 827system.cpu0.icache.overall_miss_rate::total 0.009272 # miss rate for overall accesses 828system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9885.312876 # average ReadReq miss latency 829system.cpu0.icache.ReadReq_avg_miss_latency::total 9885.312876 # average ReadReq miss latency 830system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency 831system.cpu0.icache.demand_avg_miss_latency::total 9885.312876 # average overall miss latency 832system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::total 9885.312876 # average overall miss latency | 797system.cpu0.icache.tags.tag_accesses 224410836 # Number of tag accesses 798system.cpu0.icache.tags.data_accesses 224410836 # Number of data accesses 799system.cpu0.icache.ReadReq_hits::cpu0.inst 110724084 # number of ReadReq hits 800system.cpu0.icache.ReadReq_hits::total 110724084 # number of ReadReq hits 801system.cpu0.icache.demand_hits::cpu0.inst 110724084 # number of demand (read+write) hits 802system.cpu0.icache.demand_hits::total 110724084 # number of demand (read+write) hits 803system.cpu0.icache.overall_hits::cpu0.inst 110724084 # number of overall hits 804system.cpu0.icache.overall_hits::total 110724084 # number of overall hits 805system.cpu0.icache.ReadReq_misses::cpu0.inst 987556 # number of ReadReq misses 806system.cpu0.icache.ReadReq_misses::total 987556 # number of ReadReq misses 807system.cpu0.icache.demand_misses::cpu0.inst 987556 # number of demand (read+write) misses 808system.cpu0.icache.demand_misses::total 987556 # number of demand (read+write) misses 809system.cpu0.icache.overall_misses::cpu0.inst 987556 # number of overall misses 810system.cpu0.icache.overall_misses::total 987556 # number of overall misses 811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10780435500 # number of ReadReq miss cycles 812system.cpu0.icache.ReadReq_miss_latency::total 10780435500 # number of ReadReq miss cycles 813system.cpu0.icache.demand_miss_latency::cpu0.inst 10780435500 # number of demand (read+write) miss cycles 814system.cpu0.icache.demand_miss_latency::total 10780435500 # number of demand (read+write) miss cycles 815system.cpu0.icache.overall_miss_latency::cpu0.inst 10780435500 # number of overall miss cycles 816system.cpu0.icache.overall_miss_latency::total 10780435500 # number of overall miss cycles 817system.cpu0.icache.ReadReq_accesses::cpu0.inst 111711640 # number of ReadReq accesses(hits+misses) 818system.cpu0.icache.ReadReq_accesses::total 111711640 # number of ReadReq accesses(hits+misses) 819system.cpu0.icache.demand_accesses::cpu0.inst 111711640 # number of demand (read+write) accesses 820system.cpu0.icache.demand_accesses::total 111711640 # number of demand (read+write) accesses 821system.cpu0.icache.overall_accesses::cpu0.inst 111711640 # number of overall (read+write) accesses 822system.cpu0.icache.overall_accesses::total 111711640 # number of overall (read+write) accesses 823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008840 # miss rate for ReadReq accesses 824system.cpu0.icache.ReadReq_miss_rate::total 0.008840 # miss rate for ReadReq accesses 825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008840 # miss rate for demand accesses 826system.cpu0.icache.demand_miss_rate::total 0.008840 # miss rate for demand accesses 827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008840 # miss rate for overall accesses 828system.cpu0.icache.overall_miss_rate::total 0.008840 # miss rate for overall accesses 829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10916.277659 # average ReadReq miss latency 830system.cpu0.icache.ReadReq_avg_miss_latency::total 10916.277659 # average ReadReq miss latency 831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency 832system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency 833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency 834system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency |
| 834system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 835system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 836system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 837system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 838system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 839system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 840system.cpu0.icache.fast_writes 0 # number of fast writes performed 841system.cpu0.icache.cache_copies 0 # number of cache copies performed | 835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu0.icache.fast_writes 0 # number of fast writes performed 842system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 842system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106493 # number of ReadReq MSHR misses 843system.cpu0.icache.ReadReq_mshr_misses::total 1106493 # number of ReadReq MSHR misses 844system.cpu0.icache.demand_mshr_misses::cpu0.inst 1106493 # number of demand (read+write) MSHR misses 845system.cpu0.icache.demand_mshr_misses::total 1106493 # number of demand (read+write) MSHR misses 846system.cpu0.icache.overall_mshr_misses::cpu0.inst 1106493 # number of overall MSHR misses 847system.cpu0.icache.overall_mshr_misses::total 1106493 # number of overall MSHR misses | 843system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 987556 # number of ReadReq MSHR misses 844system.cpu0.icache.ReadReq_mshr_misses::total 987556 # number of ReadReq MSHR misses 845system.cpu0.icache.demand_mshr_misses::cpu0.inst 987556 # number of demand (read+write) MSHR misses 846system.cpu0.icache.demand_mshr_misses::total 987556 # number of demand (read+write) MSHR misses 847system.cpu0.icache.overall_mshr_misses::cpu0.inst 987556 # number of overall MSHR misses 848system.cpu0.icache.overall_mshr_misses::total 987556 # number of overall MSHR misses |
| 848system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 849system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 850system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 851system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses | 849system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 850system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 851system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 852system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses |
| 852system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10384783000 # number of ReadReq MSHR miss cycles 853system.cpu0.icache.ReadReq_mshr_miss_latency::total 10384783000 # number of ReadReq MSHR miss cycles 854system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10384783000 # number of demand (read+write) MSHR miss cycles 855system.cpu0.icache.demand_mshr_miss_latency::total 10384783000 # number of demand (read+write) MSHR miss cycles 856system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10384783000 # number of overall MSHR miss cycles 857system.cpu0.icache.overall_mshr_miss_latency::total 10384783000 # number of overall MSHR miss cycles 858system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 800795500 # number of ReadReq MSHR uncacheable cycles 859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 800795500 # number of ReadReq MSHR uncacheable cycles 860system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 800795500 # number of overall MSHR uncacheable cycles 861system.cpu0.icache.overall_mshr_uncacheable_latency::total 800795500 # number of overall MSHR uncacheable cycles 862system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for ReadReq accesses 863system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009272 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for demand accesses 865system.cpu0.icache.demand_mshr_miss_rate::total 0.009272 # mshr miss rate for demand accesses 866system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for overall accesses 867system.cpu0.icache.overall_mshr_miss_rate::total 0.009272 # mshr miss rate for overall accesses 868system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average ReadReq mshr miss latency 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9385.312876 # average ReadReq mshr miss latency 870system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency 872system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency 874system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average ReadReq mshr uncacheable latency 875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136 # average ReadReq mshr uncacheable latency 876system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average overall mshr uncacheable latency 877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136 # average overall mshr uncacheable latency | 853system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10286657500 # number of ReadReq MSHR miss cycles 854system.cpu0.icache.ReadReq_mshr_miss_latency::total 10286657500 # number of ReadReq MSHR miss cycles 855system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10286657500 # number of demand (read+write) MSHR miss cycles 856system.cpu0.icache.demand_mshr_miss_latency::total 10286657500 # number of demand (read+write) MSHR miss cycles 857system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10286657500 # number of overall MSHR miss cycles 858system.cpu0.icache.overall_mshr_miss_latency::total 10286657500 # number of overall MSHR miss cycles 859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles 860system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles 861system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles 862system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles 863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for ReadReq accesses 864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008840 # mshr miss rate for ReadReq accesses 865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for demand accesses 866system.cpu0.icache.demand_mshr_miss_rate::total 0.008840 # mshr miss rate for demand accesses 867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for overall accesses 868system.cpu0.icache.overall_mshr_miss_rate::total 0.008840 # mshr miss rate for overall accesses 869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average ReadReq mshr miss latency 870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10416.277659 # average ReadReq mshr miss latency 871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency 872system.cpu0.icache.demand_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency 873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency 874system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency 875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency 876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency 877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency 878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency |
| 878system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 879system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841098 # number of hwpf issued 880system.cpu0.l2cache.prefetcher.pfIdentified 1841106 # number of prefetch candidates identified 881system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue | 880system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued 881system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified 882system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue |
| 882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 883system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 884system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 884system.cpu0.l2cache.prefetcher.pfSpanPage 237750 # number of prefetches not generated due to page crossing 885system.cpu0.l2cache.tags.replacements 269395 # number of replacements 886system.cpu0.l2cache.tags.tagsinuse 16110.328705 # Cycle average of tags in use 887system.cpu0.l2cache.tags.total_refs 3241181 # Total number of references to valid blocks. 888system.cpu0.l2cache.tags.sampled_refs 285612 # Sample count of references to valid blocks. 889system.cpu0.l2cache.tags.avg_refs 11.348196 # Average number of references to valid blocks. | 885system.cpu0.l2cache.prefetcher.pfSpanPage 209215 # number of prefetches not generated due to page crossing 886system.cpu0.l2cache.tags.replacements 245604 # number of replacements 887system.cpu0.l2cache.tags.tagsinuse 16082.851224 # Cycle average of tags in use 888system.cpu0.l2cache.tags.total_refs 2813687 # Total number of references to valid blocks. 889system.cpu0.l2cache.tags.sampled_refs 260278 # Sample count of references to valid blocks. 890system.cpu0.l2cache.tags.avg_refs 10.810314 # Average number of references to valid blocks. |
| 890system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 891system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 891system.cpu0.l2cache.tags.occ_blocks::writebacks 7729.941983 # Average occupied blocks per requestor 892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.543117 # Average occupied blocks per requestor 893system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.104661 # Average occupied blocks per requestor 894system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4692.501202 # Average occupied blocks per requestor 895system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1977.796502 # Average occupied blocks per requestor 896system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1707.441239 # Average occupied blocks per requestor 897system.cpu0.l2cache.tags.occ_percent::writebacks 0.471798 # Average percentage of cache occupancy 898system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000155 # Average percentage of cache occupancy 899system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy 900system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.286408 # Average percentage of cache occupancy 901system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120715 # Average percentage of cache occupancy 902system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104214 # Average percentage of cache occupancy 903system.cpu0.l2cache.tags.occ_percent::total 0.983296 # Average percentage of cache occupancy 904system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1097 # Occupied blocks per task id 905system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 906system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15114 # Occupied blocks per task id 907system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 908system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id 909system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 382 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3320 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7689 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3966 # Occupied blocks per task id 918system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066956 # Percentage of cache occupancy per task id 919system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 920system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922485 # Percentage of cache occupancy per task id 921system.cpu0.l2cache.tags.tag_accesses 60150726 # Number of tag accesses 922system.cpu0.l2cache.tags.data_accesses 60150726 # Number of data accesses 923system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7925 # number of ReadReq hits 924system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3539 # number of ReadReq hits 925system.cpu0.l2cache.ReadReq_hits::total 11464 # number of ReadReq hits 926system.cpu0.l2cache.Writeback_hits::writebacks 508356 # number of Writeback hits 927system.cpu0.l2cache.Writeback_hits::total 508356 # number of Writeback hits 928system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28387 # number of UpgradeReq hits 929system.cpu0.l2cache.UpgradeReq_hits::total 28387 # number of UpgradeReq hits 930system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1736 # number of SCUpgradeReq hits 931system.cpu0.l2cache.SCUpgradeReq_hits::total 1736 # number of SCUpgradeReq hits 932system.cpu0.l2cache.ReadExReq_hits::cpu0.data 229125 # number of ReadExReq hits 933system.cpu0.l2cache.ReadExReq_hits::total 229125 # number of ReadExReq hits 934system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1058458 # number of ReadCleanReq hits 935system.cpu0.l2cache.ReadCleanReq_hits::total 1058458 # number of ReadCleanReq hits 936system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 386565 # number of ReadSharedReq hits 937system.cpu0.l2cache.ReadSharedReq_hits::total 386565 # number of ReadSharedReq hits 938system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7925 # number of demand (read+write) hits 939system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3539 # number of demand (read+write) hits 940system.cpu0.l2cache.demand_hits::cpu0.inst 1058458 # number of demand (read+write) hits 941system.cpu0.l2cache.demand_hits::cpu0.data 615690 # number of demand (read+write) hits 942system.cpu0.l2cache.demand_hits::total 1685612 # number of demand (read+write) hits 943system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7925 # number of overall hits 944system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3539 # number of overall hits 945system.cpu0.l2cache.overall_hits::cpu0.inst 1058458 # number of overall hits 946system.cpu0.l2cache.overall_hits::cpu0.data 615690 # number of overall hits 947system.cpu0.l2cache.overall_hits::total 1685612 # number of overall hits 948system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 220 # number of ReadReq misses 949system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses 950system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses 951system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 25774 # number of UpgradeReq misses 952system.cpu0.l2cache.UpgradeReq_misses::total 25774 # number of UpgradeReq misses 953system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17960 # number of SCUpgradeReq misses 954system.cpu0.l2cache.SCUpgradeReq_misses::total 17960 # number of SCUpgradeReq misses 955system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses 956system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 957system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41378 # number of ReadExReq misses 958system.cpu0.l2cache.ReadExReq_misses::total 41378 # number of ReadExReq misses 959system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 48035 # number of ReadCleanReq misses 960system.cpu0.l2cache.ReadCleanReq_misses::total 48035 # number of ReadCleanReq misses 961system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94511 # number of ReadSharedReq misses 962system.cpu0.l2cache.ReadSharedReq_misses::total 94511 # number of ReadSharedReq misses 963system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 220 # number of demand (read+write) misses 964system.cpu0.l2cache.demand_misses::cpu0.itb.walker 114 # number of demand (read+write) misses 965system.cpu0.l2cache.demand_misses::cpu0.inst 48035 # number of demand (read+write) misses 966system.cpu0.l2cache.demand_misses::cpu0.data 135889 # number of demand (read+write) misses 967system.cpu0.l2cache.demand_misses::total 184258 # number of demand (read+write) misses 968system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 220 # number of overall misses 969system.cpu0.l2cache.overall_misses::cpu0.itb.walker 114 # number of overall misses 970system.cpu0.l2cache.overall_misses::cpu0.inst 48035 # number of overall misses 971system.cpu0.l2cache.overall_misses::cpu0.data 135889 # number of overall misses 972system.cpu0.l2cache.overall_misses::total 184258 # number of overall misses 973system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5406500 # number of ReadReq miss cycles 974system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2600000 # number of ReadReq miss cycles 975system.cpu0.l2cache.ReadReq_miss_latency::total 8006500 # number of ReadReq miss cycles 976system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 476714500 # number of UpgradeReq miss cycles 977system.cpu0.l2cache.UpgradeReq_miss_latency::total 476714500 # number of UpgradeReq miss cycles 978system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365472000 # number of SCUpgradeReq miss cycles 979system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365472000 # number of SCUpgradeReq miss cycles 980system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1464493 # number of SCUpgradeFailReq miss cycles 981system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1464493 # number of SCUpgradeFailReq miss cycles 982system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2004346000 # number of ReadExReq miss cycles 983system.cpu0.l2cache.ReadExReq_miss_latency::total 2004346000 # number of ReadExReq miss cycles 984system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385304000 # number of ReadCleanReq miss cycles 985system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385304000 # number of ReadCleanReq miss cycles 986system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2775342500 # number of ReadSharedReq miss cycles 987system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2775342500 # number of ReadSharedReq miss cycles 988system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5406500 # number of demand (read+write) miss cycles 989system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2600000 # number of demand (read+write) miss cycles 990system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2385304000 # number of demand (read+write) miss cycles 991system.cpu0.l2cache.demand_miss_latency::cpu0.data 4779688500 # number of demand (read+write) miss cycles 992system.cpu0.l2cache.demand_miss_latency::total 7172999000 # number of demand (read+write) miss cycles 993system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5406500 # number of overall miss cycles 994system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2600000 # number of overall miss cycles 995system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2385304000 # number of overall miss cycles 996system.cpu0.l2cache.overall_miss_latency::cpu0.data 4779688500 # number of overall miss cycles 997system.cpu0.l2cache.overall_miss_latency::total 7172999000 # number of overall miss cycles 998system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8145 # number of ReadReq accesses(hits+misses) 999system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3653 # number of ReadReq accesses(hits+misses) 1000system.cpu0.l2cache.ReadReq_accesses::total 11798 # number of ReadReq accesses(hits+misses) 1001system.cpu0.l2cache.Writeback_accesses::writebacks 508356 # number of Writeback accesses(hits+misses) 1002system.cpu0.l2cache.Writeback_accesses::total 508356 # number of Writeback accesses(hits+misses) 1003system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54161 # number of UpgradeReq accesses(hits+misses) 1004system.cpu0.l2cache.UpgradeReq_accesses::total 54161 # number of UpgradeReq accesses(hits+misses) 1005system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19696 # number of SCUpgradeReq accesses(hits+misses) 1006system.cpu0.l2cache.SCUpgradeReq_accesses::total 19696 # number of SCUpgradeReq accesses(hits+misses) 1007system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 1008system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 1009system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270503 # number of ReadExReq accesses(hits+misses) 1010system.cpu0.l2cache.ReadExReq_accesses::total 270503 # number of ReadExReq accesses(hits+misses) 1011system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1106493 # number of ReadCleanReq accesses(hits+misses) 1012system.cpu0.l2cache.ReadCleanReq_accesses::total 1106493 # number of ReadCleanReq accesses(hits+misses) 1013system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 481076 # number of ReadSharedReq accesses(hits+misses) 1014system.cpu0.l2cache.ReadSharedReq_accesses::total 481076 # number of ReadSharedReq accesses(hits+misses) 1015system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8145 # number of demand (read+write) accesses 1016system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3653 # number of demand (read+write) accesses 1017system.cpu0.l2cache.demand_accesses::cpu0.inst 1106493 # number of demand (read+write) accesses 1018system.cpu0.l2cache.demand_accesses::cpu0.data 751579 # number of demand (read+write) accesses 1019system.cpu0.l2cache.demand_accesses::total 1869870 # number of demand (read+write) accesses 1020system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8145 # number of overall (read+write) accesses 1021system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3653 # number of overall (read+write) accesses 1022system.cpu0.l2cache.overall_accesses::cpu0.inst 1106493 # number of overall (read+write) accesses 1023system.cpu0.l2cache.overall_accesses::cpu0.data 751579 # number of overall (read+write) accesses 1024system.cpu0.l2cache.overall_accesses::total 1869870 # number of overall (read+write) accesses 1025system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for ReadReq accesses 1026system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031207 # miss rate for ReadReq accesses 1027system.cpu0.l2cache.ReadReq_miss_rate::total 0.028310 # miss rate for ReadReq accesses 1028system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.475877 # miss rate for UpgradeReq accesses 1029system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.475877 # miss rate for UpgradeReq accesses 1030system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911860 # miss rate for SCUpgradeReq accesses 1031system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911860 # miss rate for SCUpgradeReq accesses | 892system.cpu0.l2cache.tags.occ_blocks::writebacks 7782.048512 # Average occupied blocks per requestor 893system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.435939 # Average occupied blocks per requestor 894system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.142248 # Average occupied blocks per requestor 895system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4563.552019 # Average occupied blocks per requestor 896system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1967.112212 # Average occupied blocks per requestor 897system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1769.560295 # Average occupied blocks per requestor 898system.cpu0.l2cache.tags.occ_percent::writebacks 0.474979 # Average percentage of cache occupancy 899system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000027 # Average percentage of cache occupancy 900system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy 901system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278537 # Average percentage of cache occupancy 902system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120063 # Average percentage of cache occupancy 903system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.108005 # Average percentage of cache occupancy 904system.cpu0.l2cache.tags.occ_percent::total 0.981619 # Average percentage of cache occupancy 905system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id 906system.cpu0.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 907system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13335 # Occupied blocks per task id 908system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 909system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1270 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 259 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1410 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 11666 # Occupied blocks per task id 916system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id 917system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 918system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.813904 # Percentage of cache occupancy per task id 919system.cpu0.l2cache.tags.tag_accesses 52809362 # Number of tag accesses 920system.cpu0.l2cache.tags.data_accesses 52809362 # Number of data accesses 921system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 5209 # number of ReadReq hits 922system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2366 # number of ReadReq hits 923system.cpu0.l2cache.ReadReq_hits::total 7575 # number of ReadReq hits 924system.cpu0.l2cache.Writeback_hits::writebacks 443106 # number of Writeback hits 925system.cpu0.l2cache.Writeback_hits::total 443106 # number of Writeback hits 926system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28064 # number of UpgradeReq hits 927system.cpu0.l2cache.UpgradeReq_hits::total 28064 # number of UpgradeReq hits 928system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1524 # number of SCUpgradeReq hits 929system.cpu0.l2cache.SCUpgradeReq_hits::total 1524 # number of SCUpgradeReq hits 930system.cpu0.l2cache.ReadExReq_hits::cpu0.data 197142 # number of ReadExReq hits 931system.cpu0.l2cache.ReadExReq_hits::total 197142 # number of ReadExReq hits 932system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 946461 # number of ReadCleanReq hits 933system.cpu0.l2cache.ReadCleanReq_hits::total 946461 # number of ReadCleanReq hits 934system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 317431 # number of ReadSharedReq hits 935system.cpu0.l2cache.ReadSharedReq_hits::total 317431 # number of ReadSharedReq hits 936system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 5209 # number of demand (read+write) hits 937system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2366 # number of demand (read+write) hits 938system.cpu0.l2cache.demand_hits::cpu0.inst 946461 # number of demand (read+write) hits 939system.cpu0.l2cache.demand_hits::cpu0.data 514573 # number of demand (read+write) hits 940system.cpu0.l2cache.demand_hits::total 1468609 # number of demand (read+write) hits 941system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 5209 # number of overall hits 942system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2366 # number of overall hits 943system.cpu0.l2cache.overall_hits::cpu0.inst 946461 # number of overall hits 944system.cpu0.l2cache.overall_hits::cpu0.data 514573 # number of overall hits 945system.cpu0.l2cache.overall_hits::total 1468609 # number of overall hits 946system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 313 # number of ReadReq misses 947system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 217 # number of ReadReq misses 948system.cpu0.l2cache.ReadReq_misses::total 530 # number of ReadReq misses 949system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 25366 # number of UpgradeReq misses 950system.cpu0.l2cache.UpgradeReq_misses::total 25366 # number of UpgradeReq misses 951system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17838 # number of SCUpgradeReq misses 952system.cpu0.l2cache.SCUpgradeReq_misses::total 17838 # number of SCUpgradeReq misses 953system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 954system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 955system.cpu0.l2cache.ReadExReq_misses::cpu0.data 38871 # number of ReadExReq misses 956system.cpu0.l2cache.ReadExReq_misses::total 38871 # number of ReadExReq misses 957system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41095 # number of ReadCleanReq misses 958system.cpu0.l2cache.ReadCleanReq_misses::total 41095 # number of ReadCleanReq misses 959system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 91142 # number of ReadSharedReq misses 960system.cpu0.l2cache.ReadSharedReq_misses::total 91142 # number of ReadSharedReq misses 961system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 313 # number of demand (read+write) misses 962system.cpu0.l2cache.demand_misses::cpu0.itb.walker 217 # number of demand (read+write) misses 963system.cpu0.l2cache.demand_misses::cpu0.inst 41095 # number of demand (read+write) misses 964system.cpu0.l2cache.demand_misses::cpu0.data 130013 # number of demand (read+write) misses 965system.cpu0.l2cache.demand_misses::total 171638 # number of demand (read+write) misses 966system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 313 # number of overall misses 967system.cpu0.l2cache.overall_misses::cpu0.itb.walker 217 # number of overall misses 968system.cpu0.l2cache.overall_misses::cpu0.inst 41095 # number of overall misses 969system.cpu0.l2cache.overall_misses::cpu0.data 130013 # number of overall misses 970system.cpu0.l2cache.overall_misses::total 171638 # number of overall misses 971system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7197500 # number of ReadReq miss cycles 972system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4644500 # number of ReadReq miss cycles 973system.cpu0.l2cache.ReadReq_miss_latency::total 11842000 # number of ReadReq miss cycles 974system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 564638000 # number of UpgradeReq miss cycles 975system.cpu0.l2cache.UpgradeReq_miss_latency::total 564638000 # number of UpgradeReq miss cycles 976system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 375101000 # number of SCUpgradeReq miss cycles 977system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 375101000 # number of SCUpgradeReq miss cycles 978system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1455000 # number of SCUpgradeFailReq miss cycles 979system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1455000 # number of SCUpgradeFailReq miss cycles 980system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2573340000 # number of ReadExReq miss cycles 981system.cpu0.l2cache.ReadExReq_miss_latency::total 2573340000 # number of ReadExReq miss cycles 982system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3117324500 # number of ReadCleanReq miss cycles 983system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3117324500 # number of ReadCleanReq miss cycles 984system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3123622500 # number of ReadSharedReq miss cycles 985system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3123622500 # number of ReadSharedReq miss cycles 986system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7197500 # number of demand (read+write) miss cycles 987system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4644500 # number of demand (read+write) miss cycles 988system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3117324500 # number of demand (read+write) miss cycles 989system.cpu0.l2cache.demand_miss_latency::cpu0.data 5696962500 # number of demand (read+write) miss cycles 990system.cpu0.l2cache.demand_miss_latency::total 8826129000 # number of demand (read+write) miss cycles 991system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7197500 # number of overall miss cycles 992system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4644500 # number of overall miss cycles 993system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3117324500 # number of overall miss cycles 994system.cpu0.l2cache.overall_miss_latency::cpu0.data 5696962500 # number of overall miss cycles 995system.cpu0.l2cache.overall_miss_latency::total 8826129000 # number of overall miss cycles 996system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 5522 # number of ReadReq accesses(hits+misses) 997system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2583 # number of ReadReq accesses(hits+misses) 998system.cpu0.l2cache.ReadReq_accesses::total 8105 # number of ReadReq accesses(hits+misses) 999system.cpu0.l2cache.Writeback_accesses::writebacks 443106 # number of Writeback accesses(hits+misses) 1000system.cpu0.l2cache.Writeback_accesses::total 443106 # number of Writeback accesses(hits+misses) 1001system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 53430 # number of UpgradeReq accesses(hits+misses) 1002system.cpu0.l2cache.UpgradeReq_accesses::total 53430 # number of UpgradeReq accesses(hits+misses) 1003system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19362 # number of SCUpgradeReq accesses(hits+misses) 1004system.cpu0.l2cache.SCUpgradeReq_accesses::total 19362 # number of SCUpgradeReq accesses(hits+misses) 1005system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1006system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1007system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 236013 # number of ReadExReq accesses(hits+misses) 1008system.cpu0.l2cache.ReadExReq_accesses::total 236013 # number of ReadExReq accesses(hits+misses) 1009system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 987556 # number of ReadCleanReq accesses(hits+misses) 1010system.cpu0.l2cache.ReadCleanReq_accesses::total 987556 # number of ReadCleanReq accesses(hits+misses) 1011system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 408573 # number of ReadSharedReq accesses(hits+misses) 1012system.cpu0.l2cache.ReadSharedReq_accesses::total 408573 # number of ReadSharedReq accesses(hits+misses) 1013system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 5522 # number of demand (read+write) accesses 1014system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2583 # number of demand (read+write) accesses 1015system.cpu0.l2cache.demand_accesses::cpu0.inst 987556 # number of demand (read+write) accesses 1016system.cpu0.l2cache.demand_accesses::cpu0.data 644586 # number of demand (read+write) accesses 1017system.cpu0.l2cache.demand_accesses::total 1640247 # number of demand (read+write) accesses 1018system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 5522 # number of overall (read+write) accesses 1019system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2583 # number of overall (read+write) accesses 1020system.cpu0.l2cache.overall_accesses::cpu0.inst 987556 # number of overall (read+write) accesses 1021system.cpu0.l2cache.overall_accesses::cpu0.data 644586 # number of overall (read+write) accesses 1022system.cpu0.l2cache.overall_accesses::total 1640247 # number of overall (read+write) accesses 1023system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for ReadReq accesses 1024system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.084011 # miss rate for ReadReq accesses 1025system.cpu0.l2cache.ReadReq_miss_rate::total 0.065392 # miss rate for ReadReq accesses 1026system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.474752 # miss rate for UpgradeReq accesses 1027system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.474752 # miss rate for UpgradeReq accesses 1028system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.921289 # miss rate for SCUpgradeReq accesses 1029system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.921289 # miss rate for SCUpgradeReq accesses |
| 1032system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1033system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1030system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1031system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1034system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.152967 # miss rate for ReadExReq accesses 1035system.cpu0.l2cache.ReadExReq_miss_rate::total 0.152967 # miss rate for ReadExReq accesses 1036system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.043412 # miss rate for ReadCleanReq accesses 1037system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.043412 # miss rate for ReadCleanReq accesses 1038system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196458 # miss rate for ReadSharedReq accesses 1039system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196458 # miss rate for ReadSharedReq accesses 1040system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for demand accesses 1041system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031207 # miss rate for demand accesses 1042system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.043412 # miss rate for demand accesses 1043system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180805 # miss rate for demand accesses 1044system.cpu0.l2cache.demand_miss_rate::total 0.098541 # miss rate for demand accesses 1045system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for overall accesses 1046system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031207 # miss rate for overall accesses 1047system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.043412 # miss rate for overall accesses 1048system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180805 # miss rate for overall accesses 1049system.cpu0.l2cache.overall_miss_rate::total 0.098541 # miss rate for overall accesses 1050system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24575 # average ReadReq miss latency 1051system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22807.017544 # average ReadReq miss latency 1052system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23971.556886 # average ReadReq miss latency 1053system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.945526 # average UpgradeReq miss latency 1054system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.945526 # average UpgradeReq miss latency 1055system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20349.220490 # average SCUpgradeReq miss latency 1056system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20349.220490 # average SCUpgradeReq miss latency 1057system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 133135.727273 # average SCUpgradeFailReq miss latency 1058system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 133135.727273 # average SCUpgradeFailReq miss latency 1059system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48439.895597 # average ReadExReq miss latency 1060system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48439.895597 # average ReadExReq miss latency 1061system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49657.624649 # average ReadCleanReq miss latency 1062system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49657.624649 # average ReadCleanReq miss latency 1063system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29365.285522 # average ReadSharedReq miss latency 1064system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29365.285522 # average ReadSharedReq miss latency 1065system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24575 # average overall miss latency 1066system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22807.017544 # average overall miss latency 1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49657.624649 # average overall miss latency 1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35173.476146 # average overall miss latency 1069system.cpu0.l2cache.demand_avg_miss_latency::total 38929.104842 # average overall miss latency 1070system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24575 # average overall miss latency 1071system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22807.017544 # average overall miss latency 1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49657.624649 # average overall miss latency 1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35173.476146 # average overall miss latency 1074system.cpu0.l2cache.overall_avg_miss_latency::total 38929.104842 # average overall miss latency 1075system.cpu0.l2cache.blocked_cycles::no_mshrs 52 # number of cycles access was blocked | 1032system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.164699 # miss rate for ReadExReq accesses 1033system.cpu0.l2cache.ReadExReq_miss_rate::total 0.164699 # miss rate for ReadExReq accesses 1034system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041613 # miss rate for ReadCleanReq accesses 1035system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041613 # miss rate for ReadCleanReq accesses 1036system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.223074 # miss rate for ReadSharedReq accesses 1037system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.223074 # miss rate for ReadSharedReq accesses 1038system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for demand accesses 1039system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.084011 # miss rate for demand accesses 1040system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041613 # miss rate for demand accesses 1041system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.201700 # miss rate for demand accesses 1042system.cpu0.l2cache.demand_miss_rate::total 0.104642 # miss rate for demand accesses 1043system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for overall accesses 1044system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.084011 # miss rate for overall accesses 1045system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041613 # miss rate for overall accesses 1046system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.201700 # miss rate for overall accesses 1047system.cpu0.l2cache.overall_miss_rate::total 0.104642 # miss rate for overall accesses 1048system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22995.207668 # average ReadReq miss latency 1049system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21403.225806 # average ReadReq miss latency 1050system.cpu0.l2cache.ReadReq_avg_miss_latency::total 22343.396226 # average ReadReq miss latency 1051system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22259.638887 # average UpgradeReq miss latency 1052system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22259.638887 # average UpgradeReq miss latency 1053system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21028.198229 # average SCUpgradeReq miss latency 1054system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21028.198229 # average SCUpgradeReq miss latency 1055system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 727500 # average SCUpgradeFailReq miss latency 1056system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 727500 # average SCUpgradeFailReq miss latency 1057system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66202.052944 # average ReadExReq miss latency 1058system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66202.052944 # average ReadExReq miss latency 1059system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 75856.539725 # average ReadCleanReq miss latency 1060system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 75856.539725 # average ReadCleanReq miss latency 1061system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34272.042527 # average ReadSharedReq miss latency 1062system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34272.042527 # average ReadSharedReq miss latency 1063system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22995.207668 # average overall miss latency 1064system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21403.225806 # average overall miss latency 1065system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 75856.539725 # average overall miss latency 1066system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43818.406621 # average overall miss latency 1067system.cpu0.l2cache.demand_avg_miss_latency::total 51422.930820 # average overall miss latency 1068system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22995.207668 # average overall miss latency 1069system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21403.225806 # average overall miss latency 1070system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 75856.539725 # average overall miss latency 1071system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43818.406621 # average overall miss latency 1072system.cpu0.l2cache.overall_avg_miss_latency::total 51422.930820 # average overall miss latency 1073system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1076system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1074system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1077system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked | 1075system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1078system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1076system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1079system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked | 1077system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1080system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1081system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1082system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1078system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1079system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1080system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1083system.cpu0.l2cache.writebacks::writebacks 196326 # number of writebacks 1084system.cpu0.l2cache.writebacks::total 196326 # number of writebacks 1085system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1152 # number of ReadExReq MSHR hits 1086system.cpu0.l2cache.ReadExReq_mshr_hits::total 1152 # number of ReadExReq MSHR hits 1087system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31 # number of ReadSharedReq MSHR hits 1088system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits 1089system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1183 # number of demand (read+write) MSHR hits 1090system.cpu0.l2cache.demand_mshr_hits::total 1183 # number of demand (read+write) MSHR hits 1091system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1183 # number of overall MSHR hits 1092system.cpu0.l2cache.overall_mshr_hits::total 1183 # number of overall MSHR hits 1093system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 220 # number of ReadReq MSHR misses 1094system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 114 # number of ReadReq MSHR misses 1095system.cpu0.l2cache.ReadReq_mshr_misses::total 334 # number of ReadReq MSHR misses 1096system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8437 # number of CleanEvict MSHR misses 1097system.cpu0.l2cache.CleanEvict_mshr_misses::total 8437 # number of CleanEvict MSHR misses 1098system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245004 # number of HardPFReq MSHR misses 1099system.cpu0.l2cache.HardPFReq_mshr_misses::total 245004 # number of HardPFReq MSHR misses 1100system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 25774 # number of UpgradeReq MSHR misses 1101system.cpu0.l2cache.UpgradeReq_mshr_misses::total 25774 # number of UpgradeReq MSHR misses 1102system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17960 # number of SCUpgradeReq MSHR misses 1103system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17960 # number of SCUpgradeReq MSHR misses 1104system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses 1105system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 1106system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40226 # number of ReadExReq MSHR misses 1107system.cpu0.l2cache.ReadExReq_mshr_misses::total 40226 # number of ReadExReq MSHR misses 1108system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 48035 # number of ReadCleanReq MSHR misses 1109system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 48035 # number of ReadCleanReq MSHR misses 1110system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94480 # number of ReadSharedReq MSHR misses 1111system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94480 # number of ReadSharedReq MSHR misses 1112system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 220 # number of demand (read+write) MSHR misses 1113system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 114 # number of demand (read+write) MSHR misses 1114system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48035 # number of demand (read+write) MSHR misses 1115system.cpu0.l2cache.demand_mshr_misses::cpu0.data 134706 # number of demand (read+write) MSHR misses 1116system.cpu0.l2cache.demand_mshr_misses::total 183075 # number of demand (read+write) MSHR misses 1117system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 220 # number of overall MSHR misses 1118system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 114 # number of overall MSHR misses 1119system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48035 # number of overall MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::cpu0.data 134706 # number of overall MSHR misses 1121system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245004 # number of overall MSHR misses 1122system.cpu0.l2cache.overall_mshr_misses::total 428079 # number of overall MSHR misses | 1081system.cpu0.l2cache.writebacks::writebacks 185810 # number of writebacks 1082system.cpu0.l2cache.writebacks::total 185810 # number of writebacks 1083system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1552 # number of ReadExReq MSHR hits 1084system.cpu0.l2cache.ReadExReq_mshr_hits::total 1552 # number of ReadExReq MSHR hits 1085system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 49 # number of ReadSharedReq MSHR hits 1086system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 49 # number of ReadSharedReq MSHR hits 1087system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1601 # number of demand (read+write) MSHR hits 1088system.cpu0.l2cache.demand_mshr_hits::total 1601 # number of demand (read+write) MSHR hits 1089system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1601 # number of overall MSHR hits 1090system.cpu0.l2cache.overall_mshr_hits::total 1601 # number of overall MSHR hits 1091system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 313 # number of ReadReq MSHR misses 1092system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 217 # number of ReadReq MSHR misses 1093system.cpu0.l2cache.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses 1094system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 7353 # number of CleanEvict MSHR misses 1095system.cpu0.l2cache.CleanEvict_mshr_misses::total 7353 # number of CleanEvict MSHR misses 1096system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 230762 # number of HardPFReq MSHR misses 1097system.cpu0.l2cache.HardPFReq_mshr_misses::total 230762 # number of HardPFReq MSHR misses 1098system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 25366 # number of UpgradeReq MSHR misses 1099system.cpu0.l2cache.UpgradeReq_mshr_misses::total 25366 # number of UpgradeReq MSHR misses 1100system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17838 # number of SCUpgradeReq MSHR misses 1101system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17838 # number of SCUpgradeReq MSHR misses 1102system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1103system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1104system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 37319 # number of ReadExReq MSHR misses 1105system.cpu0.l2cache.ReadExReq_mshr_misses::total 37319 # number of ReadExReq MSHR misses 1106system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 41095 # number of ReadCleanReq MSHR misses 1107system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 41095 # number of ReadCleanReq MSHR misses 1108system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 91093 # number of ReadSharedReq MSHR misses 1109system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 91093 # number of ReadSharedReq MSHR misses 1110system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 313 # number of demand (read+write) MSHR misses 1111system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 217 # number of demand (read+write) MSHR misses 1112system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 41095 # number of demand (read+write) MSHR misses 1113system.cpu0.l2cache.demand_mshr_misses::cpu0.data 128412 # number of demand (read+write) MSHR misses 1114system.cpu0.l2cache.demand_mshr_misses::total 170037 # number of demand (read+write) MSHR misses 1115system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 313 # number of overall MSHR misses 1116system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 217 # number of overall MSHR misses 1117system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 41095 # number of overall MSHR misses 1118system.cpu0.l2cache.overall_mshr_misses::cpu0.data 128412 # number of overall MSHR misses 1119system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 230762 # number of overall MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::total 400799 # number of overall MSHR misses |
| 1123system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable | 1121system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable |
| 1124system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable 1125system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 41357 # number of ReadReq MSHR uncacheable 1126system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28719 # number of WriteReq MSHR uncacheable 1127system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28719 # number of WriteReq MSHR uncacheable | 1122system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable 1123system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40760 # number of ReadReq MSHR uncacheable 1124system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable 1125system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28393 # number of WriteReq MSHR uncacheable |
| 1128system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses | 1126system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses |
| 1129system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses 1130system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 70076 # number of overall MSHR uncacheable misses 1131system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4086500 # number of ReadReq MSHR miss cycles 1132system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1916000 # number of ReadReq MSHR miss cycles 1133system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6002500 # number of ReadReq MSHR miss cycles 1134system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13739930078 # number of HardPFReq MSHR miss cycles 1135system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13739930078 # number of HardPFReq MSHR miss cycles 1136system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 517996000 # number of UpgradeReq MSHR miss cycles 1137system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 517996000 # number of UpgradeReq MSHR miss cycles 1138system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 267528500 # number of SCUpgradeReq MSHR miss cycles 1139system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 267528500 # number of SCUpgradeReq MSHR miss cycles 1140system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1182493 # number of SCUpgradeFailReq MSHR miss cycles 1141system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1182493 # number of SCUpgradeFailReq MSHR miss cycles 1142system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1648080000 # number of ReadExReq MSHR miss cycles 1143system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1648080000 # number of ReadExReq MSHR miss cycles 1144system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2097094000 # number of ReadCleanReq MSHR miss cycles 1145system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2097094000 # number of ReadCleanReq MSHR miss cycles 1146system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2203041000 # number of ReadSharedReq MSHR miss cycles 1147system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2203041000 # number of ReadSharedReq MSHR miss cycles 1148system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4086500 # number of demand (read+write) MSHR miss cycles 1149system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1916000 # number of demand (read+write) MSHR miss cycles 1150system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2097094000 # number of demand (read+write) MSHR miss cycles 1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3851121000 # number of demand (read+write) MSHR miss cycles 1152system.cpu0.l2cache.demand_mshr_miss_latency::total 5954217500 # number of demand (read+write) MSHR miss cycles 1153system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4086500 # number of overall MSHR miss cycles 1154system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1916000 # number of overall MSHR miss cycles 1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2097094000 # number of overall MSHR miss cycles 1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3851121000 # number of overall MSHR miss cycles 1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13739930078 # number of overall MSHR miss cycles 1158system.cpu0.l2cache.overall_mshr_miss_latency::total 19694147578 # number of overall MSHR miss cycles 1159system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 733130500 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6103617500 # number of ReadReq MSHR uncacheable cycles 1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6836748000 # number of ReadReq MSHR uncacheable cycles 1162system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4721367000 # number of WriteReq MSHR uncacheable cycles 1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4721367000 # number of WriteReq MSHR uncacheable cycles 1164system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 733130500 # number of overall MSHR uncacheable cycles 1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10824984500 # number of overall MSHR uncacheable cycles 1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11558115000 # number of overall MSHR uncacheable cycles 1167system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for ReadReq accesses 1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for ReadReq accesses 1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028310 # mshr miss rate for ReadReq accesses | 1127system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses 1128system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69153 # number of overall MSHR uncacheable misses 1129system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5319500 # number of ReadReq MSHR miss cycles 1130system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3342500 # number of ReadReq MSHR miss cycles 1131system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 8662000 # number of ReadReq MSHR miss cycles 1132system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19159534735 # number of HardPFReq MSHR miss cycles 1133system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 19159534735 # number of HardPFReq MSHR miss cycles 1134system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 795300000 # number of UpgradeReq MSHR miss cycles 1135system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 795300000 # number of UpgradeReq MSHR miss cycles 1136system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 289164000 # number of SCUpgradeReq MSHR miss cycles 1137system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 289164000 # number of SCUpgradeReq MSHR miss cycles 1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1167000 # number of SCUpgradeFailReq MSHR miss cycles 1139system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1167000 # number of SCUpgradeFailReq MSHR miss cycles 1140system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2199161500 # number of ReadExReq MSHR miss cycles 1141system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2199161500 # number of ReadExReq MSHR miss cycles 1142system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2870754500 # number of ReadCleanReq MSHR miss cycles 1143system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2870754500 # number of ReadCleanReq MSHR miss cycles 1144system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2571948500 # number of ReadSharedReq MSHR miss cycles 1145system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2571948500 # number of ReadSharedReq MSHR miss cycles 1146system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5319500 # number of demand (read+write) MSHR miss cycles 1147system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3342500 # number of demand (read+write) MSHR miss cycles 1148system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2870754500 # number of demand (read+write) MSHR miss cycles 1149system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4771110000 # number of demand (read+write) MSHR miss cycles 1150system.cpu0.l2cache.demand_mshr_miss_latency::total 7650526500 # number of demand (read+write) MSHR miss cycles 1151system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5319500 # number of overall MSHR miss cycles 1152system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3342500 # number of overall MSHR miss cycles 1153system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2870754500 # number of overall MSHR miss cycles 1154system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4771110000 # number of overall MSHR miss cycles 1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19159534735 # number of overall MSHR miss cycles 1156system.cpu0.l2cache.overall_mshr_miss_latency::total 26810061235 # number of overall MSHR miss cycles 1157system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles 1158system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6020817500 # number of ReadReq MSHR uncacheable cycles 1159system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7207029000 # number of ReadReq MSHR uncacheable cycles 1160system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4873249000 # number of WriteReq MSHR uncacheable cycles 1161system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4873249000 # number of WriteReq MSHR uncacheable cycles 1162system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles 1163system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10894066500 # number of overall MSHR uncacheable cycles 1164system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12080278000 # number of overall MSHR uncacheable cycles 1165system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for ReadReq accesses 1166system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for ReadReq accesses 1167system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065392 # mshr miss rate for ReadReq accesses |
| 1170system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1171system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1172system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1173system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1168system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1169system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1170system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1171system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1174system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.475877 # mshr miss rate for UpgradeReq accesses 1175system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.475877 # mshr miss rate for UpgradeReq accesses 1176system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911860 # mshr miss rate for SCUpgradeReq accesses 1177system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911860 # mshr miss rate for SCUpgradeReq accesses | 1172system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.474752 # mshr miss rate for UpgradeReq accesses 1173system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.474752 # mshr miss rate for UpgradeReq accesses 1174system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921289 # mshr miss rate for SCUpgradeReq accesses 1175system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.921289 # mshr miss rate for SCUpgradeReq accesses |
| 1178system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1179system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1176system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1177system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1180system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148708 # mshr miss rate for ReadExReq accesses 1181system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148708 # mshr miss rate for ReadExReq accesses 1182system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for ReadCleanReq accesses 1183system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043412 # mshr miss rate for ReadCleanReq accesses 1184system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196393 # mshr miss rate for ReadSharedReq accesses 1185system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.196393 # mshr miss rate for ReadSharedReq accesses 1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for demand accesses 1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for demand accesses 1188system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for demand accesses 1189system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for demand accesses 1190system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097908 # mshr miss rate for demand accesses 1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for overall accesses 1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for overall accesses 1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for overall accesses 1194system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for overall accesses | 1178system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158123 # mshr miss rate for ReadExReq accesses 1179system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158123 # mshr miss rate for ReadExReq accesses 1180system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for ReadCleanReq accesses 1181system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041613 # mshr miss rate for ReadCleanReq accesses 1182system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222954 # mshr miss rate for ReadSharedReq accesses 1183system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.222954 # mshr miss rate for ReadSharedReq accesses 1184system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for demand accesses 1185system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for demand accesses 1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for demand accesses 1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for demand accesses 1188system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103665 # mshr miss rate for demand accesses 1189system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for overall accesses 1190system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses 1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses 1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses |
| 1195system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1196system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228935 # mshr miss rate for overall accesses 1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average ReadReq mshr miss latency 1198system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average ReadReq mshr miss latency 1199system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886 # average ReadReq mshr miss latency 1200system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average HardPFReq mshr miss latency 1201system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658 # average HardPFReq mshr miss latency 1202system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754 # average UpgradeReq mshr miss latency 1203system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754 # average UpgradeReq mshr miss latency 1204system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214 # average SCUpgradeReq mshr miss latency 1205system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214 # average SCUpgradeReq mshr miss latency 1206system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636 # average SCUpgradeFailReq mshr miss latency 1207system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636 # average SCUpgradeFailReq mshr miss latency 1208system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581 # average ReadExReq mshr miss latency 1209system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581 # average ReadExReq mshr miss latency 1210system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average ReadCleanReq mshr miss latency 1211system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649 # average ReadCleanReq mshr miss latency 1212system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103 # average ReadSharedReq mshr miss latency 1213system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103 # average ReadSharedReq mshr miss latency 1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency 1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency 1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency 1217system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency 1218system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397 # average overall mshr miss latency 1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency 1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency 1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency 1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency 1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average overall mshr miss latency 1224system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762 # average overall mshr miss latency 1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency 1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261 # average ReadReq mshr uncacheable latency 1227system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933 # average ReadReq mshr uncacheable latency 1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582 # average WriteReq mshr uncacheable latency 1229system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582 # average WriteReq mshr uncacheable latency 1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency 1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597 # average overall mshr uncacheable latency 1232system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273 # average overall mshr uncacheable latency | 1194system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses 1195system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency 1196system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency 1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency 1198system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency 1199system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency 1200system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency 1201system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency 1202system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency 1203system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency 1204system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency 1205system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency 1206system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency 1207system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency 1208system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency 1209system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency 1210system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency 1211system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency 1212system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency 1213system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency 1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency 1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency 1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency 1217system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency 1218system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency 1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency 1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency 1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency 1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency 1223system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency 1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency 1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency 1226system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency 1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency 1228system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency 1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency 1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency |
| 1233system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1231system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1234system.cpu0.toL2Bus.trans_dist::ReadReq 64646 # Transaction distribution 1235system.cpu0.toL2Bus.trans_dist::ReadResp 1697156 # Transaction distribution 1236system.cpu0.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution 1237system.cpu0.toL2Bus.trans_dist::WriteResp 28719 # Transaction distribution 1238system.cpu0.toL2Bus.trans_dist::Writeback 871288 # Transaction distribution 1239system.cpu0.toL2Bus.trans_dist::CleanEvict 1384656 # Transaction distribution 1240system.cpu0.toL2Bus.trans_dist::HardPFReq 292494 # Transaction distribution 1241system.cpu0.toL2Bus.trans_dist::UpgradeReq 87584 # Transaction distribution 1242system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution 1243system.cpu0.toL2Bus.trans_dist::UpgradeResp 111017 # Transaction distribution 1244system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution 1245system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution 1246system.cpu0.toL2Bus.trans_dist::ReadExReq 299003 # Transaction distribution 1247system.cpu0.toL2Bus.trans_dist::ReadExResp 286103 # Transaction distribution 1248system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106493 # Transaction distribution 1249system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579158 # Transaction distribution 1250system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1251system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3315880 # Packet count per connected master and slave (bytes) 1252system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2563217 # Packet count per connected master and slave (bytes) 1253system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10051 # Packet count per connected master and slave (bytes) 1254system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22351 # Packet count per connected master and slave (bytes) 1255system.cpu0.toL2Bus.pkt_count::total 5911499 # Packet count per connected master and slave (bytes) 1256system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70851640 # Cumulative packet size per connected master and slave (bytes) 1257system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84881644 # Cumulative packet size per connected master and slave (bytes) 1258system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14612 # Cumulative packet size per connected master and slave (bytes) 1259system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32580 # Cumulative packet size per connected master and slave (bytes) 1260system.cpu0.toL2Bus.pkt_size::total 155780476 # Cumulative packet size per connected master and slave (bytes) 1261system.cpu0.toL2Bus.snoops 1106596 # Total snoops (count) 1262system.cpu0.toL2Bus.snoop_fanout::samples 4822448 # Request fanout histogram 1263system.cpu0.toL2Bus.snoop_fanout::mean 1.211081 # Request fanout histogram 1264system.cpu0.toL2Bus.snoop_fanout::stdev 0.408076 # Request fanout histogram | 1232system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. 1233system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1234system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1235system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. 1236system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1237system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1238system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution 1239system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution 1240system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution 1241system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution 1242system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution 1243system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution 1244system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution 1245system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution 1246system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution 1247system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution 1248system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 1249system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 1250system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution 1251system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution 1252system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution 1253system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution 1254system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution 1255system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) 1256system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) 1257system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) 1258system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) 1259system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) 1260system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) 1261system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) 1262system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) 1263system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) 1264system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) 1265system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) 1266system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram 1267system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram 1268system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram |
| 1265system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1269system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1266system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1267system.cpu0.toL2Bus.snoop_fanout::1 3804521 78.89% 78.89% # Request fanout histogram 1268system.cpu0.toL2Bus.snoop_fanout::2 1017927 21.11% 100.00% # Request fanout histogram | 1270system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram 1271system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram 1272system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram |
| 1269system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1273system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1270system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 1274system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1271system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1275system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1272system.cpu0.toL2Bus.snoop_fanout::total 4822448 # Request fanout histogram 1273system.cpu0.toL2Bus.reqLayer0.occupancy 2435282990 # Layer occupancy (ticks) | 1276system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram 1277system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) |
| 1274system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1278system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1275system.cpu0.toL2Bus.snoopLayer0.occupancy 113496000 # Layer occupancy (ticks) | 1279system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) |
| 1276system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1280system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1277system.cpu0.toL2Bus.respLayer0.occupancy 1668761500 # Layer occupancy (ticks) | 1281system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) |
| 1278system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1282system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1279system.cpu0.toL2Bus.respLayer1.occupancy 1211060981 # Layer occupancy (ticks) | 1283system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) |
| 1280system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1284system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1281system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) | 1285system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) |
| 1282system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1286system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1283system.cpu0.toL2Bus.respLayer3.occupancy 14212986 # Layer occupancy (ticks) | 1287system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) |
| 1284system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1285system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1286system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1287system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1288system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1289system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1290system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 1306system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1307system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1308system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1309system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1310system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1311system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1312system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1313system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1288system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1289system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1290system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1292system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1293system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1294system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1295system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 1310system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1311system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1312system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1313system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1314system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1315system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1316system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1317system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1314system.cpu1.dtb.walker.walks 3357 # Table walker walks requested 1315system.cpu1.dtb.walker.walksShort 3357 # Table walker walks initiated with short descriptors 1316system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 663 # Level at which table walker walks with short descriptors terminate 1317system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate 1318system.cpu1.dtb.walker.walkWaitTime::samples 3357 # Table walker wait (enqueue to first request) latency 1319system.cpu1.dtb.walker.walkWaitTime::0 3357 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1320system.cpu1.dtb.walker.walkWaitTime::total 3357 # Table walker wait (enqueue to first request) latency 1321system.cpu1.dtb.walker.walkCompletionTime::samples 2587 # Table walker service (enqueue to completion) latency 1322system.cpu1.dtb.walker.walkCompletionTime::mean 9934.866641 # Table walker service (enqueue to completion) latency 1323system.cpu1.dtb.walker.walkCompletionTime::gmean 9080.760096 # Table walker service (enqueue to completion) latency 1324system.cpu1.dtb.walker.walkCompletionTime::stdev 4767.740714 # Table walker service (enqueue to completion) latency 1325system.cpu1.dtb.walker.walkCompletionTime::0-4095 19 0.73% 0.73% # Table walker service (enqueue to completion) latency 1326system.cpu1.dtb.walker.walkCompletionTime::4096-8191 1032 39.89% 40.63% # Table walker service (enqueue to completion) latency 1327system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1082 41.82% 82.45% # Table walker service (enqueue to completion) latency 1328system.cpu1.dtb.walker.walkCompletionTime::12288-16383 330 12.76% 95.21% # Table walker service (enqueue to completion) latency 1329system.cpu1.dtb.walker.walkCompletionTime::20480-24575 64 2.47% 97.68% # Table walker service (enqueue to completion) latency 1330system.cpu1.dtb.walker.walkCompletionTime::24576-28671 39 1.51% 99.19% # Table walker service (enqueue to completion) latency 1331system.cpu1.dtb.walker.walkCompletionTime::28672-32767 16 0.62% 99.81% # Table walker service (enqueue to completion) latency 1332system.cpu1.dtb.walker.walkCompletionTime::40960-45055 5 0.19% 100.00% # Table walker service (enqueue to completion) latency 1333system.cpu1.dtb.walker.walkCompletionTime::total 2587 # Table walker service (enqueue to completion) latency 1334system.cpu1.dtb.walker.walksPending::samples 1655632468 # Table walker pending requests distribution 1335system.cpu1.dtb.walker.walksPending::0 1655632468 100.00% 100.00% # Table walker pending requests distribution 1336system.cpu1.dtb.walker.walksPending::total 1655632468 # Table walker pending requests distribution 1337system.cpu1.dtb.walker.walkPageSizes::4K 1932 74.68% 74.68% # Table walker page sizes translated 1338system.cpu1.dtb.walker.walkPageSizes::1M 655 25.32% 100.00% # Table walker page sizes translated 1339system.cpu1.dtb.walker.walkPageSizes::total 2587 # Table walker page sizes translated 1340system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3357 # Table walker requests started/completed, data/inst | 1318system.cpu1.dtb.walker.walks 6206 # Table walker walks requested 1319system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors 1320system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate 1321system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate 1322system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency 1323system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1324system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency 1325system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency 1326system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency 1327system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency 1328system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency 1329system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency 1330system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency 1331system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency 1332system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency 1333system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency 1334system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency 1335system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency 1336system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency 1337system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency 1338system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency 1339system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency 1340system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 1341system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency 1342system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution 1343system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution 1344system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution 1345system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated 1346system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated 1347system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated 1348system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst |
| 1341system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1349system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1342system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3357 # Table walker requests started/completed, data/inst 1343system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2587 # Table walker requests started/completed, data/inst | 1350system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst 1351system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst |
| 1344system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1352system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1345system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2587 # Table walker requests started/completed, data/inst 1346system.cpu1.dtb.walker.walkRequestOrigin::total 5944 # Table walker requests started/completed, data/inst | 1353system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst 1354system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst |
| 1347system.cpu1.dtb.inst_hits 0 # ITB inst hits 1348system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1355system.cpu1.dtb.inst_hits 0 # ITB inst hits 1356system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1349system.cpu1.dtb.read_hits 3844486 # DTB read hits 1350system.cpu1.dtb.read_misses 2847 # DTB read misses 1351system.cpu1.dtb.write_hits 3369243 # DTB write hits 1352system.cpu1.dtb.write_misses 510 # DTB write misses | 1357system.cpu1.dtb.read_hits 5575996 # DTB read hits 1358system.cpu1.dtb.read_misses 5233 # DTB read misses 1359system.cpu1.dtb.write_hits 4889133 # DTB write hits 1360system.cpu1.dtb.write_misses 973 # DTB write misses |
| 1353system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1354system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1355system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1356system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1361system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1362system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1363system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1364system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1357system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB | 1365system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB |
| 1358system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1366system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1359system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch | 1367system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch |
| 1360system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1368system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1361system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1362system.cpu1.dtb.read_accesses 3847333 # DTB read accesses 1363system.cpu1.dtb.write_accesses 3369753 # DTB write accesses | 1369system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions 1370system.cpu1.dtb.read_accesses 5581229 # DTB read accesses 1371system.cpu1.dtb.write_accesses 4890106 # DTB write accesses |
| 1364system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1372system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1365system.cpu1.dtb.hits 7213729 # DTB hits 1366system.cpu1.dtb.misses 3357 # DTB misses 1367system.cpu1.dtb.accesses 7217086 # DTB accesses | 1373system.cpu1.dtb.hits 10465129 # DTB hits 1374system.cpu1.dtb.misses 6206 # DTB misses 1375system.cpu1.dtb.accesses 10471335 # DTB accesses |
| 1368system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1369system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1373system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1374system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1375system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1389system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1390system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1391system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1392system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1393system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1394system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1395system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1396system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1376system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1377system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1378system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1379system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1380system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1381system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1382system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1383system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1397system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1398system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1399system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1400system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1401system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1402system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1403system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1404system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1397system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1398system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1399system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1400system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1401system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1402system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1403system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1404system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1405system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117 # Table walker service (enqueue to completion) latency 1406system.cpu1.itb.walker.walkCompletionTime::gmean 9623.001262 # Table walker service (enqueue to completion) latency 1407system.cpu1.itb.walker.walkCompletionTime::stdev 5682.967955 # Table walker service (enqueue to completion) latency 1408system.cpu1.itb.walker.walkCompletionTime::4096-8191 356 32.16% 32.16% # Table walker service (enqueue to completion) latency 1409system.cpu1.itb.walker.walkCompletionTime::8192-12287 499 45.08% 77.24% # Table walker service (enqueue to completion) latency 1410system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 93.59% # Table walker service (enqueue to completion) latency 1411system.cpu1.itb.walker.walkCompletionTime::16384-20479 17 1.54% 95.12% # Table walker service (enqueue to completion) latency 1412system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.21% # Table walker service (enqueue to completion) latency 1413system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.71% 97.92% # Table walker service (enqueue to completion) latency 1414system.cpu1.itb.walker.walkCompletionTime::28672-32767 12 1.08% 99.01% # Table walker service (enqueue to completion) latency 1415system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency 1416system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.45% 99.91% # Table walker service (enqueue to completion) latency 1417system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1418system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1419system.cpu1.itb.walker.walksPending::samples 1655094468 # Table walker pending requests distribution 1420system.cpu1.itb.walker.walksPending::0 1655094468 100.00% 100.00% # Table walker pending requests distribution 1421system.cpu1.itb.walker.walksPending::total 1655094468 # Table walker pending requests distribution 1422system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1423system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1424system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated | 1405system.cpu1.itb.walker.walks 2787 # Table walker walks requested 1406system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors 1407system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate 1408system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate 1409system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency 1410system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1411system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency 1412system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency 1413system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency 1414system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency 1415system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency 1416system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency 1417system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency 1418system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency 1419system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency 1420system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency 1421system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency 1422system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency 1423system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency 1424system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency 1425system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency 1426system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency 1427system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency 1428system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency 1429system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency 1430system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution 1431system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution 1432system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution 1433system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated 1434system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated 1435system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated |
| 1425system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1436system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1426system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1427system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst | 1437system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst 1438system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst |
| 1428system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1439system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1429system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1430system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1431system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1432system.cpu1.itb.inst_hits 16180944 # ITB inst hits 1433system.cpu1.itb.inst_misses 1746 # ITB inst misses | 1440system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst 1441system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst 1442system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst 1443system.cpu1.itb.inst_hits 23850368 # ITB inst hits 1444system.cpu1.itb.inst_misses 2787 # ITB inst misses |
| 1434system.cpu1.itb.read_hits 0 # DTB read hits 1435system.cpu1.itb.read_misses 0 # DTB read misses 1436system.cpu1.itb.write_hits 0 # DTB write hits 1437system.cpu1.itb.write_misses 0 # DTB write misses 1438system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1439system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1440system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1441system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1445system.cpu1.itb.read_hits 0 # DTB read hits 1446system.cpu1.itb.read_misses 0 # DTB read misses 1447system.cpu1.itb.write_hits 0 # DTB write hits 1448system.cpu1.itb.write_misses 0 # DTB write misses 1449system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1450system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1451system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1452system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1442system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB | 1453system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB |
| 1443system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1444system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1445system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1446system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1447system.cpu1.itb.read_accesses 0 # DTB read accesses 1448system.cpu1.itb.write_accesses 0 # DTB write accesses | 1454system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1455system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1456system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1457system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1458system.cpu1.itb.read_accesses 0 # DTB read accesses 1459system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1449system.cpu1.itb.inst_accesses 16182690 # ITB inst accesses 1450system.cpu1.itb.hits 16180944 # DTB hits 1451system.cpu1.itb.misses 1746 # DTB misses 1452system.cpu1.itb.accesses 16182690 # DTB accesses 1453system.cpu1.numCycles 5736568944 # number of cpu cycles simulated | 1460system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses 1461system.cpu1.itb.hits 23850368 # DTB hits 1462system.cpu1.itb.misses 2787 # DTB misses 1463system.cpu1.itb.accesses 23853155 # DTB accesses 1464system.cpu1.numCycles 5742239724 # number of cpu cycles simulated |
| 1454system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1455system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1465system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1466system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1456system.cpu1.committedInsts 15848207 # Number of instructions committed 1457system.cpu1.committedOps 19293539 # Number of ops (including micro ops) committed 1458system.cpu1.num_int_alu_accesses 17383760 # Number of integer alu accesses 1459system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses 1460system.cpu1.num_func_calls 938177 # number of times a function call or return occured 1461system.cpu1.num_conditional_control_insts 1786282 # number of instructions that are conditional controls 1462system.cpu1.num_int_insts 17383760 # number of integer instructions 1463system.cpu1.num_fp_insts 1857 # number of float instructions 1464system.cpu1.num_int_register_reads 31469136 # number of times the integer registers were read 1465system.cpu1.num_int_register_writes 12170371 # number of times the integer registers were written 1466system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1467system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1468system.cpu1.num_cc_register_reads 70461385 # number of times the CC registers were read 1469system.cpu1.num_cc_register_writes 6330901 # number of times the CC registers were written 1470system.cpu1.num_mem_refs 7446495 # number of memory refs 1471system.cpu1.num_load_insts 3955836 # Number of load instructions 1472system.cpu1.num_store_insts 3490659 # Number of store instructions 1473system.cpu1.num_idle_cycles 5686521745.715384 # Number of idle cycles 1474system.cpu1.num_busy_cycles 50047198.284615 # Number of busy cycles 1475system.cpu1.not_idle_fraction 0.008724 # Percentage of non-idle cycles 1476system.cpu1.idle_fraction 0.991276 # Percentage of idle cycles 1477system.cpu1.Branches 2803460 # Number of branches fetched 1478system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1479system.cpu1.op_class::IntAlu 12144730 61.90% 61.90% # Class of executed instruction 1480system.cpu1.op_class::IntMult 26187 0.13% 62.03% # Class of executed instruction 1481system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction 1482system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction 1483system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction 1484system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction 1485system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction 1486system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction 1487system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction 1488system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction 1489system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction 1490system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction 1491system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction 1492system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction 1493system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction 1494system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction 1495system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction 1496system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction 1497system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction 1498system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction 1499system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction 1500system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction 1501system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction 1502system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction 1503system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction 1504system.cpu1.op_class::SimdFloatMisc 3277 0.02% 62.05% # Class of executed instruction 1505system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction 1506system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction 1507system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction 1508system.cpu1.op_class::MemRead 3955836 20.16% 82.21% # Class of executed instruction 1509system.cpu1.op_class::MemWrite 3490659 17.79% 100.00% # Class of executed instruction | 1467system.cpu1.committedInsts 23084590 # Number of instructions committed 1468system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed 1469system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses 1470system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses 1471system.cpu1.num_func_calls 1341368 # number of times a function call or return occured 1472system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls 1473system.cpu1.num_int_insts 25227117 # number of integer instructions 1474system.cpu1.num_fp_insts 6988 # number of float instructions 1475system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read 1476system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written 1477system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read 1478system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written 1479system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read 1480system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written 1481system.cpu1.num_mem_refs 10752307 # number of memory refs 1482system.cpu1.num_load_insts 5706058 # Number of load instructions 1483system.cpu1.num_store_insts 5046249 # Number of store instructions 1484system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles 1485system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles 1486system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles 1487system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles 1488system.cpu1.Branches 4219564 # Number of branches fetched 1489system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction 1490system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction 1491system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction 1492system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction 1493system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction 1494system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction 1495system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction 1496system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction 1497system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction 1498system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction 1499system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction 1500system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction 1501system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction 1502system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction 1503system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction 1504system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction 1505system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction 1506system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction 1507system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction 1508system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction 1509system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction 1510system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction 1511system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction 1512system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction 1513system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction 1514system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction 1515system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction 1516system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction 1517system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction 1518system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction 1519system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction 1520system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction |
| 1510system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1511system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1521system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1522system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1512system.cpu1.op_class::total 19620755 # Class of executed instruction | 1523system.cpu1.op_class::total 28630613 # Class of executed instruction |
| 1513system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1524system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1514system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed 1515system.cpu1.dcache.tags.replacements 186869 # number of replacements 1516system.cpu1.dcache.tags.tagsinuse 468.718276 # Cycle average of tags in use 1517system.cpu1.dcache.tags.total_refs 6945303 # Total number of references to valid blocks. 1518system.cpu1.dcache.tags.sampled_refs 187221 # Sample count of references to valid blocks. 1519system.cpu1.dcache.tags.avg_refs 37.096816 # Average number of references to valid blocks. 1520system.cpu1.dcache.tags.warmup_cycle 104852682500 # Cycle when the warmup percentage was hit. 1521system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.718276 # Average occupied blocks per requestor 1522system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915465 # Average percentage of cache occupancy 1523system.cpu1.dcache.tags.occ_percent::total 0.915465 # Average percentage of cache occupancy 1524system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id 1525system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 1526system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id 1527system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 1528system.cpu1.dcache.tags.tag_accesses 14648138 # Number of tag accesses 1529system.cpu1.dcache.tags.data_accesses 14648138 # Number of data accesses 1530system.cpu1.dcache.ReadReq_hits::cpu1.data 3533706 # number of ReadReq hits 1531system.cpu1.dcache.ReadReq_hits::total 3533706 # number of ReadReq hits 1532system.cpu1.dcache.WriteReq_hits::cpu1.data 3181686 # number of WriteReq hits 1533system.cpu1.dcache.WriteReq_hits::total 3181686 # number of WriteReq hits 1534system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48716 # number of SoftPFReq hits 1535system.cpu1.dcache.SoftPFReq_hits::total 48716 # number of SoftPFReq hits 1536system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78610 # number of LoadLockedReq hits 1537system.cpu1.dcache.LoadLockedReq_hits::total 78610 # number of LoadLockedReq hits 1538system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70554 # number of StoreCondReq hits 1539system.cpu1.dcache.StoreCondReq_hits::total 70554 # number of StoreCondReq hits 1540system.cpu1.dcache.demand_hits::cpu1.data 6715392 # number of demand (read+write) hits 1541system.cpu1.dcache.demand_hits::total 6715392 # number of demand (read+write) hits 1542system.cpu1.dcache.overall_hits::cpu1.data 6764108 # number of overall hits 1543system.cpu1.dcache.overall_hits::total 6764108 # number of overall hits 1544system.cpu1.dcache.ReadReq_misses::cpu1.data 133537 # number of ReadReq misses 1545system.cpu1.dcache.ReadReq_misses::total 133537 # number of ReadReq misses 1546system.cpu1.dcache.WriteReq_misses::cpu1.data 91347 # number of WriteReq misses 1547system.cpu1.dcache.WriteReq_misses::total 91347 # number of WriteReq misses 1548system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30388 # number of SoftPFReq misses 1549system.cpu1.dcache.SoftPFReq_misses::total 30388 # number of SoftPFReq misses 1550system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17048 # number of LoadLockedReq misses 1551system.cpu1.dcache.LoadLockedReq_misses::total 17048 # number of LoadLockedReq misses 1552system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23285 # number of StoreCondReq misses 1553system.cpu1.dcache.StoreCondReq_misses::total 23285 # number of StoreCondReq misses 1554system.cpu1.dcache.demand_misses::cpu1.data 224884 # number of demand (read+write) misses 1555system.cpu1.dcache.demand_misses::total 224884 # number of demand (read+write) misses 1556system.cpu1.dcache.overall_misses::cpu1.data 255272 # number of overall misses 1557system.cpu1.dcache.overall_misses::total 255272 # number of overall misses 1558system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1938354000 # number of ReadReq miss cycles 1559system.cpu1.dcache.ReadReq_miss_latency::total 1938354000 # number of ReadReq miss cycles 1560system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2351393500 # number of WriteReq miss cycles 1561system.cpu1.dcache.WriteReq_miss_latency::total 2351393500 # number of WriteReq miss cycles 1562system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319800000 # number of LoadLockedReq miss cycles 1563system.cpu1.dcache.LoadLockedReq_miss_latency::total 319800000 # number of LoadLockedReq miss cycles 1564system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544967000 # number of StoreCondReq miss cycles 1565system.cpu1.dcache.StoreCondReq_miss_latency::total 544967000 # number of StoreCondReq miss cycles 1566system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2548000 # number of StoreCondFailReq miss cycles 1567system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2548000 # number of StoreCondFailReq miss cycles 1568system.cpu1.dcache.demand_miss_latency::cpu1.data 4289747500 # number of demand (read+write) miss cycles 1569system.cpu1.dcache.demand_miss_latency::total 4289747500 # number of demand (read+write) miss cycles 1570system.cpu1.dcache.overall_miss_latency::cpu1.data 4289747500 # number of overall miss cycles 1571system.cpu1.dcache.overall_miss_latency::total 4289747500 # number of overall miss cycles 1572system.cpu1.dcache.ReadReq_accesses::cpu1.data 3667243 # number of ReadReq accesses(hits+misses) 1573system.cpu1.dcache.ReadReq_accesses::total 3667243 # number of ReadReq accesses(hits+misses) 1574system.cpu1.dcache.WriteReq_accesses::cpu1.data 3273033 # number of WriteReq accesses(hits+misses) 1575system.cpu1.dcache.WriteReq_accesses::total 3273033 # number of WriteReq accesses(hits+misses) 1576system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79104 # number of SoftPFReq accesses(hits+misses) 1577system.cpu1.dcache.SoftPFReq_accesses::total 79104 # number of SoftPFReq accesses(hits+misses) 1578system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95658 # number of LoadLockedReq accesses(hits+misses) 1579system.cpu1.dcache.LoadLockedReq_accesses::total 95658 # number of LoadLockedReq accesses(hits+misses) 1580system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93839 # number of StoreCondReq accesses(hits+misses) 1581system.cpu1.dcache.StoreCondReq_accesses::total 93839 # number of StoreCondReq accesses(hits+misses) 1582system.cpu1.dcache.demand_accesses::cpu1.data 6940276 # number of demand (read+write) accesses 1583system.cpu1.dcache.demand_accesses::total 6940276 # number of demand (read+write) accesses 1584system.cpu1.dcache.overall_accesses::cpu1.data 7019380 # number of overall (read+write) accesses 1585system.cpu1.dcache.overall_accesses::total 7019380 # number of overall (read+write) accesses 1586system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036413 # miss rate for ReadReq accesses 1587system.cpu1.dcache.ReadReq_miss_rate::total 0.036413 # miss rate for ReadReq accesses 1588system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027909 # miss rate for WriteReq accesses 1589system.cpu1.dcache.WriteReq_miss_rate::total 0.027909 # miss rate for WriteReq accesses 1590system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384153 # miss rate for SoftPFReq accesses 1591system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384153 # miss rate for SoftPFReq accesses 1592system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178218 # miss rate for LoadLockedReq accesses 1593system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178218 # miss rate for LoadLockedReq accesses 1594system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248138 # miss rate for StoreCondReq accesses 1595system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248138 # miss rate for StoreCondReq accesses 1596system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032403 # miss rate for demand accesses 1597system.cpu1.dcache.demand_miss_rate::total 0.032403 # miss rate for demand accesses 1598system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036367 # miss rate for overall accesses 1599system.cpu1.dcache.overall_miss_rate::total 0.036367 # miss rate for overall accesses 1600system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600 # average ReadReq miss latency 1601system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600 # average ReadReq miss latency 1602system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501 # average WriteReq miss latency 1603system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501 # average WriteReq miss latency 1604system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686 # average LoadLockedReq miss latency 1605system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686 # average LoadLockedReq miss latency 1606system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718 # average StoreCondReq miss latency 1607system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718 # average StoreCondReq miss latency | 1525system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed 1526system.cpu1.dcache.tags.replacements 292035 # number of replacements 1527system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use 1528system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. 1529system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. 1530system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. 1531system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. 1532system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor 1533system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy 1534system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy 1535system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1536system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 1537system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id 1538system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 1539system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1540system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses 1541system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses 1542system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits 1543system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits 1544system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits 1545system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits 1546system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits 1547system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits 1548system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits 1549system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits 1550system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits 1551system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits 1552system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits 1553system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits 1554system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits 1555system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits 1556system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses 1557system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses 1558system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses 1559system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses 1560system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses 1561system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses 1562system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses 1563system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses 1564system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses 1565system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses 1566system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses 1567system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses 1568system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses 1569system.cpu1.dcache.overall_misses::total 361088 # number of overall misses 1570system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles 1571system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles 1572system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles 1573system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles 1574system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles 1575system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles 1576system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles 1577system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles 1578system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles 1579system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles 1580system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles 1581system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles 1582system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles 1583system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles 1584system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) 1585system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) 1586system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) 1587system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) 1588system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) 1589system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) 1590system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) 1591system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) 1592system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) 1593system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) 1594system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses 1595system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses 1596system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses 1597system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses 1598system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses 1599system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses 1600system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses 1601system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses 1602system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses 1603system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses 1604system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses 1605system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses 1606system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses 1607system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses 1608system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses 1609system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses 1610system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses 1611system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses 1612system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency 1613system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency 1614system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency 1615system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency 1616system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency 1617system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency 1618system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency 1619system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency |
| 1608system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1609system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1620system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1621system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1610system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862 # average overall miss latency 1611system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862 # average overall miss latency 1612system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294 # average overall miss latency 1613system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294 # average overall miss latency | 1622system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039 # average overall miss latency 1623system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039 # average overall miss latency 1624system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency 1625system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency |
| 1614system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1615system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1616system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1617system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1618system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1619system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1620system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1621system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1626system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1627system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1628system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1629system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1630system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1631system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1632system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1633system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1622system.cpu1.dcache.writebacks::writebacks 116740 # number of writebacks 1623system.cpu1.dcache.writebacks::total 116740 # number of writebacks 1624system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 267 # number of ReadReq MSHR hits 1625system.cpu1.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits 1626system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11810 # number of LoadLockedReq MSHR hits 1627system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11810 # number of LoadLockedReq MSHR hits 1628system.cpu1.dcache.demand_mshr_hits::cpu1.data 267 # number of demand (read+write) MSHR hits 1629system.cpu1.dcache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits 1630system.cpu1.dcache.overall_mshr_hits::cpu1.data 267 # number of overall MSHR hits 1631system.cpu1.dcache.overall_mshr_hits::total 267 # number of overall MSHR hits 1632system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133270 # number of ReadReq MSHR misses 1633system.cpu1.dcache.ReadReq_mshr_misses::total 133270 # number of ReadReq MSHR misses 1634system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91347 # number of WriteReq MSHR misses 1635system.cpu1.dcache.WriteReq_mshr_misses::total 91347 # number of WriteReq MSHR misses 1636system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29613 # number of SoftPFReq MSHR misses 1637system.cpu1.dcache.SoftPFReq_mshr_misses::total 29613 # number of SoftPFReq MSHR misses 1638system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5238 # number of LoadLockedReq MSHR misses 1639system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5238 # number of LoadLockedReq MSHR misses 1640system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23285 # number of StoreCondReq MSHR misses 1641system.cpu1.dcache.StoreCondReq_mshr_misses::total 23285 # number of StoreCondReq MSHR misses 1642system.cpu1.dcache.demand_mshr_misses::cpu1.data 224617 # number of demand (read+write) MSHR misses 1643system.cpu1.dcache.demand_mshr_misses::total 224617 # number of demand (read+write) MSHR misses 1644system.cpu1.dcache.overall_mshr_misses::cpu1.data 254230 # number of overall MSHR misses 1645system.cpu1.dcache.overall_mshr_misses::total 254230 # number of overall MSHR misses 1646system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable 1647system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2508 # number of ReadReq MSHR uncacheable 1648system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable 1649system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable 1650system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses 1651system.cpu1.dcache.overall_mshr_uncacheable_misses::total 4663 # number of overall MSHR uncacheable misses 1652system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1799290500 # number of ReadReq MSHR miss cycles 1653system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1799290500 # number of ReadReq MSHR miss cycles 1654system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2260046500 # number of WriteReq MSHR miss cycles 1655system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2260046500 # number of WriteReq MSHR miss cycles 1656system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487726000 # number of SoftPFReq MSHR miss cycles 1657system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487726000 # number of SoftPFReq MSHR miss cycles 1658system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90112000 # number of LoadLockedReq MSHR miss cycles 1659system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90112000 # number of LoadLockedReq MSHR miss cycles 1660system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521727000 # number of StoreCondReq MSHR miss cycles 1661system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521727000 # number of StoreCondReq MSHR miss cycles 1662system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2503000 # number of StoreCondFailReq MSHR miss cycles 1663system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2503000 # number of StoreCondFailReq MSHR miss cycles 1664system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4059337000 # number of demand (read+write) MSHR miss cycles 1665system.cpu1.dcache.demand_mshr_miss_latency::total 4059337000 # number of demand (read+write) MSHR miss cycles 1666system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4547063000 # number of overall MSHR miss cycles 1667system.cpu1.dcache.overall_mshr_miss_latency::total 4547063000 # number of overall MSHR miss cycles 1668system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 302228000 # number of ReadReq MSHR uncacheable cycles 1669system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 302228000 # number of ReadReq MSHR uncacheable cycles 1670system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224553500 # number of WriteReq MSHR uncacheable cycles 1671system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224553500 # number of WriteReq MSHR uncacheable cycles 1672system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 526781500 # number of overall MSHR uncacheable cycles 1673system.cpu1.dcache.overall_mshr_uncacheable_latency::total 526781500 # number of overall MSHR uncacheable cycles 1674system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036341 # mshr miss rate for ReadReq accesses 1675system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses 1676system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027909 # mshr miss rate for WriteReq accesses 1677system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027909 # mshr miss rate for WriteReq accesses 1678system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374355 # mshr miss rate for SoftPFReq accesses 1679system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374355 # mshr miss rate for SoftPFReq accesses 1680system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054758 # mshr miss rate for LoadLockedReq accesses 1681system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054758 # mshr miss rate for LoadLockedReq accesses 1682system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248138 # mshr miss rate for StoreCondReq accesses 1683system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248138 # mshr miss rate for StoreCondReq accesses 1684system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032364 # mshr miss rate for demand accesses 1685system.cpu1.dcache.demand_mshr_miss_rate::total 0.032364 # mshr miss rate for demand accesses 1686system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036218 # mshr miss rate for overall accesses 1687system.cpu1.dcache.overall_mshr_miss_rate::total 0.036218 # mshr miss rate for overall accesses 1688system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769 # average ReadReq mshr miss latency 1689system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769 # average ReadReq mshr miss latency 1690system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501 # average WriteReq mshr miss latency 1691system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501 # average WriteReq mshr miss latency 1692system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285 # average SoftPFReq mshr miss latency 1693system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285 # average SoftPFReq mshr miss latency 1694system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791 # average LoadLockedReq mshr miss latency 1695system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791 # average LoadLockedReq mshr miss latency 1696system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293 # average StoreCondReq mshr miss latency 1697system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293 # average StoreCondReq mshr miss latency | 1634system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks 1635system.cpu1.dcache.writebacks::total 180790 # number of writebacks 1636system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits 1637system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits 1638system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits 1639system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits 1640system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits 1641system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits 1642system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits 1643system.cpu1.dcache.overall_mshr_hits::total 404 # number of overall MSHR hits 1644system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189873 # number of ReadReq MSHR misses 1645system.cpu1.dcache.ReadReq_mshr_misses::total 189873 # number of ReadReq MSHR misses 1646system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 126690 # number of WriteReq MSHR misses 1647system.cpu1.dcache.WriteReq_mshr_misses::total 126690 # number of WriteReq MSHR misses 1648system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 43074 # number of SoftPFReq MSHR misses 1649system.cpu1.dcache.SoftPFReq_mshr_misses::total 43074 # number of SoftPFReq MSHR misses 1650system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5610 # number of LoadLockedReq MSHR misses 1651system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5610 # number of LoadLockedReq MSHR misses 1652system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23929 # number of StoreCondReq MSHR misses 1653system.cpu1.dcache.StoreCondReq_mshr_misses::total 23929 # number of StoreCondReq MSHR misses 1654system.cpu1.dcache.demand_mshr_misses::cpu1.data 316563 # number of demand (read+write) MSHR misses 1655system.cpu1.dcache.demand_mshr_misses::total 316563 # number of demand (read+write) MSHR misses 1656system.cpu1.dcache.overall_mshr_misses::cpu1.data 359637 # number of overall MSHR misses 1657system.cpu1.dcache.overall_mshr_misses::total 359637 # number of overall MSHR misses 1658system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable 1659system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3143 # number of ReadReq MSHR uncacheable 1660system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable 1661system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable 1662system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses 1663system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5663 # number of overall MSHR uncacheable misses 1664system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2352437000 # number of ReadReq MSHR miss cycles 1665system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2352437000 # number of ReadReq MSHR miss cycles 1666system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3307227500 # number of WriteReq MSHR miss cycles 1667system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3307227500 # number of WriteReq MSHR miss cycles 1668system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 648806500 # number of SoftPFReq MSHR miss cycles 1669system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 648806500 # number of SoftPFReq MSHR miss cycles 1670system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97651500 # number of LoadLockedReq MSHR miss cycles 1671system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97651500 # number of LoadLockedReq MSHR miss cycles 1672system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606310000 # number of StoreCondReq MSHR miss cycles 1673system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles 1674system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles 1675system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles 1676system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles 1677system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles 1678system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles 1679system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles 1680system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles 1681system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles 1682system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles 1683system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles 1684system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles 1685system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles 1686system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses 1687system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses 1688system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses 1689system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses 1690system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses 1691system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.385446 # mshr miss rate for SoftPFReq accesses 1692system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046107 # mshr miss rate for LoadLockedReq accesses 1693system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046107 # mshr miss rate for LoadLockedReq accesses 1694system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.199896 # mshr miss rate for StoreCondReq accesses 1695system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.199896 # mshr miss rate for StoreCondReq accesses 1696system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031324 # mshr miss rate for demand accesses 1697system.cpu1.dcache.demand_mshr_miss_rate::total 0.031324 # mshr miss rate for demand accesses 1698system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035197 # mshr miss rate for overall accesses 1699system.cpu1.dcache.overall_mshr_miss_rate::total 0.035197 # mshr miss rate for overall accesses 1700system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790 # average ReadReq mshr miss latency 1701system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency 1702system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency 1703system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency 1704system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency 1705system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency 1706system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency 1707system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency 1708system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency 1709system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency |
| 1698system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1699system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1710system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1711system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1700system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18072.260782 # average overall mshr miss latency 1701system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18072.260782 # average overall mshr miss latency 1702system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17885.627188 # average overall mshr miss latency 1703system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17885.627188 # average overall mshr miss latency 1704system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120505.582137 # average ReadReq mshr uncacheable latency 1705system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120505.582137 # average ReadReq mshr uncacheable latency 1706system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104201.160093 # average WriteReq mshr uncacheable latency 1707system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 104201.160093 # average WriteReq mshr uncacheable latency 1708system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 112970.512546 # average overall mshr uncacheable latency 1709system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 112970.512546 # average overall mshr uncacheable latency | 1712system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency 1713system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency 1714system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency 1715system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency 1716system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency 1717system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency 1718system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average WriteReq mshr uncacheable latency 1719system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492 # average WriteReq mshr uncacheable latency 1720system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787 # average overall mshr uncacheable latency 1721system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787 # average overall mshr uncacheable latency |
| 1710system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1722system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1711system.cpu1.icache.tags.replacements 501529 # number of replacements 1712system.cpu1.icache.tags.tagsinuse 498.573325 # Cycle average of tags in use 1713system.cpu1.icache.tags.total_refs 15678898 # Total number of references to valid blocks. 1714system.cpu1.icache.tags.sampled_refs 502041 # Sample count of references to valid blocks. 1715system.cpu1.icache.tags.avg_refs 31.230314 # Average number of references to valid blocks. 1716system.cpu1.icache.tags.warmup_cycle 84707327000 # Cycle when the warmup percentage was hit. 1717system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573325 # Average occupied blocks per requestor 1718system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973776 # Average percentage of cache occupancy 1719system.cpu1.icache.tags.occ_percent::total 0.973776 # Average percentage of cache occupancy | 1723system.cpu1.icache.tags.replacements 622414 # number of replacements 1724system.cpu1.icache.tags.tagsinuse 498.397194 # Cycle average of tags in use 1725system.cpu1.icache.tags.total_refs 23227437 # Total number of references to valid blocks. 1726system.cpu1.icache.tags.sampled_refs 622926 # Sample count of references to valid blocks. 1727system.cpu1.icache.tags.avg_refs 37.287634 # Average number of references to valid blocks. 1728system.cpu1.icache.tags.warmup_cycle 105696892000 # Cycle when the warmup percentage was hit. 1729system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.397194 # Average occupied blocks per requestor 1730system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973432 # Average percentage of cache occupancy 1731system.cpu1.icache.tags.occ_percent::total 0.973432 # Average percentage of cache occupancy |
| 1720system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1732system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1721system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 1722system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id 1723system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id | 1733system.cpu1.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 1734system.cpu1.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id 1735system.cpu1.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id |
| 1724system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1736system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1725system.cpu1.icache.tags.tag_accesses 32863919 # Number of tag accesses 1726system.cpu1.icache.tags.data_accesses 32863919 # Number of data accesses 1727system.cpu1.icache.ReadReq_hits::cpu1.inst 15678898 # number of ReadReq hits 1728system.cpu1.icache.ReadReq_hits::total 15678898 # number of ReadReq hits 1729system.cpu1.icache.demand_hits::cpu1.inst 15678898 # number of demand (read+write) hits 1730system.cpu1.icache.demand_hits::total 15678898 # number of demand (read+write) hits 1731system.cpu1.icache.overall_hits::cpu1.inst 15678898 # number of overall hits 1732system.cpu1.icache.overall_hits::total 15678898 # number of overall hits 1733system.cpu1.icache.ReadReq_misses::cpu1.inst 502041 # number of ReadReq misses 1734system.cpu1.icache.ReadReq_misses::total 502041 # number of ReadReq misses 1735system.cpu1.icache.demand_misses::cpu1.inst 502041 # number of demand (read+write) misses 1736system.cpu1.icache.demand_misses::total 502041 # number of demand (read+write) misses 1737system.cpu1.icache.overall_misses::cpu1.inst 502041 # number of overall misses 1738system.cpu1.icache.overall_misses::total 502041 # number of overall misses 1739system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4374235500 # number of ReadReq miss cycles 1740system.cpu1.icache.ReadReq_miss_latency::total 4374235500 # number of ReadReq miss cycles 1741system.cpu1.icache.demand_miss_latency::cpu1.inst 4374235500 # number of demand (read+write) miss cycles 1742system.cpu1.icache.demand_miss_latency::total 4374235500 # number of demand (read+write) miss cycles 1743system.cpu1.icache.overall_miss_latency::cpu1.inst 4374235500 # number of overall miss cycles 1744system.cpu1.icache.overall_miss_latency::total 4374235500 # number of overall miss cycles 1745system.cpu1.icache.ReadReq_accesses::cpu1.inst 16180939 # number of ReadReq accesses(hits+misses) 1746system.cpu1.icache.ReadReq_accesses::total 16180939 # number of ReadReq accesses(hits+misses) 1747system.cpu1.icache.demand_accesses::cpu1.inst 16180939 # number of demand (read+write) accesses 1748system.cpu1.icache.demand_accesses::total 16180939 # number of demand (read+write) accesses 1749system.cpu1.icache.overall_accesses::cpu1.inst 16180939 # number of overall (read+write) accesses 1750system.cpu1.icache.overall_accesses::total 16180939 # number of overall (read+write) accesses 1751system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031027 # miss rate for ReadReq accesses 1752system.cpu1.icache.ReadReq_miss_rate::total 0.031027 # miss rate for ReadReq accesses 1753system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031027 # miss rate for demand accesses 1754system.cpu1.icache.demand_miss_rate::total 0.031027 # miss rate for demand accesses 1755system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031027 # miss rate for overall accesses 1756system.cpu1.icache.overall_miss_rate::total 0.031027 # miss rate for overall accesses 1757system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8712.904922 # average ReadReq miss latency 1758system.cpu1.icache.ReadReq_avg_miss_latency::total 8712.904922 # average ReadReq miss latency 1759system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency 1760system.cpu1.icache.demand_avg_miss_latency::total 8712.904922 # average overall miss latency 1761system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency 1762system.cpu1.icache.overall_avg_miss_latency::total 8712.904922 # average overall miss latency | 1737system.cpu1.icache.tags.tag_accesses 48323652 # Number of tag accesses 1738system.cpu1.icache.tags.data_accesses 48323652 # Number of data accesses 1739system.cpu1.icache.ReadReq_hits::cpu1.inst 23227437 # number of ReadReq hits 1740system.cpu1.icache.ReadReq_hits::total 23227437 # number of ReadReq hits 1741system.cpu1.icache.demand_hits::cpu1.inst 23227437 # number of demand (read+write) hits 1742system.cpu1.icache.demand_hits::total 23227437 # number of demand (read+write) hits 1743system.cpu1.icache.overall_hits::cpu1.inst 23227437 # number of overall hits 1744system.cpu1.icache.overall_hits::total 23227437 # number of overall hits 1745system.cpu1.icache.ReadReq_misses::cpu1.inst 622926 # number of ReadReq misses 1746system.cpu1.icache.ReadReq_misses::total 622926 # number of ReadReq misses 1747system.cpu1.icache.demand_misses::cpu1.inst 622926 # number of demand (read+write) misses 1748system.cpu1.icache.demand_misses::total 622926 # number of demand (read+write) misses 1749system.cpu1.icache.overall_misses::cpu1.inst 622926 # number of overall misses 1750system.cpu1.icache.overall_misses::total 622926 # number of overall misses 1751system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5716886500 # number of ReadReq miss cycles 1752system.cpu1.icache.ReadReq_miss_latency::total 5716886500 # number of ReadReq miss cycles 1753system.cpu1.icache.demand_miss_latency::cpu1.inst 5716886500 # number of demand (read+write) miss cycles 1754system.cpu1.icache.demand_miss_latency::total 5716886500 # number of demand (read+write) miss cycles 1755system.cpu1.icache.overall_miss_latency::cpu1.inst 5716886500 # number of overall miss cycles 1756system.cpu1.icache.overall_miss_latency::total 5716886500 # number of overall miss cycles 1757system.cpu1.icache.ReadReq_accesses::cpu1.inst 23850363 # number of ReadReq accesses(hits+misses) 1758system.cpu1.icache.ReadReq_accesses::total 23850363 # number of ReadReq accesses(hits+misses) 1759system.cpu1.icache.demand_accesses::cpu1.inst 23850363 # number of demand (read+write) accesses 1760system.cpu1.icache.demand_accesses::total 23850363 # number of demand (read+write) accesses 1761system.cpu1.icache.overall_accesses::cpu1.inst 23850363 # number of overall (read+write) accesses 1762system.cpu1.icache.overall_accesses::total 23850363 # number of overall (read+write) accesses 1763system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026118 # miss rate for ReadReq accesses 1764system.cpu1.icache.ReadReq_miss_rate::total 0.026118 # miss rate for ReadReq accesses 1765system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026118 # miss rate for demand accesses 1766system.cpu1.icache.demand_miss_rate::total 0.026118 # miss rate for demand accesses 1767system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026118 # miss rate for overall accesses 1768system.cpu1.icache.overall_miss_rate::total 0.026118 # miss rate for overall accesses 1769system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9177.472926 # average ReadReq miss latency 1770system.cpu1.icache.ReadReq_avg_miss_latency::total 9177.472926 # average ReadReq miss latency 1771system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency 1772system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency 1773system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency 1774system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency |
| 1763system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1764system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1765system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1766system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1767system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1768system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1769system.cpu1.icache.fast_writes 0 # number of fast writes performed 1770system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1775system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1776system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1777system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1778system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1779system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1780system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1781system.cpu1.icache.fast_writes 0 # number of fast writes performed 1782system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1771system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 502041 # number of ReadReq MSHR misses 1772system.cpu1.icache.ReadReq_mshr_misses::total 502041 # number of ReadReq MSHR misses 1773system.cpu1.icache.demand_mshr_misses::cpu1.inst 502041 # number of demand (read+write) MSHR misses 1774system.cpu1.icache.demand_mshr_misses::total 502041 # number of demand (read+write) MSHR misses 1775system.cpu1.icache.overall_mshr_misses::cpu1.inst 502041 # number of overall MSHR misses 1776system.cpu1.icache.overall_mshr_misses::total 502041 # number of overall MSHR misses | 1783system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622926 # number of ReadReq MSHR misses 1784system.cpu1.icache.ReadReq_mshr_misses::total 622926 # number of ReadReq MSHR misses 1785system.cpu1.icache.demand_mshr_misses::cpu1.inst 622926 # number of demand (read+write) MSHR misses 1786system.cpu1.icache.demand_mshr_misses::total 622926 # number of demand (read+write) MSHR misses 1787system.cpu1.icache.overall_mshr_misses::cpu1.inst 622926 # number of overall MSHR misses 1788system.cpu1.icache.overall_mshr_misses::total 622926 # number of overall MSHR misses |
| 1777system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1778system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1779system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1780system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses | 1789system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1790system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1791system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1792system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses |
| 1781system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4123215000 # number of ReadReq MSHR miss cycles 1782system.cpu1.icache.ReadReq_mshr_miss_latency::total 4123215000 # number of ReadReq MSHR miss cycles 1783system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4123215000 # number of demand (read+write) MSHR miss cycles 1784system.cpu1.icache.demand_mshr_miss_latency::total 4123215000 # number of demand (read+write) MSHR miss cycles 1785system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4123215000 # number of overall MSHR miss cycles 1786system.cpu1.icache.overall_mshr_miss_latency::total 4123215000 # number of overall MSHR miss cycles 1787system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15225000 # number of ReadReq MSHR uncacheable cycles 1788system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15225000 # number of ReadReq MSHR uncacheable cycles 1789system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15225000 # number of overall MSHR uncacheable cycles 1790system.cpu1.icache.overall_mshr_uncacheable_latency::total 15225000 # number of overall MSHR uncacheable cycles 1791system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for ReadReq accesses 1792system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.031027 # mshr miss rate for ReadReq accesses 1793system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for demand accesses 1794system.cpu1.icache.demand_mshr_miss_rate::total 0.031027 # mshr miss rate for demand accesses 1795system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for overall accesses 1796system.cpu1.icache.overall_mshr_miss_rate::total 0.031027 # mshr miss rate for overall accesses 1797system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average ReadReq mshr miss latency 1798system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8212.904922 # average ReadReq mshr miss latency 1799system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency 1800system.cpu1.icache.demand_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency 1801system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency 1802system.cpu1.icache.overall_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency 1803system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average ReadReq mshr uncacheable latency 1804system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153 # average ReadReq mshr uncacheable latency 1805system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average overall mshr uncacheable latency 1806system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153 # average overall mshr uncacheable latency | 1793system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5405423500 # number of ReadReq MSHR miss cycles 1794system.cpu1.icache.ReadReq_mshr_miss_latency::total 5405423500 # number of ReadReq MSHR miss cycles 1795system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5405423500 # number of demand (read+write) MSHR miss cycles 1796system.cpu1.icache.demand_mshr_miss_latency::total 5405423500 # number of demand (read+write) MSHR miss cycles 1797system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5405423500 # number of overall MSHR miss cycles 1798system.cpu1.icache.overall_mshr_miss_latency::total 5405423500 # number of overall MSHR miss cycles 1799system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23975000 # number of ReadReq MSHR uncacheable cycles 1800system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23975000 # number of ReadReq MSHR uncacheable cycles 1801system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23975000 # number of overall MSHR uncacheable cycles 1802system.cpu1.icache.overall_mshr_uncacheable_latency::total 23975000 # number of overall MSHR uncacheable cycles 1803system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for ReadReq accesses 1804system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026118 # mshr miss rate for ReadReq accesses 1805system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for demand accesses 1806system.cpu1.icache.demand_mshr_miss_rate::total 0.026118 # mshr miss rate for demand accesses 1807system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for overall accesses 1808system.cpu1.icache.overall_mshr_miss_rate::total 0.026118 # mshr miss rate for overall accesses 1809system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average ReadReq mshr miss latency 1810system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8677.472926 # average ReadReq mshr miss latency 1811system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency 1812system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency 1813system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency 1814system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency 1815system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency 1816system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency 1817system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency 1818system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency |
| 1807system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1819system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1808system.cpu1.l2cache.prefetcher.num_hwpf_issued 199800 # number of hwpf issued 1809system.cpu1.l2cache.prefetcher.pfIdentified 199800 # number of prefetch candidates identified 1810system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue | 1820system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued 1821system.cpu1.l2cache.prefetcher.pfIdentified 437708 # number of prefetch candidates identified 1822system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue |
| 1811system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1812system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1823system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1824system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1813system.cpu1.l2cache.prefetcher.pfSpanPage 61752 # number of prefetches not generated due to page crossing 1814system.cpu1.l2cache.tags.replacements 45885 # number of replacements 1815system.cpu1.l2cache.tags.tagsinuse 14962.501141 # Cycle average of tags in use 1816system.cpu1.l2cache.tags.total_refs 1260771 # Total number of references to valid blocks. 1817system.cpu1.l2cache.tags.sampled_refs 60629 # Sample count of references to valid blocks. 1818system.cpu1.l2cache.tags.avg_refs 20.794851 # Average number of references to valid blocks. | 1825system.cpu1.l2cache.prefetcher.pfSpanPage 85932 # number of prefetches not generated due to page crossing 1826system.cpu1.l2cache.tags.replacements 65711 # number of replacements 1827system.cpu1.l2cache.tags.tagsinuse 15078.335139 # Cycle average of tags in use 1828system.cpu1.l2cache.tags.total_refs 1680940 # Total number of references to valid blocks. 1829system.cpu1.l2cache.tags.sampled_refs 81927 # Sample count of references to valid blocks. 1830system.cpu1.l2cache.tags.avg_refs 20.517534 # Average number of references to valid blocks. |
| 1819system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1831system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1820system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.992983 # Average occupied blocks per requestor 1821system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.872865 # Average occupied blocks per requestor 1822system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.082863 # Average occupied blocks per requestor 1823system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2870.067957 # Average occupied blocks per requestor 1824system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2148.313714 # Average occupied blocks per requestor 1825system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 992.170760 # Average occupied blocks per requestor 1826system.cpu1.l2cache.tags.occ_percent::writebacks 0.546020 # Average percentage of cache occupancy 1827system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000236 # Average percentage of cache occupancy | 1832system.cpu1.l2cache.tags.occ_blocks::writebacks 8770.071442 # Average occupied blocks per requestor 1833system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.089565 # Average occupied blocks per requestor 1834system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.088469 # Average occupied blocks per requestor 1835system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.092107 # Average occupied blocks per requestor 1836system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2103.725355 # Average occupied blocks per requestor 1837system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1007.268201 # Average occupied blocks per requestor 1838system.cpu1.l2cache.tags.occ_percent::writebacks 0.535283 # Average percentage of cache occupancy 1839system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy |
| 1828system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy | 1840system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy |
| 1829system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.175175 # Average percentage of cache occupancy 1830system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131123 # Average percentage of cache occupancy 1831system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060557 # Average percentage of cache occupancy 1832system.cpu1.l2cache.tags.occ_percent::total 0.913239 # Average percentage of cache occupancy 1833system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1179 # Occupied blocks per task id 1834system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id 1835system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13548 # Occupied blocks per task id 1836system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 1837system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 28 # Occupied blocks per task id 1838system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1149 # Occupied blocks per task id 1839system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id | 1841system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194830 # Average percentage of cache occupancy 1842system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128401 # Average percentage of cache occupancy 1843system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061479 # Average percentage of cache occupancy 1844system.cpu1.l2cache.tags.occ_percent::total 0.920309 # Average percentage of cache occupancy 1845system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1082 # Occupied blocks per task id 1846system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 1847system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15126 # Occupied blocks per task id 1848system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 1849system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 297 # Occupied blocks per task id 1850system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 350 # Occupied blocks per task id 1851system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 424 # Occupied blocks per task id 1852system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id |
| 1840system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 1853system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 1841system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 1842system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id 1843system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1569 # Occupied blocks per task id 1844system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11689 # Occupied blocks per task id 1845system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.071960 # Percentage of cache occupancy per task id 1846system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 1847system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826904 # Percentage of cache occupancy per task id 1848system.cpu1.l2cache.tags.tag_accesses 23682241 # Number of tag accesses 1849system.cpu1.l2cache.tags.data_accesses 23682241 # Number of data accesses 1850system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3041 # number of ReadReq hits 1851system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1687 # number of ReadReq hits 1852system.cpu1.l2cache.ReadReq_hits::total 4728 # number of ReadReq hits 1853system.cpu1.l2cache.Writeback_hits::writebacks 116740 # number of Writeback hits 1854system.cpu1.l2cache.Writeback_hits::total 116740 # number of Writeback hits 1855system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1450 # number of UpgradeReq hits 1856system.cpu1.l2cache.UpgradeReq_hits::total 1450 # number of UpgradeReq hits 1857system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 871 # number of SCUpgradeReq hits 1858system.cpu1.l2cache.SCUpgradeReq_hits::total 871 # number of SCUpgradeReq hits 1859system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27883 # number of ReadExReq hits 1860system.cpu1.l2cache.ReadExReq_hits::total 27883 # number of ReadExReq hits 1861system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 488673 # number of ReadCleanReq hits 1862system.cpu1.l2cache.ReadCleanReq_hits::total 488673 # number of ReadCleanReq hits 1863system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 100414 # number of ReadSharedReq hits 1864system.cpu1.l2cache.ReadSharedReq_hits::total 100414 # number of ReadSharedReq hits 1865system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3041 # number of demand (read+write) hits 1866system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1687 # number of demand (read+write) hits 1867system.cpu1.l2cache.demand_hits::cpu1.inst 488673 # number of demand (read+write) hits 1868system.cpu1.l2cache.demand_hits::cpu1.data 128297 # number of demand (read+write) hits 1869system.cpu1.l2cache.demand_hits::total 621698 # number of demand (read+write) hits 1870system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3041 # number of overall hits 1871system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1687 # number of overall hits 1872system.cpu1.l2cache.overall_hits::cpu1.inst 488673 # number of overall hits 1873system.cpu1.l2cache.overall_hits::cpu1.data 128297 # number of overall hits 1874system.cpu1.l2cache.overall_hits::total 621698 # number of overall hits 1875system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 323 # number of ReadReq misses 1876system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses 1877system.cpu1.l2cache.ReadReq_misses::total 601 # number of ReadReq misses 1878system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27681 # number of UpgradeReq misses 1879system.cpu1.l2cache.UpgradeReq_misses::total 27681 # number of UpgradeReq misses 1880system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22412 # number of SCUpgradeReq misses 1881system.cpu1.l2cache.SCUpgradeReq_misses::total 22412 # number of SCUpgradeReq misses | 1854system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 1855system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 1856system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 1857system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3207 # Occupied blocks per task id 1858system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7762 # Occupied blocks per task id 1859system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3991 # Occupied blocks per task id 1860system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.066040 # Percentage of cache occupancy per task id 1861system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 1862system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.923218 # Percentage of cache occupancy per task id 1863system.cpu1.l2cache.tags.tag_accesses 31008240 # Number of tag accesses 1864system.cpu1.l2cache.tags.data_accesses 31008240 # Number of data accesses 1865system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5928 # number of ReadReq hits 1866system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2864 # number of ReadReq hits 1867system.cpu1.l2cache.ReadReq_hits::total 8792 # number of ReadReq hits 1868system.cpu1.l2cache.Writeback_hits::writebacks 180790 # number of Writeback hits 1869system.cpu1.l2cache.Writeback_hits::total 180790 # number of Writeback hits 1870system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1732 # number of UpgradeReq hits 1871system.cpu1.l2cache.UpgradeReq_hits::total 1732 # number of UpgradeReq hits 1872system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1100 # number of SCUpgradeReq hits 1873system.cpu1.l2cache.SCUpgradeReq_hits::total 1100 # number of SCUpgradeReq hits 1874system.cpu1.l2cache.ReadExReq_hits::cpu1.data 58942 # number of ReadExReq hits 1875system.cpu1.l2cache.ReadExReq_hits::total 58942 # number of ReadExReq hits 1876system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 603650 # number of ReadCleanReq hits 1877system.cpu1.l2cache.ReadCleanReq_hits::total 603650 # number of ReadCleanReq hits 1878system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 167802 # number of ReadSharedReq hits 1879system.cpu1.l2cache.ReadSharedReq_hits::total 167802 # number of ReadSharedReq hits 1880system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5928 # number of demand (read+write) hits 1881system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2864 # number of demand (read+write) hits 1882system.cpu1.l2cache.demand_hits::cpu1.inst 603650 # number of demand (read+write) hits 1883system.cpu1.l2cache.demand_hits::cpu1.data 226744 # number of demand (read+write) hits 1884system.cpu1.l2cache.demand_hits::total 839186 # number of demand (read+write) hits 1885system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5928 # number of overall hits 1886system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2864 # number of overall hits 1887system.cpu1.l2cache.overall_hits::cpu1.inst 603650 # number of overall hits 1888system.cpu1.l2cache.overall_hits::cpu1.data 226744 # number of overall hits 1889system.cpu1.l2cache.overall_hits::total 839186 # number of overall hits 1890system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 209 # number of ReadReq misses 1891system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 176 # number of ReadReq misses 1892system.cpu1.l2cache.ReadReq_misses::total 385 # number of ReadReq misses 1893system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28345 # number of UpgradeReq misses 1894system.cpu1.l2cache.UpgradeReq_misses::total 28345 # number of UpgradeReq misses 1895system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22827 # number of SCUpgradeReq misses 1896system.cpu1.l2cache.SCUpgradeReq_misses::total 22827 # number of SCUpgradeReq misses |
| 1882system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 1883system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses | 1897system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 1898system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses |
| 1884system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34333 # number of ReadExReq misses 1885system.cpu1.l2cache.ReadExReq_misses::total 34333 # number of ReadExReq misses 1886system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13368 # number of ReadCleanReq misses 1887system.cpu1.l2cache.ReadCleanReq_misses::total 13368 # number of ReadCleanReq misses 1888system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67707 # number of ReadSharedReq misses 1889system.cpu1.l2cache.ReadSharedReq_misses::total 67707 # number of ReadSharedReq misses 1890system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 323 # number of demand (read+write) misses 1891system.cpu1.l2cache.demand_misses::cpu1.itb.walker 278 # number of demand (read+write) misses 1892system.cpu1.l2cache.demand_misses::cpu1.inst 13368 # number of demand (read+write) misses 1893system.cpu1.l2cache.demand_misses::cpu1.data 102040 # number of demand (read+write) misses 1894system.cpu1.l2cache.demand_misses::total 116009 # number of demand (read+write) misses 1895system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 323 # number of overall misses 1896system.cpu1.l2cache.overall_misses::cpu1.itb.walker 278 # number of overall misses 1897system.cpu1.l2cache.overall_misses::cpu1.inst 13368 # number of overall misses 1898system.cpu1.l2cache.overall_misses::cpu1.data 102040 # number of overall misses 1899system.cpu1.l2cache.overall_misses::total 116009 # number of overall misses 1900system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6494000 # number of ReadReq miss cycles 1901system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5572000 # number of ReadReq miss cycles 1902system.cpu1.l2cache.ReadReq_miss_latency::total 12066000 # number of ReadReq miss cycles 1903system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 531615500 # number of UpgradeReq miss cycles 1904system.cpu1.l2cache.UpgradeReq_miss_latency::total 531615500 # number of UpgradeReq miss cycles 1905system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 445738000 # number of SCUpgradeReq miss cycles 1906system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 445738000 # number of SCUpgradeReq miss cycles 1907system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2435500 # number of SCUpgradeFailReq miss cycles 1908system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2435500 # number of SCUpgradeFailReq miss cycles 1909system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1319690000 # number of ReadExReq miss cycles 1910system.cpu1.l2cache.ReadExReq_miss_latency::total 1319690000 # number of ReadExReq miss cycles 1911system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 440659500 # number of ReadCleanReq miss cycles 1912system.cpu1.l2cache.ReadCleanReq_miss_latency::total 440659500 # number of ReadCleanReq miss cycles 1913system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1471913000 # number of ReadSharedReq miss cycles 1914system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1471913000 # number of ReadSharedReq miss cycles 1915system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6494000 # number of demand (read+write) miss cycles 1916system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5572000 # number of demand (read+write) miss cycles 1917system.cpu1.l2cache.demand_miss_latency::cpu1.inst 440659500 # number of demand (read+write) miss cycles 1918system.cpu1.l2cache.demand_miss_latency::cpu1.data 2791603000 # number of demand (read+write) miss cycles 1919system.cpu1.l2cache.demand_miss_latency::total 3244328500 # number of demand (read+write) miss cycles 1920system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6494000 # number of overall miss cycles 1921system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5572000 # number of overall miss cycles 1922system.cpu1.l2cache.overall_miss_latency::cpu1.inst 440659500 # number of overall miss cycles 1923system.cpu1.l2cache.overall_miss_latency::cpu1.data 2791603000 # number of overall miss cycles 1924system.cpu1.l2cache.overall_miss_latency::total 3244328500 # number of overall miss cycles 1925system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3364 # number of ReadReq accesses(hits+misses) 1926system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1965 # number of ReadReq accesses(hits+misses) 1927system.cpu1.l2cache.ReadReq_accesses::total 5329 # number of ReadReq accesses(hits+misses) 1928system.cpu1.l2cache.Writeback_accesses::writebacks 116740 # number of Writeback accesses(hits+misses) 1929system.cpu1.l2cache.Writeback_accesses::total 116740 # number of Writeback accesses(hits+misses) 1930system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29131 # number of UpgradeReq accesses(hits+misses) 1931system.cpu1.l2cache.UpgradeReq_accesses::total 29131 # number of UpgradeReq accesses(hits+misses) 1932system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23283 # number of SCUpgradeReq accesses(hits+misses) 1933system.cpu1.l2cache.SCUpgradeReq_accesses::total 23283 # number of SCUpgradeReq accesses(hits+misses) | 1899system.cpu1.l2cache.ReadExReq_misses::cpu1.data 37671 # number of ReadExReq misses 1900system.cpu1.l2cache.ReadExReq_misses::total 37671 # number of ReadExReq misses 1901system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 19276 # number of ReadCleanReq misses 1902system.cpu1.l2cache.ReadCleanReq_misses::total 19276 # number of ReadCleanReq misses 1903system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70755 # number of ReadSharedReq misses 1904system.cpu1.l2cache.ReadSharedReq_misses::total 70755 # number of ReadSharedReq misses 1905system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 209 # number of demand (read+write) misses 1906system.cpu1.l2cache.demand_misses::cpu1.itb.walker 176 # number of demand (read+write) misses 1907system.cpu1.l2cache.demand_misses::cpu1.inst 19276 # number of demand (read+write) misses 1908system.cpu1.l2cache.demand_misses::cpu1.data 108426 # number of demand (read+write) misses 1909system.cpu1.l2cache.demand_misses::total 128087 # number of demand (read+write) misses 1910system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 209 # number of overall misses 1911system.cpu1.l2cache.overall_misses::cpu1.itb.walker 176 # number of overall misses 1912system.cpu1.l2cache.overall_misses::cpu1.inst 19276 # number of overall misses 1913system.cpu1.l2cache.overall_misses::cpu1.data 108426 # number of overall misses 1914system.cpu1.l2cache.overall_misses::total 128087 # number of overall misses 1915system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 4414000 # number of ReadReq miss cycles 1916system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3881000 # number of ReadReq miss cycles 1917system.cpu1.l2cache.ReadReq_miss_latency::total 8295000 # number of ReadReq miss cycles 1918system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 586663000 # number of UpgradeReq miss cycles 1919system.cpu1.l2cache.UpgradeReq_miss_latency::total 586663000 # number of UpgradeReq miss cycles 1920system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 490009500 # number of SCUpgradeReq miss cycles 1921system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 490009500 # number of SCUpgradeReq miss cycles 1922system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5348000 # number of SCUpgradeFailReq miss cycles 1923system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5348000 # number of SCUpgradeFailReq miss cycles 1924system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1921205500 # number of ReadExReq miss cycles 1925system.cpu1.l2cache.ReadExReq_miss_latency::total 1921205500 # number of ReadExReq miss cycles 1926system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 842911500 # number of ReadCleanReq miss cycles 1927system.cpu1.l2cache.ReadCleanReq_miss_latency::total 842911500 # number of ReadCleanReq miss cycles 1928system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1648156000 # number of ReadSharedReq miss cycles 1929system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1648156000 # number of ReadSharedReq miss cycles 1930system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 4414000 # number of demand (read+write) miss cycles 1931system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3881000 # number of demand (read+write) miss cycles 1932system.cpu1.l2cache.demand_miss_latency::cpu1.inst 842911500 # number of demand (read+write) miss cycles 1933system.cpu1.l2cache.demand_miss_latency::cpu1.data 3569361500 # number of demand (read+write) miss cycles 1934system.cpu1.l2cache.demand_miss_latency::total 4420568000 # number of demand (read+write) miss cycles 1935system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 4414000 # number of overall miss cycles 1936system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3881000 # number of overall miss cycles 1937system.cpu1.l2cache.overall_miss_latency::cpu1.inst 842911500 # number of overall miss cycles 1938system.cpu1.l2cache.overall_miss_latency::cpu1.data 3569361500 # number of overall miss cycles 1939system.cpu1.l2cache.overall_miss_latency::total 4420568000 # number of overall miss cycles 1940system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6137 # number of ReadReq accesses(hits+misses) 1941system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3040 # number of ReadReq accesses(hits+misses) 1942system.cpu1.l2cache.ReadReq_accesses::total 9177 # number of ReadReq accesses(hits+misses) 1943system.cpu1.l2cache.Writeback_accesses::writebacks 180790 # number of Writeback accesses(hits+misses) 1944system.cpu1.l2cache.Writeback_accesses::total 180790 # number of Writeback accesses(hits+misses) 1945system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30077 # number of UpgradeReq accesses(hits+misses) 1946system.cpu1.l2cache.UpgradeReq_accesses::total 30077 # number of UpgradeReq accesses(hits+misses) 1947system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23927 # number of SCUpgradeReq accesses(hits+misses) 1948system.cpu1.l2cache.SCUpgradeReq_accesses::total 23927 # number of SCUpgradeReq accesses(hits+misses) |
| 1934system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1935system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) | 1949system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1950system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) |
| 1936system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62216 # number of ReadExReq accesses(hits+misses) 1937system.cpu1.l2cache.ReadExReq_accesses::total 62216 # number of ReadExReq accesses(hits+misses) 1938system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 502041 # number of ReadCleanReq accesses(hits+misses) 1939system.cpu1.l2cache.ReadCleanReq_accesses::total 502041 # number of ReadCleanReq accesses(hits+misses) 1940system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168121 # number of ReadSharedReq accesses(hits+misses) 1941system.cpu1.l2cache.ReadSharedReq_accesses::total 168121 # number of ReadSharedReq accesses(hits+misses) 1942system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3364 # number of demand (read+write) accesses 1943system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1965 # number of demand (read+write) accesses 1944system.cpu1.l2cache.demand_accesses::cpu1.inst 502041 # number of demand (read+write) accesses 1945system.cpu1.l2cache.demand_accesses::cpu1.data 230337 # number of demand (read+write) accesses 1946system.cpu1.l2cache.demand_accesses::total 737707 # number of demand (read+write) accesses 1947system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3364 # number of overall (read+write) accesses 1948system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1965 # number of overall (read+write) accesses 1949system.cpu1.l2cache.overall_accesses::cpu1.inst 502041 # number of overall (read+write) accesses 1950system.cpu1.l2cache.overall_accesses::cpu1.data 230337 # number of overall (read+write) accesses 1951system.cpu1.l2cache.overall_accesses::total 737707 # number of overall (read+write) accesses 1952system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096017 # miss rate for ReadReq accesses 1953system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.141476 # miss rate for ReadReq accesses 1954system.cpu1.l2cache.ReadReq_miss_rate::total 0.112779 # miss rate for ReadReq accesses 1955system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950225 # miss rate for UpgradeReq accesses 1956system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950225 # miss rate for UpgradeReq accesses 1957system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962591 # miss rate for SCUpgradeReq accesses 1958system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962591 # miss rate for SCUpgradeReq accesses | 1951system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 96613 # number of ReadExReq accesses(hits+misses) 1952system.cpu1.l2cache.ReadExReq_accesses::total 96613 # number of ReadExReq accesses(hits+misses) 1953system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 622926 # number of ReadCleanReq accesses(hits+misses) 1954system.cpu1.l2cache.ReadCleanReq_accesses::total 622926 # number of ReadCleanReq accesses(hits+misses) 1955system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 238557 # number of ReadSharedReq accesses(hits+misses) 1956system.cpu1.l2cache.ReadSharedReq_accesses::total 238557 # number of ReadSharedReq accesses(hits+misses) 1957system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6137 # number of demand (read+write) accesses 1958system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3040 # number of demand (read+write) accesses 1959system.cpu1.l2cache.demand_accesses::cpu1.inst 622926 # number of demand (read+write) accesses 1960system.cpu1.l2cache.demand_accesses::cpu1.data 335170 # number of demand (read+write) accesses 1961system.cpu1.l2cache.demand_accesses::total 967273 # number of demand (read+write) accesses 1962system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6137 # number of overall (read+write) accesses 1963system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3040 # number of overall (read+write) accesses 1964system.cpu1.l2cache.overall_accesses::cpu1.inst 622926 # number of overall (read+write) accesses 1965system.cpu1.l2cache.overall_accesses::cpu1.data 335170 # number of overall (read+write) accesses 1966system.cpu1.l2cache.overall_accesses::total 967273 # number of overall (read+write) accesses 1967system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034056 # miss rate for ReadReq accesses 1968system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057895 # miss rate for ReadReq accesses 1969system.cpu1.l2cache.ReadReq_miss_rate::total 0.041953 # miss rate for ReadReq accesses 1970system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.942414 # miss rate for UpgradeReq accesses 1971system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.942414 # miss rate for UpgradeReq accesses 1972system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.954027 # miss rate for SCUpgradeReq accesses 1973system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.954027 # miss rate for SCUpgradeReq accesses |
| 1959system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1960system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1974system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1975system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1961system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.551836 # miss rate for ReadExReq accesses 1962system.cpu1.l2cache.ReadExReq_miss_rate::total 0.551836 # miss rate for ReadExReq accesses 1963system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026627 # miss rate for ReadCleanReq accesses 1964system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026627 # miss rate for ReadCleanReq accesses 1965system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.402728 # miss rate for ReadSharedReq accesses 1966system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.402728 # miss rate for ReadSharedReq accesses 1967system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096017 # miss rate for demand accesses 1968system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.141476 # miss rate for demand accesses 1969system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026627 # miss rate for demand accesses 1970system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443003 # miss rate for demand accesses 1971system.cpu1.l2cache.demand_miss_rate::total 0.157256 # miss rate for demand accesses 1972system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096017 # miss rate for overall accesses 1973system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.141476 # miss rate for overall accesses 1974system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026627 # miss rate for overall accesses 1975system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443003 # miss rate for overall accesses 1976system.cpu1.l2cache.overall_miss_rate::total 0.157256 # miss rate for overall accesses 1977system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20105.263158 # average ReadReq miss latency 1978system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20043.165468 # average ReadReq miss latency 1979system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20076.539101 # average ReadReq miss latency 1980system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19205.068459 # average UpgradeReq miss latency 1981system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19205.068459 # average UpgradeReq miss latency 1982system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19888.363377 # average SCUpgradeReq miss latency 1983system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19888.363377 # average SCUpgradeReq miss latency 1984system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1217750 # average SCUpgradeFailReq miss latency 1985system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1217750 # average SCUpgradeFailReq miss latency 1986system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38437.945999 # average ReadExReq miss latency 1987system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38437.945999 # average ReadExReq miss latency 1988system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32963.756732 # average ReadCleanReq miss latency 1989system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32963.756732 # average ReadCleanReq miss latency 1990system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21739.450869 # average ReadSharedReq miss latency 1991system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21739.450869 # average ReadSharedReq miss latency 1992system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20105.263158 # average overall miss latency 1993system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20043.165468 # average overall miss latency 1994system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32963.756732 # average overall miss latency 1995system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27357.928263 # average overall miss latency 1996system.cpu1.l2cache.demand_avg_miss_latency::total 27966.179348 # average overall miss latency 1997system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20105.263158 # average overall miss latency 1998system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20043.165468 # average overall miss latency 1999system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32963.756732 # average overall miss latency 2000system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27357.928263 # average overall miss latency 2001system.cpu1.l2cache.overall_avg_miss_latency::total 27966.179348 # average overall miss latency | 1976system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.389916 # miss rate for ReadExReq accesses 1977system.cpu1.l2cache.ReadExReq_miss_rate::total 0.389916 # miss rate for ReadExReq accesses 1978system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.030944 # miss rate for ReadCleanReq accesses 1979system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.030944 # miss rate for ReadCleanReq accesses 1980system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.296596 # miss rate for ReadSharedReq accesses 1981system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.296596 # miss rate for ReadSharedReq accesses 1982system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034056 # miss rate for demand accesses 1983system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057895 # miss rate for demand accesses 1984system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.030944 # miss rate for demand accesses 1985system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.323496 # miss rate for demand accesses 1986system.cpu1.l2cache.demand_miss_rate::total 0.132421 # miss rate for demand accesses 1987system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034056 # miss rate for overall accesses 1988system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057895 # miss rate for overall accesses 1989system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.030944 # miss rate for overall accesses 1990system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.323496 # miss rate for overall accesses 1991system.cpu1.l2cache.overall_miss_rate::total 0.132421 # miss rate for overall accesses 1992system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21119.617225 # average ReadReq miss latency 1993system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 22051.136364 # average ReadReq miss latency 1994system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21545.454545 # average ReadReq miss latency 1995system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20697.230552 # average UpgradeReq miss latency 1996system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20697.230552 # average UpgradeReq miss latency 1997system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21466.224208 # average SCUpgradeReq miss latency 1998system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21466.224208 # average SCUpgradeReq miss latency 1999system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 2674000 # average SCUpgradeFailReq miss latency 2000system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2674000 # average SCUpgradeFailReq miss latency 2001system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50999.588543 # average ReadExReq miss latency 2002system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50999.588543 # average ReadExReq miss latency 2003system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 43728.548454 # average ReadCleanReq miss latency 2004system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 43728.548454 # average ReadCleanReq miss latency 2005system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23293.844958 # average ReadSharedReq miss latency 2006system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23293.844958 # average ReadSharedReq miss latency 2007system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21119.617225 # average overall miss latency 2008system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 22051.136364 # average overall miss latency 2009system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 43728.548454 # average overall miss latency 2010system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32919.793223 # average overall miss latency 2011system.cpu1.l2cache.demand_avg_miss_latency::total 34512.229969 # average overall miss latency 2012system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21119.617225 # average overall miss latency 2013system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 22051.136364 # average overall miss latency 2014system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 43728.548454 # average overall miss latency 2015system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32919.793223 # average overall miss latency 2016system.cpu1.l2cache.overall_avg_miss_latency::total 34512.229969 # average overall miss latency |
| 2002system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2003system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2004system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2005system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2006system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2007system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2008system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2009system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2017system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2018system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2019system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2020system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2021system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2022system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2023system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2024system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2010system.cpu1.l2cache.writebacks::writebacks 30382 # number of writebacks 2011system.cpu1.l2cache.writebacks::total 30382 # number of writebacks 2012system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 91 # number of ReadExReq MSHR hits 2013system.cpu1.l2cache.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits 2014system.cpu1.l2cache.demand_mshr_hits::cpu1.data 91 # number of demand (read+write) MSHR hits 2015system.cpu1.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits 2016system.cpu1.l2cache.overall_mshr_hits::cpu1.data 91 # number of overall MSHR hits 2017system.cpu1.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits 2018system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 323 # number of ReadReq MSHR misses 2019system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 278 # number of ReadReq MSHR misses 2020system.cpu1.l2cache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses 2021system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2052 # number of CleanEvict MSHR misses 2022system.cpu1.l2cache.CleanEvict_mshr_misses::total 2052 # number of CleanEvict MSHR misses 2023system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24074 # number of HardPFReq MSHR misses 2024system.cpu1.l2cache.HardPFReq_mshr_misses::total 24074 # number of HardPFReq MSHR misses 2025system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27681 # number of UpgradeReq MSHR misses 2026system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27681 # number of UpgradeReq MSHR misses 2027system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22412 # number of SCUpgradeReq MSHR misses 2028system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22412 # number of SCUpgradeReq MSHR misses | 2025system.cpu1.l2cache.writebacks::writebacks 39052 # number of writebacks 2026system.cpu1.l2cache.writebacks::total 39052 # number of writebacks 2027system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 295 # number of ReadExReq MSHR hits 2028system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits 2029system.cpu1.l2cache.demand_mshr_hits::cpu1.data 295 # number of demand (read+write) MSHR hits 2030system.cpu1.l2cache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits 2031system.cpu1.l2cache.overall_mshr_hits::cpu1.data 295 # number of overall MSHR hits 2032system.cpu1.l2cache.overall_mshr_hits::total 295 # number of overall MSHR hits 2033system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 209 # number of ReadReq MSHR misses 2034system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 176 # number of ReadReq MSHR misses 2035system.cpu1.l2cache.ReadReq_mshr_misses::total 385 # number of ReadReq MSHR misses 2036system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2890 # number of CleanEvict MSHR misses 2037system.cpu1.l2cache.CleanEvict_mshr_misses::total 2890 # number of CleanEvict MSHR misses 2038system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35042 # number of HardPFReq MSHR misses 2039system.cpu1.l2cache.HardPFReq_mshr_misses::total 35042 # number of HardPFReq MSHR misses 2040system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28345 # number of UpgradeReq MSHR misses 2041system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28345 # number of UpgradeReq MSHR misses 2042system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22827 # number of SCUpgradeReq MSHR misses 2043system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22827 # number of SCUpgradeReq MSHR misses |
| 2029system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2030system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses | 2044system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2045system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses |
| 2031system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34242 # number of ReadExReq MSHR misses 2032system.cpu1.l2cache.ReadExReq_mshr_misses::total 34242 # number of ReadExReq MSHR misses 2033system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13368 # number of ReadCleanReq MSHR misses 2034system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13368 # number of ReadCleanReq MSHR misses 2035system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 67707 # number of ReadSharedReq MSHR misses 2036system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 67707 # number of ReadSharedReq MSHR misses 2037system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 323 # number of demand (read+write) MSHR misses 2038system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 278 # number of demand (read+write) MSHR misses 2039system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13368 # number of demand (read+write) MSHR misses 2040system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101949 # number of demand (read+write) MSHR misses 2041system.cpu1.l2cache.demand_mshr_misses::total 115918 # number of demand (read+write) MSHR misses 2042system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 323 # number of overall MSHR misses 2043system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 278 # number of overall MSHR misses 2044system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13368 # number of overall MSHR misses 2045system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101949 # number of overall MSHR misses 2046system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24074 # number of overall MSHR misses 2047system.cpu1.l2cache.overall_mshr_misses::total 139992 # number of overall MSHR misses | 2046system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 37376 # number of ReadExReq MSHR misses 2047system.cpu1.l2cache.ReadExReq_mshr_misses::total 37376 # number of ReadExReq MSHR misses 2048system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 19276 # number of ReadCleanReq MSHR misses 2049system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 19276 # number of ReadCleanReq MSHR misses 2050system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70755 # number of ReadSharedReq MSHR misses 2051system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70755 # number of ReadSharedReq MSHR misses 2052system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 209 # number of demand (read+write) MSHR misses 2053system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 176 # number of demand (read+write) MSHR misses 2054system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 19276 # number of demand (read+write) MSHR misses 2055system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108131 # number of demand (read+write) MSHR misses 2056system.cpu1.l2cache.demand_mshr_misses::total 127792 # number of demand (read+write) MSHR misses 2057system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 209 # number of overall MSHR misses 2058system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 176 # number of overall MSHR misses 2059system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 19276 # number of overall MSHR misses 2060system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108131 # number of overall MSHR misses 2061system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35042 # number of overall MSHR misses 2062system.cpu1.l2cache.overall_mshr_misses::total 162834 # number of overall MSHR misses |
| 2048system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable | 2063system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable |
| 2049system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable 2050system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2685 # number of ReadReq MSHR uncacheable 2051system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable 2052system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable | 2064system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable 2065system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3320 # number of ReadReq MSHR uncacheable 2066system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable 2067system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable |
| 2053system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses | 2068system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses |
| 2054system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses 2055system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 4840 # number of overall MSHR uncacheable misses 2056system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4556000 # number of ReadReq MSHR miss cycles 2057system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3904000 # number of ReadReq MSHR miss cycles 2058system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8460000 # number of ReadReq MSHR miss cycles 2059system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 852211217 # number of HardPFReq MSHR miss cycles 2060system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 852211217 # number of HardPFReq MSHR miss cycles 2061system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 446564500 # number of UpgradeReq MSHR miss cycles 2062system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 446564500 # number of UpgradeReq MSHR miss cycles 2063system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 346991500 # number of SCUpgradeReq MSHR miss cycles 2064system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 346991500 # number of SCUpgradeReq MSHR miss cycles 2065system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2165500 # number of SCUpgradeFailReq MSHR miss cycles 2066system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2165500 # number of SCUpgradeFailReq MSHR miss cycles 2067system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1103967000 # number of ReadExReq MSHR miss cycles 2068system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1103967000 # number of ReadExReq MSHR miss cycles 2069system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 360451500 # number of ReadCleanReq MSHR miss cycles 2070system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 360451500 # number of ReadCleanReq MSHR miss cycles 2071system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1065671000 # number of ReadSharedReq MSHR miss cycles 2072system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1065671000 # number of ReadSharedReq MSHR miss cycles 2073system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4556000 # number of demand (read+write) MSHR miss cycles 2074system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3904000 # number of demand (read+write) MSHR miss cycles 2075system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 360451500 # number of demand (read+write) MSHR miss cycles 2076system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2169638000 # number of demand (read+write) MSHR miss cycles 2077system.cpu1.l2cache.demand_mshr_miss_latency::total 2538549500 # number of demand (read+write) MSHR miss cycles 2078system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4556000 # number of overall MSHR miss cycles 2079system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3904000 # number of overall MSHR miss cycles 2080system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 360451500 # number of overall MSHR miss cycles 2081system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2169638000 # number of overall MSHR miss cycles 2082system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 852211217 # number of overall MSHR miss cycles 2083system.cpu1.l2cache.overall_mshr_miss_latency::total 3390760717 # number of overall MSHR miss cycles 2084system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13897500 # number of ReadReq MSHR uncacheable cycles 2085system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 282164000 # number of ReadReq MSHR uncacheable cycles 2086system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 296061500 # number of ReadReq MSHR uncacheable cycles 2087system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 208391000 # number of WriteReq MSHR uncacheable cycles 2088system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 208391000 # number of WriteReq MSHR uncacheable cycles 2089system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13897500 # number of overall MSHR uncacheable cycles 2090system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 490555000 # number of overall MSHR uncacheable cycles 2091system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504452500 # number of overall MSHR uncacheable cycles 2092system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for ReadReq accesses 2093system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for ReadReq accesses 2094system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.112779 # mshr miss rate for ReadReq accesses | 2069system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses 2070system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5840 # number of overall MSHR uncacheable misses 2071system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3160000 # number of ReadReq MSHR miss cycles 2072system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2825000 # number of ReadReq MSHR miss cycles 2073system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 5985000 # number of ReadReq MSHR miss cycles 2074system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2001835233 # number of HardPFReq MSHR miss cycles 2075system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2001835233 # number of HardPFReq MSHR miss cycles 2076system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 631483000 # number of UpgradeReq MSHR miss cycles 2077system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 631483000 # number of UpgradeReq MSHR miss cycles 2078system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 426660000 # number of SCUpgradeReq MSHR miss cycles 2079system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 426660000 # number of SCUpgradeReq MSHR miss cycles 2080system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5054000 # number of SCUpgradeFailReq MSHR miss cycles 2081system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5054000 # number of SCUpgradeFailReq MSHR miss cycles 2082system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1652764500 # number of ReadExReq MSHR miss cycles 2083system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1652764500 # number of ReadExReq MSHR miss cycles 2084system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 727255500 # number of ReadCleanReq MSHR miss cycles 2085system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 727255500 # number of ReadCleanReq MSHR miss cycles 2086system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1223626000 # number of ReadSharedReq MSHR miss cycles 2087system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1223626000 # number of ReadSharedReq MSHR miss cycles 2088system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 3160000 # number of demand (read+write) MSHR miss cycles 2089system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2825000 # number of demand (read+write) MSHR miss cycles 2090system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 727255500 # number of demand (read+write) MSHR miss cycles 2091system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2876390500 # number of demand (read+write) MSHR miss cycles 2092system.cpu1.l2cache.demand_mshr_miss_latency::total 3609631000 # number of demand (read+write) MSHR miss cycles 2093system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 3160000 # number of overall MSHR miss cycles 2094system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2825000 # number of overall MSHR miss cycles 2095system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 727255500 # number of overall MSHR miss cycles 2096system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2876390500 # number of overall MSHR miss cycles 2097system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2001835233 # number of overall MSHR miss cycles 2098system.cpu1.l2cache.overall_mshr_miss_latency::total 5611466233 # number of overall MSHR miss cycles 2099system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22647500 # number of ReadReq MSHR uncacheable cycles 2100system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 395196500 # number of ReadReq MSHR uncacheable cycles 2101system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 417844000 # number of ReadReq MSHR uncacheable cycles 2102system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 277400500 # number of WriteReq MSHR uncacheable cycles 2103system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 277400500 # number of WriteReq MSHR uncacheable cycles 2104system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22647500 # number of overall MSHR uncacheable cycles 2105system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 672597000 # number of overall MSHR uncacheable cycles 2106system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 695244500 # number of overall MSHR uncacheable cycles 2107system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for ReadReq accesses 2108system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for ReadReq accesses 2109system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041953 # mshr miss rate for ReadReq accesses |
| 2095system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2096system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2097system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2098system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2110system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2111system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2112system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2113system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2099system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950225 # mshr miss rate for UpgradeReq accesses 2100system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950225 # mshr miss rate for UpgradeReq accesses 2101system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962591 # mshr miss rate for SCUpgradeReq accesses 2102system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962591 # mshr miss rate for SCUpgradeReq accesses | 2114system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.942414 # mshr miss rate for UpgradeReq accesses 2115system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.942414 # mshr miss rate for UpgradeReq accesses 2116system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954027 # mshr miss rate for SCUpgradeReq accesses 2117system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954027 # mshr miss rate for SCUpgradeReq accesses |
| 2103system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2104system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2118system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2119system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2105system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550373 # mshr miss rate for ReadExReq accesses 2106system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550373 # mshr miss rate for ReadExReq accesses 2107system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for ReadCleanReq accesses 2108system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadCleanReq accesses 2109system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402728 # mshr miss rate for ReadSharedReq accesses 2110system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402728 # mshr miss rate for ReadSharedReq accesses 2111system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for demand accesses 2112system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for demand accesses 2113system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for demand accesses 2114system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for demand accesses 2115system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses 2116system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for overall accesses 2117system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for overall accesses 2118system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for overall accesses 2119system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for overall accesses | 2120system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.386863 # mshr miss rate for ReadExReq accesses 2121system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.386863 # mshr miss rate for ReadExReq accesses 2122system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for ReadCleanReq accesses 2123system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.030944 # mshr miss rate for ReadCleanReq accesses 2124system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.296596 # mshr miss rate for ReadSharedReq accesses 2125system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.296596 # mshr miss rate for ReadSharedReq accesses 2126system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for demand accesses 2127system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for demand accesses 2128system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for demand accesses 2129system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for demand accesses 2130system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132116 # mshr miss rate for demand accesses 2131system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for overall accesses 2132system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for overall accesses 2133system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for overall accesses 2134system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for overall accesses |
| 2120system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2135system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2121system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189766 # mshr miss rate for overall accesses 2122system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average ReadReq mshr miss latency 2123system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average ReadReq mshr miss latency 2124system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14076.539101 # average ReadReq mshr miss latency 2125system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average HardPFReq mshr miss latency 2126system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35399.651782 # average HardPFReq mshr miss latency 2127system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16132.527727 # average UpgradeReq mshr miss latency 2128system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16132.527727 # average UpgradeReq mshr miss latency 2129system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15482.397823 # average SCUpgradeReq mshr miss latency 2130system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823 # average SCUpgradeReq mshr miss latency 2131system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1082750 # average SCUpgradeFailReq mshr miss latency 2132system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1082750 # average SCUpgradeFailReq mshr miss latency 2133system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683 # average ReadExReq mshr miss latency 2134system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683 # average ReadExReq mshr miss latency 2135system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average ReadCleanReq mshr miss latency 2136system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732 # average ReadCleanReq mshr miss latency 2137system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869 # average ReadSharedReq mshr miss latency 2138system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869 # average ReadSharedReq mshr miss latency 2139system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency 2140system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency 2141system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency 2142system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency 2143system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21899.528115 # average overall mshr miss latency 2144system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency 2145system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency 2146system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency 2147system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency 2148system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average overall mshr miss latency 2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470 # average overall mshr miss latency 2150system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average ReadReq mshr uncacheable latency 2151system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137 # average ReadReq mshr uncacheable latency 2152system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689 # average ReadReq mshr uncacheable latency 2153system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093 # average WriteReq mshr uncacheable latency 2154system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093 # average WriteReq mshr uncacheable latency 2155system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average overall mshr uncacheable latency 2156system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961 # average overall mshr uncacheable latency 2157system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 104225.723140 # average overall mshr uncacheable latency | 2136system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168343 # mshr miss rate for overall accesses 2137system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average ReadReq mshr miss latency 2138system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average ReadReq mshr miss latency 2139system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15545.454545 # average ReadReq mshr miss latency 2140system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average HardPFReq mshr miss latency 2141system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57126.740283 # average HardPFReq mshr miss latency 2142system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22278.461810 # average UpgradeReq mshr miss latency 2143system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22278.461810 # average UpgradeReq mshr miss latency 2144system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788 # average SCUpgradeReq mshr miss latency 2145system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788 # average SCUpgradeReq mshr miss latency 2146system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2527000 # average SCUpgradeFailReq mshr miss latency 2147system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2527000 # average SCUpgradeFailReq mshr miss latency 2148system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604 # average ReadExReq mshr miss latency 2149system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604 # average ReadExReq mshr miss latency 2150system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average ReadCleanReq mshr miss latency 2151system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454 # average ReadCleanReq mshr miss latency 2152system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958 # average ReadSharedReq mshr miss latency 2153system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958 # average ReadSharedReq mshr miss latency 2154system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency 2155system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency 2156system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency 2157system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency 2158system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169 # average overall mshr miss latency 2159system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency 2160system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency 2161system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency 2162system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency 2163system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average overall mshr miss latency 2164system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734 # average overall mshr miss latency 2165system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average ReadReq mshr uncacheable latency 2166system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517 # average ReadReq mshr uncacheable latency 2167system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506 # average ReadReq mshr uncacheable latency 2168system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492 # average WriteReq mshr uncacheable latency 2169system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492 # average WriteReq mshr uncacheable latency 2170system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average overall mshr uncacheable latency 2171system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696 # average overall mshr uncacheable latency 2172system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753 # average overall mshr uncacheable latency |
| 2158system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2173system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2159system.cpu1.toL2Bus.trans_dist::ReadReq 53417 # Transaction distribution 2160system.cpu1.toL2Bus.trans_dist::ReadResp 719726 # Transaction distribution 2161system.cpu1.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution 2162system.cpu1.toL2Bus.trans_dist::WriteResp 2155 # Transaction distribution 2163system.cpu1.toL2Bus.trans_dist::Writeback 479672 # Transaction distribution 2164system.cpu1.toL2Bus.trans_dist::CleanEvict 677908 # Transaction distribution 2165system.cpu1.toL2Bus.trans_dist::HardPFReq 29213 # Transaction distribution 2166system.cpu1.toL2Bus.trans_dist::UpgradeReq 72925 # Transaction distribution 2167system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41207 # Transaction distribution 2168system.cpu1.toL2Bus.trans_dist::UpgradeResp 85236 # Transaction distribution 2169system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 2170system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution 2171system.cpu1.toL2Bus.trans_dist::ReadExReq 84437 # Transaction distribution 2172system.cpu1.toL2Bus.trans_dist::ReadExResp 66918 # Transaction distribution 2173system.cpu1.toL2Bus.trans_dist::ReadCleanReq 502041 # Transaction distribution 2174system.cpu1.toL2Bus.trans_dist::ReadSharedReq 506824 # Transaction distribution 2175system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 2176system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1497175 # Packet count per connected master and slave (bytes) 2177system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 834504 # Packet count per connected master and slave (bytes) 2178system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5289 # Packet count per connected master and slave (bytes) 2179system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9415 # Packet count per connected master and slave (bytes) 2180system.cpu1.toL2Bus.pkt_count::total 2346383 # Packet count per connected master and slave (bytes) 2181system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32131332 # Cumulative packet size per connected master and slave (bytes) 2182system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24936310 # Cumulative packet size per connected master and slave (bytes) 2183system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7860 # Cumulative packet size per connected master and slave (bytes) 2184system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13456 # Cumulative packet size per connected master and slave (bytes) 2185system.cpu1.toL2Bus.pkt_size::total 57088958 # Cumulative packet size per connected master and slave (bytes) 2186system.cpu1.toL2Bus.snoops 1117653 # Total snoops (count) 2187system.cpu1.toL2Bus.snoop_fanout::samples 2525896 # Request fanout histogram 2188system.cpu1.toL2Bus.snoop_fanout::mean 1.414848 # Request fanout histogram 2189system.cpu1.toL2Bus.snoop_fanout::stdev 0.492696 # Request fanout histogram | 2174system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. 2175system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2176system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2177system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. 2178system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2179system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2180system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution 2181system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution 2182system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution 2183system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution 2184system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution 2185system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution 2186system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution 2187system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution 2188system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution 2189system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution 2190system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution 2191system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 2192system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution 2193system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution 2194system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution 2195system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution 2196system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution 2197system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) 2198system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) 2199system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) 2200system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) 2201system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) 2202system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) 2203system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) 2204system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) 2205system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) 2206system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) 2207system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) 2208system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram 2209system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram 2210system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram |
| 2190system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2211system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2191system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2192system.cpu1.toL2Bus.snoop_fanout::1 1478032 58.52% 58.52% # Request fanout histogram 2193system.cpu1.toL2Bus.snoop_fanout::2 1047864 41.48% 100.00% # Request fanout histogram | 2212system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram 2213system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram 2214system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram |
| 2194system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2215system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2195system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 2216system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 2196system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2217system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2197system.cpu1.toL2Bus.snoop_fanout::total 2525896 # Request fanout histogram 2198system.cpu1.toL2Bus.reqLayer0.occupancy 861521000 # Layer occupancy (ticks) | 2218system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram 2219system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) |
| 2199system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2220system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2200system.cpu1.toL2Bus.snoopLayer0.occupancy 79810000 # Layer occupancy (ticks) | 2221system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) |
| 2201system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2222system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2202system.cpu1.toL2Bus.respLayer0.occupancy 753238500 # Layer occupancy (ticks) | 2223system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) |
| 2203system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2224system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2204system.cpu1.toL2Bus.respLayer1.occupancy 375346000 # Layer occupancy (ticks) | 2225system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) |
| 2205system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2226system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2206system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) | 2227system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) |
| 2207system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2228system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2208system.cpu1.toL2Bus.respLayer3.occupancy 6051499 # Layer occupancy (ticks) | 2229system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) |
| 2209system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2230system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2210system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2211system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2212system.iobus.trans_dist::WriteReq 59423 # Transaction distribution 2213system.iobus.trans_dist::WriteResp 59423 # Transaction distribution 2214system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) | 2231system.iobus.trans_dist::ReadReq 31011 # Transaction distribution 2232system.iobus.trans_dist::ReadResp 31011 # Transaction distribution 2233system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2234system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2235system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) |
| 2215system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2216system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2217system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2218system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2219system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2220system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2221system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2222system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2227system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2228system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2229system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2230system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2231system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2232system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2233system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2234system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2236system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2237system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2238system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2239system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2240system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2241system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2242system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2243system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2248system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2249system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2250system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2251system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2252system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2253system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2254system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2255system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2235system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) 2236system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2237system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2238system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) 2239system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) | 2256system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) 2257system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) 2258system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) 2259system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) 2260system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) |
| 2240system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2241system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2242system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2243system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2244system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2245system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2246system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2247system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2252system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2253system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2254system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2255system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2256system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2257system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2259system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2261system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2262system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2263system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2264system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2265system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2266system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2267system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2268system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2273system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2274system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2275system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2276system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2277system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2278system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2279system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2280system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2260system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) 2261system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2262system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2263system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) 2264system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) | 2281system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) 2282system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) 2283system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) 2284system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) 2285system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) |
| 2265system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2266system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2267system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2268system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2269system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2270system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2271system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2272system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2296system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2297system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2298system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2299system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2301system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2302system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2303system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2286system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2287system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2288system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2289system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2290system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2291system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2292system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2293system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2317system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2318system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2319system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2320system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2321system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2322system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2323system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2324system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2304system.iobus.reqLayer27.occupancy 187554192 # Layer occupancy (ticks) | 2325system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) |
| 2305system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2306system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2307system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2326system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2327system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2328system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2308system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) | 2329system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) |
| 2309system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2330system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2310system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) | 2331system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) |
| 2311system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2332system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2312system.iocache.tags.replacements 36445 # number of replacements 2313system.iocache.tags.tagsinuse 14.390549 # Cycle average of tags in use | 2333system.iocache.tags.replacements 36460 # number of replacements 2334system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use |
| 2314system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2335system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2315system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. | 2336system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. |
| 2316system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2337system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2317system.iocache.tags.warmup_cycle 288373025000 # Cycle when the warmup percentage was hit. 2318system.iocache.tags.occ_blocks::realview.ide 14.390549 # Average occupied blocks per requestor 2319system.iocache.tags.occ_percent::realview.ide 0.899409 # Average percentage of cache occupancy 2320system.iocache.tags.occ_percent::total 0.899409 # Average percentage of cache occupancy | 2338system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. 2339system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor 2340system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy 2341system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy |
| 2321system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2322system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2323system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2342system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2343system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2344system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2324system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2325system.iocache.tags.data_accesses 328311 # Number of data accesses 2326system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2327system.iocache.ReadReq_misses::total 255 # number of ReadReq misses | 2345system.iocache.tags.tag_accesses 328302 # Number of tag accesses 2346system.iocache.tags.data_accesses 328302 # Number of data accesses 2347system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses 2348system.iocache.ReadReq_misses::total 254 # number of ReadReq misses |
| 2328system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2329system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 2349system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2350system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 2330system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2331system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2332system.iocache.overall_misses::realview.ide 255 # number of overall misses 2333system.iocache.overall_misses::total 255 # number of overall misses 2334system.iocache.ReadReq_miss_latency::realview.ide 32657877 # number of ReadReq miss cycles 2335system.iocache.ReadReq_miss_latency::total 32657877 # number of ReadReq miss cycles 2336system.iocache.WriteLineReq_miss_latency::realview.ide 4277536315 # number of WriteLineReq miss cycles 2337system.iocache.WriteLineReq_miss_latency::total 4277536315 # number of WriteLineReq miss cycles 2338system.iocache.demand_miss_latency::realview.ide 32657877 # number of demand (read+write) miss cycles 2339system.iocache.demand_miss_latency::total 32657877 # number of demand (read+write) miss cycles 2340system.iocache.overall_miss_latency::realview.ide 32657877 # number of overall miss cycles 2341system.iocache.overall_miss_latency::total 32657877 # number of overall miss cycles 2342system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2343system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) | 2351system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses 2352system.iocache.demand_misses::total 254 # number of demand (read+write) misses 2353system.iocache.overall_misses::realview.ide 254 # number of overall misses 2354system.iocache.overall_misses::total 254 # number of overall misses 2355system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles 2356system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles 2357system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles 2358system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles 2359system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles 2360system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles 2361system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles 2362system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles 2363system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) 2364system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) |
| 2344system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2345system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 2365system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2366system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 2346system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2347system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2348system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2349system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses | 2367system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses 2368system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses 2369system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses 2370system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses |
| 2350system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2351system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2352system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2353system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2354system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2355system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2356system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2357system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2371system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2372system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2373system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2374system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2375system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2376system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2377system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2378system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2358system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882 # average ReadReq miss latency 2359system.iocache.ReadReq_avg_miss_latency::total 128070.105882 # average ReadReq miss latency 2360system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742 # average WriteLineReq miss latency 2361system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742 # average WriteLineReq miss latency 2362system.iocache.demand_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency 2363system.iocache.demand_avg_miss_latency::total 128070.105882 # average overall miss latency 2364system.iocache.overall_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency 2365system.iocache.overall_avg_miss_latency::total 128070.105882 # average overall miss latency 2366system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked | 2379system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency 2380system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency 2381system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency 2382system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency 2383system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency 2384system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency 2385system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency 2386system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency 2387system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked |
| 2367system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2388system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2368system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked | 2389system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked |
| 2369system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2390system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2370system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked | 2391system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked |
| 2371system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2372system.iocache.fast_writes 0 # number of fast writes performed 2373system.iocache.cache_copies 0 # number of cache copies performed | 2392system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2393system.iocache.fast_writes 0 # number of fast writes performed 2394system.iocache.cache_copies 0 # number of cache copies performed |
| 2374system.iocache.writebacks::writebacks 36190 # number of writebacks 2375system.iocache.writebacks::total 36190 # number of writebacks 2376system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2377system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses | 2395system.iocache.writebacks::writebacks 36206 # number of writebacks 2396system.iocache.writebacks::total 36206 # number of writebacks 2397system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses 2398system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses |
| 2378system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2379system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 2399system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2400system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 2380system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2381system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2382system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2383system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses 2384system.iocache.ReadReq_mshr_miss_latency::realview.ide 19907877 # number of ReadReq MSHR miss cycles 2385system.iocache.ReadReq_mshr_miss_latency::total 19907877 # number of ReadReq MSHR miss cycles 2386system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466336315 # number of WriteLineReq MSHR miss cycles 2387system.iocache.WriteLineReq_mshr_miss_latency::total 2466336315 # number of WriteLineReq MSHR miss cycles 2388system.iocache.demand_mshr_miss_latency::realview.ide 19907877 # number of demand (read+write) MSHR miss cycles 2389system.iocache.demand_mshr_miss_latency::total 19907877 # number of demand (read+write) MSHR miss cycles 2390system.iocache.overall_mshr_miss_latency::realview.ide 19907877 # number of overall MSHR miss cycles 2391system.iocache.overall_mshr_miss_latency::total 19907877 # number of overall MSHR miss cycles | 2401system.iocache.demand_mshr_misses::realview.ide 254 # number of demand (read+write) MSHR misses 2402system.iocache.demand_mshr_misses::total 254 # number of demand (read+write) MSHR misses 2403system.iocache.overall_mshr_misses::realview.ide 254 # number of overall MSHR misses 2404system.iocache.overall_mshr_misses::total 254 # number of overall MSHR misses 2405system.iocache.ReadReq_mshr_miss_latency::realview.ide 20310877 # number of ReadReq MSHR miss cycles 2406system.iocache.ReadReq_mshr_miss_latency::total 20310877 # number of ReadReq MSHR miss cycles 2407system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906590097 # number of WriteLineReq MSHR miss cycles 2408system.iocache.WriteLineReq_mshr_miss_latency::total 2906590097 # number of WriteLineReq MSHR miss cycles 2409system.iocache.demand_mshr_miss_latency::realview.ide 20310877 # number of demand (read+write) MSHR miss cycles 2410system.iocache.demand_mshr_miss_latency::total 20310877 # number of demand (read+write) MSHR miss cycles 2411system.iocache.overall_mshr_miss_latency::realview.ide 20310877 # number of overall MSHR miss cycles 2412system.iocache.overall_mshr_miss_latency::total 20310877 # number of overall MSHR miss cycles |
| 2392system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2393system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2394system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2395system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2396system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2397system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2398system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2399system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2413system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2414system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2415system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2416system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2417system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2418system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2419system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2420system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2400system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78070.105882 # average ReadReq mshr miss latency 2401system.iocache.ReadReq_avg_mshr_miss_latency::total 78070.105882 # average ReadReq mshr miss latency 2402system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68085.697742 # average WriteLineReq mshr miss latency 2403system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68085.697742 # average WriteLineReq mshr miss latency 2404system.iocache.demand_avg_mshr_miss_latency::realview.ide 78070.105882 # average overall mshr miss latency 2405system.iocache.demand_avg_mshr_miss_latency::total 78070.105882 # average overall mshr miss latency 2406system.iocache.overall_avg_mshr_miss_latency::realview.ide 78070.105882 # average overall mshr miss latency 2407system.iocache.overall_avg_mshr_miss_latency::total 78070.105882 # average overall mshr miss latency | 2421system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79964.082677 # average ReadReq mshr miss latency 2422system.iocache.ReadReq_avg_mshr_miss_latency::total 79964.082677 # average ReadReq mshr miss latency 2423system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80239.346759 # average WriteLineReq mshr miss latency 2424system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80239.346759 # average WriteLineReq mshr miss latency 2425system.iocache.demand_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency 2426system.iocache.demand_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency 2427system.iocache.overall_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency 2428system.iocache.overall_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency |
| 2408system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2429system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2409system.l2c.tags.replacements 130014 # number of replacements 2410system.l2c.tags.tagsinuse 63961.093315 # Cycle average of tags in use 2411system.l2c.tags.total_refs 392369 # Total number of references to valid blocks. 2412system.l2c.tags.sampled_refs 194378 # Sample count of references to valid blocks. 2413system.l2c.tags.avg_refs 2.018587 # Average number of references to valid blocks. | 2430system.l2c.tags.replacements 127982 # number of replacements 2431system.l2c.tags.tagsinuse 63841.400540 # Cycle average of tags in use 2432system.l2c.tags.total_refs 386797 # Total number of references to valid blocks. 2433system.l2c.tags.sampled_refs 192628 # Sample count of references to valid blocks. 2434system.l2c.tags.avg_refs 2.008000 # Average number of references to valid blocks. |
| 2414system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2435system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2415system.l2c.tags.occ_blocks::writebacks 12058.686901 # Average occupied blocks per requestor 2416system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.020417 # Average occupied blocks per requestor 2417system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045313 # Average occupied blocks per requestor 2418system.l2c.tags.occ_blocks::cpu0.inst 7839.345721 # Average occupied blocks per requestor 2419system.l2c.tags.occ_blocks::cpu0.data 2905.478880 # Average occupied blocks per requestor 2420system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37500.688357 # Average occupied blocks per requestor 2421system.l2c.tags.occ_blocks::cpu1.inst 950.717991 # Average occupied blocks per requestor 2422system.l2c.tags.occ_blocks::cpu1.data 465.629828 # Average occupied blocks per requestor 2423system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2237.479906 # Average occupied blocks per requestor 2424system.l2c.tags.occ_percent::writebacks 0.184001 # Average percentage of cache occupancy 2425system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000046 # Average percentage of cache occupancy | 2436system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor 2437system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor 2438system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor 2439system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor 2440system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # Average occupied blocks per requestor 2441system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37403.783442 # Average occupied blocks per requestor 2442system.l2c.tags.occ_blocks::cpu1.inst 1406.932882 # Average occupied blocks per requestor 2443system.l2c.tags.occ_blocks::cpu1.data 489.801266 # Average occupied blocks per requestor 2444system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2179.617757 # Average occupied blocks per requestor 2445system.l2c.tags.occ_percent::writebacks 0.183960 # Average percentage of cache occupancy 2446system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy |
| 2426system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy | 2447system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy |
| 2427system.l2c.tags.occ_percent::cpu0.inst 0.119619 # Average percentage of cache occupancy 2428system.l2c.tags.occ_percent::cpu0.data 0.044334 # Average percentage of cache occupancy 2429system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572215 # Average percentage of cache occupancy 2430system.l2c.tags.occ_percent::cpu1.inst 0.014507 # Average percentage of cache occupancy 2431system.l2c.tags.occ_percent::cpu1.data 0.007105 # Average percentage of cache occupancy 2432system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034141 # Average percentage of cache occupancy 2433system.l2c.tags.occ_percent::total 0.975969 # Average percentage of cache occupancy 2434system.l2c.tags.occ_task_id_blocks::1022 32308 # Occupied blocks per task id | 2448system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy 2449system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy 2450system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy 2451system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy 2452system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy 2453system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy 2454system.l2c.tags.occ_percent::total 0.974142 # Average percentage of cache occupancy 2455system.l2c.tags.occ_task_id_blocks::1022 31928 # Occupied blocks per task id |
| 2435system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id | 2456system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id |
| 2436system.l2c.tags.occ_task_id_blocks::1024 32052 # Occupied blocks per task id 2437system.l2c.tags.age_task_id_blocks_1022::2 225 # Occupied blocks per task id 2438system.l2c.tags.age_task_id_blocks_1022::3 4677 # Occupied blocks per task id 2439system.l2c.tags.age_task_id_blocks_1022::4 27406 # Occupied blocks per task id | 2457system.l2c.tags.occ_task_id_blocks::1024 32714 # Occupied blocks per task id 2458system.l2c.tags.age_task_id_blocks_1022::2 74 # Occupied blocks per task id 2459system.l2c.tags.age_task_id_blocks_1022::3 4325 # Occupied blocks per task id 2460system.l2c.tags.age_task_id_blocks_1022::4 27529 # Occupied blocks per task id |
| 2440system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id | 2461system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id |
| 2441system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2442system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 2443system.l2c.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 2444system.l2c.tags.age_task_id_blocks_1024::3 1819 # Occupied blocks per task id 2445system.l2c.tags.age_task_id_blocks_1024::4 29951 # Occupied blocks per task id 2446system.l2c.tags.occ_task_id_percent::1022 0.492981 # Percentage of cache occupancy per task id | 2462system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 2463system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 2464system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 2465system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id 2466system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id 2467system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id |
| 2447system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id | 2468system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id |
| 2448system.l2c.tags.occ_task_id_percent::1024 0.489075 # Percentage of cache occupancy per task id 2449system.l2c.tags.tag_accesses 5325589 # Number of tag accesses 2450system.l2c.tags.data_accesses 5325589 # Number of data accesses 2451system.l2c.Writeback_hits::writebacks 226708 # number of Writeback hits 2452system.l2c.Writeback_hits::total 226708 # number of Writeback hits 2453system.l2c.UpgradeReq_hits::cpu0.data 2021 # number of UpgradeReq hits 2454system.l2c.UpgradeReq_hits::cpu1.data 691 # number of UpgradeReq hits 2455system.l2c.UpgradeReq_hits::total 2712 # number of UpgradeReq hits 2456system.l2c.SCUpgradeReq_hits::cpu0.data 141 # number of SCUpgradeReq hits 2457system.l2c.SCUpgradeReq_hits::cpu1.data 160 # number of SCUpgradeReq hits 2458system.l2c.SCUpgradeReq_hits::total 301 # number of SCUpgradeReq hits 2459system.l2c.ReadExReq_hits::cpu0.data 3915 # number of ReadExReq hits 2460system.l2c.ReadExReq_hits::cpu1.data 1420 # number of ReadExReq hits 2461system.l2c.ReadExReq_hits::total 5335 # number of ReadExReq hits 2462system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits 2463system.l2c.ReadSharedReq_hits::cpu0.itb.walker 55 # number of ReadSharedReq hits 2464system.l2c.ReadSharedReq_hits::cpu0.inst 30090 # number of ReadSharedReq hits 2465system.l2c.ReadSharedReq_hits::cpu0.data 45920 # number of ReadSharedReq hits 2466system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45888 # number of ReadSharedReq hits 2467system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 41 # number of ReadSharedReq hits 2468system.l2c.ReadSharedReq_hits::cpu1.itb.walker 34 # number of ReadSharedReq hits 2469system.l2c.ReadSharedReq_hits::cpu1.inst 11628 # number of ReadSharedReq hits 2470system.l2c.ReadSharedReq_hits::cpu1.data 8389 # number of ReadSharedReq hits 2471system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5369 # number of ReadSharedReq hits 2472system.l2c.ReadSharedReq_hits::total 147495 # number of ReadSharedReq hits 2473system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits 2474system.l2c.demand_hits::cpu0.itb.walker 55 # number of demand (read+write) hits 2475system.l2c.demand_hits::cpu0.inst 30090 # number of demand (read+write) hits 2476system.l2c.demand_hits::cpu0.data 49835 # number of demand (read+write) hits 2477system.l2c.demand_hits::cpu0.l2cache.prefetcher 45888 # number of demand (read+write) hits 2478system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits 2479system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits 2480system.l2c.demand_hits::cpu1.inst 11628 # number of demand (read+write) hits 2481system.l2c.demand_hits::cpu1.data 9809 # number of demand (read+write) hits 2482system.l2c.demand_hits::cpu1.l2cache.prefetcher 5369 # number of demand (read+write) hits 2483system.l2c.demand_hits::total 152830 # number of demand (read+write) hits 2484system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits 2485system.l2c.overall_hits::cpu0.itb.walker 55 # number of overall hits 2486system.l2c.overall_hits::cpu0.inst 30090 # number of overall hits 2487system.l2c.overall_hits::cpu0.data 49835 # number of overall hits 2488system.l2c.overall_hits::cpu0.l2cache.prefetcher 45888 # number of overall hits 2489system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits 2490system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits 2491system.l2c.overall_hits::cpu1.inst 11628 # number of overall hits 2492system.l2c.overall_hits::cpu1.data 9809 # number of overall hits 2493system.l2c.overall_hits::cpu1.l2cache.prefetcher 5369 # number of overall hits 2494system.l2c.overall_hits::total 152830 # number of overall hits 2495system.l2c.UpgradeReq_misses::cpu0.data 8373 # number of UpgradeReq misses 2496system.l2c.UpgradeReq_misses::cpu1.data 2542 # number of UpgradeReq misses 2497system.l2c.UpgradeReq_misses::total 10915 # number of UpgradeReq misses 2498system.l2c.SCUpgradeReq_misses::cpu0.data 478 # number of SCUpgradeReq misses 2499system.l2c.SCUpgradeReq_misses::cpu1.data 1195 # number of SCUpgradeReq misses 2500system.l2c.SCUpgradeReq_misses::total 1673 # number of SCUpgradeReq misses 2501system.l2c.ReadExReq_misses::cpu0.data 11367 # number of ReadExReq misses 2502system.l2c.ReadExReq_misses::cpu1.data 8062 # number of ReadExReq misses 2503system.l2c.ReadExReq_misses::total 19429 # number of ReadExReq misses 2504system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses | 2469system.l2c.tags.occ_task_id_percent::1024 0.499176 # Percentage of cache occupancy per task id 2470system.l2c.tags.tag_accesses 5261289 # Number of tag accesses 2471system.l2c.tags.data_accesses 5261289 # Number of data accesses 2472system.l2c.Writeback_hits::writebacks 224862 # number of Writeback hits 2473system.l2c.Writeback_hits::total 224862 # number of Writeback hits 2474system.l2c.UpgradeReq_hits::cpu0.data 1507 # number of UpgradeReq hits 2475system.l2c.UpgradeReq_hits::cpu1.data 1131 # number of UpgradeReq hits 2476system.l2c.UpgradeReq_hits::total 2638 # number of UpgradeReq hits 2477system.l2c.SCUpgradeReq_hits::cpu0.data 135 # number of SCUpgradeReq hits 2478system.l2c.SCUpgradeReq_hits::cpu1.data 177 # number of SCUpgradeReq hits 2479system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits 2480system.l2c.ReadExReq_hits::cpu0.data 3596 # number of ReadExReq hits 2481system.l2c.ReadExReq_hits::cpu1.data 1989 # number of ReadExReq hits 2482system.l2c.ReadExReq_hits::total 5585 # number of ReadExReq hits 2483system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 55 # number of ReadSharedReq hits 2484system.l2c.ReadSharedReq_hits::cpu0.itb.walker 33 # number of ReadSharedReq hits 2485system.l2c.ReadSharedReq_hits::cpu0.inst 23888 # number of ReadSharedReq hits 2486system.l2c.ReadSharedReq_hits::cpu0.data 41259 # number of ReadSharedReq hits 2487system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 41598 # number of ReadSharedReq hits 2488system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 52 # number of ReadSharedReq hits 2489system.l2c.ReadSharedReq_hits::cpu1.itb.walker 64 # number of ReadSharedReq hits 2490system.l2c.ReadSharedReq_hits::cpu1.inst 16804 # number of ReadSharedReq hits 2491system.l2c.ReadSharedReq_hits::cpu1.data 11932 # number of ReadSharedReq hits 2492system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 9486 # number of ReadSharedReq hits 2493system.l2c.ReadSharedReq_hits::total 145171 # number of ReadSharedReq hits 2494system.l2c.demand_hits::cpu0.dtb.walker 55 # number of demand (read+write) hits 2495system.l2c.demand_hits::cpu0.itb.walker 33 # number of demand (read+write) hits 2496system.l2c.demand_hits::cpu0.inst 23888 # number of demand (read+write) hits 2497system.l2c.demand_hits::cpu0.data 44855 # number of demand (read+write) hits 2498system.l2c.demand_hits::cpu0.l2cache.prefetcher 41598 # number of demand (read+write) hits 2499system.l2c.demand_hits::cpu1.dtb.walker 52 # number of demand (read+write) hits 2500system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits 2501system.l2c.demand_hits::cpu1.inst 16804 # number of demand (read+write) hits 2502system.l2c.demand_hits::cpu1.data 13921 # number of demand (read+write) hits 2503system.l2c.demand_hits::cpu1.l2cache.prefetcher 9486 # number of demand (read+write) hits 2504system.l2c.demand_hits::total 150756 # number of demand (read+write) hits 2505system.l2c.overall_hits::cpu0.dtb.walker 55 # number of overall hits 2506system.l2c.overall_hits::cpu0.itb.walker 33 # number of overall hits 2507system.l2c.overall_hits::cpu0.inst 23888 # number of overall hits 2508system.l2c.overall_hits::cpu0.data 44855 # number of overall hits 2509system.l2c.overall_hits::cpu0.l2cache.prefetcher 41598 # number of overall hits 2510system.l2c.overall_hits::cpu1.dtb.walker 52 # number of overall hits 2511system.l2c.overall_hits::cpu1.itb.walker 64 # number of overall hits 2512system.l2c.overall_hits::cpu1.inst 16804 # number of overall hits 2513system.l2c.overall_hits::cpu1.data 13921 # number of overall hits 2514system.l2c.overall_hits::cpu1.l2cache.prefetcher 9486 # number of overall hits 2515system.l2c.overall_hits::total 150756 # number of overall hits 2516system.l2c.UpgradeReq_misses::cpu0.data 6940 # number of UpgradeReq misses 2517system.l2c.UpgradeReq_misses::cpu1.data 4223 # number of UpgradeReq misses 2518system.l2c.UpgradeReq_misses::total 11163 # number of UpgradeReq misses 2519system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses 2520system.l2c.SCUpgradeReq_misses::cpu1.data 1268 # number of SCUpgradeReq misses 2521system.l2c.SCUpgradeReq_misses::total 1693 # number of SCUpgradeReq misses 2522system.l2c.ReadExReq_misses::cpu0.data 11072 # number of ReadExReq misses 2523system.l2c.ReadExReq_misses::cpu1.data 8126 # number of ReadExReq misses 2524system.l2c.ReadExReq_misses::total 19198 # number of ReadExReq misses 2525system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses |
| 2505system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses | 2526system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses |
| 2506system.l2c.ReadSharedReq_misses::cpu0.inst 17941 # number of ReadSharedReq misses 2507system.l2c.ReadSharedReq_misses::cpu0.data 8815 # number of ReadSharedReq misses 2508system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134305 # number of ReadSharedReq misses 2509system.l2c.ReadSharedReq_misses::cpu1.inst 1735 # number of ReadSharedReq misses 2510system.l2c.ReadSharedReq_misses::cpu1.data 851 # number of ReadSharedReq misses 2511system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6450 # number of ReadSharedReq misses 2512system.l2c.ReadSharedReq_misses::total 170106 # number of ReadSharedReq misses 2513system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses | 2527system.l2c.ReadSharedReq_misses::cpu0.inst 17201 # number of ReadSharedReq misses 2528system.l2c.ReadSharedReq_misses::cpu0.data 8649 # number of ReadSharedReq misses 2529system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128053 # number of ReadSharedReq misses 2530system.l2c.ReadSharedReq_misses::cpu1.inst 2469 # number of ReadSharedReq misses 2531system.l2c.ReadSharedReq_misses::cpu1.data 1018 # number of ReadSharedReq misses 2532system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 10524 # number of ReadSharedReq misses 2533system.l2c.ReadSharedReq_misses::total 167922 # number of ReadSharedReq misses 2534system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses |
| 2514system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 2535system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 2515system.l2c.demand_misses::cpu0.inst 17941 # number of demand (read+write) misses 2516system.l2c.demand_misses::cpu0.data 20182 # number of demand (read+write) misses 2517system.l2c.demand_misses::cpu0.l2cache.prefetcher 134305 # number of demand (read+write) misses 2518system.l2c.demand_misses::cpu1.inst 1735 # number of demand (read+write) misses 2519system.l2c.demand_misses::cpu1.data 8913 # number of demand (read+write) misses 2520system.l2c.demand_misses::cpu1.l2cache.prefetcher 6450 # number of demand (read+write) misses 2521system.l2c.demand_misses::total 189535 # number of demand (read+write) misses 2522system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses | 2536system.l2c.demand_misses::cpu0.inst 17201 # number of demand (read+write) misses 2537system.l2c.demand_misses::cpu0.data 19721 # number of demand (read+write) misses 2538system.l2c.demand_misses::cpu0.l2cache.prefetcher 128053 # number of demand (read+write) misses 2539system.l2c.demand_misses::cpu1.inst 2469 # number of demand (read+write) misses 2540system.l2c.demand_misses::cpu1.data 9144 # number of demand (read+write) misses 2541system.l2c.demand_misses::cpu1.l2cache.prefetcher 10524 # number of demand (read+write) misses 2542system.l2c.demand_misses::total 187120 # number of demand (read+write) misses 2543system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses |
| 2523system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 2544system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 2524system.l2c.overall_misses::cpu0.inst 17941 # number of overall misses 2525system.l2c.overall_misses::cpu0.data 20182 # number of overall misses 2526system.l2c.overall_misses::cpu0.l2cache.prefetcher 134305 # number of overall misses 2527system.l2c.overall_misses::cpu1.inst 1735 # number of overall misses 2528system.l2c.overall_misses::cpu1.data 8913 # number of overall misses 2529system.l2c.overall_misses::cpu1.l2cache.prefetcher 6450 # number of overall misses 2530system.l2c.overall_misses::total 189535 # number of overall misses 2531system.l2c.UpgradeReq_miss_latency::cpu0.data 7787500 # number of UpgradeReq miss cycles 2532system.l2c.UpgradeReq_miss_latency::cpu1.data 2669500 # number of UpgradeReq miss cycles 2533system.l2c.UpgradeReq_miss_latency::total 10457000 # number of UpgradeReq miss cycles 2534system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1236500 # number of SCUpgradeReq miss cycles 2535system.l2c.SCUpgradeReq_miss_latency::cpu1.data 708000 # number of SCUpgradeReq miss cycles 2536system.l2c.SCUpgradeReq_miss_latency::total 1944500 # number of SCUpgradeReq miss cycles 2537system.l2c.ReadExReq_miss_latency::cpu0.data 1092065500 # number of ReadExReq miss cycles 2538system.l2c.ReadExReq_miss_latency::cpu1.data 658722000 # number of ReadExReq miss cycles 2539system.l2c.ReadExReq_miss_latency::total 1750787500 # number of ReadExReq miss cycles 2540system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 816000 # number of ReadSharedReq miss cycles 2541system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 166000 # number of ReadSharedReq miss cycles 2542system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1444848500 # number of ReadSharedReq miss cycles 2543system.l2c.ReadSharedReq_miss_latency::cpu0.data 766909500 # number of ReadSharedReq miss cycles 2544system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12944226902 # number of ReadSharedReq miss cycles 2545system.l2c.ReadSharedReq_miss_latency::cpu1.inst 144716500 # number of ReadSharedReq miss cycles 2546system.l2c.ReadSharedReq_miss_latency::cpu1.data 75717500 # number of ReadSharedReq miss cycles 2547system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 743765397 # number of ReadSharedReq miss cycles 2548system.l2c.ReadSharedReq_miss_latency::total 16121166299 # number of ReadSharedReq miss cycles 2549system.l2c.demand_miss_latency::cpu0.dtb.walker 816000 # number of demand (read+write) miss cycles 2550system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles 2551system.l2c.demand_miss_latency::cpu0.inst 1444848500 # number of demand (read+write) miss cycles 2552system.l2c.demand_miss_latency::cpu0.data 1858975000 # number of demand (read+write) miss cycles 2553system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12944226902 # number of demand (read+write) miss cycles 2554system.l2c.demand_miss_latency::cpu1.inst 144716500 # number of demand (read+write) miss cycles 2555system.l2c.demand_miss_latency::cpu1.data 734439500 # number of demand (read+write) miss cycles 2556system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 743765397 # number of demand (read+write) miss cycles 2557system.l2c.demand_miss_latency::total 17871953799 # number of demand (read+write) miss cycles 2558system.l2c.overall_miss_latency::cpu0.dtb.walker 816000 # number of overall miss cycles 2559system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles 2560system.l2c.overall_miss_latency::cpu0.inst 1444848500 # number of overall miss cycles 2561system.l2c.overall_miss_latency::cpu0.data 1858975000 # number of overall miss cycles 2562system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12944226902 # number of overall miss cycles 2563system.l2c.overall_miss_latency::cpu1.inst 144716500 # number of overall miss cycles 2564system.l2c.overall_miss_latency::cpu1.data 734439500 # number of overall miss cycles 2565system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 743765397 # number of overall miss cycles 2566system.l2c.overall_miss_latency::total 17871953799 # number of overall miss cycles 2567system.l2c.Writeback_accesses::writebacks 226708 # number of Writeback accesses(hits+misses) 2568system.l2c.Writeback_accesses::total 226708 # number of Writeback accesses(hits+misses) 2569system.l2c.UpgradeReq_accesses::cpu0.data 10394 # number of UpgradeReq accesses(hits+misses) 2570system.l2c.UpgradeReq_accesses::cpu1.data 3233 # number of UpgradeReq accesses(hits+misses) 2571system.l2c.UpgradeReq_accesses::total 13627 # number of UpgradeReq accesses(hits+misses) 2572system.l2c.SCUpgradeReq_accesses::cpu0.data 619 # number of SCUpgradeReq accesses(hits+misses) 2573system.l2c.SCUpgradeReq_accesses::cpu1.data 1355 # number of SCUpgradeReq accesses(hits+misses) 2574system.l2c.SCUpgradeReq_accesses::total 1974 # number of SCUpgradeReq accesses(hits+misses) 2575system.l2c.ReadExReq_accesses::cpu0.data 15282 # number of ReadExReq accesses(hits+misses) 2576system.l2c.ReadExReq_accesses::cpu1.data 9482 # number of ReadExReq accesses(hits+misses) 2577system.l2c.ReadExReq_accesses::total 24764 # number of ReadExReq accesses(hits+misses) 2578system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 88 # number of ReadSharedReq accesses(hits+misses) 2579system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 57 # number of ReadSharedReq accesses(hits+misses) 2580system.l2c.ReadSharedReq_accesses::cpu0.inst 48031 # number of ReadSharedReq accesses(hits+misses) 2581system.l2c.ReadSharedReq_accesses::cpu0.data 54735 # number of ReadSharedReq accesses(hits+misses) 2582system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180193 # number of ReadSharedReq accesses(hits+misses) 2583system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 41 # number of ReadSharedReq accesses(hits+misses) 2584system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 34 # number of ReadSharedReq accesses(hits+misses) 2585system.l2c.ReadSharedReq_accesses::cpu1.inst 13363 # number of ReadSharedReq accesses(hits+misses) 2586system.l2c.ReadSharedReq_accesses::cpu1.data 9240 # number of ReadSharedReq accesses(hits+misses) 2587system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11819 # number of ReadSharedReq accesses(hits+misses) 2588system.l2c.ReadSharedReq_accesses::total 317601 # number of ReadSharedReq accesses(hits+misses) 2589system.l2c.demand_accesses::cpu0.dtb.walker 88 # number of demand (read+write) accesses 2590system.l2c.demand_accesses::cpu0.itb.walker 57 # number of demand (read+write) accesses 2591system.l2c.demand_accesses::cpu0.inst 48031 # number of demand (read+write) accesses 2592system.l2c.demand_accesses::cpu0.data 70017 # number of demand (read+write) accesses 2593system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180193 # number of demand (read+write) accesses 2594system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses 2595system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses 2596system.l2c.demand_accesses::cpu1.inst 13363 # number of demand (read+write) accesses 2597system.l2c.demand_accesses::cpu1.data 18722 # number of demand (read+write) accesses 2598system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11819 # number of demand (read+write) accesses 2599system.l2c.demand_accesses::total 342365 # number of demand (read+write) accesses 2600system.l2c.overall_accesses::cpu0.dtb.walker 88 # number of overall (read+write) accesses 2601system.l2c.overall_accesses::cpu0.itb.walker 57 # number of overall (read+write) accesses 2602system.l2c.overall_accesses::cpu0.inst 48031 # number of overall (read+write) accesses 2603system.l2c.overall_accesses::cpu0.data 70017 # number of overall (read+write) accesses 2604system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180193 # number of overall (read+write) accesses 2605system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses 2606system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses 2607system.l2c.overall_accesses::cpu1.inst 13363 # number of overall (read+write) accesses 2608system.l2c.overall_accesses::cpu1.data 18722 # number of overall (read+write) accesses 2609system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11819 # number of overall (read+write) accesses 2610system.l2c.overall_accesses::total 342365 # number of overall (read+write) accesses 2611system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805561 # miss rate for UpgradeReq accesses 2612system.l2c.UpgradeReq_miss_rate::cpu1.data 0.786267 # miss rate for UpgradeReq accesses 2613system.l2c.UpgradeReq_miss_rate::total 0.800983 # miss rate for UpgradeReq accesses 2614system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772213 # miss rate for SCUpgradeReq accesses 2615system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.881919 # miss rate for SCUpgradeReq accesses 2616system.l2c.SCUpgradeReq_miss_rate::total 0.847518 # miss rate for SCUpgradeReq accesses 2617system.l2c.ReadExReq_miss_rate::cpu0.data 0.743816 # miss rate for ReadExReq accesses 2618system.l2c.ReadExReq_miss_rate::cpu1.data 0.850243 # miss rate for ReadExReq accesses 2619system.l2c.ReadExReq_miss_rate::total 0.784566 # miss rate for ReadExReq accesses 2620system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.079545 # miss rate for ReadSharedReq accesses 2621system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.035088 # miss rate for ReadSharedReq accesses 2622system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.373530 # miss rate for ReadSharedReq accesses 2623system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161049 # miss rate for ReadSharedReq accesses 2624system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.745340 # miss rate for ReadSharedReq accesses 2625system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.129836 # miss rate for ReadSharedReq accesses 2626system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.092100 # miss rate for ReadSharedReq accesses 2627system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.545731 # miss rate for ReadSharedReq accesses 2628system.l2c.ReadSharedReq_miss_rate::total 0.535597 # miss rate for ReadSharedReq accesses 2629system.l2c.demand_miss_rate::cpu0.dtb.walker 0.079545 # miss rate for demand accesses 2630system.l2c.demand_miss_rate::cpu0.itb.walker 0.035088 # miss rate for demand accesses 2631system.l2c.demand_miss_rate::cpu0.inst 0.373530 # miss rate for demand accesses 2632system.l2c.demand_miss_rate::cpu0.data 0.288244 # miss rate for demand accesses 2633system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.745340 # miss rate for demand accesses 2634system.l2c.demand_miss_rate::cpu1.inst 0.129836 # miss rate for demand accesses 2635system.l2c.demand_miss_rate::cpu1.data 0.476071 # miss rate for demand accesses 2636system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.545731 # miss rate for demand accesses 2637system.l2c.demand_miss_rate::total 0.553605 # miss rate for demand accesses 2638system.l2c.overall_miss_rate::cpu0.dtb.walker 0.079545 # miss rate for overall accesses 2639system.l2c.overall_miss_rate::cpu0.itb.walker 0.035088 # miss rate for overall accesses 2640system.l2c.overall_miss_rate::cpu0.inst 0.373530 # miss rate for overall accesses 2641system.l2c.overall_miss_rate::cpu0.data 0.288244 # miss rate for overall accesses 2642system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.745340 # miss rate for overall accesses 2643system.l2c.overall_miss_rate::cpu1.inst 0.129836 # miss rate for overall accesses 2644system.l2c.overall_miss_rate::cpu1.data 0.476071 # miss rate for overall accesses 2645system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.545731 # miss rate for overall accesses 2646system.l2c.overall_miss_rate::total 0.553605 # miss rate for overall accesses 2647system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 930.072853 # average UpgradeReq miss latency 2648system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1050.157356 # average UpgradeReq miss latency 2649system.l2c.UpgradeReq_avg_miss_latency::total 958.039395 # average UpgradeReq miss latency 2650system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2586.820084 # average SCUpgradeReq miss latency 2651system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 592.468619 # average SCUpgradeReq miss latency 2652system.l2c.SCUpgradeReq_avg_miss_latency::total 1162.283323 # average SCUpgradeReq miss latency 2653system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96073.326295 # average ReadExReq miss latency 2654system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81707.020590 # average ReadExReq miss latency 2655system.l2c.ReadExReq_avg_miss_latency::total 90112.074734 # average ReadExReq miss latency 2656system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 116571.428571 # average ReadSharedReq miss latency 2657system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency 2658system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80533.331475 # average ReadSharedReq miss latency 2659system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87000.510493 # average ReadSharedReq miss latency 2660system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344 # average ReadSharedReq miss latency 2661system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83410.086455 # average ReadSharedReq miss latency 2662system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88974.735605 # average ReadSharedReq miss latency 2663system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651 # average ReadSharedReq miss latency 2664system.l2c.ReadSharedReq_avg_miss_latency::total 94771.297303 # average ReadSharedReq miss latency 2665system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 116571.428571 # average overall miss latency 2666system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 2667system.l2c.demand_avg_miss_latency::cpu0.inst 80533.331475 # average overall miss latency 2668system.l2c.demand_avg_miss_latency::cpu0.data 92110.544049 # average overall miss latency 2669system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344 # average overall miss latency 2670system.l2c.demand_avg_miss_latency::cpu1.inst 83410.086455 # average overall miss latency 2671system.l2c.demand_avg_miss_latency::cpu1.data 82400.931224 # average overall miss latency 2672system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651 # average overall miss latency 2673system.l2c.demand_avg_miss_latency::total 94293.686121 # average overall miss latency 2674system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 116571.428571 # average overall miss latency 2675system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency 2676system.l2c.overall_avg_miss_latency::cpu0.inst 80533.331475 # average overall miss latency 2677system.l2c.overall_avg_miss_latency::cpu0.data 92110.544049 # average overall miss latency 2678system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344 # average overall miss latency 2679system.l2c.overall_avg_miss_latency::cpu1.inst 83410.086455 # average overall miss latency 2680system.l2c.overall_avg_miss_latency::cpu1.data 82400.931224 # average overall miss latency 2681system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651 # average overall miss latency 2682system.l2c.overall_avg_miss_latency::total 94293.686121 # average overall miss latency | 2545system.l2c.overall_misses::cpu0.inst 17201 # number of overall misses 2546system.l2c.overall_misses::cpu0.data 19721 # number of overall misses 2547system.l2c.overall_misses::cpu0.l2cache.prefetcher 128053 # number of overall misses 2548system.l2c.overall_misses::cpu1.inst 2469 # number of overall misses 2549system.l2c.overall_misses::cpu1.data 9144 # number of overall misses 2550system.l2c.overall_misses::cpu1.l2cache.prefetcher 10524 # number of overall misses 2551system.l2c.overall_misses::total 187120 # number of overall misses 2552system.l2c.UpgradeReq_miss_latency::cpu0.data 17802500 # number of UpgradeReq miss cycles 2553system.l2c.UpgradeReq_miss_latency::cpu1.data 17716000 # number of UpgradeReq miss cycles 2554system.l2c.UpgradeReq_miss_latency::total 35518500 # number of UpgradeReq miss cycles 2555system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2579000 # number of SCUpgradeReq miss cycles 2556system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2637000 # number of SCUpgradeReq miss cycles 2557system.l2c.SCUpgradeReq_miss_latency::total 5216000 # number of SCUpgradeReq miss cycles 2558system.l2c.ReadExReq_miss_latency::cpu0.data 1610292500 # number of ReadExReq miss cycles 2559system.l2c.ReadExReq_miss_latency::cpu1.data 1065510000 # number of ReadExReq miss cycles 2560system.l2c.ReadExReq_miss_latency::total 2675802500 # number of ReadExReq miss cycles 2561system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 810000 # number of ReadSharedReq miss cycles 2562system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles 2563system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2259930500 # number of ReadSharedReq miss cycles 2564system.l2c.ReadSharedReq_miss_latency::cpu0.data 1181087500 # number of ReadSharedReq miss cycles 2565system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 18423338040 # number of ReadSharedReq miss cycles 2566system.l2c.ReadSharedReq_miss_latency::cpu1.inst 329532000 # number of ReadSharedReq miss cycles 2567system.l2c.ReadSharedReq_miss_latency::cpu1.data 141154500 # number of ReadSharedReq miss cycles 2568system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1816453330 # number of ReadSharedReq miss cycles 2569system.l2c.ReadSharedReq_miss_latency::total 24152577870 # number of ReadSharedReq miss cycles 2570system.l2c.demand_miss_latency::cpu0.dtb.walker 810000 # number of demand (read+write) miss cycles 2571system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles 2572system.l2c.demand_miss_latency::cpu0.inst 2259930500 # number of demand (read+write) miss cycles 2573system.l2c.demand_miss_latency::cpu0.data 2791380000 # number of demand (read+write) miss cycles 2574system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18423338040 # number of demand (read+write) miss cycles 2575system.l2c.demand_miss_latency::cpu1.inst 329532000 # number of demand (read+write) miss cycles 2576system.l2c.demand_miss_latency::cpu1.data 1206664500 # number of demand (read+write) miss cycles 2577system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1816453330 # number of demand (read+write) miss cycles 2578system.l2c.demand_miss_latency::total 26828380370 # number of demand (read+write) miss cycles 2579system.l2c.overall_miss_latency::cpu0.dtb.walker 810000 # number of overall miss cycles 2580system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles 2581system.l2c.overall_miss_latency::cpu0.inst 2259930500 # number of overall miss cycles 2582system.l2c.overall_miss_latency::cpu0.data 2791380000 # number of overall miss cycles 2583system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18423338040 # number of overall miss cycles 2584system.l2c.overall_miss_latency::cpu1.inst 329532000 # number of overall miss cycles 2585system.l2c.overall_miss_latency::cpu1.data 1206664500 # number of overall miss cycles 2586system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1816453330 # number of overall miss cycles 2587system.l2c.overall_miss_latency::total 26828380370 # number of overall miss cycles 2588system.l2c.Writeback_accesses::writebacks 224862 # number of Writeback accesses(hits+misses) 2589system.l2c.Writeback_accesses::total 224862 # number of Writeback accesses(hits+misses) 2590system.l2c.UpgradeReq_accesses::cpu0.data 8447 # number of UpgradeReq accesses(hits+misses) 2591system.l2c.UpgradeReq_accesses::cpu1.data 5354 # number of UpgradeReq accesses(hits+misses) 2592system.l2c.UpgradeReq_accesses::total 13801 # number of UpgradeReq accesses(hits+misses) 2593system.l2c.SCUpgradeReq_accesses::cpu0.data 560 # number of SCUpgradeReq accesses(hits+misses) 2594system.l2c.SCUpgradeReq_accesses::cpu1.data 1445 # number of SCUpgradeReq accesses(hits+misses) 2595system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) 2596system.l2c.ReadExReq_accesses::cpu0.data 14668 # number of ReadExReq accesses(hits+misses) 2597system.l2c.ReadExReq_accesses::cpu1.data 10115 # number of ReadExReq accesses(hits+misses) 2598system.l2c.ReadExReq_accesses::total 24783 # number of ReadExReq accesses(hits+misses) 2599system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 61 # number of ReadSharedReq accesses(hits+misses) 2600system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) 2601system.l2c.ReadSharedReq_accesses::cpu0.inst 41089 # number of ReadSharedReq accesses(hits+misses) 2602system.l2c.ReadSharedReq_accesses::cpu0.data 49908 # number of ReadSharedReq accesses(hits+misses) 2603system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 169651 # number of ReadSharedReq accesses(hits+misses) 2604system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 52 # number of ReadSharedReq accesses(hits+misses) 2605system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 64 # number of ReadSharedReq accesses(hits+misses) 2606system.l2c.ReadSharedReq_accesses::cpu1.inst 19273 # number of ReadSharedReq accesses(hits+misses) 2607system.l2c.ReadSharedReq_accesses::cpu1.data 12950 # number of ReadSharedReq accesses(hits+misses) 2608system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 20010 # number of ReadSharedReq accesses(hits+misses) 2609system.l2c.ReadSharedReq_accesses::total 313093 # number of ReadSharedReq accesses(hits+misses) 2610system.l2c.demand_accesses::cpu0.dtb.walker 61 # number of demand (read+write) accesses 2611system.l2c.demand_accesses::cpu0.itb.walker 35 # number of demand (read+write) accesses 2612system.l2c.demand_accesses::cpu0.inst 41089 # number of demand (read+write) accesses 2613system.l2c.demand_accesses::cpu0.data 64576 # number of demand (read+write) accesses 2614system.l2c.demand_accesses::cpu0.l2cache.prefetcher 169651 # number of demand (read+write) accesses 2615system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses 2616system.l2c.demand_accesses::cpu1.itb.walker 64 # number of demand (read+write) accesses 2617system.l2c.demand_accesses::cpu1.inst 19273 # number of demand (read+write) accesses 2618system.l2c.demand_accesses::cpu1.data 23065 # number of demand (read+write) accesses 2619system.l2c.demand_accesses::cpu1.l2cache.prefetcher 20010 # number of demand (read+write) accesses 2620system.l2c.demand_accesses::total 337876 # number of demand (read+write) accesses 2621system.l2c.overall_accesses::cpu0.dtb.walker 61 # number of overall (read+write) accesses 2622system.l2c.overall_accesses::cpu0.itb.walker 35 # number of overall (read+write) accesses 2623system.l2c.overall_accesses::cpu0.inst 41089 # number of overall (read+write) accesses 2624system.l2c.overall_accesses::cpu0.data 64576 # number of overall (read+write) accesses 2625system.l2c.overall_accesses::cpu0.l2cache.prefetcher 169651 # number of overall (read+write) accesses 2626system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses 2627system.l2c.overall_accesses::cpu1.itb.walker 64 # number of overall (read+write) accesses 2628system.l2c.overall_accesses::cpu1.inst 19273 # number of overall (read+write) accesses 2629system.l2c.overall_accesses::cpu1.data 23065 # number of overall (read+write) accesses 2630system.l2c.overall_accesses::cpu1.l2cache.prefetcher 20010 # number of overall (read+write) accesses 2631system.l2c.overall_accesses::total 337876 # number of overall (read+write) accesses 2632system.l2c.UpgradeReq_miss_rate::cpu0.data 0.821593 # miss rate for UpgradeReq accesses 2633system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788756 # miss rate for UpgradeReq accesses 2634system.l2c.UpgradeReq_miss_rate::total 0.808854 # miss rate for UpgradeReq accesses 2635system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.758929 # miss rate for SCUpgradeReq accesses 2636system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.877509 # miss rate for SCUpgradeReq accesses 2637system.l2c.SCUpgradeReq_miss_rate::total 0.844389 # miss rate for SCUpgradeReq accesses 2638system.l2c.ReadExReq_miss_rate::cpu0.data 0.754840 # miss rate for ReadExReq accesses 2639system.l2c.ReadExReq_miss_rate::cpu1.data 0.803361 # miss rate for ReadExReq accesses 2640system.l2c.ReadExReq_miss_rate::total 0.774644 # miss rate for ReadExReq accesses 2641system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.098361 # miss rate for ReadSharedReq accesses 2642system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.057143 # miss rate for ReadSharedReq accesses 2643system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.418628 # miss rate for ReadSharedReq accesses 2644system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.173299 # miss rate for ReadSharedReq accesses 2645system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.754803 # miss rate for ReadSharedReq accesses 2646system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.128107 # miss rate for ReadSharedReq accesses 2647system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078610 # miss rate for ReadSharedReq accesses 2648system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.525937 # miss rate for ReadSharedReq accesses 2649system.l2c.ReadSharedReq_miss_rate::total 0.536333 # miss rate for ReadSharedReq accesses 2650system.l2c.demand_miss_rate::cpu0.dtb.walker 0.098361 # miss rate for demand accesses 2651system.l2c.demand_miss_rate::cpu0.itb.walker 0.057143 # miss rate for demand accesses 2652system.l2c.demand_miss_rate::cpu0.inst 0.418628 # miss rate for demand accesses 2653system.l2c.demand_miss_rate::cpu0.data 0.305392 # miss rate for demand accesses 2654system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.754803 # miss rate for demand accesses 2655system.l2c.demand_miss_rate::cpu1.inst 0.128107 # miss rate for demand accesses 2656system.l2c.demand_miss_rate::cpu1.data 0.396445 # miss rate for demand accesses 2657system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.525937 # miss rate for demand accesses 2658system.l2c.demand_miss_rate::total 0.553813 # miss rate for demand accesses 2659system.l2c.overall_miss_rate::cpu0.dtb.walker 0.098361 # miss rate for overall accesses 2660system.l2c.overall_miss_rate::cpu0.itb.walker 0.057143 # miss rate for overall accesses 2661system.l2c.overall_miss_rate::cpu0.inst 0.418628 # miss rate for overall accesses 2662system.l2c.overall_miss_rate::cpu0.data 0.305392 # miss rate for overall accesses 2663system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.754803 # miss rate for overall accesses 2664system.l2c.overall_miss_rate::cpu1.inst 0.128107 # miss rate for overall accesses 2665system.l2c.overall_miss_rate::cpu1.data 0.396445 # miss rate for overall accesses 2666system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.525937 # miss rate for overall accesses 2667system.l2c.overall_miss_rate::total 0.553813 # miss rate for overall accesses 2668system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2565.201729 # average UpgradeReq miss latency 2669system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4195.121951 # average UpgradeReq miss latency 2670system.l2c.UpgradeReq_avg_miss_latency::total 3181.805966 # average UpgradeReq miss latency 2671system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6068.235294 # average SCUpgradeReq miss latency 2672system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2079.652997 # average SCUpgradeReq miss latency 2673system.l2c.SCUpgradeReq_avg_miss_latency::total 3080.921441 # average SCUpgradeReq miss latency 2674system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145438.267702 # average ReadExReq miss latency 2675system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131123.554024 # average ReadExReq miss latency 2676system.l2c.ReadExReq_avg_miss_latency::total 139379.232212 # average ReadExReq miss latency 2677system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135000 # average ReadSharedReq miss latency 2678system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency 2679system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131383.669554 # average ReadSharedReq miss latency 2680system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136557.694531 # average ReadSharedReq miss latency 2681system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124 # average ReadSharedReq miss latency 2682system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133467.800729 # average ReadSharedReq miss latency 2683system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138658.644401 # average ReadSharedReq miss latency 2684system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578 # average ReadSharedReq miss latency 2685system.l2c.ReadSharedReq_avg_miss_latency::total 143832.123665 # average ReadSharedReq miss latency 2686system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135000 # average overall miss latency 2687system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2688system.l2c.demand_avg_miss_latency::cpu0.inst 131383.669554 # average overall miss latency 2689system.l2c.demand_avg_miss_latency::cpu0.data 141543.532275 # average overall miss latency 2690system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124 # average overall miss latency 2691system.l2c.demand_avg_miss_latency::cpu1.inst 133467.800729 # average overall miss latency 2692system.l2c.demand_avg_miss_latency::cpu1.data 131962.434383 # average overall miss latency 2693system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578 # average overall miss latency 2694system.l2c.demand_avg_miss_latency::total 143375.269186 # average overall miss latency 2695system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135000 # average overall miss latency 2696system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2697system.l2c.overall_avg_miss_latency::cpu0.inst 131383.669554 # average overall miss latency 2698system.l2c.overall_avg_miss_latency::cpu0.data 141543.532275 # average overall miss latency 2699system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124 # average overall miss latency 2700system.l2c.overall_avg_miss_latency::cpu1.inst 133467.800729 # average overall miss latency 2701system.l2c.overall_avg_miss_latency::cpu1.data 131962.434383 # average overall miss latency 2702system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578 # average overall miss latency 2703system.l2c.overall_avg_miss_latency::total 143375.269186 # average overall miss latency |
| 2683system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2684system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2685system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2686system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2687system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2688system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2689system.l2c.fast_writes 0 # number of fast writes performed 2690system.l2c.cache_copies 0 # number of cache copies performed | 2704system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2705system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2706system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2707system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2708system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2709system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2710system.l2c.fast_writes 0 # number of fast writes performed 2711system.l2c.cache_copies 0 # number of cache copies performed |
| 2691system.l2c.writebacks::writebacks 99996 # number of writebacks 2692system.l2c.writebacks::total 99996 # number of writebacks 2693system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits 2694system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits 2695system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits 2696system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 2697system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 2698system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits 2699system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 2700system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 2701system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits 2702system.l2c.CleanEvict_mshr_misses::writebacks 2923 # number of CleanEvict MSHR misses 2703system.l2c.CleanEvict_mshr_misses::total 2923 # number of CleanEvict MSHR misses 2704system.l2c.UpgradeReq_mshr_misses::cpu0.data 8373 # number of UpgradeReq MSHR misses 2705system.l2c.UpgradeReq_mshr_misses::cpu1.data 2542 # number of UpgradeReq MSHR misses 2706system.l2c.UpgradeReq_mshr_misses::total 10915 # number of UpgradeReq MSHR misses 2707system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 478 # number of SCUpgradeReq MSHR misses 2708system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1195 # number of SCUpgradeReq MSHR misses 2709system.l2c.SCUpgradeReq_mshr_misses::total 1673 # number of SCUpgradeReq MSHR misses 2710system.l2c.ReadExReq_mshr_misses::cpu0.data 11367 # number of ReadExReq MSHR misses 2711system.l2c.ReadExReq_mshr_misses::cpu1.data 8062 # number of ReadExReq MSHR misses 2712system.l2c.ReadExReq_mshr_misses::total 19429 # number of ReadExReq MSHR misses 2713system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses | 2712system.l2c.writebacks::writebacks 98758 # number of writebacks 2713system.l2c.writebacks::total 98758 # number of writebacks 2714system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits 2715system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 13 # number of ReadSharedReq MSHR hits 2716system.l2c.ReadSharedReq_mshr_hits::total 18 # number of ReadSharedReq MSHR hits 2717system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 2718system.l2c.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits 2719system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits 2720system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 2721system.l2c.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits 2722system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits 2723system.l2c.CleanEvict_mshr_misses::writebacks 3008 # number of CleanEvict MSHR misses 2724system.l2c.CleanEvict_mshr_misses::total 3008 # number of CleanEvict MSHR misses 2725system.l2c.UpgradeReq_mshr_misses::cpu0.data 6940 # number of UpgradeReq MSHR misses 2726system.l2c.UpgradeReq_mshr_misses::cpu1.data 4223 # number of UpgradeReq MSHR misses 2727system.l2c.UpgradeReq_mshr_misses::total 11163 # number of UpgradeReq MSHR misses 2728system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 425 # number of SCUpgradeReq MSHR misses 2729system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1268 # number of SCUpgradeReq MSHR misses 2730system.l2c.SCUpgradeReq_mshr_misses::total 1693 # number of SCUpgradeReq MSHR misses 2731system.l2c.ReadExReq_mshr_misses::cpu0.data 11072 # number of ReadExReq MSHR misses 2732system.l2c.ReadExReq_mshr_misses::cpu1.data 8126 # number of ReadExReq MSHR misses 2733system.l2c.ReadExReq_mshr_misses::total 19198 # number of ReadExReq MSHR misses 2734system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses |
| 2714system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses | 2735system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses |
| 2715system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17939 # number of ReadSharedReq MSHR misses 2716system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8815 # number of ReadSharedReq MSHR misses 2717system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134305 # number of ReadSharedReq MSHR misses 2718system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 1725 # number of ReadSharedReq MSHR misses 2719system.l2c.ReadSharedReq_mshr_misses::cpu1.data 851 # number of ReadSharedReq MSHR misses 2720system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6450 # number of ReadSharedReq MSHR misses 2721system.l2c.ReadSharedReq_mshr_misses::total 170094 # number of ReadSharedReq MSHR misses 2722system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses | 2736system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17196 # number of ReadSharedReq MSHR misses 2737system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8649 # number of ReadSharedReq MSHR misses 2738system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 128053 # number of ReadSharedReq MSHR misses 2739system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2456 # number of ReadSharedReq MSHR misses 2740system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1018 # number of ReadSharedReq MSHR misses 2741system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 10524 # number of ReadSharedReq MSHR misses 2742system.l2c.ReadSharedReq_mshr_misses::total 167904 # number of ReadSharedReq MSHR misses 2743system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses |
| 2723system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses | 2744system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses |
| 2724system.l2c.demand_mshr_misses::cpu0.inst 17939 # number of demand (read+write) MSHR misses 2725system.l2c.demand_mshr_misses::cpu0.data 20182 # number of demand (read+write) MSHR misses 2726system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134305 # number of demand (read+write) MSHR misses 2727system.l2c.demand_mshr_misses::cpu1.inst 1725 # number of demand (read+write) MSHR misses 2728system.l2c.demand_mshr_misses::cpu1.data 8913 # number of demand (read+write) MSHR misses 2729system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6450 # number of demand (read+write) MSHR misses 2730system.l2c.demand_mshr_misses::total 189523 # number of demand (read+write) MSHR misses 2731system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses | 2745system.l2c.demand_mshr_misses::cpu0.inst 17196 # number of demand (read+write) MSHR misses 2746system.l2c.demand_mshr_misses::cpu0.data 19721 # number of demand (read+write) MSHR misses 2747system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128053 # number of demand (read+write) MSHR misses 2748system.l2c.demand_mshr_misses::cpu1.inst 2456 # number of demand (read+write) MSHR misses 2749system.l2c.demand_mshr_misses::cpu1.data 9144 # number of demand (read+write) MSHR misses 2750system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10524 # number of demand (read+write) MSHR misses 2751system.l2c.demand_mshr_misses::total 187102 # number of demand (read+write) MSHR misses 2752system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses |
| 2732system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses | 2753system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses |
| 2733system.l2c.overall_mshr_misses::cpu0.inst 17939 # number of overall MSHR misses 2734system.l2c.overall_mshr_misses::cpu0.data 20182 # number of overall MSHR misses 2735system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134305 # number of overall MSHR misses 2736system.l2c.overall_mshr_misses::cpu1.inst 1725 # number of overall MSHR misses 2737system.l2c.overall_mshr_misses::cpu1.data 8913 # number of overall MSHR misses 2738system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6450 # number of overall MSHR misses 2739system.l2c.overall_mshr_misses::total 189523 # number of overall MSHR misses | 2754system.l2c.overall_mshr_misses::cpu0.inst 17196 # number of overall MSHR misses 2755system.l2c.overall_mshr_misses::cpu0.data 19721 # number of overall MSHR misses 2756system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128053 # number of overall MSHR misses 2757system.l2c.overall_mshr_misses::cpu1.inst 2456 # number of overall MSHR misses 2758system.l2c.overall_mshr_misses::cpu1.data 9144 # number of overall MSHR misses 2759system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10524 # number of overall MSHR misses 2760system.l2c.overall_mshr_misses::total 187102 # number of overall MSHR misses |
| 2740system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable | 2761system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable |
| 2741system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable | 2762system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable |
| 2742system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable | 2763system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable |
| 2743system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2504 # number of ReadReq MSHR uncacheable 2744system.l2c.ReadReq_mshr_uncacheable::total 44038 # number of ReadReq MSHR uncacheable 2745system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28719 # number of WriteReq MSHR uncacheable 2746system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable 2747system.l2c.WriteReq_mshr_uncacheable::total 30874 # number of WriteReq MSHR uncacheable | 2764system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3139 # number of ReadReq MSHR uncacheable 2765system.l2c.ReadReq_mshr_uncacheable::total 44076 # number of ReadReq MSHR uncacheable 2766system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable 2767system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable 2768system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable |
| 2748system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses | 2769system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses |
| 2749system.l2c.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses | 2770system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses |
| 2750system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses | 2771system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses |
| 2751system.l2c.overall_mshr_uncacheable_misses::cpu1.data 4659 # number of overall MSHR uncacheable misses 2752system.l2c.overall_mshr_uncacheable_misses::total 74912 # number of overall MSHR uncacheable misses 2753system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 174263500 # number of UpgradeReq MSHR miss cycles 2754system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52800500 # number of UpgradeReq MSHR miss cycles 2755system.l2c.UpgradeReq_mshr_miss_latency::total 227064000 # number of UpgradeReq MSHR miss cycles 2756system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10023500 # number of SCUpgradeReq MSHR miss cycles 2757system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 24840000 # number of SCUpgradeReq MSHR miss cycles 2758system.l2c.SCUpgradeReq_mshr_miss_latency::total 34863500 # number of SCUpgradeReq MSHR miss cycles 2759system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 978395500 # number of ReadExReq MSHR miss cycles 2760system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 578102000 # number of ReadExReq MSHR miss cycles 2761system.l2c.ReadExReq_mshr_miss_latency::total 1556497500 # number of ReadExReq MSHR miss cycles 2762system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 746000 # number of ReadSharedReq MSHR miss cycles 2763system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 146000 # number of ReadSharedReq MSHR miss cycles 2764system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1265389000 # number of ReadSharedReq MSHR miss cycles 2765system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 678759500 # number of ReadSharedReq MSHR miss cycles 2766system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11601176902 # number of ReadSharedReq MSHR miss cycles 2767system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 126976000 # number of ReadSharedReq MSHR miss cycles 2768system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 67207500 # number of ReadSharedReq MSHR miss cycles 2769system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 679265397 # number of ReadSharedReq MSHR miss cycles 2770system.l2c.ReadSharedReq_mshr_miss_latency::total 14419666299 # number of ReadSharedReq MSHR miss cycles 2771system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 746000 # number of demand (read+write) MSHR miss cycles 2772system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 146000 # number of demand (read+write) MSHR miss cycles 2773system.l2c.demand_mshr_miss_latency::cpu0.inst 1265389000 # number of demand (read+write) MSHR miss cycles 2774system.l2c.demand_mshr_miss_latency::cpu0.data 1657155000 # number of demand (read+write) MSHR miss cycles 2775system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11601176902 # number of demand (read+write) MSHR miss cycles 2776system.l2c.demand_mshr_miss_latency::cpu1.inst 126976000 # number of demand (read+write) MSHR miss cycles 2777system.l2c.demand_mshr_miss_latency::cpu1.data 645309500 # number of demand (read+write) MSHR miss cycles 2778system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 679265397 # number of demand (read+write) MSHR miss cycles 2779system.l2c.demand_mshr_miss_latency::total 15976163799 # number of demand (read+write) MSHR miss cycles 2780system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 746000 # number of overall MSHR miss cycles 2781system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 146000 # number of overall MSHR miss cycles 2782system.l2c.overall_mshr_miss_latency::cpu0.inst 1265389000 # number of overall MSHR miss cycles 2783system.l2c.overall_mshr_miss_latency::cpu0.data 1657155000 # number of overall MSHR miss cycles 2784system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11601176902 # number of overall MSHR miss cycles 2785system.l2c.overall_mshr_miss_latency::cpu1.inst 126976000 # number of overall MSHR miss cycles 2786system.l2c.overall_mshr_miss_latency::cpu1.data 645309500 # number of overall MSHR miss cycles 2787system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 679265397 # number of overall MSHR miss cycles 2788system.l2c.overall_mshr_miss_latency::total 15976163799 # number of overall MSHR miss cycles 2789system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 570734000 # number of ReadReq MSHR uncacheable cycles 2790system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5521577000 # number of ReadReq MSHR uncacheable cycles 2791system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10711500 # number of ReadReq MSHR uncacheable cycles 2792system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 237033000 # number of ReadReq MSHR uncacheable cycles 2793system.l2c.ReadReq_mshr_uncacheable_latency::total 6340055500 # number of ReadReq MSHR uncacheable cycles 2794system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4233141500 # number of WriteReq MSHR uncacheable cycles 2795system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 171755500 # number of WriteReq MSHR uncacheable cycles 2796system.l2c.WriteReq_mshr_uncacheable_latency::total 4404897000 # number of WriteReq MSHR uncacheable cycles 2797system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 570734000 # number of overall MSHR uncacheable cycles 2798system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9754718500 # number of overall MSHR uncacheable cycles 2799system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10711500 # number of overall MSHR uncacheable cycles 2800system.l2c.overall_mshr_uncacheable_latency::cpu1.data 408788500 # number of overall MSHR uncacheable cycles 2801system.l2c.overall_mshr_uncacheable_latency::total 10744952500 # number of overall MSHR uncacheable cycles | 2772system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5659 # number of overall MSHR uncacheable misses 2773system.l2c.overall_mshr_uncacheable_misses::total 74989 # number of overall MSHR uncacheable misses 2774system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 527536000 # number of UpgradeReq MSHR miss cycles 2775system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 312350000 # number of UpgradeReq MSHR miss cycles 2776system.l2c.UpgradeReq_mshr_miss_latency::total 839886000 # number of UpgradeReq MSHR miss cycles 2777system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 32879500 # number of SCUpgradeReq MSHR miss cycles 2778system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97434000 # number of SCUpgradeReq MSHR miss cycles 2779system.l2c.SCUpgradeReq_mshr_miss_latency::total 130313500 # number of SCUpgradeReq MSHR miss cycles 2780system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1499572500 # number of ReadExReq MSHR miss cycles 2781system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 984250000 # number of ReadExReq MSHR miss cycles 2782system.l2c.ReadExReq_mshr_miss_latency::total 2483822500 # number of ReadExReq MSHR miss cycles 2783system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 750000 # number of ReadSharedReq MSHR miss cycles 2784system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles 2785system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2087455500 # number of ReadSharedReq MSHR miss cycles 2786system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1094597500 # number of ReadSharedReq MSHR miss cycles 2787system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17142808040 # number of ReadSharedReq MSHR miss cycles 2788system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 303361000 # number of ReadSharedReq MSHR miss cycles 2789system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 130974500 # number of ReadSharedReq MSHR miss cycles 2790system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1711213330 # number of ReadSharedReq MSHR miss cycles 2791system.l2c.ReadSharedReq_mshr_miss_latency::total 22471411870 # number of ReadSharedReq MSHR miss cycles 2792system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 750000 # number of demand (read+write) MSHR miss cycles 2793system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles 2794system.l2c.demand_mshr_miss_latency::cpu0.inst 2087455500 # number of demand (read+write) MSHR miss cycles 2795system.l2c.demand_mshr_miss_latency::cpu0.data 2594170000 # number of demand (read+write) MSHR miss cycles 2796system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 17142808040 # number of demand (read+write) MSHR miss cycles 2797system.l2c.demand_mshr_miss_latency::cpu1.inst 303361000 # number of demand (read+write) MSHR miss cycles 2798system.l2c.demand_mshr_miss_latency::cpu1.data 1115224500 # number of demand (read+write) MSHR miss cycles 2799system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1711213330 # number of demand (read+write) MSHR miss cycles 2800system.l2c.demand_mshr_miss_latency::total 24955234370 # number of demand (read+write) MSHR miss cycles 2801system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 750000 # number of overall MSHR miss cycles 2802system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles 2803system.l2c.overall_mshr_miss_latency::cpu0.inst 2087455500 # number of overall MSHR miss cycles 2804system.l2c.overall_mshr_miss_latency::cpu0.data 2594170000 # number of overall MSHR miss cycles 2805system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17142808040 # number of overall MSHR miss cycles 2806system.l2c.overall_mshr_miss_latency::cpu1.inst 303361000 # number of overall MSHR miss cycles 2807system.l2c.overall_mshr_miss_latency::cpu1.data 1115224500 # number of overall MSHR miss cycles 2808system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1711213330 # number of overall MSHR miss cycles 2809system.l2c.overall_mshr_miss_latency::total 24955234370 # number of overall MSHR miss cycles 2810system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles 2811system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5449526500 # number of ReadReq MSHR uncacheable cycles 2812system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19461500 # number of ReadReq MSHR uncacheable cycles 2813system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 338634500 # number of ReadReq MSHR uncacheable cycles 2814system.l2c.ReadReq_mshr_uncacheable_latency::total 6831437500 # number of ReadReq MSHR uncacheable cycles 2815system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4390566000 # number of WriteReq MSHR uncacheable cycles 2816system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 234560000 # number of WriteReq MSHR uncacheable cycles 2817system.l2c.WriteReq_mshr_uncacheable_latency::total 4625126000 # number of WriteReq MSHR uncacheable cycles 2818system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles 2819system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9840092500 # number of overall MSHR uncacheable cycles 2820system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19461500 # number of overall MSHR uncacheable cycles 2821system.l2c.overall_mshr_uncacheable_latency::cpu1.data 573194500 # number of overall MSHR uncacheable cycles 2822system.l2c.overall_mshr_uncacheable_latency::total 11456563500 # number of overall MSHR uncacheable cycles |
| 2802system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2803system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 2823system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2824system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 2804system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805561 # mshr miss rate for UpgradeReq accesses 2805system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.786267 # mshr miss rate for UpgradeReq accesses 2806system.l2c.UpgradeReq_mshr_miss_rate::total 0.800983 # mshr miss rate for UpgradeReq accesses 2807system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772213 # mshr miss rate for SCUpgradeReq accesses 2808system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881919 # mshr miss rate for SCUpgradeReq accesses 2809system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.847518 # mshr miss rate for SCUpgradeReq accesses 2810system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743816 # mshr miss rate for ReadExReq accesses 2811system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850243 # mshr miss rate for ReadExReq accesses 2812system.l2c.ReadExReq_mshr_miss_rate::total 0.784566 # mshr miss rate for ReadExReq accesses 2813system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.079545 # mshr miss rate for ReadSharedReq accesses 2814system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.035088 # mshr miss rate for ReadSharedReq accesses 2815system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373488 # mshr miss rate for ReadSharedReq accesses 2816system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161049 # mshr miss rate for ReadSharedReq accesses 2817system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745340 # mshr miss rate for ReadSharedReq accesses 2818system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.129088 # mshr miss rate for ReadSharedReq accesses 2819system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.092100 # mshr miss rate for ReadSharedReq accesses 2820system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for ReadSharedReq accesses 2821system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535559 # mshr miss rate for ReadSharedReq accesses 2822system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.079545 # mshr miss rate for demand accesses 2823system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.035088 # mshr miss rate for demand accesses 2824system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373488 # mshr miss rate for demand accesses 2825system.l2c.demand_mshr_miss_rate::cpu0.data 0.288244 # mshr miss rate for demand accesses 2826system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745340 # mshr miss rate for demand accesses 2827system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129088 # mshr miss rate for demand accesses 2828system.l2c.demand_mshr_miss_rate::cpu1.data 0.476071 # mshr miss rate for demand accesses 2829system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for demand accesses 2830system.l2c.demand_mshr_miss_rate::total 0.553570 # mshr miss rate for demand accesses 2831system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.079545 # mshr miss rate for overall accesses 2832system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.035088 # mshr miss rate for overall accesses 2833system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373488 # mshr miss rate for overall accesses 2834system.l2c.overall_mshr_miss_rate::cpu0.data 0.288244 # mshr miss rate for overall accesses 2835system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745340 # mshr miss rate for overall accesses 2836system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129088 # mshr miss rate for overall accesses 2837system.l2c.overall_mshr_miss_rate::cpu1.data 0.476071 # mshr miss rate for overall accesses 2838system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for overall accesses 2839system.l2c.overall_mshr_miss_rate::total 0.553570 # mshr miss rate for overall accesses 2840system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.552251 # average UpgradeReq mshr miss latency 2841system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20771.243116 # average UpgradeReq mshr miss latency 2842system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.931745 # average UpgradeReq mshr miss latency 2843system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20969.665272 # average SCUpgradeReq mshr miss latency 2844system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.610879 # average SCUpgradeReq mshr miss latency 2845system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20838.912134 # average SCUpgradeReq mshr miss latency 2846system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86073.326295 # average ReadExReq mshr miss latency 2847system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71707.020590 # average ReadExReq mshr miss latency 2848system.l2c.ReadExReq_avg_mshr_miss_latency::total 80112.074734 # average ReadExReq mshr miss latency 2849system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average ReadSharedReq mshr miss latency 2850system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency 2851system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average ReadSharedReq mshr miss latency 2852system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77000.510493 # average ReadSharedReq mshr miss latency 2853system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average ReadSharedReq mshr miss latency 2854system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average ReadSharedReq mshr miss latency 2855system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78974.735605 # average ReadSharedReq mshr miss latency 2856system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average ReadSharedReq mshr miss latency 2857system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84774.691047 # average ReadSharedReq mshr miss latency 2858system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency 2859system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 2860system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency 2861system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency 2862system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency 2863system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency 2864system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency 2865system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency 2866system.l2c.demand_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency 2867system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency 2868system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency 2869system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency 2870system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency 2871system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency 2872system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency 2873system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency 2874system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency 2875system.l2c.overall_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency 2876system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency 2877system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535 # average ReadReq mshr uncacheable latency 2878system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average ReadReq mshr uncacheable latency 2879system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214 # average ReadReq mshr uncacheable latency 2880system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597 # average ReadReq mshr uncacheable latency 2881system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532 # average WriteReq mshr uncacheable latency 2882system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074 # average WriteReq mshr uncacheable latency 2883system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744 # average WriteReq mshr uncacheable latency 2884system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency 2885system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542 # average overall mshr uncacheable latency 2886system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average overall mshr uncacheable latency 2887system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765 # average overall mshr uncacheable latency 2888system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613 # average overall mshr uncacheable latency | 2825system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.821593 # mshr miss rate for UpgradeReq accesses 2826system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788756 # mshr miss rate for UpgradeReq accesses 2827system.l2c.UpgradeReq_mshr_miss_rate::total 0.808854 # mshr miss rate for UpgradeReq accesses 2828system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758929 # mshr miss rate for SCUpgradeReq accesses 2829system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.877509 # mshr miss rate for SCUpgradeReq accesses 2830system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.844389 # mshr miss rate for SCUpgradeReq accesses 2831system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.754840 # mshr miss rate for ReadExReq accesses 2832system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.803361 # mshr miss rate for ReadExReq accesses 2833system.l2c.ReadExReq_mshr_miss_rate::total 0.774644 # mshr miss rate for ReadExReq accesses 2834system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for ReadSharedReq accesses 2835system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for ReadSharedReq accesses 2836system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for ReadSharedReq accesses 2837system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173299 # mshr miss rate for ReadSharedReq accesses 2838system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for ReadSharedReq accesses 2839system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for ReadSharedReq accesses 2840system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078610 # mshr miss rate for ReadSharedReq accesses 2841system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for ReadSharedReq accesses 2842system.l2c.ReadSharedReq_mshr_miss_rate::total 0.536275 # mshr miss rate for ReadSharedReq accesses 2843system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for demand accesses 2844system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for demand accesses 2845system.l2c.demand_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for demand accesses 2846system.l2c.demand_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for demand accesses 2847system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for demand accesses 2848system.l2c.demand_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for demand accesses 2849system.l2c.demand_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for demand accesses 2850system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for demand accesses 2851system.l2c.demand_mshr_miss_rate::total 0.553759 # mshr miss rate for demand accesses 2852system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses 2853system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses 2854system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses 2855system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses 2856system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses 2857system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses 2858system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses 2859system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses 2860system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses 2861system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency 2862system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency 2863system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency 2864system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency 2865system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency 2866system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency 2867system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency 2868system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency 2869system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency 2870system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency 2871system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency 2872system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency 2873system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency 2874system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency 2875system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency 2876system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency 2877system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency 2878system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency 2879system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency 2880system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2881system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency 2882system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency 2883system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency 2884system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency 2885system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency 2886system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency 2887system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency 2888system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency 2889system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2890system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency 2891system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency 2892system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency 2893system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency 2894system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency 2895system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency 2896system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency 2897system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency 2898system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency 2899system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency 2900system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency 2901system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency 2902system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency 2903system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency 2904system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency 2905system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency 2906system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency 2907system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency 2908system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency 2909system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency |
| 2889system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2910system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2890system.membus.trans_dist::ReadReq 44038 # Transaction distribution 2891system.membus.trans_dist::ReadResp 214387 # Transaction distribution 2892system.membus.trans_dist::WriteReq 30874 # Transaction distribution 2893system.membus.trans_dist::WriteResp 30874 # Transaction distribution 2894system.membus.trans_dist::Writeback 136186 # Transaction distribution 2895system.membus.trans_dist::CleanEvict 15507 # Transaction distribution 2896system.membus.trans_dist::UpgradeReq 74602 # Transaction distribution 2897system.membus.trans_dist::SCUpgradeReq 39992 # Transaction distribution 2898system.membus.trans_dist::UpgradeResp 12685 # Transaction distribution 2899system.membus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution 2900system.membus.trans_dist::ReadExReq 39841 # Transaction distribution 2901system.membus.trans_dist::ReadExResp 19332 # Transaction distribution 2902system.membus.trans_dist::ReadSharedReq 170349 # Transaction distribution | 2911system.membus.trans_dist::ReadReq 44076 # Transaction distribution 2912system.membus.trans_dist::ReadResp 212234 # Transaction distribution 2913system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2914system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2915system.membus.trans_dist::Writeback 134964 # Transaction distribution 2916system.membus.trans_dist::CleanEvict 15319 # Transaction distribution 2917system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution 2918system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution 2919system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution 2920system.membus.trans_dist::ReadExReq 39815 # Transaction distribution 2921system.membus.trans_dist::ReadExResp 19093 # Transaction distribution 2922system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution |
| 2903system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2904system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution | 2923system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2924system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution |
| 2905system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) | 2925system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) |
| 2906system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 2926system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 2907system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) 2908system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 670072 # Packet count per connected master and slave (bytes) 2909system.membus.pkt_count_system.l2c.mem_side::total 791596 # Packet count per connected master and slave (bytes) 2910system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) 2911system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) 2912system.membus.pkt_count::total 900517 # Packet count per connected master and slave (bytes) 2913system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) | 2927system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) 2928system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) 2929system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) 2930system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) 2931system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) 2932system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) 2933system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) |
| 2914system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) | 2934system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) |
| 2915system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) 2916system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18557448 # Cumulative packet size per connected master and slave (bytes) 2917system.membus.pkt_size_system.l2c.mem_side::total 18747458 # Cumulative packet size per connected master and slave (bytes) 2918system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2919system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2920system.membus.pkt_size::total 21064578 # Cumulative packet size per connected master and slave (bytes) 2921system.membus.snoops 123030 # Total snoops (count) 2922system.membus.snoop_fanout::samples 587901 # Request fanout histogram | 2935system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) 2936system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) 2937system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) 2938system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) 2939system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) 2940system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) 2941system.membus.snoops 123434 # Total snoops (count) 2942system.membus.snoop_fanout::samples 584834 # Request fanout histogram |
| 2923system.membus.snoop_fanout::mean 1 # Request fanout histogram 2924system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2925system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2926system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2943system.membus.snoop_fanout::mean 1 # Request fanout histogram 2944system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2945system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2946system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2927system.membus.snoop_fanout::1 587901 100.00% 100.00% # Request fanout histogram | 2947system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram |
| 2928system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2929system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2930system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2931system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2948system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2949system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2950system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2951system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2932system.membus.snoop_fanout::total 587901 # Request fanout histogram 2933system.membus.reqLayer0.occupancy 88280499 # Layer occupancy (ticks) | 2952system.membus.snoop_fanout::total 584834 # Request fanout histogram 2953system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) |
| 2934system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2935system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2936system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2954system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2955system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2956system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2937system.membus.reqLayer2.occupancy 11327500 # Layer occupancy (ticks) | 2957system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) |
| 2938system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2958system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2939system.membus.reqLayer5.occupancy 983138119 # Layer occupancy (ticks) | 2959system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) |
| 2940system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 2960system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 2941system.membus.respLayer2.occupancy 1138149025 # Layer occupancy (ticks) | 2961system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) |
| 2942system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 2962system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2943system.membus.respLayer3.occupancy 64374606 # Layer occupancy (ticks) | 2963system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) |
| 2944system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2945system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2946system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2947system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2948system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2949system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2950system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2951system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2968system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2969system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2970system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2971system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2972system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2973system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2974system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2975system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2964system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2965system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2966system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2967system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2968system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2969system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2970system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2971system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2988system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2989system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2990system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2991system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2992system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2993system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2994system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2995system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2996system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks |
|
| 2976system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 2977system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 2978system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 2979system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 2980system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 2981system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks | 2997system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 2998system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 2999system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3000system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3001system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3002system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks |
| 2982system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks | |
| 2983system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 2984system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 2985system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks | 3003system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3004system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3005system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks |
| 2986system.toL2Bus.trans_dist::ReadReq 44042 # Transaction distribution 2987system.toL2Bus.trans_dist::ReadResp 480570 # Transaction distribution 2988system.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution 2989system.toL2Bus.trans_dist::WriteResp 30874 # Transaction distribution 2990system.toL2Bus.trans_dist::Writeback 362932 # Transaction distribution 2991system.toL2Bus.trans_dist::CleanEvict 82945 # Transaction distribution 2992system.toL2Bus.trans_dist::UpgradeReq 77217 # Transaction distribution 2993system.toL2Bus.trans_dist::SCUpgradeReq 40293 # Transaction distribution 2994system.toL2Bus.trans_dist::UpgradeResp 117510 # Transaction distribution 2995system.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution 2996system.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution 2997system.toL2Bus.trans_dist::ReadExReq 50721 # Transaction distribution 2998system.toL2Bus.trans_dist::ReadExResp 50721 # Transaction distribution 2999system.toL2Bus.trans_dist::ReadSharedReq 436543 # Transaction distribution | 3006system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. 3007system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3008system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3009system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. 3010system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3011system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3012system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution 3013system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution 3014system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 3015system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 3016system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution 3017system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution 3018system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution 3019system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution 3020system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution 3021system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution 3022system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution 3023system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution 3024system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution 3025system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution |
| 3000system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution | 3026system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution |
| 3001system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1115711 # Packet count per connected master and slave (bytes) 3002system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 276298 # Packet count per connected master and slave (bytes) 3003system.toL2Bus.pkt_count::total 1392009 # Packet count per connected master and slave (bytes) 3004system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31905816 # Cumulative packet size per connected master and slave (bytes) 3005system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4776938 # Cumulative packet size per connected master and slave (bytes) 3006system.toL2Bus.pkt_size::total 36682754 # Cumulative packet size per connected master and slave (bytes) 3007system.toL2Bus.snoops 449881 # Total snoops (count) 3008system.toL2Bus.snoop_fanout::samples 1195846 # Request fanout histogram 3009system.toL2Bus.snoop_fanout::mean 1.169748 # Request fanout histogram 3010system.toL2Bus.snoop_fanout::stdev 0.375411 # Request fanout histogram | 3027system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) 3028system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) 3029system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) 3030system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) 3031system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) 3032system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) 3033system.toL2Bus.snoops 449108 # Total snoops (count) 3034system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram 3035system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram 3036system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram |
| 3011system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3037system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3012system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3013system.toL2Bus.snoop_fanout::1 992854 83.03% 83.03% # Request fanout histogram 3014system.toL2Bus.snoop_fanout::2 202992 16.97% 100.00% # Request fanout histogram | 3038system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram 3039system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram 3040system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram |
| 3015system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 3041system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 3016system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 3042system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 3017system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3043system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3018system.toL2Bus.snoop_fanout::total 1195846 # Request fanout histogram 3019system.toL2Bus.reqLayer0.occupancy 812251839 # Layer occupancy (ticks) | 3044system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram 3045system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) |
| 3020system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3046system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3021system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) | 3047system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) |
| 3022system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3048system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3023system.toL2Bus.respLayer0.occupancy 627943021 # Layer occupancy (ticks) | 3049system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) |
| 3024system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3050system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3025system.toL2Bus.respLayer1.occupancy 221271516 # Layer occupancy (ticks) | 3051system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) |
| 3026system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3027 3028---------- End Simulation Statistics ---------- | 3052system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3053 3054---------- End Simulation Statistics ---------- |