| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.868319 # Number of seconds simulated 4sim_ticks 2868318696500 # Number of ticks simulated 5final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.868581 # Number of seconds simulated 4sim_ticks 2868581440500 # Number of ticks simulated 5final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 534652 # Simulator instruction rate (inst/s) 8host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11631340017 # Simulator tick rate (ticks/s) 10host_mem_usage 586476 # Number of bytes of host memory used 11host_seconds 246.60 # Real time elapsed on the host 12sim_insts 131846562 # Number of instructions simulated 13sim_ops 159471778 # Number of ops (including micro ops) simulated | 7host_inst_rate 717360 # Simulator instruction rate (inst/s) 8host_op_rate 867708 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15647358559 # Simulator tick rate (ticks/s) 10host_mem_usage 639748 # Number of bytes of host memory used 11host_seconds 183.33 # Real time elapsed on the host 12sim_insts 131511324 # Number of instructions simulated 13sim_ops 159074269 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory |
| 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 26system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory | 25system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 30system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory | 32system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory |
| 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 36system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 44system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory | 42system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory |
| 46system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 44system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory | 46system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory |
| 49system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) | 47system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) |
| 51system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) | 55system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) | 56system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 61system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s) |
| 68system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) |
| 70system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) | 67system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s) |
| 77system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) | 73system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) |
| 78system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 200214 # Number of read requests accepted 80system.physmem.writeReqs 175885 # Number of write requests accepted 81system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue 85system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 12188 # Per bank write bursts 92system.physmem.perBankRdBursts::1 12046 # Per bank write bursts 93system.physmem.perBankRdBursts::2 12591 # Per bank write bursts 94system.physmem.perBankRdBursts::3 12330 # Per bank write bursts 95system.physmem.perBankRdBursts::4 20750 # Per bank write bursts 96system.physmem.perBankRdBursts::5 12582 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12043 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12246 # Per bank write bursts 99system.physmem.perBankRdBursts::8 12442 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12402 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11722 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11146 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11467 # Per bank write bursts 104system.physmem.perBankRdBursts::13 11916 # Per bank write bursts 105system.physmem.perBankRdBursts::14 10852 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11341 # Per bank write bursts 107system.physmem.perBankWrBursts::0 10835 # Per bank write bursts 108system.physmem.perBankWrBursts::1 11264 # Per bank write bursts 109system.physmem.perBankWrBursts::2 11493 # Per bank write bursts 110system.physmem.perBankWrBursts::3 10899 # Per bank write bursts 111system.physmem.perBankWrBursts::4 10487 # Per bank write bursts 112system.physmem.perBankWrBursts::5 11152 # Per bank write bursts 113system.physmem.perBankWrBursts::6 11024 # Per bank write bursts 114system.physmem.perBankWrBursts::7 10595 # Per bank write bursts 115system.physmem.perBankWrBursts::8 10782 # Per bank write bursts 116system.physmem.perBankWrBursts::9 10958 # Per bank write bursts 117system.physmem.perBankWrBursts::10 10716 # Per bank write bursts 118system.physmem.perBankWrBursts::11 10408 # Per bank write bursts 119system.physmem.perBankWrBursts::12 10444 # Per bank write bursts 120system.physmem.perBankWrBursts::13 9906 # Per bank write bursts 121system.physmem.perBankWrBursts::14 9416 # Per bank write bursts 122system.physmem.perBankWrBursts::15 9817 # Per bank write bursts | 74system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 191448 # Number of read requests accepted 76system.physmem.writeReqs 168916 # Number of write requests accepted 77system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue 81system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 11402 # Per bank write bursts 88system.physmem.perBankRdBursts::1 11523 # Per bank write bursts 89system.physmem.perBankRdBursts::2 11617 # Per bank write bursts 90system.physmem.perBankRdBursts::3 11771 # Per bank write bursts 91system.physmem.perBankRdBursts::4 20348 # Per bank write bursts 92system.physmem.perBankRdBursts::5 12097 # Per bank write bursts 93system.physmem.perBankRdBursts::6 11123 # Per bank write bursts 94system.physmem.perBankRdBursts::7 11241 # Per bank write bursts 95system.physmem.perBankRdBursts::8 11419 # Per bank write bursts 96system.physmem.perBankRdBursts::9 11532 # Per bank write bursts 97system.physmem.perBankRdBursts::10 11480 # Per bank write bursts 98system.physmem.perBankRdBursts::11 10715 # Per bank write bursts 99system.physmem.perBankRdBursts::12 11252 # Per bank write bursts 100system.physmem.perBankRdBursts::13 11225 # Per bank write bursts 101system.physmem.perBankRdBursts::14 11052 # Per bank write bursts 102system.physmem.perBankRdBursts::15 11518 # Per bank write bursts 103system.physmem.perBankWrBursts::0 9249 # Per bank write bursts 104system.physmem.perBankWrBursts::1 9496 # Per bank write bursts 105system.physmem.perBankWrBursts::2 9535 # Per bank write bursts 106system.physmem.perBankWrBursts::3 9435 # Per bank write bursts 107system.physmem.perBankWrBursts::4 8870 # Per bank write bursts 108system.physmem.perBankWrBursts::5 9467 # Per bank write bursts 109system.physmem.perBankWrBursts::6 9116 # Per bank write bursts 110system.physmem.perBankWrBursts::7 8737 # Per bank write bursts 111system.physmem.perBankWrBursts::8 8796 # Per bank write bursts 112system.physmem.perBankWrBursts::9 9230 # Per bank write bursts 113system.physmem.perBankWrBursts::10 9164 # Per bank write bursts 114system.physmem.perBankWrBursts::11 8822 # Per bank write bursts 115system.physmem.perBankWrBursts::12 9029 # Per bank write bursts 116system.physmem.perBankWrBursts::13 8642 # Per bank write bursts 117system.physmem.perBankWrBursts::14 8756 # Per bank write bursts 118system.physmem.perBankWrBursts::15 8750 # Per bank write bursts |
| 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 124system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 125system.physmem.totGap 2868318254500 # Total gap between requests | 120system.physmem.numWrRetry 83 # Number of times write queue was full causing retry 121system.physmem.totGap 2868581033500 # Total gap between requests |
| 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 9742 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) | 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 9742 # Read request sizes (log2) 125system.physmem.readPktSize::3 28 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 132system.physmem.readPktSize::6 190444 # Read request sizes (log2) | 128system.physmem.readPktSize::6 181678 # Read request sizes (log2) |
| 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4436 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) | 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 4436 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 139system.physmem.writePktSize::6 171449 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see | 135system.physmem.writePktSize::6 164480 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 9686 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 8351 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 6807 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 5320 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 4456 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 3748 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 3243 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 108 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see |
| 152system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see | 148system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see |
| 153system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see | 149system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see |
| 155system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see | 151system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see |
| 156system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see | 152system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads 310system.physmem.totQLat 4855930250 # Total ticks spent queuing 311system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM 312system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers 313system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst | 183system.physmem.wrQLenPdf::15 2068 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 2292 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 3518 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 4921 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 5539 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 5714 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 6057 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 6368 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 7230 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 6739 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 7593 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 8828 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 7425 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 7470 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 10447 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 8101 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 7437 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 7053 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 1018 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 1222 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 1197 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 2183 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 1792 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 1623 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 2924 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 1971 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 1845 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 1558 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 1629 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 1406 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 1139 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 1105 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 456 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 303 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 371 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 277 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 234 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see 232system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads 290system.physmem.totQLat 4538980935 # Total ticks spent queuing 291system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM 292system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers 293system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst |
| 314system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 294system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 315system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst 316system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s 317system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s 318system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s 319system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s | 295system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst 296system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s 297system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s 298system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s 299system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s |
| 320system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 321system.physmem.busUtil 0.06 # Data bus utilization in percentage 322system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 323system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 301system.physmem.busUtil 0.06 # Data bus utilization in percentage 302system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 303system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 324system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 325system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing 326system.physmem.readRowHits 167229 # Number of row buffer hits during reads 327system.physmem.writeRowHits 112615 # Number of row buffer hits during writes 328system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads 329system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes 330system.physmem.avgGap 7626497.96 # Average gap between requests 331system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined 332system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) 333system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) 334system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) 335system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) 336system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) 337system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) 338system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) 339system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) 340system.physmem_0.averagePower 669.622475 # Core power per rank (mW) 341system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states 342system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states | 304system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 305system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing 306system.physmem.readRowHits 160412 # Number of row buffer hits during reads 307system.physmem.writeRowHits 94279 # Number of row buffer hits during writes 308system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads 309system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes 310system.physmem.avgGap 7960231.97 # Average gap between requests 311system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined 312system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ) 313system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ) 314system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ) 315system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ) 316system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) 317system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ) 318system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ) 319system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ) 320system.physmem_0.averagePower 669.504870 # Core power per rank (mW) 321system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states 322system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states |
| 343system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 323system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 344system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states | 324system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states |
| 345system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 325system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 346system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) 347system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) 348system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) 349system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) 350system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) 351system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) 352system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) 353system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) 354system.physmem_1.averagePower 669.527135 # Core power per rank (mW) 355system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states 356system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states | 326system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ) 327system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ) 328system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ) 329system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ) 330system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) 331system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ) 332system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ) 333system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ) 334system.physmem_1.averagePower 669.408745 # Core power per rank (mW) 335system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states 336system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states |
| 357system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 337system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 358system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states | 338system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states |
| 359system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 360system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 363system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 364system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 365system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 366system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory --- 39 unchanged lines hidden (view full) --- 406system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 409system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 410system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 411system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 412system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 413system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 339system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 340system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 341system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 343system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 346system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory --- 39 unchanged lines hidden (view full) --- 386system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 387system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 388system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 389system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 390system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 391system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 392system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 393system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 414system.cpu0.dtb.walker.walks 7749 # Table walker walks requested 415system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors 416system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate 417system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate 418system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency | 394system.cpu0.dtb.walker.walks 7634 # Table walker walks requested 395system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors 396system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate 397system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate 398system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency 399system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency 400system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency 401system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency 402system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency 403system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency 404system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency 405system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency 406system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency |
| 428system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency | 409system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency |
| 429system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution 432system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution 433system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution 434system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated 435system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated 436system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated 437system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst | 410system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution 413system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution 414system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution 415system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated 416system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated 417system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated 418system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst |
| 438system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 419system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 439system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst | 420system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst |
| 441system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 442system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst | 423system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst 424system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst |
| 444system.cpu0.dtb.inst_hits 0 # ITB inst hits 445system.cpu0.dtb.inst_misses 0 # ITB inst misses | 425system.cpu0.dtb.inst_hits 0 # ITB inst hits 426system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 446system.cpu0.dtb.read_hits 19044092 # DTB read hits 447system.cpu0.dtb.read_misses 6608 # DTB read misses 448system.cpu0.dtb.write_hits 15688894 # DTB write hits 449system.cpu0.dtb.write_misses 1141 # DTB write misses | 427system.cpu0.dtb.read_hits 25111402 # DTB read hits 428system.cpu0.dtb.read_misses 6533 # DTB read misses 429system.cpu0.dtb.write_hits 18719047 # DTB write hits 430system.cpu0.dtb.write_misses 1101 # DTB write misses |
| 450system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 451system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 452system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 453system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 431system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 432system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 433system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 434system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 454system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB | 435system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB |
| 455system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 436system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 456system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch | 437system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch |
| 457system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 458system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 438system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 439system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 459system.cpu0.dtb.read_accesses 19050700 # DTB read accesses 460system.cpu0.dtb.write_accesses 15690035 # DTB write accesses | 440system.cpu0.dtb.read_accesses 25117935 # DTB read accesses 441system.cpu0.dtb.write_accesses 18720148 # DTB write accesses |
| 461system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 442system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 462system.cpu0.dtb.hits 34732986 # DTB hits 463system.cpu0.dtb.misses 7749 # DTB misses 464system.cpu0.dtb.accesses 34740735 # DTB accesses | 443system.cpu0.dtb.hits 43830449 # DTB hits 444system.cpu0.dtb.misses 7634 # DTB misses 445system.cpu0.dtb.accesses 43838083 # DTB accesses |
| 465system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 21 unchanged lines hidden (view full) --- 494system.cpu0.itb.walker.walks 3348 # Table walker walks requested 495system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors 496system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate 497system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 498system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency 499system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 500system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency 501system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency | 446system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 447system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 21 unchanged lines hidden (view full) --- 475system.cpu0.itb.walker.walks 3348 # Table walker walks requested 476system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors 477system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate 478system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 479system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency 480system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency 481system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency 482system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency |
| 502system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency | 483system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency |
| 509system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency | 490system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency |
| 510system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency | 491system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency |
| 512system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency | 493system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency |
| 513system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution 514system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution 515system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution | 494system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution 495system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution 496system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution |
| 516system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated 517system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated 518system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated 519system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 520system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst 521system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst 522system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 523system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst 524system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst 525system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst | 497system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated 498system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated 499system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated 500system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 501system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst 502system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst 503system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 504system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst 505system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst 506system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst |
| 526system.cpu0.itb.inst_hits 91510827 # ITB inst hits | 507system.cpu0.itb.inst_hits 118783416 # ITB inst hits |
| 527system.cpu0.itb.inst_misses 3348 # ITB inst misses 528system.cpu0.itb.read_hits 0 # DTB read hits 529system.cpu0.itb.read_misses 0 # DTB read misses 530system.cpu0.itb.write_hits 0 # DTB write hits 531system.cpu0.itb.write_misses 0 # DTB write misses 532system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 533system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 534system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 535system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 536system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB 537system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 538system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 539system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 540system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 541system.cpu0.itb.read_accesses 0 # DTB read accesses 542system.cpu0.itb.write_accesses 0 # DTB write accesses | 508system.cpu0.itb.inst_misses 3348 # ITB inst misses 509system.cpu0.itb.read_hits 0 # DTB read hits 510system.cpu0.itb.read_misses 0 # DTB read misses 511system.cpu0.itb.write_hits 0 # DTB write hits 512system.cpu0.itb.write_misses 0 # DTB write misses 513system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 514system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 515system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 516system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 517system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB 518system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 519system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 520system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 521system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 522system.cpu0.itb.read_accesses 0 # DTB read accesses 523system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 543system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses 544system.cpu0.itb.hits 91510827 # DTB hits | 524system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses 525system.cpu0.itb.hits 118783416 # DTB hits |
| 545system.cpu0.itb.misses 3348 # DTB misses | 526system.cpu0.itb.misses 3348 # DTB misses |
| 546system.cpu0.itb.accesses 91514175 # DTB accesses 547system.cpu0.numCycles 5736637393 # number of cpu cycles simulated | 527system.cpu0.itb.accesses 118786764 # DTB accesses 528system.cpu0.numCycles 5737162881 # number of cpu cycles simulated |
| 548system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 549system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 529system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 530system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 550system.cpu0.committedInsts 89363678 # Number of instructions committed 551system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed 552system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses | 531system.cpu0.committedInsts 115118664 # Number of instructions committed 532system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed 533system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses |
| 553system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses | 534system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses |
| 554system.cpu0.num_func_calls 6606472 # number of times a function call or return occured 555system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls 556system.cpu0.num_int_insts 94350928 # number of integer instructions | 535system.cpu0.num_func_calls 12673072 # number of times a function call or return occured 536system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls 537system.cpu0.num_int_insts 123147620 # number of integer instructions |
| 557system.cpu0.num_fp_insts 9820 # number of float instructions | 538system.cpu0.num_fp_insts 9820 # number of float instructions |
| 558system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read 559system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written | 539system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read 540system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written |
| 560system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read 561system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 541system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read 542system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 562system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read 563system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written 564system.cpu0.num_mem_refs 35866705 # number of memory refs 565system.cpu0.num_load_insts 19295047 # Number of load instructions 566system.cpu0.num_store_insts 16571658 # Number of store instructions 567system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles 568system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles 569system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles 570system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles 571system.cpu0.Branches 19970568 # Number of branches fetched | 543system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read 544system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written 545system.cpu0.num_mem_refs 44965604 # number of memory refs 546system.cpu0.num_load_insts 25362826 # Number of load instructions 547system.cpu0.num_store_insts 19602778 # Number of store instructions 548system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles 549system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles 550system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles 551system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles 552system.cpu0.Branches 29061799 # Number of branches fetched |
| 572system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction | 553system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction |
| 573system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction 574system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction 575system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction 576system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction 577system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction 578system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction 579system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction 580system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction 581system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction 582system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction 583system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction 584system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction 585system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction 586system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction 587system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction 588system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction 589system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction 590system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction 591system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction 592system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction 593system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction 594system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction 595system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction 596system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction 597system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction 598system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction 599system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 600system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 601system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 602system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction 603system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction | 554system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction 555system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction 556system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 557system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 558system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 559system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 560system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 561system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 562system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 563system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 564system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 565system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 566system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 567system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 568system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 569system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 570system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 571system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 572system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 573system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 574system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 575system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 576system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 577system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 578system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 579system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction 580system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 581system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 582system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 583system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction 584system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction |
| 604system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 605system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 585system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 586system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 606system.cpu0.op_class::total 109543126 # Class of executed instruction | 587system.cpu0.op_class::total 142881904 # Class of executed instruction |
| 607system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 588system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 608system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed 609system.cpu0.dcache.tags.replacements 690539 # number of replacements 610system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use 611system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. 612system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. 613system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. 614system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. 615system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor 616system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy 617system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy | 589system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed 590system.cpu0.dcache.tags.replacements 688886 # number of replacements 591system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use 592system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks. 593system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks. 594system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks. 595system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit. 596system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor 597system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy 598system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy |
| 618system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 599system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 619system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 620system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 621system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id | 600system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 601system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id 602system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id |
| 622system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 603system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 623system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses 624system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses 625system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits 626system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits 627system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits 628system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits 629system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits 630system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits 631system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits 632system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits 633system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits 634system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits 635system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits 636system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits 637system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits 638system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits 639system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses 640system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses 641system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses 642system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses 643system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses 644system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses 645system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses 646system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses 647system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses 648system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses 649system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses 650system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses 651system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses 652system.cpu0.dcache.overall_misses::total 847118 # number of overall misses 653system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles 654system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles 655system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles 656system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles 657system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles 658system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles 659system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles 660system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles 661system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles 662system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles 663system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles 664system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles 665system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles 666system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles 667system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) 668system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) 669system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) 670system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) 671system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) 672system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) 673system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) 674system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) 675system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) 676system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) 677system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses 678system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses 679system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses 680system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses 681system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses 682system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses 683system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses 684system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses 685system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses 686system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses 687system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses 688system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses 689system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses 690system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses 691system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses 692system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses 693system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses 694system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses 695system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency 696system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency 697system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency 698system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency 699system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency 700system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency 701system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency 702system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency | 604system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses 605system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses 606system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits 607system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits 608system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits 609system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits 610system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits 611system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits 612system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits 613system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits 614system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits 615system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits 616system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits 617system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits 618system.cpu0.dcache.overall_hits::cpu0.data 42162530 # number of overall hits 619system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits 620system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses 621system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses 622system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses 623system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses 624system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses 625system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses 626system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses 627system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses 628system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses 629system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses 630system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses 631system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses 632system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses 633system.cpu0.dcache.overall_misses::total 844255 # number of overall misses 634system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles 635system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles 636system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5098069375 # number of WriteReq miss cycles 637system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles 638system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles 639system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles 640system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435652050 # number of StoreCondReq miss cycles 641system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles 642system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles 643system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles 644system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles 645system.cpu0.dcache.demand_miss_latency::total 10110788611 # number of demand (read+write) miss cycles 646system.cpu0.dcache.overall_miss_latency::cpu0.data 10110788611 # number of overall miss cycles 647system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles 648system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses) 649system.cpu0.dcache.ReadReq_accesses::total 24247552 # number of ReadReq accesses(hits+misses) 650system.cpu0.dcache.WriteReq_accesses::cpu0.data 18313081 # number of WriteReq accesses(hits+misses) 651system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses) 652system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446152 # number of SoftPFReq accesses(hits+misses) 653system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses) 654system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses) 655system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses) 656system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses) 657system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses) 658system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses 659system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses 660system.cpu0.dcache.overall_accesses::cpu0.data 43006785 # number of overall (read+write) accesses 661system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses 662system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses 663system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses 664system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses 665system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses 666system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses 667system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses 668system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses 669system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses 670system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses 671system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses 672system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses 673system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses 674system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses 675system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses 676system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency 677system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency 678system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency 679system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency 680system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency 681system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency 682system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency 683system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency |
| 703system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 704system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 684system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 685system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 705system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency 706system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency 707system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency 708system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency | 686system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency 687system.cpu0.dcache.demand_avg_miss_latency::total 14104.901889 # average overall miss latency 688system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11975.989021 # average overall miss latency 689system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency |
| 709system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 710system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 711system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 712system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 713system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 714system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 715system.cpu0.dcache.fast_writes 0 # number of fast writes performed 716system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 690system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 691system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 695system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu0.dcache.fast_writes 0 # number of fast writes performed 697system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 717system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks 718system.cpu0.dcache.writebacks::total 504116 # number of writebacks 719system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits 720system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits 721system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits 722system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits 723system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits 724system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits 725system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits 726system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits 727system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses 728system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses 729system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses 730system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses 731system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses 732system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses 733system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses 734system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses 735system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses 736system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses 737system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses 738system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses 739system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses 740system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses 741system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles 742system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles 743system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles 744system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles 745system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles 746system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles 747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles 748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles 749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles 750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles 751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles 752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles 753system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles 754system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles 755system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles 756system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles 757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles 758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles 759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles 760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles 761system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles 762system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles 763system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses 764system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses 765system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses 766system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses 767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses 768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses 769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses 770system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses 771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses 772system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses 773system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses 774system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses 775system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses 776system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses 777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency 778system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency 779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency 780system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency 781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency 782system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency 783system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency 784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency 785system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency 786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency | 698system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks 699system.cpu0.dcache.writebacks::total 504121 # number of writebacks 700system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25265 # number of ReadReq MSHR hits 701system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits 702system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits 703system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits 704system.cpu0.dcache.demand_mshr_hits::cpu0.data 25265 # number of demand (read+write) MSHR hits 705system.cpu0.dcache.demand_mshr_hits::total 25265 # number of demand (read+write) MSHR hits 706system.cpu0.dcache.overall_mshr_hits::cpu0.data 25265 # number of overall MSHR hits 707system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits 708system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368023 # number of ReadReq MSHR misses 709system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses 710system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323540 # number of WriteReq MSHR misses 711system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses 712system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100320 # number of SoftPFReq MSHR misses 713system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses 714system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6758 # number of LoadLockedReq MSHR misses 715system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses 716system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19722 # number of StoreCondReq MSHR misses 717system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses 718system.cpu0.dcache.demand_mshr_misses::cpu0.data 691563 # number of demand (read+write) MSHR misses 719system.cpu0.dcache.demand_mshr_misses::total 691563 # number of demand (read+write) MSHR misses 720system.cpu0.dcache.overall_mshr_misses::cpu0.data 791883 # number of overall MSHR misses 721system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses 722system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4066612315 # number of ReadReq MSHR miss cycles 723system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles 724system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4601719625 # number of WriteReq MSHR miss cycles 725system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles 726system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1548565203 # number of SoftPFReq MSHR miss cycles 727system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles 728system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles 729system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles 730system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 405700950 # number of StoreCondReq MSHR miss cycles 731system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 405700950 # number of StoreCondReq MSHR miss cycles 732system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles 733system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles 734system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8668331940 # number of demand (read+write) MSHR miss cycles 735system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles 736system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles 737system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles 738system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles 739system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles 740system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4820424000 # number of WriteReq MSHR uncacheable cycles 741system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4820424000 # number of WriteReq MSHR uncacheable cycles 742system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles 743system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles 744system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015178 # mshr miss rate for ReadReq accesses 745system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses 746system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017667 # mshr miss rate for WriteReq accesses 747system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017667 # mshr miss rate for WriteReq accesses 748system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses 749system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses 750system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses 751system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses 752system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses 753system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses 754system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses 755system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses 756system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses 757system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses 758system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency 759system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency 760system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency 761system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency 762system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency 763system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency 764system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency 765system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency 766system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency 767system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency |
| 787system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 768system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 769system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 789system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency 790system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency 791system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency 792system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency | 770system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency 771system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency 772system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency 773system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency |
| 793system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 795system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 797system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 799system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 774system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 775system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 776system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 777system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 778system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 779system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 780system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 800system.cpu0.icache.tags.replacements 1099798 # number of replacements 801system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use 802system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. 803system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. 804system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. 805system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. 806system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor 807system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy 808system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy | 781system.cpu0.icache.tags.replacements 1101309 # number of replacements 782system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use 783system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks. 784system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks. 785system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks. 786system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit. 787system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor 788system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy 789system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy |
| 809system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 790system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 810system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 811system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id | 791system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 792system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id |
| 812system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id 813system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 793system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id 794system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 814system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses 815system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses 816system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits 817system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits 818system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits 819system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits 820system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits 821system.cpu0.icache.overall_hits::total 90410508 # number of overall hits 822system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses 823system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses 824system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses 825system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses 826system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses 827system.cpu0.icache.overall_misses::total 1100319 # number of overall misses 828system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles 829system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles 830system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles 831system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles 832system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles 833system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles 834system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) 835system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) 836system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses 837system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses 838system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses 839system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses 840system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses 841system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses 842system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses 843system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses 844system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses 845system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses 846system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency 847system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency 848system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency 849system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency 850system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency 851system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency | 795system.cpu0.icache.tags.tag_accesses 238668662 # Number of tag accesses 796system.cpu0.icache.tags.data_accesses 238668662 # Number of data accesses 797system.cpu0.icache.ReadReq_hits::cpu0.inst 117681586 # number of ReadReq hits 798system.cpu0.icache.ReadReq_hits::total 117681586 # number of ReadReq hits 799system.cpu0.icache.demand_hits::cpu0.inst 117681586 # number of demand (read+write) hits 800system.cpu0.icache.demand_hits::total 117681586 # number of demand (read+write) hits 801system.cpu0.icache.overall_hits::cpu0.inst 117681586 # number of overall hits 802system.cpu0.icache.overall_hits::total 117681586 # number of overall hits 803system.cpu0.icache.ReadReq_misses::cpu0.inst 1101830 # number of ReadReq misses 804system.cpu0.icache.ReadReq_misses::total 1101830 # number of ReadReq misses 805system.cpu0.icache.demand_misses::cpu0.inst 1101830 # number of demand (read+write) misses 806system.cpu0.icache.demand_misses::total 1101830 # number of demand (read+write) misses 807system.cpu0.icache.overall_misses::cpu0.inst 1101830 # number of overall misses 808system.cpu0.icache.overall_misses::total 1101830 # number of overall misses 809system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10869872254 # number of ReadReq miss cycles 810system.cpu0.icache.ReadReq_miss_latency::total 10869872254 # number of ReadReq miss cycles 811system.cpu0.icache.demand_miss_latency::cpu0.inst 10869872254 # number of demand (read+write) miss cycles 812system.cpu0.icache.demand_miss_latency::total 10869872254 # number of demand (read+write) miss cycles 813system.cpu0.icache.overall_miss_latency::cpu0.inst 10869872254 # number of overall miss cycles 814system.cpu0.icache.overall_miss_latency::total 10869872254 # number of overall miss cycles 815system.cpu0.icache.ReadReq_accesses::cpu0.inst 118783416 # number of ReadReq accesses(hits+misses) 816system.cpu0.icache.ReadReq_accesses::total 118783416 # number of ReadReq accesses(hits+misses) 817system.cpu0.icache.demand_accesses::cpu0.inst 118783416 # number of demand (read+write) accesses 818system.cpu0.icache.demand_accesses::total 118783416 # number of demand (read+write) accesses 819system.cpu0.icache.overall_accesses::cpu0.inst 118783416 # number of overall (read+write) accesses 820system.cpu0.icache.overall_accesses::total 118783416 # number of overall (read+write) accesses 821system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses 822system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses 823system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses 824system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses 825system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses 826system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses 827system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9865.289794 # average ReadReq miss latency 828system.cpu0.icache.ReadReq_avg_miss_latency::total 9865.289794 # average ReadReq miss latency 829system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency 830system.cpu0.icache.demand_avg_miss_latency::total 9865.289794 # average overall miss latency 831system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency 832system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency |
| 852system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 853system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 855system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 857system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu0.icache.fast_writes 0 # number of fast writes performed 859system.cpu0.icache.cache_copies 0 # number of cache copies performed | 833system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 834system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 835system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 836system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 837system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 838system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 839system.cpu0.icache.fast_writes 0 # number of fast writes performed 840system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 860system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses 861system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses 862system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses 863system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses 864system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses 865system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses 866system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles 867system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles 868system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles 869system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles 870system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles 871system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles 872system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 873system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 874system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 875system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles 876system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses 877system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses 878system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses 879system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses 880system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses 881system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses 882system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency 883system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency 884system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency 885system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency 886system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency 887system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency | 841system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101830 # number of ReadReq MSHR misses 842system.cpu0.icache.ReadReq_mshr_misses::total 1101830 # number of ReadReq MSHR misses 843system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101830 # number of demand (read+write) MSHR misses 844system.cpu0.icache.demand_mshr_misses::total 1101830 # number of demand (read+write) MSHR misses 845system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101830 # number of overall MSHR misses 846system.cpu0.icache.overall_mshr_misses::total 1101830 # number of overall MSHR misses 847system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9761619746 # number of ReadReq MSHR miss cycles 848system.cpu0.icache.ReadReq_mshr_miss_latency::total 9761619746 # number of ReadReq MSHR miss cycles 849system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9761619746 # number of demand (read+write) MSHR miss cycles 850system.cpu0.icache.demand_mshr_miss_latency::total 9761619746 # number of demand (read+write) MSHR miss cycles 851system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9761619746 # number of overall MSHR miss cycles 852system.cpu0.icache.overall_mshr_miss_latency::total 9761619746 # number of overall MSHR miss cycles 853system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles 854system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles 855system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles 856system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles 857system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses 858system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses 859system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses 860system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses 861system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses 862system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses 863system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average ReadReq mshr miss latency 864system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8859.460848 # average ReadReq mshr miss latency 865system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency 866system.cpu0.icache.demand_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency 867system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency 868system.cpu0.icache.overall_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency |
| 888system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 889system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 890system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 891system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 869system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 870system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 871system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 872system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 873system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 893system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued 894system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified 895system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue | 874system.cpu0.l2cache.prefetcher.num_hwpf_issued 1839936 # number of hwpf issued 875system.cpu0.l2cache.prefetcher.pfIdentified 1839962 # number of prefetch candidates identified 876system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue |
| 896system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 897system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 877system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 878system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 898system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing 899system.cpu0.l2cache.tags.replacements 268426 # number of replacements 900system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use 901system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. 902system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. 903system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. | 879system.cpu0.l2cache.prefetcher.pfSpanPage 237006 # number of prefetches not generated due to page crossing 880system.cpu0.l2cache.tags.replacements 267761 # number of replacements 881system.cpu0.l2cache.tags.tagsinuse 16103.938258 # Cycle average of tags in use 882system.cpu0.l2cache.tags.total_refs 1970214 # Total number of references to valid blocks. 883system.cpu0.l2cache.tags.sampled_refs 284001 # Sample count of references to valid blocks. 884system.cpu0.l2cache.tags.avg_refs 6.937349 # Average number of references to valid blocks. |
| 904system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 885system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 905system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor 906system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor 907system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor 908system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor 909system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor 910system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor 911system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy 912system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy 913system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy 914system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy 915system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy 916system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy 917system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy 918system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id 919system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 920system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id 921system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 922system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id | 886system.cpu0.l2cache.tags.occ_blocks::writebacks 7915.761025 # Average occupied blocks per requestor 887system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.539297 # Average occupied blocks per requestor 888system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.155291 # Average occupied blocks per requestor 889system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4574.741605 # Average occupied blocks per requestor 890system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1897.934094 # Average occupied blocks per requestor 891system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1714.806946 # Average occupied blocks per requestor 892system.cpu0.l2cache.tags.occ_percent::writebacks 0.483140 # Average percentage of cache occupancy 893system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000033 # Average percentage of cache occupancy 894system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy 895system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.279220 # Average percentage of cache occupancy 896system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.115841 # Average percentage of cache occupancy 897system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104664 # Average percentage of cache occupancy 898system.cpu0.l2cache.tags.occ_percent::total 0.982906 # Average percentage of cache occupancy 899system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1117 # Occupied blocks per task id 900system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 901system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id 902system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id 903system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 261 # Occupied blocks per task id |
| 923system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id | 904system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id |
| 924system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id 925system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id | 905system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id 906system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 907system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 908system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 909system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id |
| 929system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id | 911system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id |
| 930system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7809 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3908 # Occupied blocks per task id 932system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068787 # Percentage of cache occupancy per task id 933system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 934system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921997 # Percentage of cache occupancy per task id 935system.cpu0.l2cache.tags.tag_accesses 39654154 # Number of tag accesses 936system.cpu0.l2cache.tags.data_accesses 39654154 # Number of data accesses 937system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7774 # number of ReadReq hits 938system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3610 # number of ReadReq hits 939system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053168 # number of ReadReq hits 940system.cpu0.l2cache.ReadReq_hits::cpu0.data 381762 # number of ReadReq hits 941system.cpu0.l2cache.ReadReq_hits::total 1446314 # number of ReadReq hits 942system.cpu0.l2cache.Writeback_hits::writebacks 504114 # number of Writeback hits 943system.cpu0.l2cache.Writeback_hits::total 504114 # number of Writeback hits 944system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28406 # number of UpgradeReq hits 945system.cpu0.l2cache.UpgradeReq_hits::total 28406 # number of UpgradeReq hits 946system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1700 # number of SCUpgradeReq hits 947system.cpu0.l2cache.SCUpgradeReq_hits::total 1700 # number of SCUpgradeReq hits 948system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227802 # number of ReadExReq hits 949system.cpu0.l2cache.ReadExReq_hits::total 227802 # number of ReadExReq hits 950system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7774 # number of demand (read+write) hits 951system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3610 # number of demand (read+write) hits 952system.cpu0.l2cache.demand_hits::cpu0.inst 1053168 # number of demand (read+write) hits 953system.cpu0.l2cache.demand_hits::cpu0.data 609564 # number of demand (read+write) hits 954system.cpu0.l2cache.demand_hits::total 1674116 # number of demand (read+write) hits 955system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7774 # number of overall hits 956system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3610 # number of overall hits 957system.cpu0.l2cache.overall_hits::cpu0.inst 1053168 # number of overall hits 958system.cpu0.l2cache.overall_hits::cpu0.data 609564 # number of overall hits 959system.cpu0.l2cache.overall_hits::total 1674116 # number of overall hits 960system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 215 # number of ReadReq misses 961system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 122 # number of ReadReq misses 962system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47151 # number of ReadReq misses 963system.cpu0.l2cache.ReadReq_misses::cpu0.data 94947 # number of ReadReq misses 964system.cpu0.l2cache.ReadReq_misses::total 142435 # number of ReadReq misses 965system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26586 # number of UpgradeReq misses 966system.cpu0.l2cache.UpgradeReq_misses::total 26586 # number of UpgradeReq misses 967system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18299 # number of SCUpgradeReq misses 968system.cpu0.l2cache.SCUpgradeReq_misses::total 18299 # number of SCUpgradeReq misses 969system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 970system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 971system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41687 # number of ReadExReq misses 972system.cpu0.l2cache.ReadExReq_misses::total 41687 # number of ReadExReq misses 973system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 215 # number of demand (read+write) misses 974system.cpu0.l2cache.demand_misses::cpu0.itb.walker 122 # number of demand (read+write) misses 975system.cpu0.l2cache.demand_misses::cpu0.inst 47151 # number of demand (read+write) misses 976system.cpu0.l2cache.demand_misses::cpu0.data 136634 # number of demand (read+write) misses 977system.cpu0.l2cache.demand_misses::total 184122 # number of demand (read+write) misses 978system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 215 # number of overall misses 979system.cpu0.l2cache.overall_misses::cpu0.itb.walker 122 # number of overall misses 980system.cpu0.l2cache.overall_misses::cpu0.inst 47151 # number of overall misses 981system.cpu0.l2cache.overall_misses::cpu0.data 136634 # number of overall misses 982system.cpu0.l2cache.overall_misses::total 184122 # number of overall misses 983system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4899750 # number of ReadReq miss cycles 984system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2713500 # number of ReadReq miss cycles 985system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2213649997 # number of ReadReq miss cycles 986system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2684439955 # number of ReadReq miss cycles 987system.cpu0.l2cache.ReadReq_miss_latency::total 4905703202 # number of ReadReq miss cycles 988system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 458226521 # number of UpgradeReq miss cycles 989system.cpu0.l2cache.UpgradeReq_miss_latency::total 458226521 # number of UpgradeReq miss cycles 990system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 356750783 # number of SCUpgradeReq miss cycles 991system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356750783 # number of SCUpgradeReq miss cycles 992system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1434495 # number of SCUpgradeFailReq miss cycles 993system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1434495 # number of SCUpgradeFailReq miss cycles 994system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1789174823 # number of ReadExReq miss cycles 995system.cpu0.l2cache.ReadExReq_miss_latency::total 1789174823 # number of ReadExReq miss cycles 996system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4899750 # number of demand (read+write) miss cycles 997system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2713500 # number of demand (read+write) miss cycles 998system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2213649997 # number of demand (read+write) miss cycles 999system.cpu0.l2cache.demand_miss_latency::cpu0.data 4473614778 # number of demand (read+write) miss cycles 1000system.cpu0.l2cache.demand_miss_latency::total 6694878025 # number of demand (read+write) miss cycles 1001system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4899750 # number of overall miss cycles 1002system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2713500 # number of overall miss cycles 1003system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2213649997 # number of overall miss cycles 1004system.cpu0.l2cache.overall_miss_latency::cpu0.data 4473614778 # number of overall miss cycles 1005system.cpu0.l2cache.overall_miss_latency::total 6694878025 # number of overall miss cycles 1006system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7989 # number of ReadReq accesses(hits+misses) 1007system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3732 # number of ReadReq accesses(hits+misses) 1008system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100319 # number of ReadReq accesses(hits+misses) 1009system.cpu0.l2cache.ReadReq_accesses::cpu0.data 476709 # number of ReadReq accesses(hits+misses) 1010system.cpu0.l2cache.ReadReq_accesses::total 1588749 # number of ReadReq accesses(hits+misses) 1011system.cpu0.l2cache.Writeback_accesses::writebacks 504114 # number of Writeback accesses(hits+misses) 1012system.cpu0.l2cache.Writeback_accesses::total 504114 # number of Writeback accesses(hits+misses) 1013system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54992 # number of UpgradeReq accesses(hits+misses) 1014system.cpu0.l2cache.UpgradeReq_accesses::total 54992 # number of UpgradeReq accesses(hits+misses) 1015system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19999 # number of SCUpgradeReq accesses(hits+misses) 1016system.cpu0.l2cache.SCUpgradeReq_accesses::total 19999 # number of SCUpgradeReq accesses(hits+misses) 1017system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1018system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1019system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269489 # number of ReadExReq accesses(hits+misses) 1020system.cpu0.l2cache.ReadExReq_accesses::total 269489 # number of ReadExReq accesses(hits+misses) 1021system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7989 # number of demand (read+write) accesses 1022system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3732 # number of demand (read+write) accesses 1023system.cpu0.l2cache.demand_accesses::cpu0.inst 1100319 # number of demand (read+write) accesses 1024system.cpu0.l2cache.demand_accesses::cpu0.data 746198 # number of demand (read+write) accesses 1025system.cpu0.l2cache.demand_accesses::total 1858238 # number of demand (read+write) accesses 1026system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7989 # number of overall (read+write) accesses 1027system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3732 # number of overall (read+write) accesses 1028system.cpu0.l2cache.overall_accesses::cpu0.inst 1100319 # number of overall (read+write) accesses 1029system.cpu0.l2cache.overall_accesses::cpu0.data 746198 # number of overall (read+write) accesses 1030system.cpu0.l2cache.overall_accesses::total 1858238 # number of overall (read+write) accesses 1031system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for ReadReq accesses 1032system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032690 # miss rate for ReadReq accesses 1033system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042852 # miss rate for ReadReq accesses 1034system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199172 # miss rate for ReadReq accesses 1035system.cpu0.l2cache.ReadReq_miss_rate::total 0.089652 # miss rate for ReadReq accesses 1036system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.483452 # miss rate for UpgradeReq accesses 1037system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.483452 # miss rate for UpgradeReq accesses 1038system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.914996 # miss rate for SCUpgradeReq accesses 1039system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.914996 # miss rate for SCUpgradeReq accesses | 912system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8038 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3680 # Occupied blocks per task id 914system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068176 # Percentage of cache occupancy per task id 915system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 916system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id 917system.cpu0.l2cache.tags.tag_accesses 39636813 # Number of tag accesses 918system.cpu0.l2cache.tags.data_accesses 39636813 # Number of data accesses 919system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 8046 # number of ReadReq hits 920system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3668 # number of ReadReq hits 921system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1054676 # number of ReadReq hits 922system.cpu0.l2cache.ReadReq_hits::cpu0.data 380878 # number of ReadReq hits 923system.cpu0.l2cache.ReadReq_hits::total 1447268 # number of ReadReq hits 924system.cpu0.l2cache.Writeback_hits::writebacks 504119 # number of Writeback hits 925system.cpu0.l2cache.Writeback_hits::total 504119 # number of Writeback hits 926system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28198 # number of UpgradeReq hits 927system.cpu0.l2cache.UpgradeReq_hits::total 28198 # number of UpgradeReq hits 928system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1754 # number of SCUpgradeReq hits 929system.cpu0.l2cache.SCUpgradeReq_hits::total 1754 # number of SCUpgradeReq hits 930system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225223 # number of ReadExReq hits 931system.cpu0.l2cache.ReadExReq_hits::total 225223 # number of ReadExReq hits 932system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8046 # number of demand (read+write) hits 933system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3668 # number of demand (read+write) hits 934system.cpu0.l2cache.demand_hits::cpu0.inst 1054676 # number of demand (read+write) hits 935system.cpu0.l2cache.demand_hits::cpu0.data 606101 # number of demand (read+write) hits 936system.cpu0.l2cache.demand_hits::total 1672491 # number of demand (read+write) hits 937system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8046 # number of overall hits 938system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3668 # number of overall hits 939system.cpu0.l2cache.overall_hits::cpu0.inst 1054676 # number of overall hits 940system.cpu0.l2cache.overall_hits::cpu0.data 606101 # number of overall hits 941system.cpu0.l2cache.overall_hits::total 1672491 # number of overall hits 942system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 223 # number of ReadReq misses 943system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 133 # number of ReadReq misses 944system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47154 # number of ReadReq misses 945system.cpu0.l2cache.ReadReq_misses::cpu0.data 94223 # number of ReadReq misses 946system.cpu0.l2cache.ReadReq_misses::total 141733 # number of ReadReq misses 947system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26109 # number of UpgradeReq misses 948system.cpu0.l2cache.UpgradeReq_misses::total 26109 # number of UpgradeReq misses 949system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17961 # number of SCUpgradeReq misses 950system.cpu0.l2cache.SCUpgradeReq_misses::total 17961 # number of SCUpgradeReq misses 951system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 952system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 953system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44010 # number of ReadExReq misses 954system.cpu0.l2cache.ReadExReq_misses::total 44010 # number of ReadExReq misses 955system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 223 # number of demand (read+write) misses 956system.cpu0.l2cache.demand_misses::cpu0.itb.walker 133 # number of demand (read+write) misses 957system.cpu0.l2cache.demand_misses::cpu0.inst 47154 # number of demand (read+write) misses 958system.cpu0.l2cache.demand_misses::cpu0.data 138233 # number of demand (read+write) misses 959system.cpu0.l2cache.demand_misses::total 185743 # number of demand (read+write) misses 960system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 223 # number of overall misses 961system.cpu0.l2cache.overall_misses::cpu0.itb.walker 133 # number of overall misses 962system.cpu0.l2cache.overall_misses::cpu0.inst 47154 # number of overall misses 963system.cpu0.l2cache.overall_misses::cpu0.data 138233 # number of overall misses 964system.cpu0.l2cache.overall_misses::total 185743 # number of overall misses 965system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5218750 # number of ReadReq miss cycles 966system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3033000 # number of ReadReq miss cycles 967system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2351090746 # number of ReadReq miss cycles 968system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2761351258 # number of ReadReq miss cycles 969system.cpu0.l2cache.ReadReq_miss_latency::total 5120693754 # number of ReadReq miss cycles 970system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 483042430 # number of UpgradeReq miss cycles 971system.cpu0.l2cache.UpgradeReq_miss_latency::total 483042430 # number of UpgradeReq miss cycles 972system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 364663752 # number of SCUpgradeReq miss cycles 973system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 364663752 # number of SCUpgradeReq miss cycles 974system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1698997 # number of SCUpgradeFailReq miss cycles 975system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1698997 # number of SCUpgradeFailReq miss cycles 976system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1948619833 # number of ReadExReq miss cycles 977system.cpu0.l2cache.ReadExReq_miss_latency::total 1948619833 # number of ReadExReq miss cycles 978system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5218750 # number of demand (read+write) miss cycles 979system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3033000 # number of demand (read+write) miss cycles 980system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2351090746 # number of demand (read+write) miss cycles 981system.cpu0.l2cache.demand_miss_latency::cpu0.data 4709971091 # number of demand (read+write) miss cycles 982system.cpu0.l2cache.demand_miss_latency::total 7069313587 # number of demand (read+write) miss cycles 983system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5218750 # number of overall miss cycles 984system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3033000 # number of overall miss cycles 985system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2351090746 # number of overall miss cycles 986system.cpu0.l2cache.overall_miss_latency::cpu0.data 4709971091 # number of overall miss cycles 987system.cpu0.l2cache.overall_miss_latency::total 7069313587 # number of overall miss cycles 988system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8269 # number of ReadReq accesses(hits+misses) 989system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3801 # number of ReadReq accesses(hits+misses) 990system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1101830 # number of ReadReq accesses(hits+misses) 991system.cpu0.l2cache.ReadReq_accesses::cpu0.data 475101 # number of ReadReq accesses(hits+misses) 992system.cpu0.l2cache.ReadReq_accesses::total 1589001 # number of ReadReq accesses(hits+misses) 993system.cpu0.l2cache.Writeback_accesses::writebacks 504119 # number of Writeback accesses(hits+misses) 994system.cpu0.l2cache.Writeback_accesses::total 504119 # number of Writeback accesses(hits+misses) 995system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54307 # number of UpgradeReq accesses(hits+misses) 996system.cpu0.l2cache.UpgradeReq_accesses::total 54307 # number of UpgradeReq accesses(hits+misses) 997system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19715 # number of SCUpgradeReq accesses(hits+misses) 998system.cpu0.l2cache.SCUpgradeReq_accesses::total 19715 # number of SCUpgradeReq accesses(hits+misses) 999system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1000system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1001system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269233 # number of ReadExReq accesses(hits+misses) 1002system.cpu0.l2cache.ReadExReq_accesses::total 269233 # number of ReadExReq accesses(hits+misses) 1003system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8269 # number of demand (read+write) accesses 1004system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3801 # number of demand (read+write) accesses 1005system.cpu0.l2cache.demand_accesses::cpu0.inst 1101830 # number of demand (read+write) accesses 1006system.cpu0.l2cache.demand_accesses::cpu0.data 744334 # number of demand (read+write) accesses 1007system.cpu0.l2cache.demand_accesses::total 1858234 # number of demand (read+write) accesses 1008system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8269 # number of overall (read+write) accesses 1009system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3801 # number of overall (read+write) accesses 1010system.cpu0.l2cache.overall_accesses::cpu0.inst 1101830 # number of overall (read+write) accesses 1011system.cpu0.l2cache.overall_accesses::cpu0.data 744334 # number of overall (read+write) accesses 1012system.cpu0.l2cache.overall_accesses::total 1858234 # number of overall (read+write) accesses 1013system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for ReadReq accesses 1014system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.034991 # miss rate for ReadReq accesses 1015system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042796 # miss rate for ReadReq accesses 1016system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.198322 # miss rate for ReadReq accesses 1017system.cpu0.l2cache.ReadReq_miss_rate::total 0.089196 # miss rate for ReadReq accesses 1018system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.480767 # miss rate for UpgradeReq accesses 1019system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.480767 # miss rate for UpgradeReq accesses 1020system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911032 # miss rate for SCUpgradeReq accesses 1021system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911032 # miss rate for SCUpgradeReq accesses |
| 1040system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1041system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1022system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1023system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1042system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154689 # miss rate for ReadExReq accesses 1043system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154689 # miss rate for ReadExReq accesses 1044system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for demand accesses 1045system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032690 # miss rate for demand accesses 1046system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042852 # miss rate for demand accesses 1047system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183107 # miss rate for demand accesses 1048system.cpu0.l2cache.demand_miss_rate::total 0.099084 # miss rate for demand accesses 1049system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for overall accesses 1050system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032690 # miss rate for overall accesses 1051system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042852 # miss rate for overall accesses 1052system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183107 # miss rate for overall accesses 1053system.cpu0.l2cache.overall_miss_rate::total 0.099084 # miss rate for overall accesses 1054system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average ReadReq miss latency 1055system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22241.803279 # average ReadReq miss latency 1056system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46948.102840 # average ReadReq miss latency 1057system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28273.036062 # average ReadReq miss latency 1058system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34441.697630 # average ReadReq miss latency 1059system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17235.632325 # average UpgradeReq miss latency 1060system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17235.632325 # average UpgradeReq miss latency 1061system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19495.643642 # average SCUpgradeReq miss latency 1062system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19495.643642 # average SCUpgradeReq miss latency 1063system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 179311.875000 # average SCUpgradeFailReq miss latency 1064system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 179311.875000 # average SCUpgradeFailReq miss latency 1065system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 42919.251157 # average ReadExReq miss latency 1066system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 42919.251157 # average ReadExReq miss latency 1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency 1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency 1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency 1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency 1071system.cpu0.l2cache.demand_avg_miss_latency::total 36361.097669 # average overall miss latency 1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency 1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency 1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency 1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency 1076system.cpu0.l2cache.overall_avg_miss_latency::total 36361.097669 # average overall miss latency | 1024system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163464 # miss rate for ReadExReq accesses 1025system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163464 # miss rate for ReadExReq accesses 1026system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for demand accesses 1027system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.034991 # miss rate for demand accesses 1028system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042796 # miss rate for demand accesses 1029system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185714 # miss rate for demand accesses 1030system.cpu0.l2cache.demand_miss_rate::total 0.099957 # miss rate for demand accesses 1031system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for overall accesses 1032system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.034991 # miss rate for overall accesses 1033system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042796 # miss rate for overall accesses 1034system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185714 # miss rate for overall accesses 1035system.cpu0.l2cache.overall_miss_rate::total 0.099957 # miss rate for overall accesses 1036system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average ReadReq miss latency 1037system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22804.511278 # average ReadReq miss latency 1038system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49859.836833 # average ReadReq miss latency 1039system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29306.552094 # average ReadReq miss latency 1040system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36129.156611 # average ReadReq miss latency 1041system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18500.993144 # average UpgradeReq miss latency 1042system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18500.993144 # average UpgradeReq miss latency 1043system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.087356 # average SCUpgradeReq miss latency 1044system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.087356 # average SCUpgradeReq miss latency 1045system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 242713.857143 # average SCUpgradeFailReq miss latency 1046system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 242713.857143 # average SCUpgradeFailReq miss latency 1047system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44276.751488 # average ReadExReq miss latency 1048system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44276.751488 # average ReadExReq miss latency 1049system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency 1050system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency 1051system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency 1052system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency 1053system.cpu0.l2cache.demand_avg_miss_latency::total 38059.650092 # average overall miss latency 1054system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency 1055system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency 1056system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency 1057system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency 1058system.cpu0.l2cache.overall_avg_miss_latency::total 38059.650092 # average overall miss latency |
| 1077system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1059system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1060system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1061system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1062system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1063system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1064system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1065system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1066system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1085system.cpu0.l2cache.writebacks::writebacks 196247 # number of writebacks 1086system.cpu0.l2cache.writebacks::total 196247 # number of writebacks | 1067system.cpu0.l2cache.writebacks::writebacks 195381 # number of writebacks 1068system.cpu0.l2cache.writebacks::total 195381 # number of writebacks |
| 1087system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 32 # number of ReadReq MSHR hits 1088system.cpu0.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits | 1069system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 32 # number of ReadReq MSHR hits 1070system.cpu0.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits |
| 1089system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits 1090system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits 1091system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1242 # number of demand (read+write) MSHR hits 1092system.cpu0.l2cache.demand_mshr_hits::total 1242 # number of demand (read+write) MSHR hits 1093system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1242 # number of overall MSHR hits 1094system.cpu0.l2cache.overall_mshr_hits::total 1242 # number of overall MSHR hits 1095system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 215 # number of ReadReq MSHR misses 1096system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 122 # number of ReadReq MSHR misses 1097system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47151 # number of ReadReq MSHR misses 1098system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94915 # number of ReadReq MSHR misses 1099system.cpu0.l2cache.ReadReq_mshr_misses::total 142403 # number of ReadReq MSHR misses 1100system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of HardPFReq MSHR misses 1101system.cpu0.l2cache.HardPFReq_mshr_misses::total 246323 # number of HardPFReq MSHR misses 1102system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26586 # number of UpgradeReq MSHR misses 1103system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26586 # number of UpgradeReq MSHR misses 1104system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18299 # number of SCUpgradeReq MSHR misses 1105system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18299 # number of SCUpgradeReq MSHR misses 1106system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1107system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1108system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40477 # number of ReadExReq MSHR misses 1109system.cpu0.l2cache.ReadExReq_mshr_misses::total 40477 # number of ReadExReq MSHR misses 1110system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 215 # number of demand (read+write) MSHR misses 1111system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 122 # number of demand (read+write) MSHR misses 1112system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47151 # number of demand (read+write) MSHR misses 1113system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135392 # number of demand (read+write) MSHR misses 1114system.cpu0.l2cache.demand_mshr_misses::total 182880 # number of demand (read+write) MSHR misses 1115system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 215 # number of overall MSHR misses 1116system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 122 # number of overall MSHR misses 1117system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47151 # number of overall MSHR misses 1118system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135392 # number of overall MSHR misses 1119system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of overall MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::total 429203 # number of overall MSHR misses 1121system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of ReadReq MSHR miss cycles 1122system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1859500 # number of ReadReq MSHR miss cycles 1123system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 1877090003 # number of ReadReq MSHR miss cycles 1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2013208709 # number of ReadReq MSHR miss cycles 1125system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 3895552462 # number of ReadReq MSHR miss cycles 1126system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of HardPFReq MSHR miss cycles 1127system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13906201830 # number of HardPFReq MSHR miss cycles 1128system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 448274629 # number of UpgradeReq MSHR miss cycles 1129system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 448274629 # number of UpgradeReq MSHR miss cycles 1130system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 246009723 # number of SCUpgradeReq MSHR miss cycles 1131system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 246009723 # number of SCUpgradeReq MSHR miss cycles 1132system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1112495 # number of SCUpgradeFailReq MSHR miss cycles 1133system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1112495 # number of SCUpgradeFailReq MSHR miss cycles 1134system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1381066645 # number of ReadExReq MSHR miss cycles 1135system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1381066645 # number of ReadExReq MSHR miss cycles 1136system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of demand (read+write) MSHR miss cycles 1137system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1859500 # number of demand (read+write) MSHR miss cycles 1138system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1877090003 # number of demand (read+write) MSHR miss cycles 1139system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3394275354 # number of demand (read+write) MSHR miss cycles 1140system.cpu0.l2cache.demand_mshr_miss_latency::total 5276619107 # number of demand (read+write) MSHR miss cycles 1141system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of overall MSHR miss cycles 1142system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1859500 # number of overall MSHR miss cycles 1143system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1877090003 # number of overall MSHR miss cycles 1144system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3394275354 # number of overall MSHR miss cycles 1145system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of overall MSHR miss cycles 1146system.cpu0.l2cache.overall_mshr_miss_latency::total 19182820937 # number of overall MSHR miss cycles 1147system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647209500 # number of ReadReq MSHR uncacheable cycles 1148system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5743013251 # number of ReadReq MSHR uncacheable cycles 1149system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6390222751 # number of ReadReq MSHR uncacheable cycles 1150system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4419325000 # number of WriteReq MSHR uncacheable cycles 1151system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4419325000 # number of WriteReq MSHR uncacheable cycles 1152system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647209500 # number of overall MSHR uncacheable cycles 1153system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10162338251 # number of overall MSHR uncacheable cycles 1154system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10809547751 # number of overall MSHR uncacheable cycles 1155system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for ReadReq accesses 1156system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for ReadReq accesses 1157system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for ReadReq accesses 1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses 1159system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses | 1071system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1212 # number of ReadExReq MSHR hits 1072system.cpu0.l2cache.ReadExReq_mshr_hits::total 1212 # number of ReadExReq MSHR hits 1073system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits 1074system.cpu0.l2cache.demand_mshr_hits::total 1244 # number of demand (read+write) MSHR hits 1075system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits 1076system.cpu0.l2cache.overall_mshr_hits::total 1244 # number of overall MSHR hits 1077system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 223 # number of ReadReq MSHR misses 1078system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 133 # number of ReadReq MSHR misses 1079system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47154 # number of ReadReq MSHR misses 1080system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94191 # number of ReadReq MSHR misses 1081system.cpu0.l2cache.ReadReq_mshr_misses::total 141701 # number of ReadReq MSHR misses 1082system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of HardPFReq MSHR misses 1083system.cpu0.l2cache.HardPFReq_mshr_misses::total 243995 # number of HardPFReq MSHR misses 1084system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26109 # number of UpgradeReq MSHR misses 1085system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26109 # number of UpgradeReq MSHR misses 1086system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17961 # number of SCUpgradeReq MSHR misses 1087system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17961 # number of SCUpgradeReq MSHR misses 1088system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1089system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1090system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42798 # number of ReadExReq MSHR misses 1091system.cpu0.l2cache.ReadExReq_mshr_misses::total 42798 # number of ReadExReq MSHR misses 1092system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 223 # number of demand (read+write) MSHR misses 1093system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 133 # number of demand (read+write) MSHR misses 1094system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47154 # number of demand (read+write) MSHR misses 1095system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136989 # number of demand (read+write) MSHR misses 1096system.cpu0.l2cache.demand_mshr_misses::total 184499 # number of demand (read+write) MSHR misses 1097system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 223 # number of overall MSHR misses 1098system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 133 # number of overall MSHR misses 1099system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47154 # number of overall MSHR misses 1100system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136989 # number of overall MSHR misses 1101system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of overall MSHR misses 1102system.cpu0.l2cache.overall_mshr_misses::total 428494 # number of overall MSHR misses 1103system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of ReadReq MSHR miss cycles 1104system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2168500 # number of ReadReq MSHR miss cycles 1105system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2038167254 # number of ReadReq MSHR miss cycles 1106system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2142124308 # number of ReadReq MSHR miss cycles 1107system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4186228812 # number of ReadReq MSHR miss cycles 1108system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of HardPFReq MSHR miss cycles 1109system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13497828640 # number of HardPFReq MSHR miss cycles 1110system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 512289208 # number of UpgradeReq MSHR miss cycles 1111system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 512289208 # number of UpgradeReq MSHR miss cycles 1112system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 258190050 # number of SCUpgradeReq MSHR miss cycles 1113system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 258190050 # number of SCUpgradeReq MSHR miss cycles 1114system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1347997 # number of SCUpgradeFailReq MSHR miss cycles 1115system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1347997 # number of SCUpgradeFailReq MSHR miss cycles 1116system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1547245660 # number of ReadExReq MSHR miss cycles 1117system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1547245660 # number of ReadExReq MSHR miss cycles 1118system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of demand (read+write) MSHR miss cycles 1119system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2168500 # number of demand (read+write) MSHR miss cycles 1120system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2038167254 # number of demand (read+write) MSHR miss cycles 1121system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3689369968 # number of demand (read+write) MSHR miss cycles 1122system.cpu0.l2cache.demand_mshr_miss_latency::total 5733474472 # number of demand (read+write) MSHR miss cycles 1123system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of overall MSHR miss cycles 1124system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2168500 # number of overall MSHR miss cycles 1125system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2038167254 # number of overall MSHR miss cycles 1126system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3689369968 # number of overall MSHR miss cycles 1127system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of overall MSHR miss cycles 1128system.cpu0.l2cache.overall_mshr_miss_latency::total 19231303112 # number of overall MSHR miss cycles 1129system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles 1130system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5927208500 # number of ReadReq MSHR uncacheable cycles 1131system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6657462000 # number of ReadReq MSHR uncacheable cycles 1132system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4606674000 # number of WriteReq MSHR uncacheable cycles 1133system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4606674000 # number of WriteReq MSHR uncacheable cycles 1134system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles 1135system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10533882500 # number of overall MSHR uncacheable cycles 1136system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11264136000 # number of overall MSHR uncacheable cycles 1137system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for ReadReq accesses 1138system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for ReadReq accesses 1139system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for ReadReq accesses 1140system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198255 # mshr miss rate for ReadReq accesses 1141system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089176 # mshr miss rate for ReadReq accesses |
| 1160system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1161system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1142system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1143system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1162system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses 1163system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses 1164system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses 1165system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses | 1144system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.480767 # mshr miss rate for UpgradeReq accesses 1145system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.480767 # mshr miss rate for UpgradeReq accesses 1146system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911032 # mshr miss rate for SCUpgradeReq accesses 1147system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911032 # mshr miss rate for SCUpgradeReq accesses |
| 1166system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1167system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1149system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1168system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses 1169system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses 1170system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses 1171system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses 1172system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses 1173system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses 1174system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses 1175system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses 1176system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses 1177system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses 1178system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses | 1150system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158963 # mshr miss rate for ReadExReq accesses 1151system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158963 # mshr miss rate for ReadExReq accesses 1152system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for demand accesses 1153system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for demand accesses 1154system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for demand accesses 1155system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for demand accesses 1156system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099287 # mshr miss rate for demand accesses 1157system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for overall accesses 1158system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for overall accesses 1159system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for overall accesses 1160system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for overall accesses |
| 1179system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1161system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1180system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses 1181system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency 1182system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency 1183system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency 1184system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency 1185system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency 1186system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency 1187system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency 1188system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency 1189system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency 1190system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency 1191system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency 1192system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency 1193system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency 1194system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency 1195system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency 1196system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency 1197system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency 1198system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency 1199system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency 1200system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency 1201system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency 1202system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency 1203system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency 1204system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency 1205system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency 1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency | 1162system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses 1163system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency 1164system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency 1165system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency 1166system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency 1167system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency 1168system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency 1169system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency 1170system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency 1171system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency 1172system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency 1173system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency 1174system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency 1175system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency 1176system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency 1177system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency 1178system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency 1179system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency 1180system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency 1181system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency 1182system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency 1183system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency 1184system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency 1185system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency 1186system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency 1187system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency 1188system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency |
| 1207system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1208system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1209system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1210system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1211system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1212system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1213system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1214system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1215system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1189system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1190system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1191system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1192system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1193system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1194system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1195system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1196system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1197system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1216system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution 1217system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution 1218system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution 1219system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution 1220system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution 1221system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution 1222system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1223system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution 1224system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution 1225system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution 1226system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution 1227system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution 1228system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution 1229system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution 1230system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) 1231system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) 1232system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) 1233system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) 1234system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) 1235system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) 1236system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) 1237system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) 1238system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) 1239system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) 1240system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) 1241system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram 1242system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram 1243system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram | 1198system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution 1199system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution 1200system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution 1201system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution 1202system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution 1203system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution 1204system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution 1205system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution 1206system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution 1207system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution 1208system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution 1209system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution 1210system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution 1211system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution 1212system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes) 1213system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes) 1214system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes) 1215system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes) 1216system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes) 1217system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes) 1218system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes) 1219system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes) 1220system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes) 1221system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes) 1222system.cpu0.toL2Bus.snoops 633519 # Total snoops (count) 1223system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram 1224system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram 1225system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram |
| 1244system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1245system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1246system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1247system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1226system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1227system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1228system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1229system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1248system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1249system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1250system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram 1251system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram | 1230system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram 1231system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram |
| 1252system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1232system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1253system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1254system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1255system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram 1256system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) | 1233system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1234system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1235system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram 1236system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks) |
| 1257system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1237system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1258system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) | 1238system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks) |
| 1259system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1239system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1260system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) | 1240system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks) |
| 1261system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1241system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1262system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) | 1242system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks) |
| 1263system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1264system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) 1265system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1243system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1244system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) 1245system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1266system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) | 1246system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks) |
| 1267system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1268system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1274system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 1289system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1290system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1291system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1292system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1293system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1294system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1295system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1296system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1247system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1248system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1249system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1250system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1251system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1252system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1253system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1254system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 1269system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1270system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1271system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1272system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1273system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1274system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1275system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1276system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1297system.cpu1.dtb.walker.walks 3332 # Table walker walks requested 1298system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors 1299system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate 1300system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate 1301system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency 1302system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1303system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency 1304system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency 1305system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency 1306system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency 1307system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency 1308system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency 1309system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency 1310system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency 1311system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency 1312system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency 1313system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency 1314system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1315system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency 1316system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution 1317system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution 1318system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution 1319system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated 1320system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated 1321system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated 1322system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst | 1277system.cpu1.dtb.walker.walks 3283 # Table walker walks requested 1278system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors 1279system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate 1280system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate 1281system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency 1282system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1283system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency 1284system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency 1285system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency 1286system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency 1287system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency 1288system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency 1289system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency 1290system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency 1291system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency 1292system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency 1293system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency 1294system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency 1295system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency 1296system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency 1297system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 1298system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency 1299system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution 1300system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution 1301system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution 1302system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated 1303system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated 1304system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated 1305system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst |
| 1323system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1306system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1324system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst 1325system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst | 1307system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst 1308system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst |
| 1326system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1309system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1327system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst 1328system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst | 1310system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst 1311system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst |
| 1329system.cpu1.dtb.inst_hits 0 # ITB inst hits 1330system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1312system.cpu1.dtb.inst_hits 0 # ITB inst hits 1313system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1331system.cpu1.dtb.read_hits 10115566 # DTB read hits 1332system.cpu1.dtb.read_misses 2828 # DTB read misses 1333system.cpu1.dtb.write_hits 6544640 # DTB write hits 1334system.cpu1.dtb.write_misses 504 # DTB write misses | 1314system.cpu1.dtb.read_hits 3974119 # DTB read hits 1315system.cpu1.dtb.read_misses 2776 # DTB read misses 1316system.cpu1.dtb.write_hits 3444686 # DTB write hits 1317system.cpu1.dtb.write_misses 507 # DTB write misses |
| 1335system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1336system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1337system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1338system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1318system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1319system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1320system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1321system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1339system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB | 1322system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB |
| 1340system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1323system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1341system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch | 1324system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch |
| 1342system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1343system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions | 1325system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1326system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions |
| 1344system.cpu1.dtb.read_accesses 10118394 # DTB read accesses 1345system.cpu1.dtb.write_accesses 6545144 # DTB write accesses | 1327system.cpu1.dtb.read_accesses 3976895 # DTB read accesses 1328system.cpu1.dtb.write_accesses 3445193 # DTB write accesses |
| 1346system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1329system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1347system.cpu1.dtb.hits 16660206 # DTB hits 1348system.cpu1.dtb.misses 3332 # DTB misses 1349system.cpu1.dtb.accesses 16663538 # DTB accesses | 1330system.cpu1.dtb.hits 7418805 # DTB hits 1331system.cpu1.dtb.misses 3283 # DTB misses 1332system.cpu1.dtb.accesses 7422088 # DTB accesses |
| 1350system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1351system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1354system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1355system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1356system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1357system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1371system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1372system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1373system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1374system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1375system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1376system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1377system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1378system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1333system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1334system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1335system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1336system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1337system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1338system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1339system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1340system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1354system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1355system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1356system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1357system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1358system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1359system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1360system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1361system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1379system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1380system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1381system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1382system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1383system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1384system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1385system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1386system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1387system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency 1388system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency 1389system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency 1390system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency 1391system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency 1392system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency 1393system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency 1394system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency 1395system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency 1396system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency 1397system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency 1398system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency 1399system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1400system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution 1401system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution 1402system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution 1403system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1404system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1405system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated | 1362system.cpu1.itb.walker.walks 1740 # Table walker walks requested 1363system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors 1364system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate 1365system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate 1366system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency 1367system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1368system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency 1369system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency 1370system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency 1371system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency 1372system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency 1373system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency 1374system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency 1375system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency 1376system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency 1377system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency 1378system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency 1379system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency 1380system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency 1381system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency 1382system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1383system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency 1384system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution 1385system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution 1386system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution 1387system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated 1388system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated 1389system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated |
| 1406system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1390system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1407system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1408system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst | 1391system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst 1392system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst |
| 1409system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1393system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1410system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1411system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1412system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1413system.cpu1.itb.inst_hits 44359905 # ITB inst hits 1414system.cpu1.itb.inst_misses 1746 # ITB inst misses | 1394system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst 1395system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst 1396system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst 1397system.cpu1.itb.inst_hits 16749094 # ITB inst hits 1398system.cpu1.itb.inst_misses 1740 # ITB inst misses |
| 1415system.cpu1.itb.read_hits 0 # DTB read hits 1416system.cpu1.itb.read_misses 0 # DTB read misses 1417system.cpu1.itb.write_hits 0 # DTB write hits 1418system.cpu1.itb.write_misses 0 # DTB write misses 1419system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1420system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1421system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1422system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1399system.cpu1.itb.read_hits 0 # DTB read hits 1400system.cpu1.itb.read_misses 0 # DTB read misses 1401system.cpu1.itb.write_hits 0 # DTB write hits 1402system.cpu1.itb.write_misses 0 # DTB write misses 1403system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1404system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1405system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1406system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1423system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB | 1407system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB |
| 1424system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1425system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1426system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1427system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1428system.cpu1.itb.read_accesses 0 # DTB read accesses 1429system.cpu1.itb.write_accesses 0 # DTB write accesses | 1408system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1409system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1410system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1411system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1412system.cpu1.itb.read_accesses 0 # DTB read accesses 1413system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1430system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses 1431system.cpu1.itb.hits 44359905 # DTB hits 1432system.cpu1.itb.misses 1746 # DTB misses 1433system.cpu1.itb.accesses 44361651 # DTB accesses 1434system.cpu1.numCycles 5735725430 # number of cpu cycles simulated | 1414system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses 1415system.cpu1.itb.hits 16749094 # DTB hits 1416system.cpu1.itb.misses 1740 # DTB misses 1417system.cpu1.itb.accesses 16750834 # DTB accesses 1418system.cpu1.numCycles 5736248293 # number of cpu cycles simulated |
| 1435system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1436system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1419system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1420system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1437system.cpu1.committedInsts 42482884 # Number of instructions committed 1438system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed 1439system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses | 1421system.cpu1.committedInsts 16392660 # Number of instructions committed 1422system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed 1423system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses |
| 1440system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses | 1424system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses |
| 1441system.cpu1.num_func_calls 7121857 # number of times a function call or return occured 1442system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls 1443system.cpu1.num_int_insts 47161467 # number of integer instructions | 1425system.cpu1.num_func_calls 1033061 # number of times a function call or return occured 1426system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls 1427system.cpu1.num_int_insts 17976734 # number of integer instructions |
| 1444system.cpu1.num_fp_insts 1857 # number of float instructions | 1428system.cpu1.num_fp_insts 1857 # number of float instructions |
| 1445system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read 1446system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written | 1429system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read 1430system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written |
| 1447system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1448system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written | 1431system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1432system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written |
| 1449system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read 1450system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written 1451system.cpu1.num_mem_refs 16924073 # number of memory refs 1452system.cpu1.num_load_insts 10229886 # Number of load instructions 1453system.cpu1.num_store_insts 6694187 # Number of store instructions 1454system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles 1455system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles 1456system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles 1457system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles 1458system.cpu1.Branches 12116511 # Number of branches fetched | 1433system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read 1434system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written 1435system.cpu1.num_mem_refs 7653523 # number of memory refs 1436system.cpu1.num_load_insts 4085696 # Number of load instructions 1437system.cpu1.num_store_insts 3567827 # Number of store instructions 1438system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles 1439system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles 1440system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles 1441system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles 1442system.cpu1.Branches 2968133 # Number of branches fetched |
| 1459system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction | 1443system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction |
| 1460system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction 1461system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction 1462system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction 1463system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction 1464system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction 1465system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction 1466system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction 1467system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction 1468system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction 1469system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction 1470system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction 1471system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction 1472system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction 1473system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction 1474system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction 1475system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction 1476system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction 1477system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction 1478system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction 1479system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction 1480system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction 1481system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction 1482system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction 1483system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction 1484system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction 1485system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction 1486system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction 1487system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction 1488system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction 1489system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction 1490system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction | 1444system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction 1445system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction 1446system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction 1447system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction 1448system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction 1449system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction 1450system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction 1451system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction 1452system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction 1453system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction 1454system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction 1455system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction 1456system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction 1457system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction 1458system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction 1459system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction 1460system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction 1461system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction 1462system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction 1463system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction 1464system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction 1465system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction 1466system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction 1467system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction 1468system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction 1469system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction 1470system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction 1471system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction 1472system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction 1473system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction 1474system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction |
| 1491system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1492system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1475system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1476system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1493system.cpu1.op_class::total 54073981 # Class of executed instruction | 1477system.cpu1.op_class::total 20309210 # Class of executed instruction |
| 1494system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1478system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1495system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed 1496system.cpu1.dcache.tags.replacements 191058 # number of replacements 1497system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use 1498system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. 1499system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. 1500system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. 1501system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. 1502system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor 1503system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy 1504system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy 1505system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id 1506system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id 1507system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id 1508system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id 1509system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses 1510system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses 1511system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits 1512system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits 1513system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits 1514system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits 1515system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits 1516system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits 1517system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits 1518system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits 1519system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits 1520system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits 1521system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits 1522system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits 1523system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits 1524system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits 1525system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses 1526system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses 1527system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses 1528system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses 1529system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses 1530system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses 1531system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses 1532system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses 1533system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses 1534system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses 1535system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses 1536system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses 1537system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses 1538system.cpu1.dcache.overall_misses::total 260939 # number of overall misses 1539system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles 1540system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles 1541system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles 1542system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles 1543system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles 1544system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles 1545system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles 1546system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles 1547system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles 1548system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles 1549system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles 1550system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles 1551system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles 1552system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles 1553system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) 1554system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) 1555system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) 1556system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) 1557system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) 1558system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) 1559system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) 1560system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) 1561system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) 1562system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) 1563system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses 1564system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses 1565system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses 1566system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses 1567system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses 1568system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses 1569system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses 1570system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses 1571system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses 1572system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses 1573system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses 1574system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses 1575system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses 1576system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses 1577system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses 1578system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses 1579system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses 1580system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses 1581system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency 1582system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency 1583system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency 1584system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency 1585system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency 1586system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency 1587system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency 1588system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency | 1479system.cpu1.kern.inst.quiesce 2726 # number of quiesce instructions executed 1480system.cpu1.dcache.tags.replacements 187627 # number of replacements 1481system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use 1482system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks. 1483system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks. 1484system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks. 1485system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit. 1486system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor 1487system.cpu1.dcache.tags.occ_percent::cpu1.data 0.908623 # Average percentage of cache occupancy 1488system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy 1489system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id 1490system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id 1491system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id 1492system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id 1493system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses 1494system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses 1495system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits 1496system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits 1497system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits 1498system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits 1499system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits 1500system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits 1501system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits 1502system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits 1503system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits 1504system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits 1505system.cpu1.dcache.demand_hits::cpu1.data 6915261 # number of demand (read+write) hits 1506system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits 1507system.cpu1.dcache.overall_hits::cpu1.data 6964975 # number of overall hits 1508system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits 1509system.cpu1.dcache.ReadReq_misses::cpu1.data 134401 # number of ReadReq misses 1510system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses 1511system.cpu1.dcache.WriteReq_misses::cpu1.data 90853 # number of WriteReq misses 1512system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses 1513system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses 1514system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses 1515system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses 1516system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses 1517system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses 1518system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses 1519system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses 1520system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses 1521system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses 1522system.cpu1.dcache.overall_misses::total 255750 # number of overall misses 1523system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles 1524system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles 1525system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles 1526system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles 1527system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles 1528system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles 1529system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 552026738 # number of StoreCondReq miss cycles 1530system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles 1531system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles 1532system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles 1533system.cpu1.dcache.demand_miss_latency::cpu1.data 4185537359 # number of demand (read+write) miss cycles 1534system.cpu1.dcache.demand_miss_latency::total 4185537359 # number of demand (read+write) miss cycles 1535system.cpu1.dcache.overall_miss_latency::cpu1.data 4185537359 # number of overall miss cycles 1536system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles 1537system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses) 1538system.cpu1.dcache.ReadReq_accesses::total 3793741 # number of ReadReq accesses(hits+misses) 1539system.cpu1.dcache.WriteReq_accesses::cpu1.data 3346774 # number of WriteReq accesses(hits+misses) 1540system.cpu1.dcache.WriteReq_accesses::total 3346774 # number of WriteReq accesses(hits+misses) 1541system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80210 # number of SoftPFReq accesses(hits+misses) 1542system.cpu1.dcache.SoftPFReq_accesses::total 80210 # number of SoftPFReq accesses(hits+misses) 1543system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97108 # number of LoadLockedReq accesses(hits+misses) 1544system.cpu1.dcache.LoadLockedReq_accesses::total 97108 # number of LoadLockedReq accesses(hits+misses) 1545system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95278 # number of StoreCondReq accesses(hits+misses) 1546system.cpu1.dcache.StoreCondReq_accesses::total 95278 # number of StoreCondReq accesses(hits+misses) 1547system.cpu1.dcache.demand_accesses::cpu1.data 7140515 # number of demand (read+write) accesses 1548system.cpu1.dcache.demand_accesses::total 7140515 # number of demand (read+write) accesses 1549system.cpu1.dcache.overall_accesses::cpu1.data 7220725 # number of overall (read+write) accesses 1550system.cpu1.dcache.overall_accesses::total 7220725 # number of overall (read+write) accesses 1551system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035427 # miss rate for ReadReq accesses 1552system.cpu1.dcache.ReadReq_miss_rate::total 0.035427 # miss rate for ReadReq accesses 1553system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027146 # miss rate for WriteReq accesses 1554system.cpu1.dcache.WriteReq_miss_rate::total 0.027146 # miss rate for WriteReq accesses 1555system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380202 # miss rate for SoftPFReq accesses 1556system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380202 # miss rate for SoftPFReq accesses 1557system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178420 # miss rate for LoadLockedReq accesses 1558system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses 1559system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246290 # miss rate for StoreCondReq accesses 1560system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246290 # miss rate for StoreCondReq accesses 1561system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031546 # miss rate for demand accesses 1562system.cpu1.dcache.demand_miss_rate::total 0.031546 # miss rate for demand accesses 1563system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035419 # miss rate for overall accesses 1564system.cpu1.dcache.overall_miss_rate::total 0.035419 # miss rate for overall accesses 1565system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14374.312691 # average ReadReq miss latency 1566system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency 1567system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24805.073679 # average WriteReq miss latency 1568system.cpu1.dcache.WriteReq_avg_miss_latency::total 24805.073679 # average WriteReq miss latency 1569system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18352.346185 # average LoadLockedReq miss latency 1570system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18352.346185 # average LoadLockedReq miss latency 1571system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23524.534987 # average StoreCondReq miss latency 1572system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency |
| 1589system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1590system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1573system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1574system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1591system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency 1592system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency 1593system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency 1594system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency | 1575system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency 1576system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency 1577system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency 1578system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency |
| 1595system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1596system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1597system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1598system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1599system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1600system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1601system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1602system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1579system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1580system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1581system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1582system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1583system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1584system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1585system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1586system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1603system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks 1604system.cpu1.dcache.writebacks::total 118649 # number of writebacks 1605system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits 1606system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits 1607system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits 1608system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits 1609system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits 1610system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits 1611system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits 1612system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits 1613system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses 1614system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses 1615system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses 1616system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses 1617system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses 1618system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses 1619system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses 1620system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses 1621system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses 1622system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses 1623system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses 1624system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses 1625system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses 1626system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses 1627system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles 1628system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles 1629system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles 1630system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles 1631system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles 1632system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles 1633system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles 1634system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles 1635system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles 1636system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles 1637system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles 1638system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles 1639system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles 1640system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles 1641system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles 1642system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles 1643system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles 1644system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles 1645system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles 1646system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles 1647system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles 1648system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles 1649system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses 1650system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses 1651system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses 1652system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses 1653system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses 1654system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses 1655system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses 1656system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses 1657system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses 1658system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses 1659system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses 1660system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses 1661system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses 1662system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses 1663system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency 1664system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency 1665system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency 1666system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency 1667system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency 1668system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency 1669system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency 1670system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency 1671system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency 1672system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency | 1587system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks 1588system.cpu1.dcache.writebacks::total 117066 # number of writebacks 1589system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits 1590system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits 1591system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits 1592system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits 1593system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits 1594system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits 1595system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits 1596system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits 1597system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses 1598system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses 1599system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses 1600system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses 1601system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses 1602system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses 1603system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses 1604system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses 1605system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses 1606system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses 1607system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses 1608system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses 1609system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses 1610system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses 1611system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles 1612system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles 1613system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles 1614system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles 1615system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles 1616system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles 1617system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles 1618system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles 1619system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles 1620system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles 1621system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles 1622system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles 1623system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles 1624system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles 1625system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles 1626system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles 1627system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles 1628system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles 1629system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles 1630system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles 1631system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles 1632system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles 1633system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses 1634system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses 1635system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses 1636system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses 1637system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses 1638system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses 1639system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses 1640system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses 1641system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses 1642system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses 1643system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses 1644system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses 1645system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses 1646system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses 1647system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency 1648system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency 1649system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency 1650system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency 1651system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency 1652system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency 1653system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency 1654system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency 1655system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency 1656system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency |
| 1673system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1674system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1657system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1658system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1675system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency 1676system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency 1677system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency 1678system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency | 1659system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency 1660system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency 1661system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency 1662system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency |
| 1679system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1680system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1681system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1682system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1683system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1684system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1685system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1663system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1664system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1665system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1666system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1667system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1668system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1669system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1686system.cpu1.icache.tags.replacements 526723 # number of replacements 1687system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use 1688system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. 1689system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. 1690system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. 1691system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. 1692system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor 1693system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy 1694system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy | 1670system.cpu1.icache.tags.replacements 506368 # number of replacements 1671system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use 1672system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks. 1673system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks. 1674system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks. 1675system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit. 1676system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor 1677system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy 1678system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy |
| 1695system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1679system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1696system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 1697system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id | 1680system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1681system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id |
| 1698system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1699system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1682system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1683system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1700system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses 1701system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses 1702system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits 1703system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits 1704system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits 1705system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits 1706system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits 1707system.cpu1.icache.overall_hits::total 43832665 # number of overall hits 1708system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses 1709system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses 1710system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses 1711system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses 1712system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses 1713system.cpu1.icache.overall_misses::total 527235 # number of overall misses 1714system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles 1715system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles 1716system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles 1717system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles 1718system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles 1719system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles 1720system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) 1721system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) 1722system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses 1723system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses 1724system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses 1725system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses 1726system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses 1727system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses 1728system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses 1729system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses 1730system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses 1731system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses 1732system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency 1733system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency 1734system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency 1735system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency 1736system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency 1737system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency | 1684system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses 1685system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses 1686system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits 1687system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits 1688system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits 1689system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits 1690system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits 1691system.cpu1.icache.overall_hits::total 16242209 # number of overall hits 1692system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses 1693system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses 1694system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses 1695system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses 1696system.cpu1.icache.overall_misses::cpu1.inst 506880 # number of overall misses 1697system.cpu1.icache.overall_misses::total 506880 # number of overall misses 1698system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4441098014 # number of ReadReq miss cycles 1699system.cpu1.icache.ReadReq_miss_latency::total 4441098014 # number of ReadReq miss cycles 1700system.cpu1.icache.demand_miss_latency::cpu1.inst 4441098014 # number of demand (read+write) miss cycles 1701system.cpu1.icache.demand_miss_latency::total 4441098014 # number of demand (read+write) miss cycles 1702system.cpu1.icache.overall_miss_latency::cpu1.inst 4441098014 # number of overall miss cycles 1703system.cpu1.icache.overall_miss_latency::total 4441098014 # number of overall miss cycles 1704system.cpu1.icache.ReadReq_accesses::cpu1.inst 16749089 # number of ReadReq accesses(hits+misses) 1705system.cpu1.icache.ReadReq_accesses::total 16749089 # number of ReadReq accesses(hits+misses) 1706system.cpu1.icache.demand_accesses::cpu1.inst 16749089 # number of demand (read+write) accesses 1707system.cpu1.icache.demand_accesses::total 16749089 # number of demand (read+write) accesses 1708system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses 1709system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses 1710system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses 1711system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses 1712system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses 1713system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses 1714system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses 1715system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses 1716system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency 1717system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency 1718system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency 1719system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency 1720system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency 1721system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency |
| 1738system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1739system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1740system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1741system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1742system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1743system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1744system.cpu1.icache.fast_writes 0 # number of fast writes performed 1745system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1722system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1723system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1724system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1725system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1726system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1727system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1728system.cpu1.icache.fast_writes 0 # number of fast writes performed 1729system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1746system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses 1747system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses 1748system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses 1749system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses 1750system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses 1751system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses 1752system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles 1753system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles 1754system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles 1755system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles 1756system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles 1757system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles 1758system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles 1759system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles 1760system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles 1761system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles 1762system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses 1763system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses 1764system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses 1765system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses 1766system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses 1767system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses 1768system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency 1769system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency 1770system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency 1771system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency 1772system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency 1773system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency | 1730system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506880 # number of ReadReq MSHR misses 1731system.cpu1.icache.ReadReq_mshr_misses::total 506880 # number of ReadReq MSHR misses 1732system.cpu1.icache.demand_mshr_misses::cpu1.inst 506880 # number of demand (read+write) MSHR misses 1733system.cpu1.icache.demand_mshr_misses::total 506880 # number of demand (read+write) MSHR misses 1734system.cpu1.icache.overall_mshr_misses::cpu1.inst 506880 # number of overall MSHR misses 1735system.cpu1.icache.overall_mshr_misses::total 506880 # number of overall MSHR misses 1736system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933409986 # number of ReadReq MSHR miss cycles 1737system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933409986 # number of ReadReq MSHR miss cycles 1738system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933409986 # number of demand (read+write) MSHR miss cycles 1739system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles 1740system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933409986 # number of overall MSHR miss cycles 1741system.cpu1.icache.overall_mshr_miss_latency::total 3933409986 # number of overall MSHR miss cycles 1742system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15446750 # number of ReadReq MSHR uncacheable cycles 1743system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles 1744system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles 1745system.cpu1.icache.overall_mshr_uncacheable_latency::total 15446750 # number of overall MSHR uncacheable cycles 1746system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for ReadReq accesses 1747system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030263 # mshr miss rate for ReadReq accesses 1748system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for demand accesses 1749system.cpu1.icache.demand_mshr_miss_rate::total 0.030263 # mshr miss rate for demand accesses 1750system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for overall accesses 1751system.cpu1.icache.overall_mshr_miss_rate::total 0.030263 # mshr miss rate for overall accesses 1752system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average ReadReq mshr miss latency 1753system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7760.041797 # average ReadReq mshr miss latency 1754system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency 1755system.cpu1.icache.demand_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency 1756system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency 1757system.cpu1.icache.overall_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency |
| 1774system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1775system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1776system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1777system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1778system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1758system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1759system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1760system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1761system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1762system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1779system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued 1780system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified 1781system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue | 1763system.cpu1.l2cache.prefetcher.num_hwpf_issued 194594 # number of hwpf issued 1764system.cpu1.l2cache.prefetcher.pfIdentified 194618 # number of prefetch candidates identified 1765system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue |
| 1782system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1783system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1766system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1767system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1784system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing 1785system.cpu1.l2cache.tags.replacements 47689 # number of replacements 1786system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use 1787system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. 1788system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. 1789system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. | 1768system.cpu1.l2cache.prefetcher.pfSpanPage 58318 # number of prefetches not generated due to page crossing 1769system.cpu1.l2cache.tags.replacements 39568 # number of replacements 1770system.cpu1.l2cache.tags.tagsinuse 14853.795199 # Cycle average of tags in use 1771system.cpu1.l2cache.tags.total_refs 710508 # Total number of references to valid blocks. 1772system.cpu1.l2cache.tags.sampled_refs 54174 # Sample count of references to valid blocks. 1773system.cpu1.l2cache.tags.avg_refs 13.115295 # Average number of references to valid blocks. |
| 1790system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1774system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1791system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor 1792system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor 1793system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor 1794system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor 1795system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor 1796system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor 1797system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy 1798system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 1799system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy 1800system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy 1801system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy 1802system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy 1803system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy 1804system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id 1805system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id 1806system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id 1807system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id 1808system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id | 1775system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.748297 # Average occupied blocks per requestor 1776system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.024093 # Average occupied blocks per requestor 1777system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.068283 # Average occupied blocks per requestor 1778system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor 1779system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor 1780system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 684.742061 # Average occupied blocks per requestor 1781system.cpu1.l2cache.tags.occ_percent::writebacks 0.546005 # Average percentage of cache occupancy 1782system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000246 # Average percentage of cache occupancy 1783system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy 1784system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201419 # Average percentage of cache occupancy 1785system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.117015 # Average percentage of cache occupancy 1786system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041793 # Average percentage of cache occupancy 1787system.cpu1.l2cache.tags.occ_percent::total 0.906604 # Average percentage of cache occupancy 1788system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id 1789system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1790system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13469 # Occupied blocks per task id 1791system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id 1792system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id 1793system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1075 # Occupied blocks per task id |
| 1809system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id | 1794system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id |
| 1810system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 1811system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id 1812system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id 1813system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id 1814system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id 1815system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id 1816system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id 1817system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses 1818system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses 1819system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits 1820system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits 1821system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits 1822system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits 1823system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits 1824system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits 1825system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits 1826system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits 1827system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits 1828system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits 1829system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # number of SCUpgradeReq hits 1830system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28139 # number of ReadExReq hits 1831system.cpu1.l2cache.ReadExReq_hits::total 28139 # number of ReadExReq hits 1832system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits 1833system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1729 # number of demand (read+write) hits 1834system.cpu1.l2cache.demand_hits::cpu1.inst 513133 # number of demand (read+write) hits 1835system.cpu1.l2cache.demand_hits::cpu1.data 130859 # number of demand (read+write) hits 1836system.cpu1.l2cache.demand_hits::total 648812 # number of demand (read+write) hits 1837system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits 1838system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1729 # number of overall hits 1839system.cpu1.l2cache.overall_hits::cpu1.inst 513133 # number of overall hits 1840system.cpu1.l2cache.overall_hits::cpu1.data 130859 # number of overall hits 1841system.cpu1.l2cache.overall_hits::total 648812 # number of overall hits 1842system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses 1843system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses 1844system.cpu1.l2cache.ReadReq_misses::cpu1.inst 14102 # number of ReadReq misses 1845system.cpu1.l2cache.ReadReq_misses::cpu1.data 69212 # number of ReadReq misses 1846system.cpu1.l2cache.ReadReq_misses::total 83911 # number of ReadReq misses 1847system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28339 # number of UpgradeReq misses 1848system.cpu1.l2cache.UpgradeReq_misses::total 28339 # number of UpgradeReq misses 1849system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22509 # number of SCUpgradeReq misses 1850system.cpu1.l2cache.SCUpgradeReq_misses::total 22509 # number of SCUpgradeReq misses 1851system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 1852system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1853system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35184 # number of ReadExReq misses 1854system.cpu1.l2cache.ReadExReq_misses::total 35184 # number of ReadExReq misses 1855system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses 1856system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses 1857system.cpu1.l2cache.demand_misses::cpu1.inst 14102 # number of demand (read+write) misses 1858system.cpu1.l2cache.demand_misses::cpu1.data 104396 # number of demand (read+write) misses 1859system.cpu1.l2cache.demand_misses::total 119095 # number of demand (read+write) misses 1860system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses 1861system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses 1862system.cpu1.l2cache.overall_misses::cpu1.inst 14102 # number of overall misses 1863system.cpu1.l2cache.overall_misses::cpu1.data 104396 # number of overall misses 1864system.cpu1.l2cache.overall_misses::total 119095 # number of overall misses 1865system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6369000 # number of ReadReq miss cycles 1866system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5421000 # number of ReadReq miss cycles 1867system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 483830740 # number of ReadReq miss cycles 1868system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1476489366 # number of ReadReq miss cycles 1869system.cpu1.l2cache.ReadReq_miss_latency::total 1972110106 # number of ReadReq miss cycles 1870system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 522569379 # number of UpgradeReq miss cycles 1871system.cpu1.l2cache.UpgradeReq_miss_latency::total 522569379 # number of UpgradeReq miss cycles 1872system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 435248439 # number of SCUpgradeReq miss cycles 1873system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 435248439 # number of SCUpgradeReq miss cycles 1874system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1586000 # number of SCUpgradeFailReq miss cycles 1875system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1586000 # number of SCUpgradeFailReq miss cycles 1876system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1289152696 # number of ReadExReq miss cycles 1877system.cpu1.l2cache.ReadExReq_miss_latency::total 1289152696 # number of ReadExReq miss cycles 1878system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6369000 # number of demand (read+write) miss cycles 1879system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5421000 # number of demand (read+write) miss cycles 1880system.cpu1.l2cache.demand_miss_latency::cpu1.inst 483830740 # number of demand (read+write) miss cycles 1881system.cpu1.l2cache.demand_miss_latency::cpu1.data 2765642062 # number of demand (read+write) miss cycles 1882system.cpu1.l2cache.demand_miss_latency::total 3261262802 # number of demand (read+write) miss cycles 1883system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6369000 # number of overall miss cycles 1884system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5421000 # number of overall miss cycles 1885system.cpu1.l2cache.overall_miss_latency::cpu1.inst 483830740 # number of overall miss cycles 1886system.cpu1.l2cache.overall_miss_latency::cpu1.data 2765642062 # number of overall miss cycles 1887system.cpu1.l2cache.overall_miss_latency::total 3261262802 # number of overall miss cycles 1888system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3412 # number of ReadReq accesses(hits+misses) 1889system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2005 # number of ReadReq accesses(hits+misses) 1890system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 527235 # number of ReadReq accesses(hits+misses) 1891system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171932 # number of ReadReq accesses(hits+misses) 1892system.cpu1.l2cache.ReadReq_accesses::total 704584 # number of ReadReq accesses(hits+misses) 1893system.cpu1.l2cache.Writeback_accesses::writebacks 118649 # number of Writeback accesses(hits+misses) 1894system.cpu1.l2cache.Writeback_accesses::total 118649 # number of Writeback accesses(hits+misses) 1895system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29824 # number of UpgradeReq accesses(hits+misses) 1896system.cpu1.l2cache.UpgradeReq_accesses::total 29824 # number of UpgradeReq accesses(hits+misses) 1897system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23376 # number of SCUpgradeReq accesses(hits+misses) 1898system.cpu1.l2cache.SCUpgradeReq_accesses::total 23376 # number of SCUpgradeReq accesses(hits+misses) 1899system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1900system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1901system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63323 # number of ReadExReq accesses(hits+misses) 1902system.cpu1.l2cache.ReadExReq_accesses::total 63323 # number of ReadExReq accesses(hits+misses) 1903system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3412 # number of demand (read+write) accesses 1904system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2005 # number of demand (read+write) accesses 1905system.cpu1.l2cache.demand_accesses::cpu1.inst 527235 # number of demand (read+write) accesses 1906system.cpu1.l2cache.demand_accesses::cpu1.data 235255 # number of demand (read+write) accesses 1907system.cpu1.l2cache.demand_accesses::total 767907 # number of demand (read+write) accesses 1908system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3412 # number of overall (read+write) accesses 1909system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2005 # number of overall (read+write) accesses 1910system.cpu1.l2cache.overall_accesses::cpu1.inst 527235 # number of overall (read+write) accesses 1911system.cpu1.l2cache.overall_accesses::cpu1.data 235255 # number of overall (read+write) accesses 1912system.cpu1.l2cache.overall_accesses::total 767907 # number of overall (read+write) accesses 1913system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for ReadReq accesses 1914system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137656 # miss rate for ReadReq accesses 1915system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026747 # miss rate for ReadReq accesses 1916system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402554 # miss rate for ReadReq accesses 1917system.cpu1.l2cache.ReadReq_miss_rate::total 0.119093 # miss rate for ReadReq accesses 1918system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950208 # miss rate for UpgradeReq accesses 1919system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950208 # miss rate for UpgradeReq accesses 1920system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962911 # miss rate for SCUpgradeReq accesses 1921system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962911 # miss rate for SCUpgradeReq accesses | 1795system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1796system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 1797system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1497 # Occupied blocks per task id 1798system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11681 # Occupied blocks per task id 1799system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068542 # Percentage of cache occupancy per task id 1800system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1801system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.822083 # Percentage of cache occupancy per task id 1802system.cpu1.l2cache.tags.tag_accesses 14802624 # Number of tag accesses 1803system.cpu1.l2cache.tags.data_accesses 14802624 # Number of data accesses 1804system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2949 # number of ReadReq hits 1805system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1668 # number of ReadReq hits 1806system.cpu1.l2cache.ReadReq_hits::cpu1.inst 493694 # number of ReadReq hits 1807system.cpu1.l2cache.ReadReq_hits::cpu1.data 102403 # number of ReadReq hits 1808system.cpu1.l2cache.ReadReq_hits::total 600714 # number of ReadReq hits 1809system.cpu1.l2cache.Writeback_hits::writebacks 117066 # number of Writeback hits 1810system.cpu1.l2cache.Writeback_hits::total 117066 # number of Writeback hits 1811system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1062 # number of UpgradeReq hits 1812system.cpu1.l2cache.UpgradeReq_hits::total 1062 # number of UpgradeReq hits 1813system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 911 # number of SCUpgradeReq hits 1814system.cpu1.l2cache.SCUpgradeReq_hits::total 911 # number of SCUpgradeReq hits 1815system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27911 # number of ReadExReq hits 1816system.cpu1.l2cache.ReadExReq_hits::total 27911 # number of ReadExReq hits 1817system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2949 # number of demand (read+write) hits 1818system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1668 # number of demand (read+write) hits 1819system.cpu1.l2cache.demand_hits::cpu1.inst 493694 # number of demand (read+write) hits 1820system.cpu1.l2cache.demand_hits::cpu1.data 130314 # number of demand (read+write) hits 1821system.cpu1.l2cache.demand_hits::total 628625 # number of demand (read+write) hits 1822system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2949 # number of overall hits 1823system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1668 # number of overall hits 1824system.cpu1.l2cache.overall_hits::cpu1.inst 493694 # number of overall hits 1825system.cpu1.l2cache.overall_hits::cpu1.data 130314 # number of overall hits 1826system.cpu1.l2cache.overall_hits::total 628625 # number of overall hits 1827system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 319 # number of ReadReq misses 1828system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses 1829system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13186 # number of ReadReq misses 1830system.cpu1.l2cache.ReadReq_misses::cpu1.data 66797 # number of ReadReq misses 1831system.cpu1.l2cache.ReadReq_misses::total 80569 # number of ReadReq misses 1832system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27938 # number of UpgradeReq misses 1833system.cpu1.l2cache.UpgradeReq_misses::total 27938 # number of UpgradeReq misses 1834system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22546 # number of SCUpgradeReq misses 1835system.cpu1.l2cache.SCUpgradeReq_misses::total 22546 # number of SCUpgradeReq misses 1836system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 1837system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 1838system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33942 # number of ReadExReq misses 1839system.cpu1.l2cache.ReadExReq_misses::total 33942 # number of ReadExReq misses 1840system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 319 # number of demand (read+write) misses 1841system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses 1842system.cpu1.l2cache.demand_misses::cpu1.inst 13186 # number of demand (read+write) misses 1843system.cpu1.l2cache.demand_misses::cpu1.data 100739 # number of demand (read+write) misses 1844system.cpu1.l2cache.demand_misses::total 114511 # number of demand (read+write) misses 1845system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 319 # number of overall misses 1846system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses 1847system.cpu1.l2cache.overall_misses::cpu1.inst 13186 # number of overall misses 1848system.cpu1.l2cache.overall_misses::cpu1.data 100739 # number of overall misses 1849system.cpu1.l2cache.overall_misses::total 114511 # number of overall misses 1850system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6370500 # number of ReadReq miss cycles 1851system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5365500 # number of ReadReq miss cycles 1852system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 469517986 # number of ReadReq miss cycles 1853system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1430715000 # number of ReadReq miss cycles 1854system.cpu1.l2cache.ReadReq_miss_latency::total 1911968986 # number of ReadReq miss cycles 1855system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536455892 # number of UpgradeReq miss cycles 1856system.cpu1.l2cache.UpgradeReq_miss_latency::total 536455892 # number of UpgradeReq miss cycles 1857system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 454234073 # number of SCUpgradeReq miss cycles 1858system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 454234073 # number of SCUpgradeReq miss cycles 1859system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2847500 # number of SCUpgradeFailReq miss cycles 1860system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2847500 # number of SCUpgradeFailReq miss cycles 1861system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1211409437 # number of ReadExReq miss cycles 1862system.cpu1.l2cache.ReadExReq_miss_latency::total 1211409437 # number of ReadExReq miss cycles 1863system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6370500 # number of demand (read+write) miss cycles 1864system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5365500 # number of demand (read+write) miss cycles 1865system.cpu1.l2cache.demand_miss_latency::cpu1.inst 469517986 # number of demand (read+write) miss cycles 1866system.cpu1.l2cache.demand_miss_latency::cpu1.data 2642124437 # number of demand (read+write) miss cycles 1867system.cpu1.l2cache.demand_miss_latency::total 3123378423 # number of demand (read+write) miss cycles 1868system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6370500 # number of overall miss cycles 1869system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5365500 # number of overall miss cycles 1870system.cpu1.l2cache.overall_miss_latency::cpu1.inst 469517986 # number of overall miss cycles 1871system.cpu1.l2cache.overall_miss_latency::cpu1.data 2642124437 # number of overall miss cycles 1872system.cpu1.l2cache.overall_miss_latency::total 3123378423 # number of overall miss cycles 1873system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3268 # number of ReadReq accesses(hits+misses) 1874system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1935 # number of ReadReq accesses(hits+misses) 1875system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 506880 # number of ReadReq accesses(hits+misses) 1876system.cpu1.l2cache.ReadReq_accesses::cpu1.data 169200 # number of ReadReq accesses(hits+misses) 1877system.cpu1.l2cache.ReadReq_accesses::total 681283 # number of ReadReq accesses(hits+misses) 1878system.cpu1.l2cache.Writeback_accesses::writebacks 117066 # number of Writeback accesses(hits+misses) 1879system.cpu1.l2cache.Writeback_accesses::total 117066 # number of Writeback accesses(hits+misses) 1880system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29000 # number of UpgradeReq accesses(hits+misses) 1881system.cpu1.l2cache.UpgradeReq_accesses::total 29000 # number of UpgradeReq accesses(hits+misses) 1882system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23457 # number of SCUpgradeReq accesses(hits+misses) 1883system.cpu1.l2cache.SCUpgradeReq_accesses::total 23457 # number of SCUpgradeReq accesses(hits+misses) 1884system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 1885system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 1886system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61853 # number of ReadExReq accesses(hits+misses) 1887system.cpu1.l2cache.ReadExReq_accesses::total 61853 # number of ReadExReq accesses(hits+misses) 1888system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3268 # number of demand (read+write) accesses 1889system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1935 # number of demand (read+write) accesses 1890system.cpu1.l2cache.demand_accesses::cpu1.inst 506880 # number of demand (read+write) accesses 1891system.cpu1.l2cache.demand_accesses::cpu1.data 231053 # number of demand (read+write) accesses 1892system.cpu1.l2cache.demand_accesses::total 743136 # number of demand (read+write) accesses 1893system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3268 # number of overall (read+write) accesses 1894system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1935 # number of overall (read+write) accesses 1895system.cpu1.l2cache.overall_accesses::cpu1.inst 506880 # number of overall (read+write) accesses 1896system.cpu1.l2cache.overall_accesses::cpu1.data 231053 # number of overall (read+write) accesses 1897system.cpu1.l2cache.overall_accesses::total 743136 # number of overall (read+write) accesses 1898system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for ReadReq accesses 1899system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137984 # miss rate for ReadReq accesses 1900system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026014 # miss rate for ReadReq accesses 1901system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.394781 # miss rate for ReadReq accesses 1902system.cpu1.l2cache.ReadReq_miss_rate::total 0.118261 # miss rate for ReadReq accesses 1903system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.963379 # miss rate for UpgradeReq accesses 1904system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.963379 # miss rate for UpgradeReq accesses 1905system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961163 # miss rate for SCUpgradeReq accesses 1906system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961163 # miss rate for SCUpgradeReq accesses |
| 1922system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1923system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1907system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1908system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1924system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555627 # miss rate for ReadExReq accesses 1925system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555627 # miss rate for ReadExReq accesses 1926system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for demand accesses 1927system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137656 # miss rate for demand accesses 1928system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026747 # miss rate for demand accesses 1929system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443757 # miss rate for demand accesses 1930system.cpu1.l2cache.demand_miss_rate::total 0.155090 # miss rate for demand accesses 1931system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for overall accesses 1932system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137656 # miss rate for overall accesses 1933system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026747 # miss rate for overall accesses 1934system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443757 # miss rate for overall accesses 1935system.cpu1.l2cache.overall_miss_rate::total 0.155090 # miss rate for overall accesses 1936system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average ReadReq miss latency 1937system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19641.304348 # average ReadReq miss latency 1938system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34309.370302 # average ReadReq miss latency 1939system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21332.852193 # average ReadReq miss latency 1940system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23502.402617 # average ReadReq miss latency 1941system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18439.937154 # average UpgradeReq miss latency 1942system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18439.937154 # average UpgradeReq miss latency 1943system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19336.640411 # average SCUpgradeReq miss latency 1944system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19336.640411 # average SCUpgradeReq miss latency 1945system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 528666.666667 # average SCUpgradeFailReq miss latency 1946system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528666.666667 # average SCUpgradeFailReq miss latency 1947system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36640.310823 # average ReadExReq miss latency 1948system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36640.310823 # average ReadExReq miss latency 1949system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency 1950system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency 1951system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency 1952system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency 1953system.cpu1.l2cache.demand_avg_miss_latency::total 27383.708821 # average overall miss latency 1954system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency 1955system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency 1956system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency 1957system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency 1958system.cpu1.l2cache.overall_avg_miss_latency::total 27383.708821 # average overall miss latency | 1909system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.548753 # miss rate for ReadExReq accesses 1910system.cpu1.l2cache.ReadExReq_miss_rate::total 0.548753 # miss rate for ReadExReq accesses 1911system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for demand accesses 1912system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137984 # miss rate for demand accesses 1913system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026014 # miss rate for demand accesses 1914system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.436000 # miss rate for demand accesses 1915system.cpu1.l2cache.demand_miss_rate::total 0.154092 # miss rate for demand accesses 1916system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for overall accesses 1917system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137984 # miss rate for overall accesses 1918system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026014 # miss rate for overall accesses 1919system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.436000 # miss rate for overall accesses 1920system.cpu1.l2cache.overall_miss_rate::total 0.154092 # miss rate for overall accesses 1921system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average ReadReq miss latency 1922system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20095.505618 # average ReadReq miss latency 1923system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35607.309722 # average ReadReq miss latency 1924system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21418.851146 # average ReadReq miss latency 1925system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23730.826819 # average ReadReq miss latency 1926system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19201.656955 # average UpgradeReq miss latency 1927system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19201.656955 # average UpgradeReq miss latency 1928system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20146.991617 # average SCUpgradeReq miss latency 1929system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20146.991617 # average SCUpgradeReq miss latency 1930system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 316388.888889 # average SCUpgradeFailReq miss latency 1931system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 316388.888889 # average SCUpgradeFailReq miss latency 1932system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 35690.573243 # average ReadExReq miss latency 1933system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35690.573243 # average ReadExReq miss latency 1934system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency 1935system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency 1936system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency 1937system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency 1938system.cpu1.l2cache.demand_avg_miss_latency::total 27275.793793 # average overall miss latency 1939system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency 1940system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency 1941system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency 1942system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency 1943system.cpu1.l2cache.overall_avg_miss_latency::total 27275.793793 # average overall miss latency |
| 1959system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1960system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1961system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1962system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1963system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1964system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1965system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1966system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1944system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1945system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1946system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1947system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1948system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1949system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1950system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1951system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1967system.cpu1.l2cache.writebacks::writebacks 31472 # number of writebacks 1968system.cpu1.l2cache.writebacks::total 31472 # number of writebacks 1969system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 76 # number of ReadExReq MSHR hits 1970system.cpu1.l2cache.ReadExReq_mshr_hits::total 76 # number of ReadExReq MSHR hits 1971system.cpu1.l2cache.demand_mshr_hits::cpu1.data 76 # number of demand (read+write) MSHR hits 1972system.cpu1.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 1973system.cpu1.l2cache.overall_mshr_hits::cpu1.data 76 # number of overall MSHR hits 1974system.cpu1.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits 1975system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses 1976system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 276 # number of ReadReq MSHR misses 1977system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 14102 # number of ReadReq MSHR misses 1978system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 69212 # number of ReadReq MSHR misses 1979system.cpu1.l2cache.ReadReq_mshr_misses::total 83911 # number of ReadReq MSHR misses 1980system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of HardPFReq MSHR misses 1981system.cpu1.l2cache.HardPFReq_mshr_misses::total 24018 # number of HardPFReq MSHR misses 1982system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28339 # number of UpgradeReq MSHR misses 1983system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28339 # number of UpgradeReq MSHR misses 1984system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22509 # number of SCUpgradeReq MSHR misses 1985system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22509 # number of SCUpgradeReq MSHR misses 1986system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 1987system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1988system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35108 # number of ReadExReq MSHR misses 1989system.cpu1.l2cache.ReadExReq_mshr_misses::total 35108 # number of ReadExReq MSHR misses 1990system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses 1991system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 276 # number of demand (read+write) MSHR misses 1992system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 14102 # number of demand (read+write) MSHR misses 1993system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104320 # number of demand (read+write) MSHR misses 1994system.cpu1.l2cache.demand_mshr_misses::total 119019 # number of demand (read+write) MSHR misses 1995system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses 1996system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 276 # number of overall MSHR misses 1997system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 14102 # number of overall MSHR misses 1998system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104320 # number of overall MSHR misses 1999system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of overall MSHR misses 2000system.cpu1.l2cache.overall_mshr_misses::total 143037 # number of overall MSHR misses 2001system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of ReadReq MSHR miss cycles 2002system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3489000 # number of ReadReq MSHR miss cycles 2003system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 384250260 # number of ReadReq MSHR miss cycles 2004system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 991800372 # number of ReadReq MSHR miss cycles 2005system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1383661632 # number of ReadReq MSHR miss cycles 2006system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of HardPFReq MSHR miss cycles 2007system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 814752860 # number of HardPFReq MSHR miss cycles 2008system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 402368047 # number of UpgradeReq MSHR miss cycles 2009system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 402368047 # number of UpgradeReq MSHR miss cycles 2010system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306023777 # number of SCUpgradeReq MSHR miss cycles 2011system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306023777 # number of SCUpgradeReq MSHR miss cycles 2012system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1341000 # number of SCUpgradeFailReq MSHR miss cycles 2013system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1341000 # number of SCUpgradeFailReq MSHR miss cycles 2014system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031661014 # number of ReadExReq MSHR miss cycles 2015system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031661014 # number of ReadExReq MSHR miss cycles 2016system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of demand (read+write) MSHR miss cycles 2017system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3489000 # number of demand (read+write) MSHR miss cycles 2018system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 384250260 # number of demand (read+write) MSHR miss cycles 2019system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2023461386 # number of demand (read+write) MSHR miss cycles 2020system.cpu1.l2cache.demand_mshr_miss_latency::total 2415322646 # number of demand (read+write) MSHR miss cycles 2021system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of overall MSHR miss cycles 2022system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3489000 # number of overall MSHR miss cycles 2023system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles 2024system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles 2025system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles 2026system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles 2027system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles 2028system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles 2029system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles 2030system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles 2031system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles 2032system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles 2033system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles 2034system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles 2035system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses 2036system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses 2037system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses 2038system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses 2039system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses | 1952system.cpu1.l2cache.writebacks::writebacks 25242 # number of writebacks 1953system.cpu1.l2cache.writebacks::total 25242 # number of writebacks 1954system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 89 # number of ReadExReq MSHR hits 1955system.cpu1.l2cache.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits 1956system.cpu1.l2cache.demand_mshr_hits::cpu1.data 89 # number of demand (read+write) MSHR hits 1957system.cpu1.l2cache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits 1958system.cpu1.l2cache.overall_mshr_hits::cpu1.data 89 # number of overall MSHR hits 1959system.cpu1.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits 1960system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 319 # number of ReadReq MSHR misses 1961system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses 1962system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 13186 # number of ReadReq MSHR misses 1963system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66797 # number of ReadReq MSHR misses 1964system.cpu1.l2cache.ReadReq_mshr_misses::total 80569 # number of ReadReq MSHR misses 1965system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of HardPFReq MSHR misses 1966system.cpu1.l2cache.HardPFReq_mshr_misses::total 22684 # number of HardPFReq MSHR misses 1967system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27938 # number of UpgradeReq MSHR misses 1968system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27938 # number of UpgradeReq MSHR misses 1969system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22546 # number of SCUpgradeReq MSHR misses 1970system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22546 # number of SCUpgradeReq MSHR misses 1971system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 1972system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 1973system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33853 # number of ReadExReq MSHR misses 1974system.cpu1.l2cache.ReadExReq_mshr_misses::total 33853 # number of ReadExReq MSHR misses 1975system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 319 # number of demand (read+write) MSHR misses 1976system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses 1977system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13186 # number of demand (read+write) MSHR misses 1978system.cpu1.l2cache.demand_mshr_misses::cpu1.data 100650 # number of demand (read+write) MSHR misses 1979system.cpu1.l2cache.demand_mshr_misses::total 114422 # number of demand (read+write) MSHR misses 1980system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 319 # number of overall MSHR misses 1981system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses 1982system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13186 # number of overall MSHR misses 1983system.cpu1.l2cache.overall_mshr_misses::cpu1.data 100650 # number of overall MSHR misses 1984system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of overall MSHR misses 1985system.cpu1.l2cache.overall_mshr_misses::total 137106 # number of overall MSHR misses 1986system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of ReadReq MSHR miss cycles 1987system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3630000 # number of ReadReq MSHR miss cycles 1988system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 382998014 # number of ReadReq MSHR miss cycles 1989system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 996392500 # number of ReadReq MSHR miss cycles 1990system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1387317514 # number of ReadReq MSHR miss cycles 1991system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of HardPFReq MSHR miss cycles 1992system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 708613533 # number of HardPFReq MSHR miss cycles 1993system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 439996296 # number of UpgradeReq MSHR miss cycles 1994system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 439996296 # number of UpgradeReq MSHR miss cycles 1995system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 340047738 # number of SCUpgradeReq MSHR miss cycles 1996system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 340047738 # number of SCUpgradeReq MSHR miss cycles 1997system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2503000 # number of SCUpgradeFailReq MSHR miss cycles 1998system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2503000 # number of SCUpgradeFailReq MSHR miss cycles 1999system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 980626782 # number of ReadExReq MSHR miss cycles 2000system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 980626782 # number of ReadExReq MSHR miss cycles 2001system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of demand (read+write) MSHR miss cycles 2002system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3630000 # number of demand (read+write) MSHR miss cycles 2003system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 382998014 # number of demand (read+write) MSHR miss cycles 2004system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1977019282 # number of demand (read+write) MSHR miss cycles 2005system.cpu1.l2cache.demand_mshr_miss_latency::total 2367944296 # number of demand (read+write) MSHR miss cycles 2006system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of overall MSHR miss cycles 2007system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3630000 # number of overall MSHR miss cycles 2008system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 382998014 # number of overall MSHR miss cycles 2009system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1977019282 # number of overall MSHR miss cycles 2010system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of overall MSHR miss cycles 2011system.cpu1.l2cache.overall_mshr_miss_latency::total 3076557829 # number of overall MSHR miss cycles 2012system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14041750 # number of ReadReq MSHR uncacheable cycles 2013system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 382270250 # number of ReadReq MSHR uncacheable cycles 2014system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 396312000 # number of ReadReq MSHR uncacheable cycles 2015system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 262085000 # number of WriteReq MSHR uncacheable cycles 2016system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 262085000 # number of WriteReq MSHR uncacheable cycles 2017system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14041750 # number of overall MSHR uncacheable cycles 2018system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 644355250 # number of overall MSHR uncacheable cycles 2019system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 658397000 # number of overall MSHR uncacheable cycles 2020system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for ReadReq accesses 2022system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for ReadReq accesses 2023system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.394781 # mshr miss rate for ReadReq accesses 2024system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118261 # mshr miss rate for ReadReq accesses |
| 2040system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2041system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2025system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2026system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2042system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses 2043system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses 2044system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses 2045system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses | 2027system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.963379 # mshr miss rate for UpgradeReq accesses 2028system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.963379 # mshr miss rate for UpgradeReq accesses 2029system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961163 # mshr miss rate for SCUpgradeReq accesses 2030system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961163 # mshr miss rate for SCUpgradeReq accesses |
| 2046system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2047system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2031system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2032system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2048system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses 2049system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses 2050system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses 2051system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses 2052system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses 2053system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses 2054system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses 2055system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses 2056system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses 2057system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses 2058system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses | 2033system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547314 # mshr miss rate for ReadExReq accesses 2034system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547314 # mshr miss rate for ReadExReq accesses 2035system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for demand accesses 2036system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for demand accesses 2037system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for demand accesses 2038system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for demand accesses 2039system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153972 # mshr miss rate for demand accesses 2040system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for overall accesses 2041system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for overall accesses 2042system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for overall accesses 2043system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for overall accesses |
| 2059system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2044system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2060system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses 2061system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency 2062system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency 2063system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency 2064system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency 2065system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency 2066system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency 2067system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency 2068system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency 2069system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency 2070system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency 2071system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency 2072system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency 2073system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency 2074system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency 2075system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency 2076system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency 2077system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency 2078system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency 2079system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency 2080system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency 2081system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency 2082system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency 2083system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency 2084system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency 2085system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency 2086system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency | 2045system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184497 # mshr miss rate for overall accesses 2046system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average ReadReq mshr miss latency 2047system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average ReadReq mshr miss latency 2048system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average ReadReq mshr miss latency 2049system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14916.725302 # average ReadReq mshr miss latency 2050system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17218.998796 # average ReadReq mshr miss latency 2051system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average HardPFReq mshr miss latency 2052system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31238.473506 # average HardPFReq mshr miss latency 2053system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15749.026272 # average UpgradeReq mshr miss latency 2054system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15749.026272 # average UpgradeReq mshr miss latency 2055system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15082.397676 # average SCUpgradeReq mshr miss latency 2056system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.397676 # average SCUpgradeReq mshr miss latency 2057system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 278111.111111 # average SCUpgradeFailReq mshr miss latency 2058system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency 2059system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency 2060system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency 2061system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency 2062system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency 2063system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency 2064system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency 2065system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency 2066system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency 2067system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency 2068system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency 2069system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency 2070system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency 2071system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency |
| 2087system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2088system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2089system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2090system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2091system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2092system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2093system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2094system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2095system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2072system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2073system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2074system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2075system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2076system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2077system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2078system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2079system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2080system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2096system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution 2097system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution 2098system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution 2099system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution 2100system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution 2101system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution 2102system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 2103system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution 2104system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution 2105system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution 2106system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 2107system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution 2108system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution 2109system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution 2110system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) 2111system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) 2112system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) 2113system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) 2114system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) 2115system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) 2116system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) 2117system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) 2118system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) 2119system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) 2120system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) 2121system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram 2122system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram 2123system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram | 2081system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution 2082system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution 2083system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution 2084system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution 2085system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution 2086system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution 2087system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution 2088system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution 2089system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution 2090system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution 2091system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution 2092system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution 2093system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution 2094system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution 2095system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes) 2096system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes) 2097system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes) 2098system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes) 2099system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes) 2100system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes) 2101system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes) 2102system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes) 2103system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes) 2104system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes) 2105system.cpu1.toL2Bus.snoops 567913 # Total snoops (count) 2106system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram 2107system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram 2108system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram |
| 2124system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2125system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2126system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2127system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 2109system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2110system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2111system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2112system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 2128system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2129system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2130system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram 2131system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram | 2113system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram 2114system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram |
| 2132system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2115system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2133system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2134system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2135system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram 2136system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) | 2116system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2117system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 2118system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram 2119system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks) |
| 2137system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2120system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2138system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) | 2121system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks) |
| 2139system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2122system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2140system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) | 2123system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks) |
| 2141system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2124system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2142system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) | 2125system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks) |
| 2143system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2126system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2144system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) | 2127system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) |
| 2145system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2128system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2146system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) | 2129system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks) |
| 2147system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2130system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2148system.iobus.trans_dist::ReadReq 31024 # Transaction distribution 2149system.iobus.trans_dist::ReadResp 31024 # Transaction distribution 2150system.iobus.trans_dist::WriteReq 59440 # Transaction distribution 2151system.iobus.trans_dist::WriteResp 23216 # Transaction distribution | 2131system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2132system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2133system.iobus.trans_dist::WriteReq 59423 # Transaction distribution 2134system.iobus.trans_dist::WriteResp 23199 # Transaction distribution |
| 2152system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2135system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2153system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) | 2136system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) |
| 2154system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2157system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2158system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2160system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2166system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2167system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2168system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2169system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2170system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2171system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2172system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2173system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2137system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2138system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2139system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2140system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2141system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2142system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2143system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2144system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2149system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2150system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2151system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2152system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2153system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2154system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2155system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2156system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2174system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) | 2157system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) |
| 2175system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2176system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) | 2158system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2159system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) |
| 2177system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) | 2160system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) 2161system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) |
| 2179system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2182system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2183system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2185system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2191system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2192system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2193system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2194system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2195system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2196system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2197system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2198system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2162system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2163system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2164system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2165system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2166system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2167system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2168system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2169system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2174system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2175system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2176system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2177system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2178system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2179system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2180system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2181system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2199system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) | 2182system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) |
| 2200system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2201system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) | 2183system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2184system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) |
| 2202system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) 2203system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) | 2185system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) 2186system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) |
| 2204system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2205system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2206system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2207system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2208system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2209system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2210system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2211system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2235system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2236system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2237system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2238system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2239system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2240system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2241system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2242system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2187system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2188system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2189system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2190system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2191system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2192system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2193system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2194system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2218system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2219system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2220system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2221system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2222system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2223system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2224system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2225system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2243system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) | 2226system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks) |
| 2244system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2245system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2246system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2227system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2228system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2229system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2247system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) | 2230system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) |
| 2248system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2231system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2249system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) | 2232system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks) |
| 2250system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2251system.iocache.tags.replacements 36445 # number of replacements | 2233system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2234system.iocache.tags.replacements 36445 # number of replacements |
| 2252system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use | 2235system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use |
| 2253system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2254system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2255system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2236system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2237system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2238system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2256system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. 2257system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor 2258system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy 2259system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy | 2239system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit. 2240system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor 2241system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy 2242system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy |
| 2260system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2261system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2262system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2263system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2264system.iocache.tags.data_accesses 328311 # Number of data accesses 2265system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2266system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2267system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2268system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2269system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2270system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2271system.iocache.overall_misses::realview.ide 255 # number of overall misses 2272system.iocache.overall_misses::total 255 # number of overall misses | 2243system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2244system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2245system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2246system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2247system.iocache.tags.data_accesses 328311 # Number of data accesses 2248system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2249system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2250system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2251system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 2252system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses 2253system.iocache.demand_misses::total 255 # number of demand (read+write) misses 2254system.iocache.overall_misses::realview.ide 255 # number of overall misses 2255system.iocache.overall_misses::total 255 # number of overall misses |
| 2273system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles 2274system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles 2275system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles 2276system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles 2277system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles 2278system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles 2279system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles 2280system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles | 2256system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles 2257system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles 2258system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles 2259system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles 2260system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles 2261system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles 2262system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles 2263system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles |
| 2281system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2282system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2283system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2284system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2285system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2286system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2287system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2288system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2289system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2290system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2291system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2292system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2293system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2294system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2295system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2296system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2264system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2265system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2266system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2267system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 2268system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses 2269system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses 2270system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses 2271system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses 2272system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2273system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2274system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2275system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2276system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2277system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2278system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2279system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2297system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency 2298system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency 2299system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency 2300system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency 2301system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency 2302system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency 2303system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency 2304system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency 2305system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked | 2280system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency 2281system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency 2282system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency 2283system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency 2284system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency 2285system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency 2286system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency 2287system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency 2288system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked |
| 2306system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2289system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2307system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked | 2290system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked |
| 2308system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2291system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2309system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked | 2292system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked |
| 2310system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2311system.iocache.fast_writes 0 # number of fast writes performed 2312system.iocache.cache_copies 0 # number of cache copies performed 2313system.iocache.writebacks::writebacks 36190 # number of writebacks 2314system.iocache.writebacks::total 36190 # number of writebacks 2315system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2316system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2317system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2318system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2319system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2320system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2321system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2322system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses | 2293system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2294system.iocache.fast_writes 0 # number of fast writes performed 2295system.iocache.cache_copies 0 # number of cache copies performed 2296system.iocache.writebacks::writebacks 36190 # number of writebacks 2297system.iocache.writebacks::total 36190 # number of writebacks 2298system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2299system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2300system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2301system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses 2302system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses 2303system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses 2304system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses 2305system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses |
| 2323system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles 2324system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles 2325system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles 2326system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles 2327system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles 2328system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles 2329system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles 2330system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles | 2306system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles 2307system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles 2308system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles 2309system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles 2310system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles 2311system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles 2312system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles 2313system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles |
| 2331system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2332system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2333system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2334system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2335system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2336system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2337system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2338system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2314system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2315system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2316system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2317system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2318system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2319system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2320system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2321system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2339system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency 2340system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency 2341system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency 2342system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency 2343system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency 2344system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency 2345system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency 2346system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency | 2322system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency 2323system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency 2324system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency 2325system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency 2326system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency 2327system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency 2328system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency 2329system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency |
| 2347system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2330system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2348system.l2c.tags.replacements 130735 # number of replacements 2349system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use 2350system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. 2351system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. 2352system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. | 2331system.l2c.tags.replacements 120296 # number of replacements 2332system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use 2333system.l2c.tags.total_refs 339434 # Total number of references to valid blocks. 2334system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks. 2335system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks. |
| 2353system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2336system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2354system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor 2355system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor 2356system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor 2357system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor 2358system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor 2359system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor 2360system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor 2361system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor 2362system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor 2363system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor 2364system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy 2365system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 2366system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 2367system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy 2368system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy 2369system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy 2370system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 2371system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy 2372system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy 2373system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy 2374system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy 2375system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id 2376system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 2377system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id 2378system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id 2379system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id 2380system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id 2381system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 2382system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2383system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 2384system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id 2385system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id 2386system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id 2387system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id 2388system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 2389system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id 2390system.l2c.tags.tag_accesses 4931105 # Number of tag accesses 2391system.l2c.tags.data_accesses 4931105 # Number of data accesses 2392system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits 2393system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 2394system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits 2395system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits 2396system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits 2397system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits 2398system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits 2399system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits 2400system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits 2401system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits 2402system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits 2403system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits 2404system.l2c.Writeback_hits::total 227719 # number of Writeback hits 2405system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits 2406system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits 2407system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits 2408system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits 2409system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits 2410system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits 2411system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits 2412system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits 2413system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits 2414system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits 2415system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 2416system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits 2417system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits 2418system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits 2419system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits 2420system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits 2421system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits 2422system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits 2423system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits 2424system.l2c.demand_hits::total 151998 # number of demand (read+write) hits 2425system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits 2426system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 2427system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits 2428system.l2c.overall_hits::cpu0.data 49428 # number of overall hits 2429system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits 2430system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits 2431system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits 2432system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits 2433system.l2c.overall_hits::cpu1.data 10034 # number of overall hits 2434system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits 2435system.l2c.overall_hits::total 151998 # number of overall hits | 2337system.l2c.tags.occ_blocks::writebacks 11082.113172 # Average occupied blocks per requestor 2338system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.011404 # Average occupied blocks per requestor 2339system.l2c.tags.occ_blocks::cpu0.itb.walker 0.058569 # Average occupied blocks per requestor 2340system.l2c.tags.occ_blocks::cpu0.inst 7219.690376 # Average occupied blocks per requestor 2341system.l2c.tags.occ_blocks::cpu0.data 2883.100910 # Average occupied blocks per requestor 2342system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39595.862719 # Average occupied blocks per requestor 2343system.l2c.tags.occ_blocks::cpu1.inst 1402.790170 # Average occupied blocks per requestor 2344system.l2c.tags.occ_blocks::cpu1.data 257.162663 # Average occupied blocks per requestor 2345system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1460.646056 # Average occupied blocks per requestor 2346system.l2c.tags.occ_percent::writebacks 0.169100 # Average percentage of cache occupancy 2347system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy 2348system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2349system.l2c.tags.occ_percent::cpu0.inst 0.110164 # Average percentage of cache occupancy 2350system.l2c.tags.occ_percent::cpu0.data 0.043993 # Average percentage of cache occupancy 2351system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.604185 # Average percentage of cache occupancy 2352system.l2c.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy 2353system.l2c.tags.occ_percent::cpu1.data 0.003924 # Average percentage of cache occupancy 2354system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022288 # Average percentage of cache occupancy 2355system.l2c.tags.occ_percent::total 0.975120 # Average percentage of cache occupancy 2356system.l2c.tags.occ_task_id_blocks::1022 33682 # Occupied blocks per task id 2357system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2358system.l2c.tags.occ_task_id_blocks::1024 30706 # Occupied blocks per task id 2359system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id 2360system.l2c.tags.age_task_id_blocks_1022::2 154 # Occupied blocks per task id 2361system.l2c.tags.age_task_id_blocks_1022::3 4910 # Occupied blocks per task id 2362system.l2c.tags.age_task_id_blocks_1022::4 28614 # Occupied blocks per task id 2363system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2364system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 2365system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 2366system.l2c.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id 2367system.l2c.tags.age_task_id_blocks_1024::3 1859 # Occupied blocks per task id 2368system.l2c.tags.age_task_id_blocks_1024::4 28608 # Occupied blocks per task id 2369system.l2c.tags.occ_task_id_percent::1022 0.513947 # Percentage of cache occupancy per task id 2370system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2371system.l2c.tags.occ_task_id_percent::1024 0.468536 # Percentage of cache occupancy per task id 2372system.l2c.tags.tag_accesses 4789457 # Number of tag accesses 2373system.l2c.tags.data_accesses 4789457 # Number of data accesses 2374system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits 2375system.l2c.ReadReq_hits::cpu0.itb.walker 70 # number of ReadReq hits 2376system.l2c.ReadReq_hits::cpu0.inst 29564 # number of ReadReq hits 2377system.l2c.ReadReq_hits::cpu0.data 45272 # number of ReadReq hits 2378system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47744 # number of ReadReq hits 2379system.l2c.ReadReq_hits::cpu1.dtb.walker 28 # number of ReadReq hits 2380system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits 2381system.l2c.ReadReq_hits::cpu1.inst 10986 # number of ReadReq hits 2382system.l2c.ReadReq_hits::cpu1.data 7565 # number of ReadReq hits 2383system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4624 # number of ReadReq hits 2384system.l2c.ReadReq_hits::total 145969 # number of ReadReq hits 2385system.l2c.Writeback_hits::writebacks 220623 # number of Writeback hits 2386system.l2c.Writeback_hits::total 220623 # number of Writeback hits 2387system.l2c.UpgradeReq_hits::cpu0.data 2700 # number of UpgradeReq hits 2388system.l2c.UpgradeReq_hits::cpu1.data 726 # number of UpgradeReq hits 2389system.l2c.UpgradeReq_hits::total 3426 # number of UpgradeReq hits 2390system.l2c.SCUpgradeReq_hits::cpu0.data 152 # number of SCUpgradeReq hits 2391system.l2c.SCUpgradeReq_hits::cpu1.data 169 # number of SCUpgradeReq hits 2392system.l2c.SCUpgradeReq_hits::total 321 # number of SCUpgradeReq hits 2393system.l2c.ReadExReq_hits::cpu0.data 4139 # number of ReadExReq hits 2394system.l2c.ReadExReq_hits::cpu1.data 2014 # number of ReadExReq hits 2395system.l2c.ReadExReq_hits::total 6153 # number of ReadExReq hits 2396system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits 2397system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits 2398system.l2c.demand_hits::cpu0.inst 29564 # number of demand (read+write) hits 2399system.l2c.demand_hits::cpu0.data 49411 # number of demand (read+write) hits 2400system.l2c.demand_hits::cpu0.l2cache.prefetcher 47744 # number of demand (read+write) hits 2401system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits 2402system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits 2403system.l2c.demand_hits::cpu1.inst 10986 # number of demand (read+write) hits 2404system.l2c.demand_hits::cpu1.data 9579 # number of demand (read+write) hits 2405system.l2c.demand_hits::cpu1.l2cache.prefetcher 4624 # number of demand (read+write) hits 2406system.l2c.demand_hits::total 152122 # number of demand (read+write) hits 2407system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits 2408system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits 2409system.l2c.overall_hits::cpu0.inst 29564 # number of overall hits 2410system.l2c.overall_hits::cpu0.data 49411 # number of overall hits 2411system.l2c.overall_hits::cpu0.l2cache.prefetcher 47744 # number of overall hits 2412system.l2c.overall_hits::cpu1.dtb.walker 28 # number of overall hits 2413system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits 2414system.l2c.overall_hits::cpu1.inst 10986 # number of overall hits 2415system.l2c.overall_hits::cpu1.data 9579 # number of overall hits 2416system.l2c.overall_hits::cpu1.l2cache.prefetcher 4624 # number of overall hits 2417system.l2c.overall_hits::total 152122 # number of overall hits |
| 2436system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 2437system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 2418system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 2419system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 2438system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses 2439system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses 2440system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses 2441system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses 2442system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses 2443system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses 2444system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses 2445system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses 2446system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses 2447system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses 2448system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses 2449system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses 2450system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses 2451system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses 2452system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses 2453system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses 2454system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses | 2420system.l2c.ReadReq_misses::cpu0.inst 17590 # number of ReadReq misses 2421system.l2c.ReadReq_misses::cpu0.data 8761 # number of ReadReq misses 2422system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq misses 2423system.l2c.ReadReq_misses::cpu1.inst 2200 # number of ReadReq misses 2424system.l2c.ReadReq_misses::cpu1.data 584 # number of ReadReq misses 2425system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq misses 2426system.l2c.ReadReq_misses::total 164735 # number of ReadReq misses 2427system.l2c.UpgradeReq_misses::cpu0.data 8579 # number of UpgradeReq misses 2428system.l2c.UpgradeReq_misses::cpu1.data 2656 # number of UpgradeReq misses 2429system.l2c.UpgradeReq_misses::total 11235 # number of UpgradeReq misses 2430system.l2c.SCUpgradeReq_misses::cpu0.data 453 # number of SCUpgradeReq misses 2431system.l2c.SCUpgradeReq_misses::cpu1.data 1262 # number of SCUpgradeReq misses 2432system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses 2433system.l2c.ReadExReq_misses::cpu0.data 10640 # number of ReadExReq misses 2434system.l2c.ReadExReq_misses::cpu1.data 6753 # number of ReadExReq misses 2435system.l2c.ReadExReq_misses::total 17393 # number of ReadExReq misses |
| 2455system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2456system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 2436system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2437system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 2457system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses 2458system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses 2459system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses 2460system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 2461system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses 2462system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses 2463system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses 2464system.l2c.demand_misses::total 190894 # number of demand (read+write) misses | 2438system.l2c.demand_misses::cpu0.inst 17590 # number of demand (read+write) misses 2439system.l2c.demand_misses::cpu0.data 19401 # number of demand (read+write) misses 2440system.l2c.demand_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) misses 2441system.l2c.demand_misses::cpu1.inst 2200 # number of demand (read+write) misses 2442system.l2c.demand_misses::cpu1.data 7337 # number of demand (read+write) misses 2443system.l2c.demand_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) misses 2444system.l2c.demand_misses::total 182128 # number of demand (read+write) misses |
| 2465system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2466system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 2445system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2446system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 2467system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses 2468system.l2c.overall_misses::cpu0.data 20281 # number of overall misses 2469system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses 2470system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 2471system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses 2472system.l2c.overall_misses::cpu1.data 9486 # number of overall misses 2473system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # number of overall misses 2474system.l2c.overall_misses::total 190894 # number of overall misses 2475system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 494750 # number of ReadReq miss cycles 2476system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 2477system.l2c.ReadReq_miss_latency::cpu0.inst 1299838245 # number of ReadReq miss cycles 2478system.l2c.ReadReq_miss_latency::cpu0.data 708631748 # number of ReadReq miss cycles 2479system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of ReadReq miss cycles 2480system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 75000 # number of ReadReq miss cycles 2481system.l2c.ReadReq_miss_latency::cpu1.inst 182647247 # number of ReadReq miss cycles 2482system.l2c.ReadReq_miss_latency::cpu1.data 78676500 # number of ReadReq miss cycles 2483system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of ReadReq miss cycles 2484system.l2c.ReadReq_miss_latency::total 16020624042 # number of ReadReq miss cycles 2485system.l2c.UpgradeReq_miss_latency::cpu0.data 5423319 # number of UpgradeReq miss cycles 2486system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles 2487system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles 2488system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles 2489system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles 2490system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles 2491system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles 2492system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles 2493system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles 2494system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles 2495system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 2496system.l2c.demand_miss_latency::cpu0.inst 1299838245 # number of demand (read+write) miss cycles 2497system.l2c.demand_miss_latency::cpu0.data 1597496411 # number of demand (read+write) miss cycles 2498system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of demand (read+write) miss cycles 2499system.l2c.demand_miss_latency::cpu1.dtb.walker 75000 # number of demand (read+write) miss cycles 2500system.l2c.demand_miss_latency::cpu1.inst 182647247 # number of demand (read+write) miss cycles 2501system.l2c.demand_miss_latency::cpu1.data 706193472 # number of demand (read+write) miss cycles 2502system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of demand (read+write) miss cycles 2503system.l2c.demand_miss_latency::total 17537005677 # number of demand (read+write) miss cycles 2504system.l2c.overall_miss_latency::cpu0.dtb.walker 494750 # number of overall miss cycles 2505system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 2506system.l2c.overall_miss_latency::cpu0.inst 1299838245 # number of overall miss cycles 2507system.l2c.overall_miss_latency::cpu0.data 1597496411 # number of overall miss cycles 2508system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of overall miss cycles 2509system.l2c.overall_miss_latency::cpu1.dtb.walker 75000 # number of overall miss cycles 2510system.l2c.overall_miss_latency::cpu1.inst 182647247 # number of overall miss cycles 2511system.l2c.overall_miss_latency::cpu1.data 706193472 # number of overall miss cycles 2512system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of overall miss cycles 2513system.l2c.overall_miss_latency::total 17537005677 # number of overall miss cycles 2514system.l2c.ReadReq_accesses::cpu0.dtb.walker 89 # number of ReadReq accesses(hits+misses) 2515system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) 2516system.l2c.ReadReq_accesses::cpu0.inst 47151 # number of ReadReq accesses(hits+misses) 2517system.l2c.ReadReq_accesses::cpu0.data 54460 # number of ReadReq accesses(hits+misses) 2518system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180488 # number of ReadReq accesses(hits+misses) 2519system.l2c.ReadReq_accesses::cpu1.dtb.walker 35 # number of ReadReq accesses(hits+misses) 2520system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) 2521system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) 2522system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) 2523system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) 2524system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) 2525system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) 2526system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) 2527system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) 2528system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) 2529system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) 2530system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # number of SCUpgradeReq accesses(hits+misses) 2531system.l2c.SCUpgradeReq_accesses::cpu1.data 1373 # number of SCUpgradeReq accesses(hits+misses) 2532system.l2c.SCUpgradeReq_accesses::total 2295 # number of SCUpgradeReq accesses(hits+misses) 2533system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) 2534system.l2c.ReadExReq_accesses::cpu1.data 10059 # number of ReadExReq accesses(hits+misses) 2535system.l2c.ReadExReq_accesses::total 25308 # number of ReadExReq accesses(hits+misses) 2536system.l2c.demand_accesses::cpu0.dtb.walker 89 # number of demand (read+write) accesses 2537system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses 2538system.l2c.demand_accesses::cpu0.inst 47151 # number of demand (read+write) accesses 2539system.l2c.demand_accesses::cpu0.data 69709 # number of demand (read+write) accesses 2540system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180488 # number of demand (read+write) accesses 2541system.l2c.demand_accesses::cpu1.dtb.walker 35 # number of demand (read+write) accesses 2542system.l2c.demand_accesses::cpu1.itb.walker 41 # number of demand (read+write) accesses 2543system.l2c.demand_accesses::cpu1.inst 14102 # number of demand (read+write) accesses 2544system.l2c.demand_accesses::cpu1.data 19520 # number of demand (read+write) accesses 2545system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11692 # number of demand (read+write) accesses 2546system.l2c.demand_accesses::total 342892 # number of demand (read+write) accesses 2547system.l2c.overall_accesses::cpu0.dtb.walker 89 # number of overall (read+write) accesses 2548system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses 2549system.l2c.overall_accesses::cpu0.inst 47151 # number of overall (read+write) accesses 2550system.l2c.overall_accesses::cpu0.data 69709 # number of overall (read+write) accesses 2551system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180488 # number of overall (read+write) accesses 2552system.l2c.overall_accesses::cpu1.dtb.walker 35 # number of overall (read+write) accesses 2553system.l2c.overall_accesses::cpu1.itb.walker 41 # number of overall (read+write) accesses 2554system.l2c.overall_accesses::cpu1.inst 14102 # number of overall (read+write) accesses 2555system.l2c.overall_accesses::cpu1.data 19520 # number of overall (read+write) accesses 2556system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11692 # number of overall (read+write) accesses 2557system.l2c.overall_accesses::total 342892 # number of overall (read+write) accesses 2558system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for ReadReq accesses 2559system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses 2560system.l2c.ReadReq_miss_rate::cpu0.inst 0.377065 # miss rate for ReadReq accesses 2561system.l2c.ReadReq_miss_rate::cpu0.data 0.163313 # miss rate for ReadReq accesses 2562system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for ReadReq accesses 2563system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for ReadReq accesses 2564system.l2c.ReadReq_miss_rate::cpu1.inst 0.172671 # miss rate for ReadReq accesses 2565system.l2c.ReadReq_miss_rate::cpu1.data 0.097664 # miss rate for ReadReq accesses 2566system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for ReadReq accesses 2567system.l2c.ReadReq_miss_rate::total 0.538267 # miss rate for ReadReq accesses 2568system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790063 # miss rate for UpgradeReq accesses 2569system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790076 # miss rate for UpgradeReq accesses 2570system.l2c.UpgradeReq_miss_rate::total 0.790066 # miss rate for UpgradeReq accesses 2571system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822126 # miss rate for SCUpgradeReq accesses 2572system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.880554 # miss rate for SCUpgradeReq accesses 2573system.l2c.SCUpgradeReq_miss_rate::total 0.857081 # miss rate for SCUpgradeReq accesses 2574system.l2c.ReadExReq_miss_rate::cpu0.data 0.746737 # miss rate for ReadExReq accesses 2575system.l2c.ReadExReq_miss_rate::cpu1.data 0.851178 # miss rate for ReadExReq accesses 2576system.l2c.ReadExReq_miss_rate::total 0.788249 # miss rate for ReadExReq accesses 2577system.l2c.demand_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for demand accesses 2578system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses 2579system.l2c.demand_miss_rate::cpu0.inst 0.377065 # miss rate for demand accesses 2580system.l2c.demand_miss_rate::cpu0.data 0.290938 # miss rate for demand accesses 2581system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for demand accesses 2582system.l2c.demand_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for demand accesses 2583system.l2c.demand_miss_rate::cpu1.inst 0.172671 # miss rate for demand accesses 2584system.l2c.demand_miss_rate::cpu1.data 0.485963 # miss rate for demand accesses 2585system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for demand accesses 2586system.l2c.demand_miss_rate::total 0.556718 # miss rate for demand accesses 2587system.l2c.overall_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for overall accesses 2588system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses 2589system.l2c.overall_miss_rate::cpu0.inst 0.377065 # miss rate for overall accesses 2590system.l2c.overall_miss_rate::cpu0.data 0.290938 # miss rate for overall accesses 2591system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for overall accesses 2592system.l2c.overall_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for overall accesses 2593system.l2c.overall_miss_rate::cpu1.inst 0.172671 # miss rate for overall accesses 2594system.l2c.overall_miss_rate::cpu1.data 0.485963 # miss rate for overall accesses 2595system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for overall accesses 2596system.l2c.overall_miss_rate::total 0.556718 # miss rate for overall accesses 2597system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average ReadReq miss latency 2598system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 2599system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909 # average ReadReq miss latency 2600system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376 # average ReadReq miss latency 2601system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average ReadReq miss latency 2602system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 75000 # average ReadReq miss latency 2603system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75009.136345 # average ReadReq miss latency 2604system.l2c.ReadReq_avg_miss_latency::cpu1.data 85147.727273 # average ReadReq miss latency 2605system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average ReadReq miss latency 2606system.l2c.ReadReq_avg_miss_latency::total 93718.003112 # average ReadReq miss latency 2607system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 610.115761 # average UpgradeReq miss latency 2608system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 727.539337 # average UpgradeReq miss latency 2609system.l2c.UpgradeReq_avg_miss_latency::total 638.986002 # average UpgradeReq miss latency 2610system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 897.067282 # average SCUpgradeReq miss latency 2611system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 501.219189 # average SCUpgradeReq miss latency 2612system.l2c.SCUpgradeReq_avg_miss_latency::total 653.762583 # average SCUpgradeReq miss latency 2613system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78059.599807 # average ReadExReq miss latency 2614system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73290.933427 # average ReadExReq miss latency 2615system.l2c.ReadExReq_avg_miss_latency::total 76012.914682 # average ReadExReq miss latency 2616system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency 2617system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 2618system.l2c.demand_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency 2619system.l2c.demand_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency 2620system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency 2621system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency 2622system.l2c.demand_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency 2623system.l2c.demand_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency 2624system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency 2625system.l2c.demand_avg_miss_latency::total 91867.767855 # average overall miss latency 2626system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency 2627system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 2628system.l2c.overall_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency 2629system.l2c.overall_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency 2630system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency 2631system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency 2632system.l2c.overall_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency 2633system.l2c.overall_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency 2634system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency 2635system.l2c.overall_avg_miss_latency::total 91867.767855 # average overall miss latency | 2447system.l2c.overall_misses::cpu0.inst 17590 # number of overall misses 2448system.l2c.overall_misses::cpu0.data 19401 # number of overall misses 2449system.l2c.overall_misses::cpu0.l2cache.prefetcher 130188 # number of overall misses 2450system.l2c.overall_misses::cpu1.inst 2200 # number of overall misses 2451system.l2c.overall_misses::cpu1.data 7337 # number of overall misses 2452system.l2c.overall_misses::cpu1.l2cache.prefetcher 5403 # number of overall misses 2453system.l2c.overall_misses::total 182128 # number of overall misses 2454system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 549750 # number of ReadReq miss cycles 2455system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles 2456system.l2c.ReadReq_miss_latency::cpu0.inst 1421225252 # number of ReadReq miss cycles 2457system.l2c.ReadReq_miss_latency::cpu0.data 758301308 # number of ReadReq miss cycles 2458system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of ReadReq miss cycles 2459system.l2c.ReadReq_miss_latency::cpu1.inst 181920507 # number of ReadReq miss cycles 2460system.l2c.ReadReq_miss_latency::cpu1.data 52732500 # number of ReadReq miss cycles 2461system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of ReadReq miss cycles 2462system.l2c.ReadReq_miss_latency::total 15758293199 # number of ReadReq miss cycles 2463system.l2c.UpgradeReq_miss_latency::cpu0.data 14082590 # number of UpgradeReq miss cycles 2464system.l2c.UpgradeReq_miss_latency::cpu1.data 2976406 # number of UpgradeReq miss cycles 2465system.l2c.UpgradeReq_miss_latency::total 17058996 # number of UpgradeReq miss cycles 2466system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1006973 # number of SCUpgradeReq miss cycles 2467system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1562950 # number of SCUpgradeReq miss cycles 2468system.l2c.SCUpgradeReq_miss_latency::total 2569923 # number of SCUpgradeReq miss cycles 2469system.l2c.ReadExReq_miss_latency::cpu0.data 947359927 # number of ReadExReq miss cycles 2470system.l2c.ReadExReq_miss_latency::cpu1.data 541992722 # number of ReadExReq miss cycles 2471system.l2c.ReadExReq_miss_latency::total 1489352649 # number of ReadExReq miss cycles 2472system.l2c.demand_miss_latency::cpu0.dtb.walker 549750 # number of demand (read+write) miss cycles 2473system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles 2474system.l2c.demand_miss_latency::cpu0.inst 1421225252 # number of demand (read+write) miss cycles 2475system.l2c.demand_miss_latency::cpu0.data 1705661235 # number of demand (read+write) miss cycles 2476system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of demand (read+write) miss cycles 2477system.l2c.demand_miss_latency::cpu1.inst 181920507 # number of demand (read+write) miss cycles 2478system.l2c.demand_miss_latency::cpu1.data 594725222 # number of demand (read+write) miss cycles 2479system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of demand (read+write) miss cycles 2480system.l2c.demand_miss_latency::total 17247645848 # number of demand (read+write) miss cycles 2481system.l2c.overall_miss_latency::cpu0.dtb.walker 549750 # number of overall miss cycles 2482system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles 2483system.l2c.overall_miss_latency::cpu0.inst 1421225252 # number of overall miss cycles 2484system.l2c.overall_miss_latency::cpu0.data 1705661235 # number of overall miss cycles 2485system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of overall miss cycles 2486system.l2c.overall_miss_latency::cpu1.inst 181920507 # number of overall miss cycles 2487system.l2c.overall_miss_latency::cpu1.data 594725222 # number of overall miss cycles 2488system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of overall miss cycles 2489system.l2c.overall_miss_latency::total 17247645848 # number of overall miss cycles 2490system.l2c.ReadReq_accesses::cpu0.dtb.walker 90 # number of ReadReq accesses(hits+misses) 2491system.l2c.ReadReq_accesses::cpu0.itb.walker 72 # number of ReadReq accesses(hits+misses) 2492system.l2c.ReadReq_accesses::cpu0.inst 47154 # number of ReadReq accesses(hits+misses) 2493system.l2c.ReadReq_accesses::cpu0.data 54033 # number of ReadReq accesses(hits+misses) 2494system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 177932 # number of ReadReq accesses(hits+misses) 2495system.l2c.ReadReq_accesses::cpu1.dtb.walker 28 # number of ReadReq accesses(hits+misses) 2496system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) 2497system.l2c.ReadReq_accesses::cpu1.inst 13186 # number of ReadReq accesses(hits+misses) 2498system.l2c.ReadReq_accesses::cpu1.data 8149 # number of ReadReq accesses(hits+misses) 2499system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 10027 # number of ReadReq accesses(hits+misses) 2500system.l2c.ReadReq_accesses::total 310704 # number of ReadReq accesses(hits+misses) 2501system.l2c.Writeback_accesses::writebacks 220623 # number of Writeback accesses(hits+misses) 2502system.l2c.Writeback_accesses::total 220623 # number of Writeback accesses(hits+misses) 2503system.l2c.UpgradeReq_accesses::cpu0.data 11279 # number of UpgradeReq accesses(hits+misses) 2504system.l2c.UpgradeReq_accesses::cpu1.data 3382 # number of UpgradeReq accesses(hits+misses) 2505system.l2c.UpgradeReq_accesses::total 14661 # number of UpgradeReq accesses(hits+misses) 2506system.l2c.SCUpgradeReq_accesses::cpu0.data 605 # number of SCUpgradeReq accesses(hits+misses) 2507system.l2c.SCUpgradeReq_accesses::cpu1.data 1431 # number of SCUpgradeReq accesses(hits+misses) 2508system.l2c.SCUpgradeReq_accesses::total 2036 # number of SCUpgradeReq accesses(hits+misses) 2509system.l2c.ReadExReq_accesses::cpu0.data 14779 # number of ReadExReq accesses(hits+misses) 2510system.l2c.ReadExReq_accesses::cpu1.data 8767 # number of ReadExReq accesses(hits+misses) 2511system.l2c.ReadExReq_accesses::total 23546 # number of ReadExReq accesses(hits+misses) 2512system.l2c.demand_accesses::cpu0.dtb.walker 90 # number of demand (read+write) accesses 2513system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses 2514system.l2c.demand_accesses::cpu0.inst 47154 # number of demand (read+write) accesses 2515system.l2c.demand_accesses::cpu0.data 68812 # number of demand (read+write) accesses 2516system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177932 # number of demand (read+write) accesses 2517system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses 2518system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses 2519system.l2c.demand_accesses::cpu1.inst 13186 # number of demand (read+write) accesses 2520system.l2c.demand_accesses::cpu1.data 16916 # number of demand (read+write) accesses 2521system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10027 # number of demand (read+write) accesses 2522system.l2c.demand_accesses::total 334250 # number of demand (read+write) accesses 2523system.l2c.overall_accesses::cpu0.dtb.walker 90 # number of overall (read+write) accesses 2524system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses 2525system.l2c.overall_accesses::cpu0.inst 47154 # number of overall (read+write) accesses 2526system.l2c.overall_accesses::cpu0.data 68812 # number of overall (read+write) accesses 2527system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177932 # number of overall (read+write) accesses 2528system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses 2529system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses 2530system.l2c.overall_accesses::cpu1.inst 13186 # number of overall (read+write) accesses 2531system.l2c.overall_accesses::cpu1.data 16916 # number of overall (read+write) accesses 2532system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10027 # number of overall (read+write) accesses 2533system.l2c.overall_accesses::total 334250 # number of overall (read+write) accesses 2534system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for ReadReq accesses 2535system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadReq accesses 2536system.l2c.ReadReq_miss_rate::cpu0.inst 0.373033 # miss rate for ReadReq accesses 2537system.l2c.ReadReq_miss_rate::cpu0.data 0.162142 # miss rate for ReadReq accesses 2538system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for ReadReq accesses 2539system.l2c.ReadReq_miss_rate::cpu1.inst 0.166844 # miss rate for ReadReq accesses 2540system.l2c.ReadReq_miss_rate::cpu1.data 0.071665 # miss rate for ReadReq accesses 2541system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for ReadReq accesses 2542system.l2c.ReadReq_miss_rate::total 0.530199 # miss rate for ReadReq accesses 2543system.l2c.UpgradeReq_miss_rate::cpu0.data 0.760617 # miss rate for UpgradeReq accesses 2544system.l2c.UpgradeReq_miss_rate::cpu1.data 0.785334 # miss rate for UpgradeReq accesses 2545system.l2c.UpgradeReq_miss_rate::total 0.766319 # miss rate for UpgradeReq accesses 2546system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.748760 # miss rate for SCUpgradeReq accesses 2547system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.881901 # miss rate for SCUpgradeReq accesses 2548system.l2c.SCUpgradeReq_miss_rate::total 0.842338 # miss rate for SCUpgradeReq accesses 2549system.l2c.ReadExReq_miss_rate::cpu0.data 0.719940 # miss rate for ReadExReq accesses 2550system.l2c.ReadExReq_miss_rate::cpu1.data 0.770275 # miss rate for ReadExReq accesses 2551system.l2c.ReadExReq_miss_rate::total 0.738682 # miss rate for ReadExReq accesses 2552system.l2c.demand_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for demand accesses 2553system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses 2554system.l2c.demand_miss_rate::cpu0.inst 0.373033 # miss rate for demand accesses 2555system.l2c.demand_miss_rate::cpu0.data 0.281942 # miss rate for demand accesses 2556system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for demand accesses 2557system.l2c.demand_miss_rate::cpu1.inst 0.166844 # miss rate for demand accesses 2558system.l2c.demand_miss_rate::cpu1.data 0.433731 # miss rate for demand accesses 2559system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for demand accesses 2560system.l2c.demand_miss_rate::total 0.544886 # miss rate for demand accesses 2561system.l2c.overall_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for overall accesses 2562system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses 2563system.l2c.overall_miss_rate::cpu0.inst 0.373033 # miss rate for overall accesses 2564system.l2c.overall_miss_rate::cpu0.data 0.281942 # miss rate for overall accesses 2565system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for overall accesses 2566system.l2c.overall_miss_rate::cpu1.inst 0.166844 # miss rate for overall accesses 2567system.l2c.overall_miss_rate::cpu1.data 0.433731 # miss rate for overall accesses 2568system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for overall accesses 2569system.l2c.overall_miss_rate::total 0.544886 # miss rate for overall accesses 2570system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average ReadReq miss latency 2571system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency 2572system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80797.342354 # average ReadReq miss latency 2573system.l2c.ReadReq_avg_miss_latency::cpu0.data 86554.195640 # average ReadReq miss latency 2574system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average ReadReq miss latency 2575system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82691.139545 # average ReadReq miss latency 2576system.l2c.ReadReq_avg_miss_latency::cpu1.data 90295.376712 # average ReadReq miss latency 2577system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average ReadReq miss latency 2578system.l2c.ReadReq_avg_miss_latency::total 95658.440520 # average ReadReq miss latency 2579system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1641.518825 # average UpgradeReq miss latency 2580system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1120.634789 # average UpgradeReq miss latency 2581system.l2c.UpgradeReq_avg_miss_latency::total 1518.379706 # average UpgradeReq miss latency 2582system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2222.898455 # average SCUpgradeReq miss latency 2583system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1238.470681 # average SCUpgradeReq miss latency 2584system.l2c.SCUpgradeReq_avg_miss_latency::total 1498.497376 # average SCUpgradeReq miss latency 2585system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89037.587124 # average ReadExReq miss latency 2586system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80259.547164 # average ReadExReq miss latency 2587system.l2c.ReadExReq_avg_miss_latency::total 85629.428448 # average ReadExReq miss latency 2588system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency 2589system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency 2590system.l2c.demand_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency 2591system.l2c.demand_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency 2592system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency 2593system.l2c.demand_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency 2594system.l2c.demand_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency 2595system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency 2596system.l2c.demand_avg_miss_latency::total 94700.682202 # average overall miss latency 2597system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency 2598system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency 2599system.l2c.overall_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency 2600system.l2c.overall_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency 2601system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency 2602system.l2c.overall_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency 2603system.l2c.overall_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency 2604system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency 2605system.l2c.overall_avg_miss_latency::total 94700.682202 # average overall miss latency |
| 2636system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2637system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2638system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2639system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2640system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2641system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2642system.l2c.fast_writes 0 # number of fast writes performed 2643system.l2c.cache_copies 0 # number of cache copies performed | 2606system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2607system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2608system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2609system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2610system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2611system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2612system.l2c.fast_writes 0 # number of fast writes performed 2613system.l2c.cache_copies 0 # number of cache copies performed |
| 2644system.l2c.writebacks::writebacks 99035 # number of writebacks 2645system.l2c.writebacks::total 99035 # number of writebacks 2646system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2647system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits 2648system.l2c.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 2649system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2650system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits 2651system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 2652system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2653system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits 2654system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits | 2614system.l2c.writebacks::writebacks 92066 # number of writebacks 2615system.l2c.writebacks::total 92066 # number of writebacks 2616system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits 2617system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits 2618system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits 2619system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 2620system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits 2621system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 2622system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 2623system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits 2624system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits |
| 2655system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses 2656system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses | 2625system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses 2626system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses |
| 2657system.l2c.ReadReq_mshr_misses::cpu0.inst 17779 # number of ReadReq MSHR misses 2658system.l2c.ReadReq_mshr_misses::cpu0.data 8894 # number of ReadReq MSHR misses 2659system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq MSHR misses 2660system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses 2661system.l2c.ReadReq_mshr_misses::cpu1.inst 2432 # number of ReadReq MSHR misses 2662system.l2c.ReadReq_mshr_misses::cpu1.data 923 # number of ReadReq MSHR misses 2663system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq MSHR misses 2664system.l2c.ReadReq_mshr_misses::total 170941 # number of ReadReq MSHR misses 2665system.l2c.UpgradeReq_mshr_misses::cpu0.data 8889 # number of UpgradeReq MSHR misses 2666system.l2c.UpgradeReq_mshr_misses::cpu1.data 2898 # number of UpgradeReq MSHR misses 2667system.l2c.UpgradeReq_mshr_misses::total 11787 # number of UpgradeReq MSHR misses 2668system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 758 # number of SCUpgradeReq MSHR misses 2669system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1209 # number of SCUpgradeReq MSHR misses 2670system.l2c.SCUpgradeReq_mshr_misses::total 1967 # number of SCUpgradeReq MSHR misses 2671system.l2c.ReadExReq_mshr_misses::cpu0.data 11387 # number of ReadExReq MSHR misses 2672system.l2c.ReadExReq_mshr_misses::cpu1.data 8562 # number of ReadExReq MSHR misses 2673system.l2c.ReadExReq_mshr_misses::total 19949 # number of ReadExReq MSHR misses | 2627system.l2c.ReadReq_mshr_misses::cpu0.inst 17588 # number of ReadReq MSHR misses 2628system.l2c.ReadReq_mshr_misses::cpu0.data 8761 # number of ReadReq MSHR misses 2629system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq MSHR misses 2630system.l2c.ReadReq_mshr_misses::cpu1.inst 2195 # number of ReadReq MSHR misses 2631system.l2c.ReadReq_mshr_misses::cpu1.data 584 # number of ReadReq MSHR misses 2632system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq MSHR misses 2633system.l2c.ReadReq_mshr_misses::total 164728 # number of ReadReq MSHR misses 2634system.l2c.UpgradeReq_mshr_misses::cpu0.data 8579 # number of UpgradeReq MSHR misses 2635system.l2c.UpgradeReq_mshr_misses::cpu1.data 2656 # number of UpgradeReq MSHR misses 2636system.l2c.UpgradeReq_mshr_misses::total 11235 # number of UpgradeReq MSHR misses 2637system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 453 # number of SCUpgradeReq MSHR misses 2638system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1262 # number of SCUpgradeReq MSHR misses 2639system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses 2640system.l2c.ReadExReq_mshr_misses::cpu0.data 10640 # number of ReadExReq MSHR misses 2641system.l2c.ReadExReq_mshr_misses::cpu1.data 6753 # number of ReadExReq MSHR misses 2642system.l2c.ReadExReq_mshr_misses::total 17393 # number of ReadExReq MSHR misses |
| 2674system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2675system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses | 2643system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2644system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses |
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| 2684system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2685system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses | 2652system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2653system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses |
| 2686system.l2c.overall_mshr_misses::cpu0.inst 17779 # number of overall MSHR misses 2687system.l2c.overall_mshr_misses::cpu0.data 20281 # number of overall MSHR misses 2688system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of overall MSHR misses 2689system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses 2690system.l2c.overall_mshr_misses::cpu1.inst 2432 # number of overall MSHR misses 2691system.l2c.overall_mshr_misses::cpu1.data 9485 # number of overall MSHR misses 2692system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of overall MSHR misses 2693system.l2c.overall_mshr_misses::total 190890 # number of overall MSHR misses 2694system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 408750 # number of ReadReq MSHR miss cycles 2695system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 2696system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1075716745 # number of ReadReq MSHR miss cycles 2697system.l2c.ReadReq_mshr_miss_latency::cpu0.data 597785248 # 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number of demand (read+write) MSHR miss cycles 2718system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles 2719system.l2c.demand_mshr_miss_latency::cpu1.inst 151904497 # number of demand (read+write) MSHR miss cycles 2720system.l2c.demand_mshr_miss_latency::cpu1.data 586405026 # number of demand (read+write) MSHR miss cycles 2721system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of demand (read+write) MSHR miss cycles 2722system.l2c.demand_mshr_miss_latency::total 15156032153 # number of demand (read+write) MSHR miss cycles 2723system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 408750 # number of overall MSHR miss cycles 2724system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 2725system.l2c.overall_mshr_miss_latency::cpu0.inst 1075716745 # number of overall MSHR miss cycles 2726system.l2c.overall_mshr_miss_latency::cpu0.data 1344091583 # number of overall MSHR miss cycles 2727system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of overall MSHR miss cycles 2728system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles 2729system.l2c.overall_mshr_miss_latency::cpu1.inst 151904497 # number of overall MSHR miss cycles 2730system.l2c.overall_mshr_miss_latency::cpu1.data 586405026 # number of overall MSHR miss cycles 2731system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of overall MSHR miss cycles 2732system.l2c.overall_mshr_miss_latency::total 15156032153 # number of overall MSHR miss cycles 2733system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476665000 # number of ReadReq MSHR uncacheable cycles 2734system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5183212748 # number of ReadReq MSHR uncacheable cycles 2735system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9260500 # number of ReadReq MSHR uncacheable cycles 2736system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 424539000 # number of ReadReq MSHR uncacheable cycles 2737system.l2c.ReadReq_mshr_uncacheable_latency::total 6093677248 # number of ReadReq MSHR uncacheable cycles 2738system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3944737000 # number of WriteReq MSHR uncacheable cycles 2739system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 304049000 # number of WriteReq MSHR uncacheable cycles 2740system.l2c.WriteReq_mshr_uncacheable_latency::total 4248786000 # number of WriteReq MSHR uncacheable cycles 2741system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476665000 # number of overall MSHR uncacheable cycles 2742system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9127949748 # number of overall MSHR uncacheable cycles 2743system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles 2744system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles 2745system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles 2746system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses 2747system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses 2748system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses 2749system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses 2750system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses 2751system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses 2752system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses 2753system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses 2754system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses 2755system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses 2756system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses 2757system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses 2758system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses 2759system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses 2760system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses 2761system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses 2762system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses 2763system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses 2764system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses 2765system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses 2766system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses 2767system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses 2768system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses 2769system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses 2770system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses 2771system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses 2772system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses 2773system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for demand accesses 2774system.l2c.demand_mshr_miss_rate::total 0.556706 # mshr miss rate for demand accesses 2775system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for overall accesses 2776system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses 2777system.l2c.overall_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for overall accesses 2778system.l2c.overall_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for overall accesses 2779system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for overall accesses 2780system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for overall accesses 2781system.l2c.overall_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for overall accesses 2782system.l2c.overall_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for overall accesses 2783system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses 2784system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses 2785system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency 2786system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 2787system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency 2788system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency 2789system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency 2790system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2791system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency 2792system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency 2793system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency 2794system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency 2795system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency 2796system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency 2797system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency 2798system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency 2799system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency 2800system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency 2801system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency 2802system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency 2803system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency 2804system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency 2805system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2806system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency 2807system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency 2808system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency 2809system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2810system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency 2811system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency 2812system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency 2813system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency 2814system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency 2815system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2816system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency 2817system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency 2818system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency 2819system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2820system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency 2821system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency 2822system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency 2823system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency | 2654system.l2c.overall_mshr_misses::cpu0.inst 17588 # number of overall MSHR misses 2655system.l2c.overall_mshr_misses::cpu0.data 19401 # number of overall MSHR misses 2656system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of overall MSHR misses 2657system.l2c.overall_mshr_misses::cpu1.inst 2195 # number of overall MSHR misses 2658system.l2c.overall_mshr_misses::cpu1.data 7337 # number of overall MSHR misses 2659system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of overall MSHR misses 2660system.l2c.overall_mshr_misses::total 182121 # number of overall MSHR misses 2661system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 462250 # number of ReadReq MSHR miss cycles 2662system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles 2663system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1200652248 # number of ReadReq MSHR miss cycles 2664system.l2c.ReadReq_mshr_miss_latency::cpu0.data 648693692 # number of ReadReq MSHR miss cycles 2665system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of ReadReq MSHR miss cycles 2666system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 154097993 # number of ReadReq MSHR miss cycles 2667system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45421500 # number of ReadReq MSHR miss cycles 2668system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of ReadReq MSHR miss cycles 2669system.l2c.ReadReq_mshr_miss_latency::total 13719540491 # number of ReadReq MSHR miss cycles 2670system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 153128559 # number of UpgradeReq MSHR miss cycles 2671system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47338644 # number of UpgradeReq MSHR miss cycles 2672system.l2c.UpgradeReq_mshr_miss_latency::total 200467203 # number of UpgradeReq MSHR miss cycles 2673system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8146450 # number of SCUpgradeReq MSHR miss cycles 2674system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22467762 # number of SCUpgradeReq MSHR miss cycles 2675system.l2c.SCUpgradeReq_mshr_miss_latency::total 30614212 # number of SCUpgradeReq MSHR miss cycles 2676system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 815815573 # number of ReadExReq MSHR miss cycles 2677system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457532278 # number of ReadExReq MSHR miss cycles 2678system.l2c.ReadExReq_mshr_miss_latency::total 1273347851 # number of ReadExReq MSHR miss cycles 2679system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 462250 # number of demand (read+write) MSHR miss cycles 2680system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles 2681system.l2c.demand_mshr_miss_latency::cpu0.inst 1200652248 # number of demand (read+write) MSHR miss cycles 2682system.l2c.demand_mshr_miss_latency::cpu0.data 1464509265 # number of demand (read+write) MSHR miss cycles 2683system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of demand (read+write) MSHR miss cycles 2684system.l2c.demand_mshr_miss_latency::cpu1.inst 154097993 # number of demand (read+write) MSHR miss cycles 2685system.l2c.demand_mshr_miss_latency::cpu1.data 502953778 # number of demand (read+write) MSHR miss cycles 2686system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of demand (read+write) MSHR miss cycles 2687system.l2c.demand_mshr_miss_latency::total 14992888342 # number of demand (read+write) MSHR miss cycles 2688system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 462250 # number of overall MSHR miss cycles 2689system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles 2690system.l2c.overall_mshr_miss_latency::cpu0.inst 1200652248 # number of overall MSHR miss cycles 2691system.l2c.overall_mshr_miss_latency::cpu0.data 1464509265 # number of overall MSHR miss cycles 2692system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of overall MSHR miss cycles 2693system.l2c.overall_mshr_miss_latency::cpu1.inst 154097993 # number of overall MSHR miss cycles 2694system.l2c.overall_mshr_miss_latency::cpu1.data 502953778 # number of overall MSHR miss cycles 2695system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of overall MSHR miss cycles 2696system.l2c.overall_mshr_miss_latency::total 14992888342 # number of overall MSHR miss cycles 2697system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 549810500 # number of ReadReq MSHR uncacheable cycles 2698system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5306549000 # number of ReadReq MSHR uncacheable cycles 2699system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10505750 # number of ReadReq MSHR uncacheable cycles 2700system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321692750 # number of ReadReq MSHR uncacheable cycles 2701system.l2c.ReadReq_mshr_uncacheable_latency::total 6188558000 # number of ReadReq MSHR uncacheable cycles 2702system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4079142000 # number of WriteReq MSHR uncacheable cycles 2703system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216691500 # number of WriteReq MSHR uncacheable cycles 2704system.l2c.WriteReq_mshr_uncacheable_latency::total 4295833500 # number of WriteReq MSHR uncacheable cycles 2705system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles 2706system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9385691000 # number of overall MSHR uncacheable cycles 2707system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10505750 # number of overall MSHR uncacheable cycles 2708system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538384250 # number of overall MSHR uncacheable cycles 2709system.l2c.overall_mshr_uncacheable_latency::total 10484391500 # number of overall MSHR uncacheable cycles 2710system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for ReadReq accesses 2711system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for ReadReq accesses 2712system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for ReadReq accesses 2713system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.162142 # mshr miss rate for ReadReq accesses 2714system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for ReadReq accesses 2715system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for ReadReq accesses 2716system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071665 # mshr miss rate for ReadReq accesses 2717system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for ReadReq accesses 2718system.l2c.ReadReq_mshr_miss_rate::total 0.530177 # mshr miss rate for ReadReq accesses 2719system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.760617 # mshr miss rate for UpgradeReq accesses 2720system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785334 # mshr miss rate for UpgradeReq accesses 2721system.l2c.UpgradeReq_mshr_miss_rate::total 0.766319 # mshr miss rate for UpgradeReq accesses 2722system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.748760 # mshr miss rate for SCUpgradeReq accesses 2723system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881901 # mshr miss rate for SCUpgradeReq accesses 2724system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.842338 # mshr miss rate for SCUpgradeReq accesses 2725system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719940 # mshr miss rate for ReadExReq accesses 2726system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.770275 # mshr miss rate for ReadExReq accesses 2727system.l2c.ReadExReq_mshr_miss_rate::total 0.738682 # mshr miss rate for ReadExReq accesses 2728system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for demand accesses 2729system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for demand accesses 2730system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for demand accesses 2731system.l2c.demand_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for demand accesses 2732system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for demand accesses 2733system.l2c.demand_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for demand accesses 2734system.l2c.demand_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for demand accesses 2735system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for demand accesses 2736system.l2c.demand_mshr_miss_rate::total 0.544865 # mshr miss rate for demand accesses 2737system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for overall accesses 2738system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for overall accesses 2739system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for overall accesses 2740system.l2c.overall_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for overall accesses 2741system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for overall accesses 2742system.l2c.overall_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for overall accesses 2743system.l2c.overall_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for overall accesses 2744system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for overall accesses 2745system.l2c.overall_mshr_miss_rate::total 0.544865 # mshr miss rate for overall accesses 2746system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average ReadReq mshr miss latency 2747system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency 2748system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average ReadReq mshr miss latency 2749system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74043.338888 # average ReadReq mshr miss latency 2750system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average ReadReq mshr miss latency 2751system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average ReadReq mshr miss latency 2752system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77776.541096 # average ReadReq mshr miss latency 2753system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average ReadReq mshr miss latency 2754system.l2c.ReadReq_avg_mshr_miss_latency::total 83286.026000 # average ReadReq mshr miss latency 2755system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.231729 # average UpgradeReq mshr miss latency 2756system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17823.284639 # average UpgradeReq mshr miss latency 2757system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17843.097730 # average UpgradeReq mshr miss latency 2758system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17983.333333 # average SCUpgradeReq mshr miss latency 2759system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.297940 # average SCUpgradeReq mshr miss latency 2760system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17850.852478 # average SCUpgradeReq mshr miss latency 2761system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76674.395959 # average ReadExReq mshr miss latency 2762system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67752.447505 # average ReadExReq mshr miss latency 2763system.l2c.ReadExReq_avg_mshr_miss_latency::total 73210.363422 # average ReadExReq mshr miss latency 2764system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency 2765system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency 2766system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency 2767system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency 2768system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency 2769system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency 2770system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency 2771system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency 2772system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency 2773system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency 2774system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency 2775system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency 2776system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency 2777system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency 2778system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency 2779system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency 2780system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency 2781system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency |
| 2824system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2825system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2826system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2827system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2828system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2829system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2830system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2831system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2832system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2833system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2834system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2835system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2836system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2837system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2782system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2783system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2784system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2785system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2786system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2787system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2788system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2789system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2790system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2791system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2792system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2793system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2794system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2795system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2838system.membus.trans_dist::ReadReq 215303 # Transaction distribution 2839system.membus.trans_dist::ReadResp 215303 # Transaction distribution 2840system.membus.trans_dist::WriteReq 30982 # Transaction distribution 2841system.membus.trans_dist::WriteResp 30982 # Transaction distribution 2842system.membus.trans_dist::Writeback 135225 # Transaction distribution | 2796system.membus.trans_dist::ReadReq 209058 # Transaction distribution 2797system.membus.trans_dist::ReadResp 209058 # Transaction distribution 2798system.membus.trans_dist::WriteReq 30943 # Transaction distribution 2799system.membus.trans_dist::WriteResp 30943 # Transaction distribution 2800system.membus.trans_dist::Writeback 128256 # Transaction distribution |
| 2843system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2844system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2801system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2802system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2845system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution 2846system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution 2847system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution 2848system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 2849system.membus.trans_dist::ReadExReq 40350 # Transaction distribution 2850system.membus.trans_dist::ReadExResp 19836 # Transaction distribution 2851system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) | 2803system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution 2804system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution 2805system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution 2806system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 2807system.membus.trans_dist::ReadExReq 37613 # Transaction distribution 2808system.membus.trans_dist::ReadExResp 17283 # Transaction distribution 2809system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) |
| 2852system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 2810system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 2853system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) 2854system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) 2855system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) | 2811system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes) 2812system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes) 2813system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes) |
| 2856system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) 2857system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) | 2814system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) 2815system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) |
| 2858system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) 2859system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) | 2816system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes) 2817system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) |
| 2860system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) | 2818system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) |
| 2861system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) 2862system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) 2863system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) | 2819system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes) 2820system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes) 2821system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes) |
| 2864system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2865system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) | 2822system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 2823system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) |
| 2866system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) 2867system.membus.snoops 123675 # Total snoops (count) 2868system.membus.snoop_fanout::samples 499419 # Request fanout histogram | 2824system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes) 2825system.membus.snoops 125085 # Total snoops (count) 2826system.membus.snoop_fanout::samples 484369 # Request fanout histogram |
| 2869system.membus.snoop_fanout::mean 1 # Request fanout histogram 2870system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2871system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2872system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2827system.membus.snoop_fanout::mean 1 # Request fanout histogram 2828system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2829system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2830system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2873system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram | 2831system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram |
| 2874system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2875system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2876system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2877system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2832system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2833system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2834system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2835system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2878system.membus.snoop_fanout::total 499419 # Request fanout histogram 2879system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) | 2836system.membus.snoop_fanout::total 484369 # Request fanout histogram 2837system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks) |
| 2880system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2881system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 2882system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2838system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2839system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 2840system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2883system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) | 2841system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) |
| 2884system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2842system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2885system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) 2886system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 2887system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) 2888system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 2889system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) | 2843system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks) 2844system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2845system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks) 2846system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2847system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks) |
| 2890system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2891system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2892system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2893system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2894system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2895system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2896system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2897system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2914system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2915system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2916system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2917system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2918system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2919system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2920system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2921system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2848system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2849system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2850system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2851system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2852system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2853system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2854system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2855system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2872system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2873system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2874system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2875system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2876system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2877system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2878system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2879system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2922system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution 2923system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution 2924system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution 2925system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution 2926system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution 2927system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 2928system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution 2929system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution 2930system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution 2931system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution 2932system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution 2933system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution 2934system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution 2935system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) 2936system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) 2937system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) 2938system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) 2939system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) 2940system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) 2941system.toL2Bus.snoops 286323 # Total snoops (count) 2942system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram 2943system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram 2944system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram | 2880system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution 2881system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution 2882system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution 2883system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution 2884system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution 2885system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution 2886system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution 2887system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution 2888system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution 2889system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution 2890system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution 2891system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution 2892system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution 2893system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes) 2894system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes) 2895system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes) 2896system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes) 2897system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes) 2898system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes) 2899system.toL2Bus.snoops 289326 # Total snoops (count) 2900system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram 2901system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram 2902system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram |
| 2945system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2946system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2903system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2904system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2947system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram 2948system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram | 2905system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram 2906system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram |
| 2949system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2950system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2951system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2907system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2908system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2909system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2952system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram 2953system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) 2954system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2955system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) | 2910system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram 2911system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks) 2912system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2913system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) |
| 2956system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2914system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2957system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) 2958system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2959system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) | 2915system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks) 2916system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2917system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks) |
| 2960system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2961 2962---------- End Simulation Statistics ---------- | 2918system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2919 2920---------- End Simulation Statistics ---------- |