| stats.txt (10535:4ccec5baf82c) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.866913 # Number of seconds simulated 4sim_ticks 2866913114000 # Number of ticks simulated 5final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.867049 # Number of seconds simulated 4sim_ticks 2867048515500 # Number of ticks simulated 5final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 786450 # Simulator instruction rate (inst/s) 8host_op_rate 951292 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17090693254 # Simulator tick rate (ticks/s) 10host_mem_usage 609256 # Number of bytes of host memory used 11host_seconds 167.75 # Real time elapsed on the host 12sim_insts 131924636 # Number of instructions simulated 13sim_ops 159576421 # Number of ops (including micro ops) simulated | 7host_inst_rate 753572 # Simulator instruction rate (inst/s) 8host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16376301643 # Simulator tick rate (ticks/s) 10host_mem_usage 607016 # Number of bytes of host memory used 11host_seconds 175.07 # Real time elapsed on the host 12sim_insts 131930165 # Number of instructions simulated 13sim_ops 159581077 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory | 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory | 23system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory |
| 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 27system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory | 27system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 34system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 35system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory | 34system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory |
| 36system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory | 41system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory | 42system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory |
| 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 45system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 47system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory | 46system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 48system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 51system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory | 50system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory |
| 53system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 55system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 57system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 60system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) |
| 63system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) | 61system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s) | 62system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 67system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 71system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s) | 69system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) |
| 74system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 71system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 76system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) | 73system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) |
| 80system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 77system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 81system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 205263 # Number of read requests accepted 87system.physmem.writeReqs 140582 # Number of write requests accepted 88system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue 92system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue 96system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one 97system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 12846 # Per bank write bursts 99system.physmem.perBankRdBursts::1 12299 # Per bank write bursts 100system.physmem.perBankRdBursts::2 13037 # Per bank write bursts 101system.physmem.perBankRdBursts::3 12736 # Per bank write bursts 102system.physmem.perBankRdBursts::4 21227 # Per bank write bursts 103system.physmem.perBankRdBursts::5 12513 # Per bank write bursts 104system.physmem.perBankRdBursts::6 12853 # Per bank write bursts 105system.physmem.perBankRdBursts::7 12957 # Per bank write bursts 106system.physmem.perBankRdBursts::8 12050 # Per bank write bursts 107system.physmem.perBankRdBursts::9 12106 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12270 # Per bank write bursts 109system.physmem.perBankRdBursts::11 11010 # Per bank write bursts 110system.physmem.perBankRdBursts::12 11804 # Per bank write bursts 111system.physmem.perBankRdBursts::13 12158 # Per bank write bursts 112system.physmem.perBankRdBursts::14 11709 # Per bank write bursts 113system.physmem.perBankRdBursts::15 11437 # Per bank write bursts 114system.physmem.perBankWrBursts::0 8735 # Per bank write bursts 115system.physmem.perBankWrBursts::1 8638 # Per bank write bursts 116system.physmem.perBankWrBursts::2 9213 # Per bank write bursts 117system.physmem.perBankWrBursts::3 8824 # Per bank write bursts 118system.physmem.perBankWrBursts::4 8594 # Per bank write bursts 119system.physmem.perBankWrBursts::5 8713 # Per bank write bursts 120system.physmem.perBankWrBursts::6 8840 # Per bank write bursts 121system.physmem.perBankWrBursts::7 8875 # Per bank write bursts 122system.physmem.perBankWrBursts::8 8399 # Per bank write bursts 123system.physmem.perBankWrBursts::9 8546 # Per bank write bursts 124system.physmem.perBankWrBursts::10 8611 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8118 # Per bank write bursts 126system.physmem.perBankWrBursts::12 8409 # Per bank write bursts 127system.physmem.perBankWrBursts::13 8327 # Per bank write bursts 128system.physmem.perBankWrBursts::14 8185 # Per bank write bursts 129system.physmem.perBankWrBursts::15 7610 # Per bank write bursts | 78system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 204505 # Number of read requests accepted 84system.physmem.writeReqs 176547 # Number of write requests accepted 85system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue 89system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 12666 # Per bank write bursts 96system.physmem.perBankRdBursts::1 12263 # Per bank write bursts 97system.physmem.perBankRdBursts::2 12897 # Per bank write bursts 98system.physmem.perBankRdBursts::3 12449 # Per bank write bursts 99system.physmem.perBankRdBursts::4 21010 # Per bank write bursts 100system.physmem.perBankRdBursts::5 12626 # Per bank write bursts 101system.physmem.perBankRdBursts::6 12991 # Per bank write bursts 102system.physmem.perBankRdBursts::7 13024 # Per bank write bursts 103system.physmem.perBankRdBursts::8 12039 # Per bank write bursts 104system.physmem.perBankRdBursts::9 12109 # Per bank write bursts 105system.physmem.perBankRdBursts::10 12276 # Per bank write bursts 106system.physmem.perBankRdBursts::11 10996 # Per bank write bursts 107system.physmem.perBankRdBursts::12 11725 # Per bank write bursts 108system.physmem.perBankRdBursts::13 12231 # Per bank write bursts 109system.physmem.perBankRdBursts::14 11672 # Per bank write bursts 110system.physmem.perBankRdBursts::15 11389 # Per bank write bursts 111system.physmem.perBankWrBursts::0 10702 # Per bank write bursts 112system.physmem.perBankWrBursts::1 10814 # Per bank write bursts 113system.physmem.perBankWrBursts::2 11122 # Per bank write bursts 114system.physmem.perBankWrBursts::3 10684 # Per bank write bursts 115system.physmem.perBankWrBursts::4 10817 # Per bank write bursts 116system.physmem.perBankWrBursts::5 11014 # Per bank write bursts 117system.physmem.perBankWrBursts::6 11094 # Per bank write bursts 118system.physmem.perBankWrBursts::7 11085 # Per bank write bursts 119system.physmem.perBankWrBursts::8 10650 # Per bank write bursts 120system.physmem.perBankWrBursts::9 11040 # Per bank write bursts 121system.physmem.perBankWrBursts::10 10845 # Per bank write bursts 122system.physmem.perBankWrBursts::11 10150 # Per bank write bursts 123system.physmem.perBankWrBursts::12 10760 # Per bank write bursts 124system.physmem.perBankWrBursts::13 10359 # Per bank write bursts 125system.physmem.perBankWrBursts::14 10115 # Per bank write bursts 126system.physmem.perBankWrBursts::15 9574 # Per bank write bursts |
| 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 131system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 132system.physmem.totGap 2866912757000 # Total gap between requests | 128system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 129system.physmem.totGap 2867048141000 # Total gap between requests |
| 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 9742 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 0 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 9742 # Read request sizes (log2) 133system.physmem.readPktSize::3 28 # Read request sizes (log2) 134system.physmem.readPktSize::4 0 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 139system.physmem.readPktSize::6 195493 # Read request sizes (log2) | 136system.physmem.readPktSize::6 194735 # Read request sizes (log2) |
| 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 4436 # Write request sizes (log2) 140system.physmem.writePktSize::3 0 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 146system.physmem.writePktSize::6 136146 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 172111 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see |
| 157system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see | 154system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see |
| 158system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see | 155system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see |
| 159system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see | 156system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see |
| 160system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see | 157system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see |
| 161system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see | 158system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see |
| 162system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see | 159system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 164system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes | 191system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes | 258system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 263system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads 297system.physmem.totQLat 5976562250 # Total ticks spent queuing 298system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM 299system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers 300system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst | 260system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads 314system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads 315system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads 316system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads 317system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads 318system.physmem.totQLat 5974898500 # Total ticks spent queuing 319system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM 320system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers 321system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst |
| 301system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 322system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 302system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst 303system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s 304system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 305system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s 306system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s | 323system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst 324system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s 325system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s 326system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s 327system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s |
| 307system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 328system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 308system.physmem.busUtil 0.06 # Data bus utilization in percentage | 329system.physmem.busUtil 0.07 # Data bus utilization in percentage |
| 309system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads | 330system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads |
| 310system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 311system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing 312system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing 313system.physmem.readRowHits 175010 # Number of row buffer hits during reads 314system.physmem.writeRowHits 85700 # Number of row buffer hits during writes 315system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads 316system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes 317system.physmem.avgGap 8289588.56 # Average gap between requests 318system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined 319system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states 320system.physmem.memoryStateTime::REF 95732520000 # Time in different power states | 331system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 332system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing 333system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing 334system.physmem.readRowHits 174382 # Number of row buffer hits during reads 335system.physmem.writeRowHits 117590 # Number of row buffer hits during writes 336system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads 337system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes 338system.physmem.avgGap 7524033.84 # Average gap between requests 339system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined 340system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states 341system.physmem.memoryStateTime::REF 95736940000 # Time in different power states |
| 321system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 342system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 322system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states | 343system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states |
| 323system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 344system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 324system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ) 325system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ) 326system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ) 327system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ) 328system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ) 329system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ) 330system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ) 331system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ) 332system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ) 333system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ) 334system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ) 335system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ) 336system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ) 337system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ) 338system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ) 339system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ) 340system.physmem.averagePower::0 669.485397 # Core power per rank (mW) 341system.physmem.averagePower::1 669.364885 # Core power per rank (mW) | 345system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) 346system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) 347system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) 348system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) 349system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) 350system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) 351system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) 352system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) 353system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) 354system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) 355system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) 356system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) 357system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) 358system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) 359system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) 360system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) 361system.physmem.averagePower::0 669.533155 # Core power per rank (mW) 362system.physmem.averagePower::1 669.414075 # Core power per rank (mW) |
| 342system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 348system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 32 unchanged lines hidden (view full) --- 382system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 388system.cpu0.dtb.inst_hits 0 # ITB inst hits 389system.cpu0.dtb.inst_misses 0 # ITB inst misses | 363system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 365system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 366system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 367system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 368system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 369system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 370system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 32 unchanged lines hidden (view full) --- 403system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 404system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 405system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 406system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 407system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 408system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 409system.cpu0.dtb.inst_hits 0 # ITB inst hits 410system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 390system.cpu0.dtb.read_hits 24351477 # DTB read hits 391system.cpu0.dtb.read_misses 6408 # DTB read misses 392system.cpu0.dtb.write_hits 18124986 # DTB write hits 393system.cpu0.dtb.write_misses 1114 # DTB write misses | 411system.cpu0.dtb.read_hits 22739909 # DTB read hits 412system.cpu0.dtb.read_misses 4142 # DTB read misses 413system.cpu0.dtb.write_hits 16676295 # DTB write hits 414system.cpu0.dtb.write_misses 677 # DTB write misses |
| 394system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 395system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 396system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 397system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 415system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 416system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 417system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 418system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 398system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB | 419system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB |
| 399system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 420system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 400system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch | 421system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch |
| 401system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 422system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 402system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 403system.cpu0.dtb.read_accesses 24357885 # DTB read accesses 404system.cpu0.dtb.write_accesses 18126100 # DTB write accesses | 423system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions 424system.cpu0.dtb.read_accesses 22744051 # DTB read accesses 425system.cpu0.dtb.write_accesses 16676972 # DTB write accesses |
| 405system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 426system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 406system.cpu0.dtb.hits 42476463 # DTB hits 407system.cpu0.dtb.misses 7522 # DTB misses 408system.cpu0.dtb.accesses 42483985 # DTB accesses | 427system.cpu0.dtb.hits 39416204 # DTB hits 428system.cpu0.dtb.misses 4819 # DTB misses 429system.cpu0.dtb.accesses 39421023 # DTB accesses |
| 409system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 410system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 411system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 412system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 413system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 414system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 415system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 416system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 422system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 423system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 424system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 425system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 426system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 427system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 428system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 429system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 430system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 431system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 432system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 433system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 434system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 435system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 436system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 437system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 443system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 445system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 446system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 447system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 448system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 449system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 450system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 430system.cpu0.itb.inst_hits 115065570 # ITB inst hits 431system.cpu0.itb.inst_misses 3350 # ITB inst misses | 451system.cpu0.itb.inst_hits 107931670 # ITB inst hits 452system.cpu0.itb.inst_misses 2300 # ITB inst misses |
| 432system.cpu0.itb.read_hits 0 # DTB read hits 433system.cpu0.itb.read_misses 0 # DTB read misses 434system.cpu0.itb.write_hits 0 # DTB write hits 435system.cpu0.itb.write_misses 0 # DTB write misses 436system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 437system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 438system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 439system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 453system.cpu0.itb.read_hits 0 # DTB read hits 454system.cpu0.itb.read_misses 0 # DTB read misses 455system.cpu0.itb.write_hits 0 # DTB write hits 456system.cpu0.itb.write_misses 0 # DTB write misses 457system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 458system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 459system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 460system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 440system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB | 461system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB |
| 441system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 442system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 443system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 445system.cpu0.itb.read_accesses 0 # DTB read accesses 446system.cpu0.itb.write_accesses 0 # DTB write accesses | 462system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 463system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 464system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 465system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 466system.cpu0.itb.read_accesses 0 # DTB read accesses 467system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 447system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses 448system.cpu0.itb.hits 115065570 # DTB hits 449system.cpu0.itb.misses 3350 # DTB misses 450system.cpu0.itb.accesses 115068920 # DTB accesses 451system.cpu0.numCycles 5733826228 # number of cpu cycles simulated | 468system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses 469system.cpu0.itb.hits 107931670 # DTB hits 470system.cpu0.itb.misses 2300 # DTB misses 471system.cpu0.itb.accesses 107933970 # DTB accesses 472system.cpu0.numCycles 5733190951 # number of cpu cycles simulated |
| 452system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 453system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 473system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 474system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 454system.cpu0.committedInsts 111421445 # Number of instructions committed 455system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed 456system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses 457system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 458system.cpu0.num_func_calls 12527454 # number of times a function call or return occured 459system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls 460system.cpu0.num_int_insts 119418221 # number of integer instructions 461system.cpu0.num_fp_insts 9755 # number of float instructions 462system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read 463system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written 464system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 465system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 466system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read 467system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written 468system.cpu0.num_mem_refs 43585923 # number of memory refs 469system.cpu0.num_load_insts 24597873 # Number of load instructions 470system.cpu0.num_store_insts 18988050 # Number of store instructions 471system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles 472system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles 473system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles 474system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles 475system.cpu0.Branches 28215151 # Number of branches fetched 476system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction 477system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction 478system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction 479system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction 480system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction 481system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction 482system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction 483system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction 484system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction 485system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction 486system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction 487system.cpu0.op_class::SimdAddAcc 0 0.00% 68.51% # Class of executed instruction 488system.cpu0.op_class::SimdAlu 0 0.00% 68.51% # Class of executed instruction 489system.cpu0.op_class::SimdCmp 0 0.00% 68.51% # Class of executed instruction 490system.cpu0.op_class::SimdCvt 0 0.00% 68.51% # Class of executed instruction 491system.cpu0.op_class::SimdMisc 0 0.00% 68.51% # Class of executed instruction 492system.cpu0.op_class::SimdMult 0 0.00% 68.51% # Class of executed instruction 493system.cpu0.op_class::SimdMultAcc 0 0.00% 68.51% # Class of executed instruction 494system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction 495system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction 496system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction 497system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction 498system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction 499system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction 500system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction 501system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction 502system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction 503system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction 504system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction 505system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction 506system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction 507system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction | 475system.cpu0.committedInsts 104697045 # Number of instructions committed 476system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed 477system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses 478system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses 479system.cpu0.num_func_calls 12218983 # number of times a function call or return occured 480system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls 481system.cpu0.num_int_insts 112138973 # number of integer instructions 482system.cpu0.num_fp_insts 4560 # number of float instructions 483system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read 484system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written 485system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read 486system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 487system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read 488system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written 489system.cpu0.num_mem_refs 40473955 # number of memory refs 490system.cpu0.num_load_insts 22968630 # Number of load instructions 491system.cpu0.num_store_insts 17505325 # Number of store instructions 492system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles 493system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles 494system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles 495system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles 496system.cpu0.Branches 26957408 # Number of branches fetched 497system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction 498system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction 499system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction 500system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction 501system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction 502system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction 503system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction 504system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction 505system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction 506system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction 507system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction 508system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction 509system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction 510system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction 511system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction 512system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction 513system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction 514system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction 515system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction 516system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction 517system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction 518system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction 519system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction 520system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction 521system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction 522system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction 523system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction 524system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction 525system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction 526system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction 527system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction 528system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction |
| 508system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 509system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 529system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 530system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 510system.cpu0.op_class::total 138426785 # Class of executed instruction | 531system.cpu0.op_class::total 130069369 # Class of executed instruction |
| 511system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 532system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 512system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed 513system.cpu0.dcache.tags.replacements 658574 # number of replacements 514system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use 515system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks. 516system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks. 517system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks. | 533system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed 534system.cpu0.dcache.tags.replacements 555287 # number of replacements 535system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use 536system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. 537system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. 538system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. |
| 518system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. | 539system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. |
| 519system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor 520system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy 521system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy 522system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 523system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 524system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 525system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 526system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 527system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses 528system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses 529system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits 530system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits 531system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits 532system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits 533system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits 534system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits 535system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits 536system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits 537system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits 538system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits 539system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits 540system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits 541system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits 542system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits 543system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses 544system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses 545system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses 546system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses 547system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses 548system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses 549system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses 550system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses 551system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses 552system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses 553system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses 554system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses 555system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses 556system.cpu0.dcache.overall_misses::total 764106 # number of overall misses 557system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles 558system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles 559system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles 560system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles 561system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles 562system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles 563system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles 564system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles 565system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles 566system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles 567system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles 568system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles 569system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles 570system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles 571system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses) 572system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses) 573system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses) 574system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses) 575system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses) 576system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses) 577system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses) 578system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses) 579system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses) 580system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses) 581system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses 582system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses 583system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses 584system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses 585system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses 586system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses 587system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses 588system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses 589system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses 590system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses 591system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses 592system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses 593system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses 594system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses 595system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses 596system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses 597system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses 598system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses 599system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency 600system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency 601system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency 602system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency 603system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency 604system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency 605system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency 606system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency | 540system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor 541system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy 542system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy 543system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 544system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id 545system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 546system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id 547system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses 548system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses 549system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits 550system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits 551system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits 552system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits 553system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits 554system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits 555system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits 556system.cpu0.dcache.LoadLockedReq_hits::total 334336 # number of LoadLockedReq hits 557system.cpu0.dcache.StoreCondReq_hits::cpu0.data 329300 # number of StoreCondReq hits 558system.cpu0.dcache.StoreCondReq_hits::total 329300 # number of StoreCondReq hits 559system.cpu0.dcache.demand_hits::cpu0.data 37695589 # number of demand (read+write) hits 560system.cpu0.dcache.demand_hits::total 37695589 # number of demand (read+write) hits 561system.cpu0.dcache.overall_hits::cpu0.data 38000302 # number of overall hits 562system.cpu0.dcache.overall_hits::total 38000302 # number of overall hits 563system.cpu0.dcache.ReadReq_misses::cpu0.data 304912 # number of ReadReq misses 564system.cpu0.dcache.ReadReq_misses::total 304912 # number of ReadReq misses 565system.cpu0.dcache.WriteReq_misses::cpu0.data 263418 # number of WriteReq misses 566system.cpu0.dcache.WriteReq_misses::total 263418 # number of WriteReq misses 567system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92252 # number of SoftPFReq misses 568system.cpu0.dcache.SoftPFReq_misses::total 92252 # number of SoftPFReq misses 569system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20070 # number of LoadLockedReq misses 570system.cpu0.dcache.LoadLockedReq_misses::total 20070 # number of LoadLockedReq misses 571system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20705 # number of StoreCondReq misses 572system.cpu0.dcache.StoreCondReq_misses::total 20705 # number of StoreCondReq misses 573system.cpu0.dcache.demand_misses::cpu0.data 568330 # number of demand (read+write) misses 574system.cpu0.dcache.demand_misses::total 568330 # number of demand (read+write) misses 575system.cpu0.dcache.overall_misses::cpu0.data 660582 # number of overall misses 576system.cpu0.dcache.overall_misses::total 660582 # number of overall misses 577system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3916535020 # number of ReadReq miss cycles 578system.cpu0.dcache.ReadReq_miss_latency::total 3916535020 # number of ReadReq miss cycles 579system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4029841681 # number of WriteReq miss cycles 580system.cpu0.dcache.WriteReq_miss_latency::total 4029841681 # number of WriteReq miss cycles 581system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 322461501 # number of LoadLockedReq miss cycles 582system.cpu0.dcache.LoadLockedReq_miss_latency::total 322461501 # number of LoadLockedReq miss cycles 583system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 462579693 # number of StoreCondReq miss cycles 584system.cpu0.dcache.StoreCondReq_miss_latency::total 462579693 # number of StoreCondReq miss cycles 585system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq miss cycles 586system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1480500 # number of StoreCondFailReq miss cycles 587system.cpu0.dcache.demand_miss_latency::cpu0.data 7946376701 # number of demand (read+write) miss cycles 588system.cpu0.dcache.demand_miss_latency::total 7946376701 # number of demand (read+write) miss cycles 589system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles 590system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles 591system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) 592system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) 593system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) 594system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) 595system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) 596system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) 597system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) 598system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) 599system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) 600system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) 601system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses 602system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses 603system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses 604system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses 605system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses 606system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses 607system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses 608system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses 609system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232393 # miss rate for SoftPFReq accesses 610system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232393 # miss rate for SoftPFReq accesses 611system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056630 # miss rate for LoadLockedReq accesses 612system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056630 # miss rate for LoadLockedReq accesses 613system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.059156 # miss rate for StoreCondReq accesses 614system.cpu0.dcache.StoreCondReq_miss_rate::total 0.059156 # miss rate for StoreCondReq accesses 615system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014853 # miss rate for demand accesses 616system.cpu0.dcache.demand_miss_rate::total 0.014853 # miss rate for demand accesses 617system.cpu0.dcache.overall_miss_rate::cpu0.data 0.017087 # miss rate for overall accesses 618system.cpu0.dcache.overall_miss_rate::total 0.017087 # miss rate for overall accesses 619system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12844.804468 # average ReadReq miss latency 620system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468 # average ReadReq miss latency 621system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570 # average WriteReq miss latency 622system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570 # average WriteReq miss latency 623system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106 # average LoadLockedReq miss latency 624system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106 # average LoadLockedReq miss latency 625system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587 # average StoreCondReq miss latency 626system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587 # average StoreCondReq miss latency |
| 607system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 608system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 627system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 628system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 609system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency 610system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency 611system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency 612system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency | 629system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494 # average overall miss latency 630system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494 # average overall miss latency 631system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency 632system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency |
| 613system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 614system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 616system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 617system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 618system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu0.dcache.fast_writes 0 # number of fast writes performed 620system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 633system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 634system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 635system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 636system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 637system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 638system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 639system.cpu0.dcache.fast_writes 0 # number of fast writes performed 640system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 621system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks 622system.cpu0.dcache.writebacks::total 483361 # number of writebacks 623system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits 624system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits 625system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits 626system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits 627system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits 628system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits 629system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits 630system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits 631system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses 632system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses 633system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses 634system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses 635system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses 636system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses 637system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses 638system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses 639system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses 640system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses 641system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses 642system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses 643system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses 644system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses 645system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles 646system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles 647system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles 648system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles 649system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles 650system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles 651system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles 652system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles 653system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles 654system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles 655system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles 656system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles 657system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles 658system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles 659system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles 660system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles 661system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles 662system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles 663system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles 664system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles 665system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles 666system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles 667system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses 668system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses 669system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses 670system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses 671system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses 672system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses 673system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses 674system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses 675system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses 676system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses 677system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses 678system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses 679system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses 680system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses 681system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency 682system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency 683system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency 684system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency 685system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency 686system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency 687system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency 688system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency 689system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency 690system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency | 641system.cpu0.dcache.writebacks::writebacks 420867 # number of writebacks 642system.cpu0.dcache.writebacks::total 420867 # number of writebacks 643system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7211 # number of ReadReq MSHR hits 644system.cpu0.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits 645system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14132 # number of LoadLockedReq MSHR hits 646system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14132 # number of LoadLockedReq MSHR hits 647system.cpu0.dcache.demand_mshr_hits::cpu0.data 7211 # number of demand (read+write) MSHR hits 648system.cpu0.dcache.demand_mshr_hits::total 7211 # number of demand (read+write) MSHR hits 649system.cpu0.dcache.overall_mshr_hits::cpu0.data 7211 # number of overall MSHR hits 650system.cpu0.dcache.overall_mshr_hits::total 7211 # number of overall MSHR hits 651system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 297701 # number of ReadReq MSHR misses 652system.cpu0.dcache.ReadReq_mshr_misses::total 297701 # number of ReadReq MSHR misses 653system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 263418 # number of WriteReq MSHR misses 654system.cpu0.dcache.WriteReq_mshr_misses::total 263418 # number of WriteReq MSHR misses 655system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 83423 # number of SoftPFReq MSHR misses 656system.cpu0.dcache.SoftPFReq_mshr_misses::total 83423 # number of SoftPFReq MSHR misses 657system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5938 # number of LoadLockedReq MSHR misses 658system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5938 # number of LoadLockedReq MSHR misses 659system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20705 # number of StoreCondReq MSHR misses 660system.cpu0.dcache.StoreCondReq_mshr_misses::total 20705 # number of StoreCondReq MSHR misses 661system.cpu0.dcache.demand_mshr_misses::cpu0.data 561119 # number of demand (read+write) MSHR misses 662system.cpu0.dcache.demand_mshr_misses::total 561119 # number of demand (read+write) MSHR misses 663system.cpu0.dcache.overall_mshr_misses::cpu0.data 644542 # number of overall MSHR misses 664system.cpu0.dcache.overall_mshr_misses::total 644542 # number of overall MSHR misses 665system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3232031980 # number of ReadReq MSHR miss cycles 666system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3232031980 # number of ReadReq MSHR miss cycles 667system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3494328319 # number of WriteReq MSHR miss cycles 668system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3494328319 # number of WriteReq MSHR miss cycles 669system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1040331239 # number of SoftPFReq MSHR miss cycles 670system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1040331239 # number of SoftPFReq MSHR miss cycles 671system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86260500 # number of LoadLockedReq MSHR miss cycles 672system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86260500 # number of LoadLockedReq MSHR miss cycles 673system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 420440307 # number of StoreCondReq MSHR miss cycles 674system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 420440307 # number of StoreCondReq MSHR miss cycles 675system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1400500 # number of StoreCondFailReq MSHR miss cycles 676system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1400500 # number of StoreCondFailReq MSHR miss cycles 677system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6726360299 # number of demand (read+write) MSHR miss cycles 678system.cpu0.dcache.demand_mshr_miss_latency::total 6726360299 # number of demand (read+write) MSHR miss cycles 679system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7766691538 # number of overall MSHR miss cycles 680system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles 681system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles 682system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles 683system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles 684system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles 685system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles 686system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles 687system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses 688system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses 689system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses 690system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses 691system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses 692system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses 693system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses 694system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses 695system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses 696system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses 697system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses 698system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses 699system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses 700system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses 701system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency 702system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency 703system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency 704system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency 705system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency 706system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency 707system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency 708system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency 709system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency 710system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency |
| 691system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 692system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 711system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 712system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 693system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency 694system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency 695system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency 696system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency | 713system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency 714system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency 715system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency 716system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency |
| 697system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 698system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 699system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 700system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 701system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 702system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 703system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 717system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 718system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 719system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 720system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 721system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 722system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 723system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 704system.cpu0.icache.tags.replacements 1061124 # number of replacements 705system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use 706system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks. 707system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks. 708system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks. | 724system.cpu0.icache.tags.replacements 945322 # number of replacements 725system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use 726system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. 727system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. 728system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. |
| 709system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. | 729system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. |
| 710system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor | 730system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor |
| 711system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 712system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy 713system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 731system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 732system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy 733system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 714system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 715system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 716system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id | 734system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id 735system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id 736system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id |
| 717system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 737system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 718system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses 719system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses 720system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits 721system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits 722system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits 723system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits 724system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits 725system.cpu0.icache.overall_hits::total 114003925 # number of overall hits 726system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses 727system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses 728system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses 729system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses 730system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses 731system.cpu0.icache.overall_misses::total 1061645 # number of overall misses 732system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles 733system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles 734system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles 735system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles 736system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles 737system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles 738system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses) 739system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses) 740system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses 741system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses 742system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses 743system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses 744system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses 745system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses 746system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses 747system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses 748system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses 749system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses 750system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency 751system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency 752system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency 753system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency 754system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency 755system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency | 738system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses 739system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses 740system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits 741system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits 742system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits 743system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits 744system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits 745system.cpu0.icache.overall_hits::total 106985827 # number of overall hits 746system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses 747system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses 748system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses 749system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses 750system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses 751system.cpu0.icache.overall_misses::total 945843 # number of overall misses 752system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles 753system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles 754system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles 755system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles 756system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles 757system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles 758system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) 759system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) 760system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses 761system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses 762system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses 763system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses 764system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses 765system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses 766system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses 767system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses 768system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses 769system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses 770system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency 771system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency 772system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency 773system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency 774system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency 775system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency |
| 756system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 762system.cpu0.icache.fast_writes 0 # number of fast writes performed 763system.cpu0.icache.cache_copies 0 # number of cache copies performed | 776system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 777system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 778system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 779system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 780system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 781system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 782system.cpu0.icache.fast_writes 0 # number of fast writes performed 783system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 764system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses 765system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses 766system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses 767system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses 768system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # number of overall MSHR misses 769system.cpu0.icache.overall_mshr_misses::total 1061645 # number of overall MSHR misses 770system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407816003 # number of ReadReq MSHR miss cycles 771system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407816003 # number of ReadReq MSHR miss cycles 772system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407816003 # number of demand (read+write) MSHR miss cycles 773system.cpu0.icache.demand_mshr_miss_latency::total 7407816003 # number of demand (read+write) MSHR miss cycles 774system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407816003 # number of overall MSHR miss cycles 775system.cpu0.icache.overall_mshr_miss_latency::total 7407816003 # number of overall MSHR miss cycles | 784system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 945843 # number of ReadReq MSHR misses 785system.cpu0.icache.ReadReq_mshr_misses::total 945843 # number of ReadReq MSHR misses 786system.cpu0.icache.demand_mshr_misses::cpu0.inst 945843 # number of demand (read+write) MSHR misses 787system.cpu0.icache.demand_mshr_misses::total 945843 # number of demand (read+write) MSHR misses 788system.cpu0.icache.overall_mshr_misses::cpu0.inst 945843 # number of overall MSHR misses 789system.cpu0.icache.overall_mshr_misses::total 945843 # number of overall MSHR misses 790system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6605629733 # number of ReadReq MSHR miss cycles 791system.cpu0.icache.ReadReq_mshr_miss_latency::total 6605629733 # number of ReadReq MSHR miss cycles 792system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6605629733 # number of demand (read+write) MSHR miss cycles 793system.cpu0.icache.demand_mshr_miss_latency::total 6605629733 # number of demand (read+write) MSHR miss cycles 794system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6605629733 # number of overall MSHR miss cycles 795system.cpu0.icache.overall_mshr_miss_latency::total 6605629733 # number of overall MSHR miss cycles |
| 776system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 777system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 778system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 779system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles | 796system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 797system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 798system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 799system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles |
| 780system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses 781system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses 782system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses 783system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses 784system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses 785system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses 786system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency 787system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency 788system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency 789system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency 790system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency 791system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency | 800system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for ReadReq accesses 801system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses 802system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for demand accesses 803system.cpu0.icache.demand_mshr_miss_rate::total 0.008763 # mshr miss rate for demand accesses 804system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for overall accesses 805system.cpu0.icache.overall_mshr_miss_rate::total 0.008763 # mshr miss rate for overall accesses 806system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average ReadReq mshr miss latency 807system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6983.854332 # average ReadReq mshr miss latency 808system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency 809system.cpu0.icache.demand_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency 810system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency 811system.cpu0.icache.overall_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency |
| 792system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 793system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 794system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 795system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 796system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 812system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 813system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 814system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 815system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 816system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 797system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified 798system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr 799system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache 800system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue | 817system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 8798864 # number of hwpf identified 818system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 212139 # number of hwpf that were already in mshr 819system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 8184021 # number of hwpf that were already in the cache 820system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 360 # number of hwpf that were already in the prefetch queue |
| 801system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 821system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 802system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated 803system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued 804system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page | 822system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 34 # number of hwpf removed because MSHR allocated 823system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 402310 # number of hwpf issued 824system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 695408 # number of hwpf spanning a virtual page |
| 805system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 825system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 806system.cpu0.l2cache.tags.replacements 357554 # number of replacements 807system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use 808system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks. 809system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks. 810system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks. | 826system.cpu0.l2cache.tags.replacements 309925 # number of replacements 827system.cpu0.l2cache.tags.tagsinuse 16107.929627 # Cycle average of tags in use 828system.cpu0.l2cache.tags.total_refs 1687462 # Total number of references to valid blocks. 829system.cpu0.l2cache.tags.sampled_refs 325154 # Sample count of references to valid blocks. 830system.cpu0.l2cache.tags.avg_refs 5.189732 # Average number of references to valid blocks. |
| 811system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 831system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 812system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor 813system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor 814system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor 815system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor 816system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor 817system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor 818system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy 819system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy 820system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 821system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy 822system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy 823system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy 824system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy 825system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id 826system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 827system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id 828system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id 829system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id 830system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id 831system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id 832system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id 833system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 834system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 835system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 836system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id 837system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id 838system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id 839system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id 840system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 841system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id 842system.cpu0.l2cache.tags.tag_accesses 38013369 # Number of tag accesses 843system.cpu0.l2cache.tags.data_accesses 38013369 # Number of data accesses 844system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7065 # number of ReadReq hits 845system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3186 # number of ReadReq hits 846system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1046032 # number of ReadReq hits 847system.cpu0.l2cache.ReadReq_hits::cpu0.data 372434 # number of ReadReq hits 848system.cpu0.l2cache.ReadReq_hits::total 1428717 # number of ReadReq hits 849system.cpu0.l2cache.Writeback_hits::writebacks 483361 # number of Writeback hits 850system.cpu0.l2cache.Writeback_hits::total 483361 # number of Writeback hits 851system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10097 # number of UpgradeReq hits 852system.cpu0.l2cache.UpgradeReq_hits::total 10097 # number of UpgradeReq hits 853system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2054 # number of SCUpgradeReq hits 854system.cpu0.l2cache.SCUpgradeReq_hits::total 2054 # number of SCUpgradeReq hits 855system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212764 # number of ReadExReq hits 856system.cpu0.l2cache.ReadExReq_hits::total 212764 # number of ReadExReq hits 857system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7065 # number of demand (read+write) hits 858system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3186 # number of demand (read+write) hits 859system.cpu0.l2cache.demand_hits::cpu0.inst 1046032 # number of demand (read+write) hits 860system.cpu0.l2cache.demand_hits::cpu0.data 585198 # number of demand (read+write) hits 861system.cpu0.l2cache.demand_hits::total 1641481 # number of demand (read+write) hits 862system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7065 # number of overall hits 863system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3186 # number of overall hits 864system.cpu0.l2cache.overall_hits::cpu0.inst 1046032 # number of overall hits 865system.cpu0.l2cache.overall_hits::cpu0.data 585198 # number of overall hits 866system.cpu0.l2cache.overall_hits::total 1641481 # number of overall hits 867system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 284 # number of ReadReq misses 868system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 213 # number of ReadReq misses 869system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15613 # number of ReadReq misses 870system.cpu0.l2cache.ReadReq_misses::cpu0.data 83733 # number of ReadReq misses 871system.cpu0.l2cache.ReadReq_misses::total 99843 # number of ReadReq misses 872system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29803 # number of UpgradeReq misses 873system.cpu0.l2cache.UpgradeReq_misses::total 29803 # number of UpgradeReq misses 874system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19308 # number of SCUpgradeReq misses 875system.cpu0.l2cache.SCUpgradeReq_misses::total 19308 # number of SCUpgradeReq misses | 832system.cpu0.l2cache.tags.occ_blocks::writebacks 6744.420736 # Average occupied blocks per requestor 833system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.207457 # Average occupied blocks per requestor 834system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.111326 # Average occupied blocks per requestor 835system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 773.977995 # Average occupied blocks per requestor 836system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1150.108298 # Average occupied blocks per requestor 837system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7436.103816 # Average occupied blocks per requestor 838system.cpu0.l2cache.tags.occ_percent::writebacks 0.411647 # Average percentage of cache occupancy 839system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000196 # Average percentage of cache occupancy 840system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy 841system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.047240 # Average percentage of cache occupancy 842system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.070197 # Average percentage of cache occupancy 843system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.453864 # Average percentage of cache occupancy 844system.cpu0.l2cache.tags.occ_percent::total 0.983150 # Average percentage of cache occupancy 845system.cpu0.l2cache.tags.occ_task_id_blocks::1022 9588 # Occupied blocks per task id 846system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 847system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5627 # Occupied blocks per task id 848system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id 849system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1190 # Occupied blocks per task id 850system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 8332 # Occupied blocks per task id 851system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 852system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 853system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id 854system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1207 # Occupied blocks per task id 855system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4155 # Occupied blocks per task id 856system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.585205 # Percentage of cache occupancy per task id 857system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 858system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.343445 # Percentage of cache occupancy per task id 859system.cpu0.l2cache.tags.tag_accesses 33371196 # Number of tag accesses 860system.cpu0.l2cache.tags.data_accesses 33371196 # Number of data accesses 861system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4956 # number of ReadReq hits 862system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2411 # number of ReadReq hits 863system.cpu0.l2cache.ReadReq_hits::cpu0.inst 933239 # number of ReadReq hits 864system.cpu0.l2cache.ReadReq_hits::cpu0.data 309750 # number of ReadReq hits 865system.cpu0.l2cache.ReadReq_hits::total 1250356 # number of ReadReq hits 866system.cpu0.l2cache.Writeback_hits::writebacks 420867 # number of Writeback hits 867system.cpu0.l2cache.Writeback_hits::total 420867 # number of Writeback hits 868system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 9645 # number of UpgradeReq hits 869system.cpu0.l2cache.UpgradeReq_hits::total 9645 # number of UpgradeReq hits 870system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1640 # number of SCUpgradeReq hits 871system.cpu0.l2cache.SCUpgradeReq_hits::total 1640 # number of SCUpgradeReq hits 872system.cpu0.l2cache.ReadExReq_hits::cpu0.data 182991 # number of ReadExReq hits 873system.cpu0.l2cache.ReadExReq_hits::total 182991 # number of ReadExReq hits 874system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4956 # number of demand (read+write) hits 875system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2411 # number of demand (read+write) hits 876system.cpu0.l2cache.demand_hits::cpu0.inst 933239 # number of demand (read+write) hits 877system.cpu0.l2cache.demand_hits::cpu0.data 492741 # number of demand (read+write) hits 878system.cpu0.l2cache.demand_hits::total 1433347 # number of demand (read+write) hits 879system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4956 # number of overall hits 880system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2411 # number of overall hits 881system.cpu0.l2cache.overall_hits::cpu0.inst 933239 # number of overall hits 882system.cpu0.l2cache.overall_hits::cpu0.data 492741 # number of overall hits 883system.cpu0.l2cache.overall_hits::total 1433347 # number of overall hits 884system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 350 # number of ReadReq misses 885system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 252 # number of ReadReq misses 886system.cpu0.l2cache.ReadReq_misses::cpu0.inst 12604 # number of ReadReq misses 887system.cpu0.l2cache.ReadReq_misses::cpu0.data 77312 # number of ReadReq misses 888system.cpu0.l2cache.ReadReq_misses::total 90518 # number of ReadReq misses 889system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29431 # number of UpgradeReq misses 890system.cpu0.l2cache.UpgradeReq_misses::total 29431 # number of UpgradeReq misses 891system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19057 # number of SCUpgradeReq misses 892system.cpu0.l2cache.SCUpgradeReq_misses::total 19057 # number of SCUpgradeReq misses |
| 876system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 877system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses | 893system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 894system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses |
| 878system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44911 # number of ReadExReq misses 879system.cpu0.l2cache.ReadExReq_misses::total 44911 # number of ReadExReq misses 880system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 284 # number of demand (read+write) misses 881system.cpu0.l2cache.demand_misses::cpu0.itb.walker 213 # number of demand (read+write) misses 882system.cpu0.l2cache.demand_misses::cpu0.inst 15613 # number of demand (read+write) misses 883system.cpu0.l2cache.demand_misses::cpu0.data 128644 # number of demand (read+write) misses 884system.cpu0.l2cache.demand_misses::total 144754 # number of demand (read+write) misses 885system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 284 # number of overall misses 886system.cpu0.l2cache.overall_misses::cpu0.itb.walker 213 # number of overall misses 887system.cpu0.l2cache.overall_misses::cpu0.inst 15613 # number of overall misses 888system.cpu0.l2cache.overall_misses::cpu0.data 128644 # number of overall misses 889system.cpu0.l2cache.overall_misses::total 144754 # number of overall misses 890system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6608000 # number of ReadReq miss cycles 891system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4758500 # number of ReadReq miss cycles 892system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598124482 # number of ReadReq miss cycles 893system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2271341908 # number of ReadReq miss cycles 894system.cpu0.l2cache.ReadReq_miss_latency::total 2880832890 # number of ReadReq miss cycles 895system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522877259 # number of UpgradeReq miss cycles 896system.cpu0.l2cache.UpgradeReq_miss_latency::total 522877259 # number of UpgradeReq miss cycles 897system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377985887 # number of SCUpgradeReq miss cycles 898system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377985887 # number of SCUpgradeReq miss cycles 899system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1224995 # number of SCUpgradeFailReq miss cycles 900system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1224995 # number of SCUpgradeFailReq miss cycles 901system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513514605 # number of ReadExReq miss cycles 902system.cpu0.l2cache.ReadExReq_miss_latency::total 1513514605 # number of ReadExReq miss cycles 903system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6608000 # number of demand (read+write) miss cycles 904system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4758500 # number of demand (read+write) miss cycles 905system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598124482 # number of demand (read+write) miss cycles 906system.cpu0.l2cache.demand_miss_latency::cpu0.data 3784856513 # number of demand (read+write) miss cycles 907system.cpu0.l2cache.demand_miss_latency::total 4394347495 # number of demand (read+write) miss cycles 908system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6608000 # number of overall miss cycles 909system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4758500 # number of overall miss cycles 910system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598124482 # number of overall miss cycles 911system.cpu0.l2cache.overall_miss_latency::cpu0.data 3784856513 # number of overall miss cycles 912system.cpu0.l2cache.overall_miss_latency::total 4394347495 # number of overall miss cycles 913system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7349 # number of ReadReq accesses(hits+misses) 914system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3399 # number of ReadReq accesses(hits+misses) 915system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061645 # number of ReadReq accesses(hits+misses) 916system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456167 # number of ReadReq accesses(hits+misses) 917system.cpu0.l2cache.ReadReq_accesses::total 1528560 # number of ReadReq accesses(hits+misses) 918system.cpu0.l2cache.Writeback_accesses::writebacks 483361 # number of Writeback accesses(hits+misses) 919system.cpu0.l2cache.Writeback_accesses::total 483361 # number of Writeback accesses(hits+misses) 920system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39900 # number of UpgradeReq accesses(hits+misses) 921system.cpu0.l2cache.UpgradeReq_accesses::total 39900 # number of UpgradeReq accesses(hits+misses) 922system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21362 # number of SCUpgradeReq accesses(hits+misses) 923system.cpu0.l2cache.SCUpgradeReq_accesses::total 21362 # number of SCUpgradeReq accesses(hits+misses) | 895system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41351 # number of ReadExReq misses 896system.cpu0.l2cache.ReadExReq_misses::total 41351 # number of ReadExReq misses 897system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 350 # number of demand (read+write) misses 898system.cpu0.l2cache.demand_misses::cpu0.itb.walker 252 # number of demand (read+write) misses 899system.cpu0.l2cache.demand_misses::cpu0.inst 12604 # number of demand (read+write) misses 900system.cpu0.l2cache.demand_misses::cpu0.data 118663 # number of demand (read+write) misses 901system.cpu0.l2cache.demand_misses::total 131869 # number of demand (read+write) misses 902system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 350 # number of overall misses 903system.cpu0.l2cache.overall_misses::cpu0.itb.walker 252 # number of overall misses 904system.cpu0.l2cache.overall_misses::cpu0.inst 12604 # number of overall misses 905system.cpu0.l2cache.overall_misses::cpu0.data 118663 # number of overall misses 906system.cpu0.l2cache.overall_misses::total 131869 # number of overall misses 907system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7623500 # number of ReadReq miss cycles 908system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5202000 # number of ReadReq miss cycles 909system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 531081224 # number of ReadReq miss cycles 910system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2111775663 # number of ReadReq miss cycles 911system.cpu0.l2cache.ReadReq_miss_latency::total 2655682387 # number of ReadReq miss cycles 912system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 520147939 # number of UpgradeReq miss cycles 913system.cpu0.l2cache.UpgradeReq_miss_latency::total 520147939 # number of UpgradeReq miss cycles 914system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 371818814 # number of SCUpgradeReq miss cycles 915system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 371818814 # number of SCUpgradeReq miss cycles 916system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1360495 # number of SCUpgradeFailReq miss cycles 917system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1360495 # number of SCUpgradeFailReq miss cycles 918system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1399039190 # number of ReadExReq miss cycles 919system.cpu0.l2cache.ReadExReq_miss_latency::total 1399039190 # number of ReadExReq miss cycles 920system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7623500 # number of demand (read+write) miss cycles 921system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5202000 # number of demand (read+write) miss cycles 922system.cpu0.l2cache.demand_miss_latency::cpu0.inst 531081224 # number of demand (read+write) miss cycles 923system.cpu0.l2cache.demand_miss_latency::cpu0.data 3510814853 # number of demand (read+write) miss cycles 924system.cpu0.l2cache.demand_miss_latency::total 4054721577 # number of demand (read+write) miss cycles 925system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7623500 # number of overall miss cycles 926system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5202000 # number of overall miss cycles 927system.cpu0.l2cache.overall_miss_latency::cpu0.inst 531081224 # number of overall miss cycles 928system.cpu0.l2cache.overall_miss_latency::cpu0.data 3510814853 # number of overall miss cycles 929system.cpu0.l2cache.overall_miss_latency::total 4054721577 # number of overall miss cycles 930system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) 931system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2663 # number of ReadReq accesses(hits+misses) 932system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 945843 # number of ReadReq accesses(hits+misses) 933system.cpu0.l2cache.ReadReq_accesses::cpu0.data 387062 # number of ReadReq accesses(hits+misses) 934system.cpu0.l2cache.ReadReq_accesses::total 1340874 # number of ReadReq accesses(hits+misses) 935system.cpu0.l2cache.Writeback_accesses::writebacks 420867 # number of Writeback accesses(hits+misses) 936system.cpu0.l2cache.Writeback_accesses::total 420867 # number of Writeback accesses(hits+misses) 937system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39076 # number of UpgradeReq accesses(hits+misses) 938system.cpu0.l2cache.UpgradeReq_accesses::total 39076 # number of UpgradeReq accesses(hits+misses) 939system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20697 # number of SCUpgradeReq accesses(hits+misses) 940system.cpu0.l2cache.SCUpgradeReq_accesses::total 20697 # number of SCUpgradeReq accesses(hits+misses) |
| 924system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 925system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) | 941system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 942system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) |
| 926system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257675 # number of ReadExReq accesses(hits+misses) 927system.cpu0.l2cache.ReadExReq_accesses::total 257675 # number of ReadExReq accesses(hits+misses) 928system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7349 # number of demand (read+write) accesses 929system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3399 # number of demand (read+write) accesses 930system.cpu0.l2cache.demand_accesses::cpu0.inst 1061645 # number of demand (read+write) accesses 931system.cpu0.l2cache.demand_accesses::cpu0.data 713842 # number of demand (read+write) accesses 932system.cpu0.l2cache.demand_accesses::total 1786235 # number of demand (read+write) accesses 933system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7349 # number of overall (read+write) accesses 934system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3399 # number of overall (read+write) accesses 935system.cpu0.l2cache.overall_accesses::cpu0.inst 1061645 # number of overall (read+write) accesses 936system.cpu0.l2cache.overall_accesses::cpu0.data 713842 # number of overall (read+write) accesses 937system.cpu0.l2cache.overall_accesses::total 1786235 # number of overall (read+write) accesses 938system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for ReadReq accesses 939system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.062665 # miss rate for ReadReq accesses 940system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014706 # miss rate for ReadReq accesses 941system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183558 # miss rate for ReadReq accesses 942system.cpu0.l2cache.ReadReq_miss_rate::total 0.065318 # miss rate for ReadReq accesses 943system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.746942 # miss rate for UpgradeReq accesses 944system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.746942 # miss rate for UpgradeReq accesses 945system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.903848 # miss rate for SCUpgradeReq accesses 946system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.903848 # miss rate for SCUpgradeReq accesses | 943system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 224342 # number of ReadExReq accesses(hits+misses) 944system.cpu0.l2cache.ReadExReq_accesses::total 224342 # number of ReadExReq accesses(hits+misses) 945system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses 946system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2663 # number of demand (read+write) accesses 947system.cpu0.l2cache.demand_accesses::cpu0.inst 945843 # number of demand (read+write) accesses 948system.cpu0.l2cache.demand_accesses::cpu0.data 611404 # number of demand (read+write) accesses 949system.cpu0.l2cache.demand_accesses::total 1565216 # number of demand (read+write) accesses 950system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses 951system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2663 # number of overall (read+write) accesses 952system.cpu0.l2cache.overall_accesses::cpu0.inst 945843 # number of overall (read+write) accesses 953system.cpu0.l2cache.overall_accesses::cpu0.data 611404 # number of overall (read+write) accesses 954system.cpu0.l2cache.overall_accesses::total 1565216 # number of overall (read+write) accesses 955system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065963 # miss rate for ReadReq accesses 956system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.094630 # miss rate for ReadReq accesses 957system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.013326 # miss rate for ReadReq accesses 958system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199741 # miss rate for ReadReq accesses 959system.cpu0.l2cache.ReadReq_miss_rate::total 0.067507 # miss rate for ReadReq accesses 960system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.753173 # miss rate for UpgradeReq accesses 961system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.753173 # miss rate for UpgradeReq accesses 962system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.920761 # miss rate for SCUpgradeReq accesses 963system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.920761 # miss rate for SCUpgradeReq accesses |
| 947system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 948system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 964system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 965system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 949system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174293 # miss rate for ReadExReq accesses 950system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174293 # miss rate for ReadExReq accesses 951system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for demand accesses 952system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.062665 # miss rate for demand accesses 953system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014706 # miss rate for demand accesses 954system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180214 # miss rate for demand accesses 955system.cpu0.l2cache.demand_miss_rate::total 0.081039 # miss rate for demand accesses 956system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for overall accesses 957system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.062665 # miss rate for overall accesses 958system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014706 # miss rate for overall accesses 959system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180214 # miss rate for overall accesses 960system.cpu0.l2cache.overall_miss_rate::total 0.081039 # miss rate for overall accesses 961system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average ReadReq miss latency 962system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22340.375587 # average ReadReq miss latency 963system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38309.388458 # average ReadReq miss latency 964system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27126.006568 # average ReadReq miss latency 965system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28853.629098 # average ReadReq miss latency 966system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17544.450525 # average UpgradeReq miss latency 967system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525 # average UpgradeReq miss latency 968system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312 # average SCUpgradeReq miss latency 969system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19576.646312 # average SCUpgradeReq miss latency 970system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 153124.375000 # average SCUpgradeFailReq miss latency 971system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 153124.375000 # average SCUpgradeFailReq miss latency 972system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33700.309612 # average ReadExReq miss latency 973system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33700.309612 # average ReadExReq miss latency 974system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency 975system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency 976system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency 977system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency 978system.cpu0.l2cache.demand_avg_miss_latency::total 30357.347604 # average overall miss latency 979system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency 980system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency 981system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency 982system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency 983system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604 # average overall miss latency 984system.cpu0.l2cache.blocked_cycles::no_mshrs 6544 # number of cycles access was blocked | 966system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.184321 # miss rate for ReadExReq accesses 967system.cpu0.l2cache.ReadExReq_miss_rate::total 0.184321 # miss rate for ReadExReq accesses 968system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065963 # miss rate for demand accesses 969system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.094630 # miss rate for demand accesses 970system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.013326 # miss rate for demand accesses 971system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.194083 # miss rate for demand accesses 972system.cpu0.l2cache.demand_miss_rate::total 0.084250 # miss rate for demand accesses 973system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065963 # miss rate for overall accesses 974system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.094630 # miss rate for overall accesses 975system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.013326 # miss rate for overall accesses 976system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.194083 # miss rate for overall accesses 977system.cpu0.l2cache.overall_miss_rate::total 0.084250 # miss rate for overall accesses 978system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21781.428571 # average ReadReq miss latency 979system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20642.857143 # average ReadReq miss latency 980system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 42135.927007 # average ReadReq miss latency 981system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27314.979085 # average ReadReq miss latency 982system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29338.721437 # average ReadReq miss latency 983system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17673.471476 # average UpgradeReq miss latency 984system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17673.471476 # average UpgradeReq miss latency 985system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19510.878627 # average SCUpgradeReq miss latency 986system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19510.878627 # average SCUpgradeReq miss latency 987system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 170061.875000 # average SCUpgradeFailReq miss latency 988system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 170061.875000 # average SCUpgradeFailReq miss latency 989system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33833.261348 # average ReadExReq miss latency 990system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33833.261348 # average ReadExReq miss latency 991system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21781.428571 # average overall miss latency 992system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20642.857143 # average overall miss latency 993system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 42135.927007 # average overall miss latency 994system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29586.432612 # average overall miss latency 995system.cpu0.l2cache.demand_avg_miss_latency::total 30748.102867 # average overall miss latency 996system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21781.428571 # average overall miss latency 997system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20642.857143 # average overall miss latency 998system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 42135.927007 # average overall miss latency 999system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29586.432612 # average overall miss latency 1000system.cpu0.l2cache.overall_avg_miss_latency::total 30748.102867 # average overall miss latency 1001system.cpu0.l2cache.blocked_cycles::no_mshrs 6541 # number of cycles access was blocked |
| 985system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1002system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 986system.cpu0.l2cache.blocked::no_mshrs 99 # number of cycles access was blocked | 1003system.cpu0.l2cache.blocked::no_mshrs 102 # number of cycles access was blocked |
| 987system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1004system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 988system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 66.101010 # average number of cycles each access was blocked | 1005system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 64.127451 # average number of cycles each access was blocked |
| 989system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 990system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 991system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1006system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1007system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1008system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 992system.cpu0.l2cache.writebacks::writebacks 205226 # number of writebacks 993system.cpu0.l2cache.writebacks::total 205226 # number of writebacks 994system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2290 # number of ReadReq MSHR hits 995system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2728 # number of ReadReq MSHR hits 996system.cpu0.l2cache.ReadReq_mshr_hits::total 5018 # number of ReadReq MSHR hits 997system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits 998system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits 999system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2290 # number of demand (read+write) MSHR hits 1000system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3938 # number of demand (read+write) MSHR hits 1001system.cpu0.l2cache.demand_mshr_hits::total 6228 # number of demand (read+write) MSHR hits 1002system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2290 # number of overall MSHR hits 1003system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3938 # number of overall MSHR hits 1004system.cpu0.l2cache.overall_mshr_hits::total 6228 # number of overall MSHR hits 1005system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 284 # number of ReadReq MSHR misses 1006system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 213 # number of ReadReq MSHR misses 1007system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13323 # number of ReadReq MSHR misses 1008system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 81005 # number of ReadReq MSHR misses 1009system.cpu0.l2cache.ReadReq_mshr_misses::total 94825 # number of ReadReq MSHR misses 1010system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of HardPFReq MSHR misses 1011system.cpu0.l2cache.HardPFReq_mshr_misses::total 445317 # number of HardPFReq MSHR misses 1012system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29803 # number of UpgradeReq MSHR misses 1013system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29803 # number of UpgradeReq MSHR misses 1014system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19308 # number of SCUpgradeReq MSHR misses 1015system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19308 # number of SCUpgradeReq MSHR misses | 1009system.cpu0.l2cache.writebacks::writebacks 191905 # number of writebacks 1010system.cpu0.l2cache.writebacks::total 191905 # number of writebacks 1011system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1866 # number of ReadReq MSHR hits 1012system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2687 # number of ReadReq MSHR hits 1013system.cpu0.l2cache.ReadReq_mshr_hits::total 4553 # number of ReadReq MSHR hits 1014system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1034 # number of ReadExReq MSHR hits 1015system.cpu0.l2cache.ReadExReq_mshr_hits::total 1034 # number of ReadExReq MSHR hits 1016system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1866 # number of demand (read+write) MSHR hits 1017system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3721 # number of demand (read+write) MSHR hits 1018system.cpu0.l2cache.demand_mshr_hits::total 5587 # number of demand (read+write) MSHR hits 1019system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1866 # number of overall MSHR hits 1020system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3721 # number of overall MSHR hits 1021system.cpu0.l2cache.overall_mshr_hits::total 5587 # number of overall MSHR hits 1022system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 350 # number of ReadReq MSHR misses 1023system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 252 # number of ReadReq MSHR misses 1024system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 10738 # number of ReadReq MSHR misses 1025system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 74625 # number of ReadReq MSHR misses 1026system.cpu0.l2cache.ReadReq_mshr_misses::total 85965 # number of ReadReq MSHR misses 1027system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 402307 # number of HardPFReq MSHR misses 1028system.cpu0.l2cache.HardPFReq_mshr_misses::total 402307 # number of HardPFReq MSHR misses 1029system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29431 # number of UpgradeReq MSHR misses 1030system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29431 # number of UpgradeReq MSHR misses 1031system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19057 # number of SCUpgradeReq MSHR misses 1032system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19057 # number of SCUpgradeReq MSHR misses |
| 1016system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1017system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses | 1033system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1034system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses |
| 1018system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43701 # number of ReadExReq MSHR misses 1019system.cpu0.l2cache.ReadExReq_mshr_misses::total 43701 # number of ReadExReq MSHR misses 1020system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 284 # number of demand (read+write) MSHR misses 1021system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 213 # number of demand (read+write) MSHR misses 1022system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13323 # number of demand (read+write) MSHR misses 1023system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124706 # number of demand (read+write) MSHR misses 1024system.cpu0.l2cache.demand_mshr_misses::total 138526 # number of demand (read+write) MSHR misses 1025system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 284 # number of overall MSHR misses 1026system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 213 # number of overall MSHR misses 1027system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13323 # number of overall MSHR misses 1028system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124706 # number of overall MSHR misses 1029system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of overall MSHR misses 1030system.cpu0.l2cache.overall_mshr_misses::total 583843 # number of overall MSHR misses 1031system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of ReadReq MSHR miss cycles 1032system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3267500 # number of ReadReq MSHR miss cycles 1033system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457593766 # number of ReadReq MSHR miss cycles 1034system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1665461966 # number of ReadReq MSHR miss cycles 1035system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2130941732 # number of ReadReq MSHR miss cycles 1036system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of HardPFReq MSHR miss cycles 1037system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17831693567 # number of HardPFReq MSHR miss cycles 1038system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489548028 # number of UpgradeReq MSHR miss cycles 1039system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489548028 # number of UpgradeReq MSHR miss cycles 1040system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261537598 # number of SCUpgradeReq MSHR miss cycles 1041system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261537598 # number of SCUpgradeReq MSHR miss cycles 1042system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 965995 # number of SCUpgradeFailReq MSHR miss cycles 1043system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 965995 # number of SCUpgradeFailReq MSHR miss cycles 1044system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080387358 # number of ReadExReq MSHR miss cycles 1045system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080387358 # number of ReadExReq MSHR miss cycles 1046system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of demand (read+write) MSHR miss cycles 1047system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3267500 # number of demand (read+write) MSHR miss cycles 1048system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457593766 # number of demand (read+write) MSHR miss cycles 1049system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2745849324 # number of demand (read+write) MSHR miss cycles 1050system.cpu0.l2cache.demand_mshr_miss_latency::total 3211329090 # number of demand (read+write) MSHR miss cycles 1051system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of overall MSHR miss cycles 1052system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3267500 # number of overall MSHR miss cycles 1053system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457593766 # number of overall MSHR miss cycles 1054system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2745849324 # number of overall MSHR miss cycles 1055system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of overall MSHR miss cycles 1056system.cpu0.l2cache.overall_mshr_miss_latency::total 21043022657 # number of overall MSHR miss cycles | 1035system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40317 # number of ReadExReq MSHR misses 1036system.cpu0.l2cache.ReadExReq_mshr_misses::total 40317 # number of ReadExReq MSHR misses 1037system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 350 # number of demand (read+write) MSHR misses 1038system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 252 # number of demand (read+write) MSHR misses 1039system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 10738 # number of demand (read+write) MSHR misses 1040system.cpu0.l2cache.demand_mshr_misses::cpu0.data 114942 # number of demand (read+write) MSHR misses 1041system.cpu0.l2cache.demand_mshr_misses::total 126282 # number of demand (read+write) MSHR misses 1042system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 350 # number of overall MSHR misses 1043system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 252 # number of overall MSHR misses 1044system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 10738 # number of overall MSHR misses 1045system.cpu0.l2cache.overall_mshr_misses::cpu0.data 114942 # number of overall MSHR misses 1046system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 402307 # number of overall MSHR misses 1047system.cpu0.l2cache.overall_mshr_misses::total 528589 # number of overall MSHR misses 1048system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5172000 # number of ReadReq MSHR miss cycles 1049system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3438000 # number of ReadReq MSHR miss cycles 1050system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 413002773 # number of ReadReq MSHR miss cycles 1051system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1551195475 # number of ReadReq MSHR miss cycles 1052system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1972808248 # number of ReadReq MSHR miss cycles 1053system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16697606620 # number of HardPFReq MSHR miss cycles 1054system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16697606620 # number of HardPFReq MSHR miss cycles 1055system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 471565864 # number of UpgradeReq MSHR miss cycles 1056system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 471565864 # number of UpgradeReq MSHR miss cycles 1057system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 257027175 # number of SCUpgradeReq MSHR miss cycles 1058system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 257027175 # number of SCUpgradeReq MSHR miss cycles 1059system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1080495 # number of SCUpgradeFailReq MSHR miss cycles 1060system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1080495 # number of SCUpgradeFailReq MSHR miss cycles 1061system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1011507025 # number of ReadExReq MSHR miss cycles 1062system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1011507025 # number of ReadExReq MSHR miss cycles 1063system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5172000 # number of demand (read+write) MSHR miss cycles 1064system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3438000 # number of demand (read+write) MSHR miss cycles 1065system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 413002773 # number of demand (read+write) MSHR miss cycles 1066system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2562702500 # number of demand (read+write) MSHR miss cycles 1067system.cpu0.l2cache.demand_mshr_miss_latency::total 2984315273 # number of demand (read+write) MSHR miss cycles 1068system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5172000 # number of overall MSHR miss cycles 1069system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3438000 # number of overall MSHR miss cycles 1070system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 413002773 # number of overall MSHR miss cycles 1071system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2562702500 # number of overall MSHR miss cycles 1072system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16697606620 # number of overall MSHR miss cycles 1073system.cpu0.l2cache.overall_mshr_miss_latency::total 19681921893 # number of overall MSHR miss cycles |
| 1057system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles | 1074system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles |
| 1058system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328411497 # number of ReadReq MSHR uncacheable cycles 1059system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975619997 # number of ReadReq MSHR uncacheable cycles 1060system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3986952006 # number of WriteReq MSHR uncacheable cycles 1061system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3986952006 # number of WriteReq MSHR uncacheable cycles | 1075system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5320901002 # number of ReadReq MSHR uncacheable cycles 1076system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5968109502 # number of ReadReq MSHR uncacheable cycles 1077system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3975516507 # number of WriteReq MSHR uncacheable cycles 1078system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3975516507 # number of WriteReq MSHR uncacheable cycles |
| 1062system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles | 1079system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles |
| 1063system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315363503 # number of overall MSHR uncacheable cycles 1064system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962572003 # number of overall MSHR uncacheable cycles 1065system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for ReadReq accesses 1066system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for ReadReq accesses 1067system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for ReadReq accesses 1068system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177578 # mshr miss rate for ReadReq accesses 1069system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062036 # mshr miss rate for ReadReq accesses | 1080system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9296417509 # number of overall MSHR uncacheable cycles 1081system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9943626009 # number of overall MSHR uncacheable cycles 1082system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for ReadReq accesses 1083system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for ReadReq accesses 1084system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for ReadReq accesses 1085system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.192799 # mshr miss rate for ReadReq accesses 1086system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.064111 # mshr miss rate for ReadReq accesses |
| 1070system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1071system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1087system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1088system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1072system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.746942 # mshr miss rate for UpgradeReq accesses 1073system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.746942 # mshr miss rate for UpgradeReq accesses 1074system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.903848 # mshr miss rate for SCUpgradeReq accesses 1075system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.903848 # mshr miss rate for SCUpgradeReq accesses | 1089system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.753173 # mshr miss rate for UpgradeReq accesses 1090system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.753173 # mshr miss rate for UpgradeReq accesses 1091system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.920761 # mshr miss rate for SCUpgradeReq accesses 1092system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.920761 # mshr miss rate for SCUpgradeReq accesses |
| 1076system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1077system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1093system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1094system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1078system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses 1079system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses 1080system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses 1081system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses 1082system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for demand accesses 1083system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for demand accesses 1084system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077552 # mshr miss rate for demand accesses 1085system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses 1086system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses 1087system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses 1088system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses | 1095system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.179712 # mshr miss rate for ReadExReq accesses 1096system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.179712 # mshr miss rate for ReadExReq accesses 1097system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for demand accesses 1098system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for demand accesses 1099system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for demand accesses 1100system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for demand accesses 1101system.cpu0.l2cache.demand_mshr_miss_rate::total 0.080680 # mshr miss rate for demand accesses 1102system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065963 # mshr miss rate for overall accesses 1103system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.094630 # mshr miss rate for overall accesses 1104system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.011353 # mshr miss rate for overall accesses 1105system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187997 # mshr miss rate for overall accesses |
| 1089system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1106system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1090system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses 1091system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency 1092system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency 1093system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency 1094system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency 1095system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency 1096system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency 1097system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency 1098system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency 1099system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency 1100system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency 1101system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency 1102system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency 1103system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency 1104system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency 1105system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency 1106system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency 1107system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency 1108system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency 1109system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency 1110system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency 1111system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency 1112system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency 1113system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency 1114system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency 1115system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency 1116system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency | 1107system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses 1108system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency 1109system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency 1110system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency 1111system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency 1112system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency 1113system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency 1114system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency 1115system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency 1116system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency 1117system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency 1118system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency 1119system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency 1120system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency 1121system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency 1122system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency 1123system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency 1124system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency 1125system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency 1126system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency 1127system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency 1128system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency 1129system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency 1130system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency 1131system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency 1132system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency 1133system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency |
| 1117system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1118system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1119system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1120system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1121system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1122system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1123system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1124system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1125system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1134system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1135system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1136system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1137system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1138system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1139system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1140system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1141system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1142system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1126system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution 1127system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution 1128system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution 1129system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution 1130system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution 1131system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution 1132system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 1133system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution 1134system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution 1135system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution 1136system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 1137system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 1138system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution 1139system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution 1140system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes) 1141system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes) 1142system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes) 1143system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes) 1144system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes) 1145system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes) 1146system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes) 1147system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes) 1148system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes) 1149system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes) 1150system.cpu0.toL2Bus.snoops 988296 # Total snoops (count) 1151system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram 1152system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram 1153system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram | 1143system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution 1144system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution 1145system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution 1146system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution 1147system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution 1148system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution 1149system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1150system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution 1151system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution 1152system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution 1153system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution 1154system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution 1155system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution 1156system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution 1157system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) 1158system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) 1159system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) 1160system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) 1161system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) 1162system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) 1163system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) 1164system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) 1165system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) 1166system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) 1168system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram 1169system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram 1170system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram |
| 1154system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1155system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1156system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1157system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1158system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1159system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1171system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1172system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1173system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1174system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1175system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1176system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1160system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram 1161system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram | 1177system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram 1178system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram |
| 1162system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1163system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1164system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1179system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1180system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1181system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1165system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram 1166system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks) | 1182system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram 1183system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) |
| 1167system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1184system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1168system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks) | 1185system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) |
| 1169system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1186system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1170system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks) 1171system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1172system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks) | 1187system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) 1188system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1189system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) |
| 1173system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1190system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1174system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) | 1191system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) |
| 1175system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1192system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1176system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks) | 1193system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) |
| 1177system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1178system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1179system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1180system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1181system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1182system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1183system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1184system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1193system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1194system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1195system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1196system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1197system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1198system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1199system.cpu1.dtb.inst_hits 0 # ITB inst hits 1200system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1194system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1195system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1196system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1197system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1198system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1199system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1200system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1201system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1210system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1211system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1212system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1213system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1214system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1215system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1216system.cpu1.dtb.inst_hits 0 # ITB inst hits 1217system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1201system.cpu1.dtb.read_hits 4826061 # DTB read hits 1202system.cpu1.dtb.read_misses 2744 # DTB read misses 1203system.cpu1.dtb.write_hits 4130169 # DTB write hits 1204system.cpu1.dtb.write_misses 524 # DTB write misses | 1218system.cpu1.dtb.read_hits 6438534 # DTB read hits 1219system.cpu1.dtb.read_misses 5066 # DTB read misses 1220system.cpu1.dtb.write_hits 5578600 # DTB write hits 1221system.cpu1.dtb.write_misses 983 # DTB write misses |
| 1205system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1206system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1207system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1208system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1222system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1223system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1224system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1225system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1209system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB | 1226system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB |
| 1210system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1227system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1211system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch | 1228system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch |
| 1212system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1229system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1213system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1214system.cpu1.dtb.read_accesses 4828805 # DTB read accesses 1215system.cpu1.dtb.write_accesses 4130693 # DTB write accesses | 1230system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions 1231system.cpu1.dtb.read_accesses 6443600 # DTB read accesses 1232system.cpu1.dtb.write_accesses 5579583 # DTB write accesses |
| 1216system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1233system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1217system.cpu1.dtb.hits 8956230 # DTB hits 1218system.cpu1.dtb.misses 3268 # DTB misses 1219system.cpu1.dtb.accesses 8959498 # DTB accesses | 1234system.cpu1.dtb.hits 12017134 # DTB hits 1235system.cpu1.dtb.misses 6049 # DTB misses 1236system.cpu1.dtb.accesses 12023183 # DTB accesses |
| 1220system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1221system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1222system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1223system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1224system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1225system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1226system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1227system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1233system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1234system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1235system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1236system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1237system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1238system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1239system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1240system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1237system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1238system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1239system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1240system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1241system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1242system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1243system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1244system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1250system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1251system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1252system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1253system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1254system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1255system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1256system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1257system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1241system.cpu1.itb.inst_hits 20883965 # ITB inst hits 1242system.cpu1.itb.inst_misses 1747 # ITB inst misses | 1258system.cpu1.itb.inst_hits 28023624 # ITB inst hits 1259system.cpu1.itb.inst_misses 2794 # ITB inst misses |
| 1243system.cpu1.itb.read_hits 0 # DTB read hits 1244system.cpu1.itb.read_misses 0 # DTB read misses 1245system.cpu1.itb.write_hits 0 # DTB write hits 1246system.cpu1.itb.write_misses 0 # DTB write misses 1247system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1248system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1249system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1250system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1260system.cpu1.itb.read_hits 0 # DTB read hits 1261system.cpu1.itb.read_misses 0 # DTB read misses 1262system.cpu1.itb.write_hits 0 # DTB write hits 1263system.cpu1.itb.write_misses 0 # DTB write misses 1264system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1265system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1266system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1267system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1251system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB | 1268system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB |
| 1252system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1253system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1254system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1255system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1256system.cpu1.itb.read_accesses 0 # DTB read accesses 1257system.cpu1.itb.write_accesses 0 # DTB write accesses | 1269system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1270system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1271system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1272system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1273system.cpu1.itb.read_accesses 0 # DTB read accesses 1274system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1258system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses 1259system.cpu1.itb.hits 20883965 # DTB hits 1260system.cpu1.itb.misses 1747 # DTB misses 1261system.cpu1.itb.accesses 20885712 # DTB accesses 1262system.cpu1.numCycles 5732918807 # number of cpu cycles simulated | 1275system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses 1276system.cpu1.itb.hits 28023624 # DTB hits 1277system.cpu1.itb.misses 2794 # DTB misses 1278system.cpu1.itb.accesses 28026418 # DTB accesses 1279system.cpu1.numCycles 5734097031 # number of cpu cycles simulated |
| 1263system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1264system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1280system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1281system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1265system.cpu1.committedInsts 20503191 # Number of instructions committed 1266system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed 1267system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses 1268system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 1269system.cpu1.num_func_calls 1209330 # number of times a function call or return occured 1270system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls 1271system.cpu1.num_int_insts 22184707 # number of integer instructions 1272system.cpu1.num_fp_insts 1792 # number of float instructions 1273system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read 1274system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written 1275system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 1276system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1277system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read 1278system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written 1279system.cpu1.num_mem_refs 9245671 # number of memory refs 1280system.cpu1.num_load_insts 4945342 # Number of load instructions 1281system.cpu1.num_store_insts 4300329 # Number of store instructions 1282system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles 1283system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles 1284system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles 1285system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles 1286system.cpu1.Branches 3891928 # Number of branches fetched 1287system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction 1288system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction 1289system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction 1290system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction 1291system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction 1292system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction 1293system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction 1294system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction 1295system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction 1296system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction 1297system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction 1298system.cpu1.op_class::SimdAddAcc 0 0.00% 63.44% # Class of executed instruction 1299system.cpu1.op_class::SimdAlu 0 0.00% 63.44% # Class of executed instruction 1300system.cpu1.op_class::SimdCmp 0 0.00% 63.44% # Class of executed instruction 1301system.cpu1.op_class::SimdCvt 0 0.00% 63.44% # Class of executed instruction 1302system.cpu1.op_class::SimdMisc 0 0.00% 63.44% # Class of executed instruction 1303system.cpu1.op_class::SimdMult 0 0.00% 63.44% # Class of executed instruction 1304system.cpu1.op_class::SimdMultAcc 0 0.00% 63.44% # Class of executed instruction 1305system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction 1306system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction 1307system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction 1308system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction 1309system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction 1310system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction 1311system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction 1312system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction 1313system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction 1314system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction 1315system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction 1316system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction 1317system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction 1318system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction | 1282system.cpu1.committedInsts 27233120 # Number of instructions committed 1283system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed 1284system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses 1285system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses 1286system.cpu1.num_func_calls 1518648 # number of times a function call or return occured 1287system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls 1288system.cpu1.num_int_insts 29468029 # number of integer instructions 1289system.cpu1.num_fp_insts 6988 # number of float instructions 1290system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read 1291system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written 1292system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read 1293system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written 1294system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read 1295system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written 1296system.cpu1.num_mem_refs 12358568 # number of memory refs 1297system.cpu1.num_load_insts 6575418 # Number of load instructions 1298system.cpu1.num_store_insts 5783150 # Number of store instructions 1299system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles 1300system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles 1301system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles 1302system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles 1303system.cpu1.Branches 5151142 # Number of branches fetched 1304system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction 1305system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction 1306system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction 1307system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction 1308system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction 1309system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction 1310system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction 1311system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction 1312system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction 1313system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction 1314system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction 1315system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction 1316system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction 1317system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction 1318system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction 1319system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction 1320system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction 1321system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction 1322system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction 1323system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction 1324system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction 1325system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction 1326system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction 1327system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction 1328system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction 1329system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction 1330system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction 1331system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction 1332system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction 1333system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction 1334system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction 1335system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction |
| 1319system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1320system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1336system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1337system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1321system.cpu1.op_class::total 25296825 # Class of executed instruction | 1338system.cpu1.op_class::total 33659368 # Class of executed instruction |
| 1322system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1339system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1323system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed 1324system.cpu1.dcache.tags.replacements 218952 # number of replacements 1325system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use 1326system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks. 1327system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks. 1328system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks. | 1340system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed 1341system.cpu1.dcache.tags.replacements 321673 # number of replacements 1342system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use 1343system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. 1344system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. 1345system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. |
| 1329system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. | 1346system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. |
| 1330system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor 1331system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy 1332system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy 1333system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id 1334system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 1335system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id 1336system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id 1337system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses 1338system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses 1339system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits 1340system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits 1341system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits 1342system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits 1343system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits 1344system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits 1345system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits 1346system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits 1347system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits 1348system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits 1349system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits 1350system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits 1351system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits 1352system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits 1353system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses 1354system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses 1355system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses 1356system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses 1357system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses 1358system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses 1359system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses 1360system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses 1361system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses 1362system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses 1363system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses 1364system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses 1365system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses 1366system.cpu1.dcache.overall_misses::total 293221 # number of overall misses 1367system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles 1368system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles 1369system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles 1370system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles 1371system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles 1372system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles 1373system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles 1374system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles 1375system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles 1376system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles 1377system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles 1378system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles 1379system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles 1380system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles 1381system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses) 1382system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses) 1383system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses) 1384system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses) 1385system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses) 1386system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses) 1387system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses) 1388system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses) 1389system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses) 1390system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses) 1391system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses 1392system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses 1393system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses 1394system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses 1395system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses 1396system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses 1397system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses 1398system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses 1399system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses 1400system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses 1401system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses 1402system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses 1403system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses 1404system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses 1405system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses 1406system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses 1407system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses 1408system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses 1409system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency 1410system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency 1411system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency 1412system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency 1413system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency 1414system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency 1415system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency 1416system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency | 1347system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor 1348system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy 1349system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy 1350system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1351system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 1352system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 1353system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id 1354system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1355system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses 1356system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses 1357system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits 1358system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits 1359system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits 1360system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits 1361system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits 1362system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits 1363system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits 1364system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits 1365system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits 1366system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits 1367system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits 1368system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits 1369system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits 1370system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits 1371system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses 1372system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses 1373system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses 1374system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses 1375system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses 1376system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses 1377system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses 1378system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses 1379system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses 1380system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses 1381system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses 1382system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses 1383system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses 1384system.cpu1.dcache.overall_misses::total 396537 # number of overall misses 1385system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles 1386system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles 1387system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles 1388system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles 1389system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles 1390system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles 1391system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles 1392system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles 1393system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles 1394system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles 1395system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles 1396system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles 1397system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles 1398system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles 1399system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) 1400system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) 1401system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) 1402system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) 1403system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) 1404system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) 1405system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) 1406system.cpu1.dcache.LoadLockedReq_accesses::total 130412 # number of LoadLockedReq accesses(hits+misses) 1407system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 128020 # number of StoreCondReq accesses(hits+misses) 1408system.cpu1.dcache.StoreCondReq_accesses::total 128020 # number of StoreCondReq accesses(hits+misses) 1409system.cpu1.dcache.demand_accesses::cpu1.data 11617109 # number of demand (read+write) accesses 1410system.cpu1.dcache.demand_accesses::total 11617109 # number of demand (read+write) accesses 1411system.cpu1.dcache.overall_accesses::cpu1.data 11747740 # number of overall (read+write) accesses 1412system.cpu1.dcache.overall_accesses::total 11747740 # number of overall (read+write) accesses 1413system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034058 # miss rate for ReadReq accesses 1414system.cpu1.dcache.ReadReq_miss_rate::total 0.034058 # miss rate for ReadReq accesses 1415system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025358 # miss rate for WriteReq accesses 1416system.cpu1.dcache.WriteReq_miss_rate::total 0.025358 # miss rate for WriteReq accesses 1417system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.369369 # miss rate for SoftPFReq accesses 1418system.cpu1.dcache.SoftPFReq_miss_rate::total 0.369369 # miss rate for SoftPFReq accesses 1419system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149733 # miss rate for LoadLockedReq accesses 1420system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149733 # miss rate for LoadLockedReq accesses 1421system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.186455 # miss rate for StoreCondReq accesses 1422system.cpu1.dcache.StoreCondReq_miss_rate::total 0.186455 # miss rate for StoreCondReq accesses 1423system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029980 # miss rate for demand accesses 1424system.cpu1.dcache.demand_miss_rate::total 0.029980 # miss rate for demand accesses 1425system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033754 # miss rate for overall accesses 1426system.cpu1.dcache.overall_miss_rate::total 0.033754 # miss rate for overall accesses 1427system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13259.947636 # average ReadReq miss latency 1428system.cpu1.dcache.ReadReq_avg_miss_latency::total 13259.947636 # average ReadReq miss latency 1429system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19351.787948 # average WriteReq miss latency 1430system.cpu1.dcache.WriteReq_avg_miss_latency::total 19351.787948 # average WriteReq miss latency 1431system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17401.239361 # average LoadLockedReq miss latency 1432system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17401.239361 # average LoadLockedReq miss latency 1433system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23054.927440 # average StoreCondReq miss latency 1434system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23054.927440 # average StoreCondReq miss latency |
| 1417system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1418system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1435system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1436system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1419system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605 # average overall miss latency 1420system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605 # average overall miss latency 1421system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122 # average overall miss latency 1422system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122 # average overall miss latency | 1437system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15675.162941 # average overall miss latency 1438system.cpu1.dcache.demand_avg_miss_latency::total 15675.162941 # average overall miss latency 1439system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency 1440system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency |
| 1423system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1424system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1425system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1426system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1427system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1428system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1429system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1430system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1441system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1442system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1443system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1444system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1445system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1446system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1447system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1448system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1431system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks 1432system.cpu1.dcache.writebacks::total 135060 # number of writebacks 1433system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits 1434system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits 1435system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits 1436system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 1437system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # number of LoadLockedReq MSHR hits 1438system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12325 # number of LoadLockedReq MSHR hits 1439system.cpu1.dcache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits 1440system.cpu1.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits 1441system.cpu1.dcache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits 1442system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits 1443system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154894 # number of ReadReq MSHR misses 1444system.cpu1.dcache.ReadReq_mshr_misses::total 154894 # number of ReadReq MSHR misses 1445system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103785 # number of WriteReq MSHR misses 1446system.cpu1.dcache.WriteReq_mshr_misses::total 103785 # number of WriteReq MSHR misses 1447system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33053 # number of SoftPFReq MSHR misses 1448system.cpu1.dcache.SoftPFReq_mshr_misses::total 33053 # number of SoftPFReq MSHR misses 1449system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5608 # number of LoadLockedReq MSHR misses 1450system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5608 # number of LoadLockedReq MSHR misses 1451system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23205 # number of StoreCondReq MSHR misses 1452system.cpu1.dcache.StoreCondReq_mshr_misses::total 23205 # number of StoreCondReq MSHR misses 1453system.cpu1.dcache.demand_mshr_misses::cpu1.data 258679 # number of demand (read+write) MSHR misses 1454system.cpu1.dcache.demand_mshr_misses::total 258679 # number of demand (read+write) MSHR misses 1455system.cpu1.dcache.overall_mshr_misses::cpu1.data 291732 # number of overall MSHR misses 1456system.cpu1.dcache.overall_mshr_misses::total 291732 # number of overall MSHR misses 1457system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1899677974 # number of ReadReq MSHR miss cycles 1458system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1899677974 # number of ReadReq MSHR miss cycles 1459system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2055753168 # number of WriteReq MSHR miss cycles 1460system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2055753168 # number of WriteReq MSHR miss cycles 1461system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496489496 # number of SoftPFReq MSHR miss cycles 1462system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496489496 # number of SoftPFReq MSHR miss cycles 1463system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84032750 # number of LoadLockedReq MSHR miss cycles 1464system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84032750 # number of LoadLockedReq MSHR miss cycles 1465system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490566779 # number of StoreCondReq MSHR miss cycles 1466system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490566779 # number of StoreCondReq MSHR miss cycles 1467system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1599500 # number of StoreCondFailReq MSHR miss cycles 1468system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1599500 # number of StoreCondFailReq MSHR miss cycles 1469system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3955431142 # number of demand (read+write) MSHR miss cycles 1470system.cpu1.dcache.demand_mshr_miss_latency::total 3955431142 # number of demand (read+write) MSHR miss cycles 1471system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4451920638 # number of overall MSHR miss cycles 1472system.cpu1.dcache.overall_mshr_miss_latency::total 4451920638 # number of overall MSHR miss cycles 1473system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961065499 # number of ReadReq MSHR uncacheable cycles 1474system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961065499 # number of ReadReq MSHR uncacheable cycles 1475system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382997 # number of WriteReq MSHR uncacheable cycles 1476system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382997 # number of WriteReq MSHR uncacheable cycles 1477system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794448496 # number of overall MSHR uncacheable cycles 1478system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794448496 # number of overall MSHR uncacheable cycles 1479system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033549 # mshr miss rate for ReadReq accesses 1480system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033549 # mshr miss rate for ReadReq accesses 1481system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025803 # mshr miss rate for WriteReq accesses 1482system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025803 # mshr miss rate for WriteReq accesses 1483system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.336038 # mshr miss rate for SoftPFReq accesses 1484system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.336038 # mshr miss rate for SoftPFReq accesses 1485system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053352 # mshr miss rate for LoadLockedReq accesses 1486system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses 1487system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225635 # mshr miss rate for StoreCondReq accesses 1488system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225635 # mshr miss rate for StoreCondReq accesses 1489system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses 1490system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses 1491system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033388 # mshr miss rate for overall accesses 1492system.cpu1.dcache.overall_mshr_miss_rate::total 0.033388 # mshr miss rate for overall accesses 1493system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178 # average ReadReq mshr miss latency 1494system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency 1495system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215 # average WriteReq mshr miss latency 1496system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215 # average WriteReq mshr miss latency 1497system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587 # average SoftPFReq mshr miss latency 1498system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587 # average SoftPFReq mshr miss latency 1499system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency 1500system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency 1501system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency 1502system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency | 1449system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks 1450system.cpu1.dcache.writebacks::total 197265 # number of writebacks 1451system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits 1452system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits 1453system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits 1454system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits 1455system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits 1456system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits 1457system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits 1458system.cpu1.dcache.overall_mshr_hits::total 459 # number of overall MSHR hits 1459system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 209743 # number of ReadReq MSHR misses 1460system.cpu1.dcache.ReadReq_mshr_misses::total 209743 # number of ReadReq MSHR misses 1461system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 138084 # number of WriteReq MSHR misses 1462system.cpu1.dcache.WriteReq_mshr_misses::total 138084 # number of WriteReq MSHR misses 1463system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 46648 # number of SoftPFReq MSHR misses 1464system.cpu1.dcache.SoftPFReq_mshr_misses::total 46648 # number of SoftPFReq MSHR misses 1465system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6022 # number of LoadLockedReq MSHR misses 1466system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6022 # number of LoadLockedReq MSHR misses 1467system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23870 # number of StoreCondReq MSHR misses 1468system.cpu1.dcache.StoreCondReq_mshr_misses::total 23870 # number of StoreCondReq MSHR misses 1469system.cpu1.dcache.demand_mshr_misses::cpu1.data 347827 # number of demand (read+write) MSHR misses 1470system.cpu1.dcache.demand_mshr_misses::total 347827 # number of demand (read+write) MSHR misses 1471system.cpu1.dcache.overall_mshr_misses::cpu1.data 394475 # number of overall MSHR misses 1472system.cpu1.dcache.overall_mshr_misses::total 394475 # number of overall MSHR misses 1473system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2356483739 # number of ReadReq MSHR miss cycles 1474system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2356483739 # number of ReadReq MSHR miss cycles 1475system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2388185713 # number of WriteReq MSHR miss cycles 1476system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2388185713 # number of WriteReq MSHR miss cycles 1477system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 637646247 # number of SoftPFReq MSHR miss cycles 1478system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 637646247 # number of SoftPFReq MSHR miss cycles 1479system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87580250 # number of LoadLockedReq MSHR miss cycles 1480system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87580250 # number of LoadLockedReq MSHR miss cycles 1481system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 501268882 # number of StoreCondReq MSHR miss cycles 1482system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 501268882 # number of StoreCondReq MSHR miss cycles 1483system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1557000 # number of StoreCondFailReq MSHR miss cycles 1484system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1557000 # number of StoreCondFailReq MSHR miss cycles 1485system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4744669452 # number of demand (read+write) MSHR miss cycles 1486system.cpu1.dcache.demand_mshr_miss_latency::total 4744669452 # number of demand (read+write) MSHR miss cycles 1487system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5382315699 # number of overall MSHR miss cycles 1488system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles 1489system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles 1490system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles 1491system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles 1492system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles 1493system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles 1494system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles 1495system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses 1496system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # mshr miss rate for ReadReq accesses 1497system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025358 # mshr miss rate for WriteReq accesses 1498system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025358 # mshr miss rate for WriteReq accesses 1499system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.357097 # mshr miss rate for SoftPFReq accesses 1500system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.357097 # mshr miss rate for SoftPFReq accesses 1501system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046177 # mshr miss rate for LoadLockedReq accesses 1502system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses 1503system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.186455 # mshr miss rate for StoreCondReq accesses 1504system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.186455 # mshr miss rate for StoreCondReq accesses 1505system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029941 # mshr miss rate for demand accesses 1506system.cpu1.dcache.demand_mshr_miss_rate::total 0.029941 # mshr miss rate for demand accesses 1507system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033579 # mshr miss rate for overall accesses 1508system.cpu1.dcache.overall_mshr_miss_rate::total 0.033579 # mshr miss rate for overall accesses 1509system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761 # average ReadReq mshr miss latency 1510system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761 # average ReadReq mshr miss latency 1511system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080 # average WriteReq mshr miss latency 1512system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080 # average WriteReq mshr miss latency 1513system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876 # average SoftPFReq mshr miss latency 1514system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876 # average SoftPFReq mshr miss latency 1515system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597 # average LoadLockedReq mshr miss latency 1516system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597 # average LoadLockedReq mshr miss latency 1517system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163 # average StoreCondReq mshr miss latency 1518system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163 # average StoreCondReq mshr miss latency |
| 1503system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1504system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1519system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1520system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1505system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency 1506system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency 1507system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency 1508system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency | 1521system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867 # average overall mshr miss latency 1522system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867 # average overall mshr miss latency 1523system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457 # average overall mshr miss latency 1524system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457 # average overall mshr miss latency |
| 1509system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1510system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1511system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1512system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1513system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1514system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1525system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1526system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1527system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1528system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1529system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1530system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1531system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1516system.cpu1.icache.tags.replacements 565004 # number of replacements 1517system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use 1518system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks. 1519system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks. 1520system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks. | 1532system.cpu1.icache.tags.replacements 680772 # number of replacements 1533system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use 1534system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. 1535system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. 1536system.cpu1.icache.tags.avg_refs 40.133533 # Average number of references to valid blocks. |
| 1521system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. | 1537system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. |
| 1522system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor 1523system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy 1524system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy | 1538system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.691095 # Average occupied blocks per requestor 1539system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974006 # Average percentage of cache occupancy 1540system.cpu1.icache.tags.occ_percent::total 0.974006 # Average percentage of cache occupancy |
| 1525system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1541system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1526system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id 1527system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id 1528system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id | 1542system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 1543system.cpu1.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 1544system.cpu1.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id |
| 1529system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1545system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1530system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses 1531system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses 1532system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits 1533system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits 1534system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits 1535system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits 1536system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits 1537system.cpu1.icache.overall_hits::total 20318443 # number of overall hits 1538system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses 1539system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses 1540system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses 1541system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses 1542system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses 1543system.cpu1.icache.overall_misses::total 565517 # number of overall misses 1544system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles 1545system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles 1546system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles 1547system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles 1548system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles 1549system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles 1550system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses) 1551system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses) 1552system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses 1553system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses 1554system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses 1555system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses 1556system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses 1557system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses 1558system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses 1559system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses 1560system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses 1561system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses 1562system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency 1563system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency 1564system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency 1565system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency 1566system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency 1567system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency | 1546system.cpu1.icache.tags.tag_accesses 56728523 # Number of tag accesses 1547system.cpu1.icache.tags.data_accesses 56728523 # Number of data accesses 1548system.cpu1.icache.ReadReq_hits::cpu1.inst 27342334 # number of ReadReq hits 1549system.cpu1.icache.ReadReq_hits::total 27342334 # number of ReadReq hits 1550system.cpu1.icache.demand_hits::cpu1.inst 27342334 # number of demand (read+write) hits 1551system.cpu1.icache.demand_hits::total 27342334 # number of demand (read+write) hits 1552system.cpu1.icache.overall_hits::cpu1.inst 27342334 # number of overall hits 1553system.cpu1.icache.overall_hits::total 27342334 # number of overall hits 1554system.cpu1.icache.ReadReq_misses::cpu1.inst 681285 # number of ReadReq misses 1555system.cpu1.icache.ReadReq_misses::total 681285 # number of ReadReq misses 1556system.cpu1.icache.demand_misses::cpu1.inst 681285 # number of demand (read+write) misses 1557system.cpu1.icache.demand_misses::total 681285 # number of demand (read+write) misses 1558system.cpu1.icache.overall_misses::cpu1.inst 681285 # number of overall misses 1559system.cpu1.icache.overall_misses::total 681285 # number of overall misses 1560system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5656981010 # number of ReadReq miss cycles 1561system.cpu1.icache.ReadReq_miss_latency::total 5656981010 # number of ReadReq miss cycles 1562system.cpu1.icache.demand_miss_latency::cpu1.inst 5656981010 # number of demand (read+write) miss cycles 1563system.cpu1.icache.demand_miss_latency::total 5656981010 # number of demand (read+write) miss cycles 1564system.cpu1.icache.overall_miss_latency::cpu1.inst 5656981010 # number of overall miss cycles 1565system.cpu1.icache.overall_miss_latency::total 5656981010 # number of overall miss cycles 1566system.cpu1.icache.ReadReq_accesses::cpu1.inst 28023619 # number of ReadReq accesses(hits+misses) 1567system.cpu1.icache.ReadReq_accesses::total 28023619 # number of ReadReq accesses(hits+misses) 1568system.cpu1.icache.demand_accesses::cpu1.inst 28023619 # number of demand (read+write) accesses 1569system.cpu1.icache.demand_accesses::total 28023619 # number of demand (read+write) accesses 1570system.cpu1.icache.overall_accesses::cpu1.inst 28023619 # number of overall (read+write) accesses 1571system.cpu1.icache.overall_accesses::total 28023619 # number of overall (read+write) accesses 1572system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024311 # miss rate for ReadReq accesses 1573system.cpu1.icache.ReadReq_miss_rate::total 0.024311 # miss rate for ReadReq accesses 1574system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024311 # miss rate for demand accesses 1575system.cpu1.icache.demand_miss_rate::total 0.024311 # miss rate for demand accesses 1576system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024311 # miss rate for overall accesses 1577system.cpu1.icache.overall_miss_rate::total 0.024311 # miss rate for overall accesses 1578system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8303.398739 # average ReadReq miss latency 1579system.cpu1.icache.ReadReq_avg_miss_latency::total 8303.398739 # average ReadReq miss latency 1580system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency 1581system.cpu1.icache.demand_avg_miss_latency::total 8303.398739 # average overall miss latency 1582system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency 1583system.cpu1.icache.overall_avg_miss_latency::total 8303.398739 # average overall miss latency |
| 1568system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1569system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1570system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1571system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1572system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1573system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1574system.cpu1.icache.fast_writes 0 # number of fast writes performed 1575system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1584system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1585system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1586system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1587system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1588system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1589system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1590system.cpu1.icache.fast_writes 0 # number of fast writes performed 1591system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1576system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses 1577system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses 1578system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses 1579system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses 1580system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses 1581system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses 1582system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles 1583system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles 1584system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles 1585system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles 1586system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles 1587system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles | 1592system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses 1593system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses 1594system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses 1595system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses 1596system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses 1597system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses 1598system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles 1599system.cpu1.icache.ReadReq_mshr_miss_latency::total 4634848490 # number of ReadReq MSHR miss cycles 1600system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4634848490 # number of demand (read+write) MSHR miss cycles 1601system.cpu1.icache.demand_mshr_miss_latency::total 4634848490 # number of demand (read+write) MSHR miss cycles 1602system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4634848490 # number of overall MSHR miss cycles 1603system.cpu1.icache.overall_mshr_miss_latency::total 4634848490 # number of overall MSHR miss cycles |
| 1588system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles 1589system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles 1590system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles 1591system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles | 1604system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles 1605system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles 1606system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles 1607system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles |
| 1592system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses 1593system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses 1594system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses 1595system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses 1596system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses 1597system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses 1598system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency 1599system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency 1600system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency 1601system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency 1602system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency 1603system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency | 1608system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for ReadReq accesses 1609system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024311 # mshr miss rate for ReadReq accesses 1610system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for demand accesses 1611system.cpu1.icache.demand_mshr_miss_rate::total 0.024311 # mshr miss rate for demand accesses 1612system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for overall accesses 1613system.cpu1.icache.overall_mshr_miss_rate::total 0.024311 # mshr miss rate for overall accesses 1614system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average ReadReq mshr miss latency 1615system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6803.097808 # average ReadReq mshr miss latency 1616system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency 1617system.cpu1.icache.demand_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency 1618system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency 1619system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency |
| 1604system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1605system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1606system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1607system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1608system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1620system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1621system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1622system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1623system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1624system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1609system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified 1610system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr 1611system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache 1612system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue | 1625system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified 1626system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr 1627system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache 1628system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue |
| 1613system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1629system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1614system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated 1615system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued 1616system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page | 1630system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated 1631system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued 1632system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page |
| 1617system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1633system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1618system.cpu1.l2cache.tags.replacements 85089 # number of replacements 1619system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use 1620system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks. 1621system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks. 1622system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks. 1623system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit. 1624system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor 1625system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor 1626system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor 1627system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor 1628system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor 1629system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor 1630system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy 1631system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 1632system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy 1633system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy 1634system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy 1635system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy 1636system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy 1637system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id 1638system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1639system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id 1640system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id 1641system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id 1642system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id 1643system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1644system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1645system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id 1646system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id 1647system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id 1648system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id 1649system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1650system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id 1651system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses 1652system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses 1653system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits 1654system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits 1655system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits 1656system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits 1657system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits 1658system.cpu1.l2cache.Writeback_hits::writebacks 135060 # number of Writeback hits 1659system.cpu1.l2cache.Writeback_hits::total 135060 # number of Writeback hits 1660system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1609 # number of UpgradeReq hits 1661system.cpu1.l2cache.UpgradeReq_hits::total 1609 # number of UpgradeReq hits 1662system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 861 # number of SCUpgradeReq hits 1663system.cpu1.l2cache.SCUpgradeReq_hits::total 861 # number of SCUpgradeReq hits 1664system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39179 # number of ReadExReq hits 1665system.cpu1.l2cache.ReadExReq_hits::total 39179 # number of ReadExReq hits 1666system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2996 # number of demand (read+write) hits 1667system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1704 # number of demand (read+write) hits 1668system.cpu1.l2cache.demand_hits::cpu1.inst 559876 # number of demand (read+write) hits 1669system.cpu1.l2cache.demand_hits::cpu1.data 162423 # number of demand (read+write) hits 1670system.cpu1.l2cache.demand_hits::total 726999 # number of demand (read+write) hits 1671system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2996 # number of overall hits 1672system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1704 # number of overall hits 1673system.cpu1.l2cache.overall_hits::cpu1.inst 559876 # number of overall hits 1674system.cpu1.l2cache.overall_hits::cpu1.data 162423 # number of overall hits 1675system.cpu1.l2cache.overall_hits::total 726999 # number of overall hits 1676system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses 1677system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses 1678system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5641 # number of ReadReq misses 1679system.cpu1.l2cache.ReadReq_misses::cpu1.data 70311 # number of ReadReq misses 1680system.cpu1.l2cache.ReadReq_misses::total 76567 # number of ReadReq misses 1681system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29399 # number of UpgradeReq misses 1682system.cpu1.l2cache.UpgradeReq_misses::total 29399 # number of UpgradeReq misses 1683system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22337 # number of SCUpgradeReq misses 1684system.cpu1.l2cache.SCUpgradeReq_misses::total 22337 # number of SCUpgradeReq misses 1685system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 1686system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1687system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33598 # number of ReadExReq misses 1688system.cpu1.l2cache.ReadExReq_misses::total 33598 # number of ReadExReq misses 1689system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses 1690system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses 1691system.cpu1.l2cache.demand_misses::cpu1.inst 5641 # number of demand (read+write) misses 1692system.cpu1.l2cache.demand_misses::cpu1.data 103909 # number of demand (read+write) misses 1693system.cpu1.l2cache.demand_misses::total 110165 # number of demand (read+write) misses 1694system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses 1695system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses 1696system.cpu1.l2cache.overall_misses::cpu1.inst 5641 # number of overall misses 1697system.cpu1.l2cache.overall_misses::cpu1.data 103909 # number of overall misses 1698system.cpu1.l2cache.overall_misses::total 110165 # number of overall misses 1699system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6952000 # number of ReadReq miss cycles 1700system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5546000 # number of ReadReq miss cycles 1701system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192723218 # number of ReadReq miss cycles 1702system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1546712890 # number of ReadReq miss cycles 1703system.cpu1.l2cache.ReadReq_miss_latency::total 1751934108 # number of ReadReq miss cycles 1704system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537154147 # number of UpgradeReq miss cycles 1705system.cpu1.l2cache.UpgradeReq_miss_latency::total 537154147 # number of UpgradeReq miss cycles 1706system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436854563 # number of SCUpgradeReq miss cycles 1707system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436854563 # number of SCUpgradeReq miss cycles 1708system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1562500 # number of SCUpgradeFailReq miss cycles 1709system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1562500 # number of SCUpgradeFailReq miss cycles 1710system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1072389357 # number of ReadExReq miss cycles 1711system.cpu1.l2cache.ReadExReq_miss_latency::total 1072389357 # number of ReadExReq miss cycles 1712system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6952000 # number of demand (read+write) miss cycles 1713system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5546000 # number of demand (read+write) miss cycles 1714system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192723218 # number of demand (read+write) miss cycles 1715system.cpu1.l2cache.demand_miss_latency::cpu1.data 2619102247 # number of demand (read+write) miss cycles 1716system.cpu1.l2cache.demand_miss_latency::total 2824323465 # number of demand (read+write) miss cycles 1717system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6952000 # number of overall miss cycles 1718system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5546000 # number of overall miss cycles 1719system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192723218 # number of overall miss cycles 1720system.cpu1.l2cache.overall_miss_latency::cpu1.data 2619102247 # number of overall miss cycles 1721system.cpu1.l2cache.overall_miss_latency::total 2824323465 # number of overall miss cycles 1722system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3334 # number of ReadReq accesses(hits+misses) 1723system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) 1724system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565517 # number of ReadReq accesses(hits+misses) 1725system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193555 # number of ReadReq accesses(hits+misses) 1726system.cpu1.l2cache.ReadReq_accesses::total 764387 # number of ReadReq accesses(hits+misses) 1727system.cpu1.l2cache.Writeback_accesses::writebacks 135060 # number of Writeback accesses(hits+misses) 1728system.cpu1.l2cache.Writeback_accesses::total 135060 # number of Writeback accesses(hits+misses) 1729system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31008 # number of UpgradeReq accesses(hits+misses) 1730system.cpu1.l2cache.UpgradeReq_accesses::total 31008 # number of UpgradeReq accesses(hits+misses) 1731system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23198 # number of SCUpgradeReq accesses(hits+misses) 1732system.cpu1.l2cache.SCUpgradeReq_accesses::total 23198 # number of SCUpgradeReq accesses(hits+misses) 1733system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1734system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1735system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72777 # number of ReadExReq accesses(hits+misses) 1736system.cpu1.l2cache.ReadExReq_accesses::total 72777 # number of ReadExReq accesses(hits+misses) 1737system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3334 # number of demand (read+write) accesses 1738system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses 1739system.cpu1.l2cache.demand_accesses::cpu1.inst 565517 # number of demand (read+write) accesses 1740system.cpu1.l2cache.demand_accesses::cpu1.data 266332 # number of demand (read+write) accesses 1741system.cpu1.l2cache.demand_accesses::total 837164 # number of demand (read+write) accesses 1742system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3334 # number of overall (read+write) accesses 1743system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses 1744system.cpu1.l2cache.overall_accesses::cpu1.inst 565517 # number of overall (read+write) accesses 1745system.cpu1.l2cache.overall_accesses::cpu1.data 266332 # number of overall (read+write) accesses 1746system.cpu1.l2cache.overall_accesses::total 837164 # number of overall (read+write) accesses 1747system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for ReadReq accesses 1748system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.139828 # miss rate for ReadReq accesses 1749system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009975 # miss rate for ReadReq accesses 1750system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363261 # miss rate for ReadReq accesses 1751system.cpu1.l2cache.ReadReq_miss_rate::total 0.100168 # miss rate for ReadReq accesses 1752system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.948110 # miss rate for UpgradeReq accesses 1753system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.948110 # miss rate for UpgradeReq accesses 1754system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962885 # miss rate for SCUpgradeReq accesses 1755system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962885 # miss rate for SCUpgradeReq accesses | 1634system.cpu1.l2cache.tags.replacements 130093 # number of replacements 1635system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use 1636system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. 1637system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. 1638system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. 1639system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1640system.cpu1.l2cache.tags.occ_blocks::writebacks 4806.943324 # Average occupied blocks per requestor 1641system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.120223 # Average occupied blocks per requestor 1642system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.343631 # Average occupied blocks per requestor 1643system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 874.835505 # Average occupied blocks per requestor 1644system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1500.703163 # Average occupied blocks per requestor 1645system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8425.517990 # Average occupied blocks per requestor 1646system.cpu1.l2cache.tags.occ_percent::writebacks 0.293393 # Average percentage of cache occupancy 1647system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy 1648system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000082 # Average percentage of cache occupancy 1649system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053396 # Average percentage of cache occupancy 1650system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091596 # Average percentage of cache occupancy 1651system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.514253 # Average percentage of cache occupancy 1652system.cpu1.l2cache.tags.occ_percent::total 0.952909 # Average percentage of cache occupancy 1653system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7913 # Occupied blocks per task id 1654system.cpu1.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 1655system.cpu1.l2cache.tags.occ_task_id_blocks::1024 8324 # Occupied blocks per task id 1656system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 47 # Occupied blocks per task id 1657system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id 1658system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id 1659system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id 1660system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id 1661system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 1662system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1663system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1664system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 1665system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 1666system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id 1667system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id 1668system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # Occupied blocks per task id 1669system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.482971 # Percentage of cache occupancy per task id 1670system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 1671system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.508057 # Percentage of cache occupancy per task id 1672system.cpu1.l2cache.tags.tag_accesses 21325891 # Number of tag accesses 1673system.cpu1.l2cache.tags.data_accesses 21325891 # Number of data accesses 1674system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5234 # number of ReadReq hits 1675system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2693 # number of ReadReq hits 1676system.cpu1.l2cache.ReadReq_hits::cpu1.inst 672894 # number of ReadReq hits 1677system.cpu1.l2cache.ReadReq_hits::cpu1.data 186024 # number of ReadReq hits 1678system.cpu1.l2cache.ReadReq_hits::total 866845 # number of ReadReq hits 1679system.cpu1.l2cache.Writeback_hits::writebacks 197265 # number of Writeback hits 1680system.cpu1.l2cache.Writeback_hits::total 197265 # number of Writeback hits 1681system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2024 # number of UpgradeReq hits 1682system.cpu1.l2cache.UpgradeReq_hits::total 2024 # number of UpgradeReq hits 1683system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1217 # number of SCUpgradeReq hits 1684system.cpu1.l2cache.SCUpgradeReq_hits::total 1217 # number of SCUpgradeReq hits 1685system.cpu1.l2cache.ReadExReq_hits::cpu1.data 69989 # number of ReadExReq hits 1686system.cpu1.l2cache.ReadExReq_hits::total 69989 # number of ReadExReq hits 1687system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5234 # number of demand (read+write) hits 1688system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2693 # number of demand (read+write) hits 1689system.cpu1.l2cache.demand_hits::cpu1.inst 672894 # number of demand (read+write) hits 1690system.cpu1.l2cache.demand_hits::cpu1.data 256013 # number of demand (read+write) hits 1691system.cpu1.l2cache.demand_hits::total 936834 # number of demand (read+write) hits 1692system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5234 # number of overall hits 1693system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2693 # number of overall hits 1694system.cpu1.l2cache.overall_hits::cpu1.inst 672894 # number of overall hits 1695system.cpu1.l2cache.overall_hits::cpu1.data 256013 # number of overall hits 1696system.cpu1.l2cache.overall_hits::total 936834 # number of overall hits 1697system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 261 # number of ReadReq misses 1698system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 216 # number of ReadReq misses 1699system.cpu1.l2cache.ReadReq_misses::cpu1.inst 8391 # number of ReadReq misses 1700system.cpu1.l2cache.ReadReq_misses::cpu1.data 76389 # number of ReadReq misses 1701system.cpu1.l2cache.ReadReq_misses::total 85257 # number of ReadReq misses 1702system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29955 # number of UpgradeReq misses 1703system.cpu1.l2cache.UpgradeReq_misses::total 29955 # number of UpgradeReq misses 1704system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22648 # number of SCUpgradeReq misses 1705system.cpu1.l2cache.SCUpgradeReq_misses::total 22648 # number of SCUpgradeReq misses 1706system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 1707system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1708system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36116 # number of ReadExReq misses 1709system.cpu1.l2cache.ReadExReq_misses::total 36116 # number of ReadExReq misses 1710system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 261 # number of demand (read+write) misses 1711system.cpu1.l2cache.demand_misses::cpu1.itb.walker 216 # number of demand (read+write) misses 1712system.cpu1.l2cache.demand_misses::cpu1.inst 8391 # number of demand (read+write) misses 1713system.cpu1.l2cache.demand_misses::cpu1.data 112505 # number of demand (read+write) misses 1714system.cpu1.l2cache.demand_misses::total 121373 # number of demand (read+write) misses 1715system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 261 # number of overall misses 1716system.cpu1.l2cache.overall_misses::cpu1.itb.walker 216 # number of overall misses 1717system.cpu1.l2cache.overall_misses::cpu1.inst 8391 # number of overall misses 1718system.cpu1.l2cache.overall_misses::cpu1.data 112505 # number of overall misses 1719system.cpu1.l2cache.overall_misses::total 121373 # number of overall misses 1720system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5754999 # number of ReadReq miss cycles 1721system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4668500 # number of ReadReq miss cycles 1722system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 255474477 # number of ReadReq miss cycles 1723system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1702549656 # number of ReadReq miss cycles 1724system.cpu1.l2cache.ReadReq_miss_latency::total 1968447632 # number of ReadReq miss cycles 1725system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 542491459 # number of UpgradeReq miss cycles 1726system.cpu1.l2cache.UpgradeReq_miss_latency::total 542491459 # number of UpgradeReq miss cycles 1727system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 444517157 # number of SCUpgradeReq miss cycles 1728system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 444517157 # number of SCUpgradeReq miss cycles 1729system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1522000 # number of SCUpgradeFailReq miss cycles 1730system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1522000 # number of SCUpgradeFailReq miss cycles 1731system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1159011538 # number of ReadExReq miss cycles 1732system.cpu1.l2cache.ReadExReq_miss_latency::total 1159011538 # number of ReadExReq miss cycles 1733system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5754999 # number of demand (read+write) miss cycles 1734system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4668500 # number of demand (read+write) miss cycles 1735system.cpu1.l2cache.demand_miss_latency::cpu1.inst 255474477 # number of demand (read+write) miss cycles 1736system.cpu1.l2cache.demand_miss_latency::cpu1.data 2861561194 # number of demand (read+write) miss cycles 1737system.cpu1.l2cache.demand_miss_latency::total 3127459170 # number of demand (read+write) miss cycles 1738system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5754999 # number of overall miss cycles 1739system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4668500 # number of overall miss cycles 1740system.cpu1.l2cache.overall_miss_latency::cpu1.inst 255474477 # number of overall miss cycles 1741system.cpu1.l2cache.overall_miss_latency::cpu1.data 2861561194 # number of overall miss cycles 1742system.cpu1.l2cache.overall_miss_latency::total 3127459170 # number of overall miss cycles 1743system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 5495 # number of ReadReq accesses(hits+misses) 1744system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2909 # number of ReadReq accesses(hits+misses) 1745system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 681285 # number of ReadReq accesses(hits+misses) 1746system.cpu1.l2cache.ReadReq_accesses::cpu1.data 262413 # number of ReadReq accesses(hits+misses) 1747system.cpu1.l2cache.ReadReq_accesses::total 952102 # number of ReadReq accesses(hits+misses) 1748system.cpu1.l2cache.Writeback_accesses::writebacks 197265 # number of Writeback accesses(hits+misses) 1749system.cpu1.l2cache.Writeback_accesses::total 197265 # number of Writeback accesses(hits+misses) 1750system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31979 # number of UpgradeReq accesses(hits+misses) 1751system.cpu1.l2cache.UpgradeReq_accesses::total 31979 # number of UpgradeReq accesses(hits+misses) 1752system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23865 # number of SCUpgradeReq accesses(hits+misses) 1753system.cpu1.l2cache.SCUpgradeReq_accesses::total 23865 # number of SCUpgradeReq accesses(hits+misses) 1754system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1755system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1756system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 106105 # number of ReadExReq accesses(hits+misses) 1757system.cpu1.l2cache.ReadExReq_accesses::total 106105 # number of ReadExReq accesses(hits+misses) 1758system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 5495 # number of demand (read+write) accesses 1759system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2909 # number of demand (read+write) accesses 1760system.cpu1.l2cache.demand_accesses::cpu1.inst 681285 # number of demand (read+write) accesses 1761system.cpu1.l2cache.demand_accesses::cpu1.data 368518 # number of demand (read+write) accesses 1762system.cpu1.l2cache.demand_accesses::total 1058207 # number of demand (read+write) accesses 1763system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 5495 # number of overall (read+write) accesses 1764system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2909 # number of overall (read+write) accesses 1765system.cpu1.l2cache.overall_accesses::cpu1.inst 681285 # number of overall (read+write) accesses 1766system.cpu1.l2cache.overall_accesses::cpu1.data 368518 # number of overall (read+write) accesses 1767system.cpu1.l2cache.overall_accesses::total 1058207 # number of overall (read+write) accesses 1768system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for ReadReq accesses 1769system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.074252 # miss rate for ReadReq accesses 1770system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.012316 # miss rate for ReadReq accesses 1771system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.291102 # miss rate for ReadReq accesses 1772system.cpu1.l2cache.ReadReq_miss_rate::total 0.089546 # miss rate for ReadReq accesses 1773system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936708 # miss rate for UpgradeReq accesses 1774system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936708 # miss rate for UpgradeReq accesses 1775system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.949005 # miss rate for SCUpgradeReq accesses 1776system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.949005 # miss rate for SCUpgradeReq accesses |
| 1756system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1757system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1777system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1778system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1758system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.461657 # miss rate for ReadExReq accesses 1759system.cpu1.l2cache.ReadExReq_miss_rate::total 0.461657 # miss rate for ReadExReq accesses 1760system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for demand accesses 1761system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.139828 # miss rate for demand accesses 1762system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009975 # miss rate for demand accesses 1763system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.390148 # miss rate for demand accesses 1764system.cpu1.l2cache.demand_miss_rate::total 0.131593 # miss rate for demand accesses 1765system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for overall accesses 1766system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.139828 # miss rate for overall accesses 1767system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009975 # miss rate for overall accesses 1768system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.390148 # miss rate for overall accesses 1769system.cpu1.l2cache.overall_miss_rate::total 0.131593 # miss rate for overall accesses 1770system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average ReadReq miss latency 1771system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650 # average ReadReq miss latency 1772system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758 # average ReadReq miss latency 1773system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730 # average ReadReq miss latency 1774system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830 # average ReadReq miss latency 1775system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686 # average UpgradeReq miss latency 1776system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686 # average UpgradeReq miss latency 1777system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151 # average SCUpgradeReq miss latency 1778system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151 # average SCUpgradeReq miss latency 1779system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714 # average SCUpgradeFailReq miss latency 1780system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714 # average SCUpgradeFailReq miss latency 1781system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807 # average ReadExReq miss latency 1782system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807 # average ReadExReq miss latency 1783system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency 1784system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency 1785system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency 1786system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency 1787system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046 # average overall miss latency 1788system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency 1789system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency 1790system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency 1791system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency 1792system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046 # average overall miss latency 1793system.cpu1.l2cache.blocked_cycles::no_mshrs 1642 # number of cycles access was blocked | 1779system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.340380 # miss rate for ReadExReq accesses 1780system.cpu1.l2cache.ReadExReq_miss_rate::total 0.340380 # miss rate for ReadExReq accesses 1781system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for demand accesses 1782system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.074252 # miss rate for demand accesses 1783system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.012316 # miss rate for demand accesses 1784system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.305290 # miss rate for demand accesses 1785system.cpu1.l2cache.demand_miss_rate::total 0.114697 # miss rate for demand accesses 1786system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for overall accesses 1787system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.074252 # miss rate for overall accesses 1788system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.012316 # miss rate for overall accesses 1789system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.305290 # miss rate for overall accesses 1790system.cpu1.l2cache.overall_miss_rate::total 0.114697 # miss rate for overall accesses 1791system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22049.804598 # average ReadReq miss latency 1792system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21613.425926 # average ReadReq miss latency 1793system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30446.249196 # average ReadReq miss latency 1794system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22287.890351 # average ReadReq miss latency 1795system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23088.398982 # average ReadReq miss latency 1796system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18110.213954 # average UpgradeReq miss latency 1797system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18110.213954 # average UpgradeReq miss latency 1798system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19627.214633 # average SCUpgradeReq miss latency 1799system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19627.214633 # average SCUpgradeReq miss latency 1800system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 304400 # average SCUpgradeFailReq miss latency 1801system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 304400 # average SCUpgradeFailReq miss latency 1802system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32091.359453 # average ReadExReq miss latency 1803system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32091.359453 # average ReadExReq miss latency 1804system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22049.804598 # average overall miss latency 1805system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21613.425926 # average overall miss latency 1806system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30446.249196 # average overall miss latency 1807system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25434.969059 # average overall miss latency 1808system.cpu1.l2cache.demand_avg_miss_latency::total 25767.338453 # average overall miss latency 1809system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22049.804598 # average overall miss latency 1810system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21613.425926 # average overall miss latency 1811system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30446.249196 # average overall miss latency 1812system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25434.969059 # average overall miss latency 1813system.cpu1.l2cache.overall_avg_miss_latency::total 25767.338453 # average overall miss latency 1814system.cpu1.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked |
| 1794system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1815system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1795system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked | 1816system.cpu1.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked |
| 1796system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1817system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1797system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.914286 # average number of cycles each access was blocked | 1818system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 31.794118 # average number of cycles each access was blocked |
| 1798system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1799system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1800system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1819system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1820system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1821system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1801system.cpu1.l2cache.writebacks::writebacks 35198 # number of writebacks 1802system.cpu1.l2cache.writebacks::total 35198 # number of writebacks 1803system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 739 # number of ReadReq MSHR hits 1804system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 100 # number of ReadReq MSHR hits 1805system.cpu1.l2cache.ReadReq_mshr_hits::total 839 # number of ReadReq MSHR hits 1806system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 193 # number of ReadExReq MSHR hits 1807system.cpu1.l2cache.ReadExReq_mshr_hits::total 193 # number of ReadExReq MSHR hits 1808system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 739 # number of demand (read+write) MSHR hits 1809system.cpu1.l2cache.demand_mshr_hits::cpu1.data 293 # number of demand (read+write) MSHR hits 1810system.cpu1.l2cache.demand_mshr_hits::total 1032 # number of demand (read+write) MSHR hits 1811system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 739 # number of overall MSHR hits 1812system.cpu1.l2cache.overall_mshr_hits::cpu1.data 293 # number of overall MSHR hits 1813system.cpu1.l2cache.overall_mshr_hits::total 1032 # number of overall MSHR hits 1814system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 338 # number of ReadReq MSHR misses 1815system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses 1816system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4902 # number of ReadReq MSHR misses 1817system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70211 # number of ReadReq MSHR misses 1818system.cpu1.l2cache.ReadReq_mshr_misses::total 75728 # number of ReadReq MSHR misses 1819system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of HardPFReq MSHR misses 1820system.cpu1.l2cache.HardPFReq_mshr_misses::total 119097 # number of HardPFReq MSHR misses 1821system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29399 # number of UpgradeReq MSHR misses 1822system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29399 # number of UpgradeReq MSHR misses 1823system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22337 # number of SCUpgradeReq MSHR misses 1824system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22337 # number of SCUpgradeReq MSHR misses 1825system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses 1826system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1827system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33405 # number of ReadExReq MSHR misses 1828system.cpu1.l2cache.ReadExReq_mshr_misses::total 33405 # number of ReadExReq MSHR misses 1829system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 338 # number of demand (read+write) MSHR misses 1830system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses 1831system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4902 # number of demand (read+write) MSHR misses 1832system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103616 # number of demand (read+write) MSHR misses 1833system.cpu1.l2cache.demand_mshr_misses::total 109133 # number of demand (read+write) MSHR misses 1834system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 338 # number of overall MSHR misses 1835system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses 1836system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4902 # number of overall MSHR misses 1837system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103616 # number of overall MSHR misses 1838system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of overall MSHR misses 1839system.cpu1.l2cache.overall_mshr_misses::total 228230 # number of overall MSHR misses 1840system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of ReadReq MSHR miss cycles 1841system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3607000 # number of ReadReq MSHR miss cycles 1842system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143902025 # number of ReadReq MSHR miss cycles 1843system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1053014200 # number of ReadReq MSHR miss cycles 1844system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1205109225 # number of ReadReq MSHR miss cycles 1845system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of HardPFReq MSHR miss cycles 1846system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3247389638 # number of HardPFReq MSHR miss cycles 1847system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430450689 # number of UpgradeReq MSHR miss cycles 1848system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430450689 # number of UpgradeReq MSHR miss cycles 1849system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306453691 # number of SCUpgradeReq MSHR miss cycles 1850system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306453691 # number of SCUpgradeReq MSHR miss cycles 1851system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1303500 # number of SCUpgradeFailReq MSHR miss cycles 1852system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1303500 # number of SCUpgradeFailReq MSHR miss cycles 1853system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820460623 # number of ReadExReq MSHR miss cycles 1854system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820460623 # number of ReadExReq MSHR miss cycles 1855system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of demand (read+write) MSHR miss cycles 1856system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3607000 # number of demand (read+write) MSHR miss cycles 1857system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143902025 # number of demand (read+write) MSHR miss cycles 1858system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1873474823 # number of demand (read+write) MSHR miss cycles 1859system.cpu1.l2cache.demand_mshr_miss_latency::total 2025569848 # number of demand (read+write) MSHR miss cycles 1860system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of overall MSHR miss cycles 1861system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3607000 # number of overall MSHR miss cycles 1862system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143902025 # number of overall MSHR miss cycles 1863system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1873474823 # number of overall MSHR miss cycles 1864system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of overall MSHR miss cycles 1865system.cpu1.l2cache.overall_mshr_miss_latency::total 5272959486 # number of overall MSHR miss cycles | 1822system.cpu1.l2cache.writebacks::writebacks 47807 # number of writebacks 1823system.cpu1.l2cache.writebacks::total 47807 # number of writebacks 1824system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1186 # number of ReadReq MSHR hits 1825system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 145 # number of ReadReq MSHR hits 1826system.cpu1.l2cache.ReadReq_mshr_hits::total 1331 # number of ReadReq MSHR hits 1827system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 387 # number of ReadExReq MSHR hits 1828system.cpu1.l2cache.ReadExReq_mshr_hits::total 387 # number of ReadExReq MSHR hits 1829system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1186 # number of demand (read+write) MSHR hits 1830system.cpu1.l2cache.demand_mshr_hits::cpu1.data 532 # number of demand (read+write) MSHR hits 1831system.cpu1.l2cache.demand_mshr_hits::total 1718 # number of demand (read+write) MSHR hits 1832system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1186 # number of overall MSHR hits 1833system.cpu1.l2cache.overall_mshr_hits::cpu1.data 532 # number of overall MSHR hits 1834system.cpu1.l2cache.overall_mshr_hits::total 1718 # number of overall MSHR hits 1835system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 261 # number of ReadReq MSHR misses 1836system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 216 # number of ReadReq MSHR misses 1837system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 7205 # number of ReadReq MSHR misses 1838system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 76244 # number of ReadReq MSHR misses 1839system.cpu1.l2cache.ReadReq_mshr_misses::total 83926 # number of ReadReq MSHR misses 1840system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 158839 # number of HardPFReq MSHR misses 1841system.cpu1.l2cache.HardPFReq_mshr_misses::total 158839 # number of HardPFReq MSHR misses 1842system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29955 # number of UpgradeReq MSHR misses 1843system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29955 # number of UpgradeReq MSHR misses 1844system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22648 # number of SCUpgradeReq MSHR misses 1845system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22648 # number of SCUpgradeReq MSHR misses 1846system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 1847system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1848system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35729 # number of ReadExReq MSHR misses 1849system.cpu1.l2cache.ReadExReq_mshr_misses::total 35729 # number of ReadExReq MSHR misses 1850system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 261 # number of demand (read+write) MSHR misses 1851system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 216 # number of demand (read+write) MSHR misses 1852system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 7205 # number of demand (read+write) MSHR misses 1853system.cpu1.l2cache.demand_mshr_misses::cpu1.data 111973 # number of demand (read+write) MSHR misses 1854system.cpu1.l2cache.demand_mshr_misses::total 119655 # number of demand (read+write) MSHR misses 1855system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 261 # number of overall MSHR misses 1856system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 216 # number of overall MSHR misses 1857system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 7205 # number of overall MSHR misses 1858system.cpu1.l2cache.overall_mshr_misses::cpu1.data 111973 # number of overall MSHR misses 1859system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 158839 # number of overall MSHR misses 1860system.cpu1.l2cache.overall_mshr_misses::total 278494 # number of overall MSHR misses 1861system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3927001 # number of ReadReq MSHR miss cycles 1862system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3156500 # number of ReadReq MSHR miss cycles 1863system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 186017515 # number of ReadReq MSHR miss cycles 1864system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1165742936 # number of ReadReq MSHR miss cycles 1865system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1358843952 # number of ReadReq MSHR miss cycles 1866system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 4336083136 # number of HardPFReq MSHR miss cycles 1867system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 4336083136 # number of HardPFReq MSHR miss cycles 1868system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 450926825 # number of UpgradeReq MSHR miss cycles 1869system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 450926825 # number of UpgradeReq MSHR miss cycles 1870system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 312179089 # number of SCUpgradeReq MSHR miss cycles 1871system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 312179089 # number of SCUpgradeReq MSHR miss cycles 1872system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1277000 # number of SCUpgradeFailReq MSHR miss cycles 1873system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1277000 # number of SCUpgradeFailReq MSHR miss cycles 1874system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 867144190 # number of ReadExReq MSHR miss cycles 1875system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 867144190 # number of ReadExReq MSHR miss cycles 1876system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 3927001 # number of demand (read+write) MSHR miss cycles 1877system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3156500 # number of demand (read+write) MSHR miss cycles 1878system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 186017515 # number of demand (read+write) MSHR miss cycles 1879system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2032887126 # number of demand (read+write) MSHR miss cycles 1880system.cpu1.l2cache.demand_mshr_miss_latency::total 2225988142 # number of demand (read+write) MSHR miss cycles 1881system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 3927001 # number of overall MSHR miss cycles 1882system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3156500 # number of overall MSHR miss cycles 1883system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 186017515 # number of overall MSHR miss cycles 1884system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2032887126 # number of overall MSHR miss cycles 1885system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 4336083136 # number of overall MSHR miss cycles 1886system.cpu1.l2cache.overall_mshr_miss_latency::total 6562071278 # number of overall MSHR miss cycles |
| 1866system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles | 1887system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles |
| 1867system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles 1868system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles 1869system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles 1870system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles | 1888system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 923111999 # number of ReadReq MSHR uncacheable cycles 1889system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 935587499 # number of ReadReq MSHR uncacheable cycles 1890system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 807820502 # number of WriteReq MSHR uncacheable cycles 1891system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 807820502 # number of WriteReq MSHR uncacheable cycles |
| 1871system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles | 1892system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles |
| 1872system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles 1873system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles 1874system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses 1875system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses 1876system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses 1877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses 1878system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses | 1893system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1730932501 # number of overall MSHR uncacheable cycles 1894system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1743408001 # number of overall MSHR uncacheable cycles 1895system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for ReadReq accesses 1896system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for ReadReq accesses 1897system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for ReadReq accesses 1898system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.290550 # mshr miss rate for ReadReq accesses 1899system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.088148 # mshr miss rate for ReadReq accesses |
| 1879system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1880system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1900system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1901system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1881system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses 1882system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses 1883system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses 1884system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses | 1902system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936708 # mshr miss rate for UpgradeReq accesses 1903system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936708 # mshr miss rate for UpgradeReq accesses 1904system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949005 # mshr miss rate for SCUpgradeReq accesses 1905system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.949005 # mshr miss rate for SCUpgradeReq accesses |
| 1885system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1886system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1906system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1907system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1887system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses 1888system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses 1889system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses 1890system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses 1891system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses 1892system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses 1893system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses 1894system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses 1895system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses 1896system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses 1897system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses | 1908system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.336732 # mshr miss rate for ReadExReq accesses 1909system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.336732 # mshr miss rate for ReadExReq accesses 1910system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for demand accesses 1911system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for demand accesses 1912system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for demand accesses 1913system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for demand accesses 1914system.cpu1.l2cache.demand_mshr_miss_rate::total 0.113073 # mshr miss rate for demand accesses 1915system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for overall accesses 1916system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for overall accesses 1917system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for overall accesses 1918system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for overall accesses |
| 1898system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1919system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1899system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses 1900system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency 1901system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency 1902system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency 1903system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency 1904system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency 1905system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency 1906system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency 1907system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency 1908system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency 1909system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency 1910system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency 1911system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency 1912system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency 1913system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency 1914system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency 1915system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency 1916system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency 1917system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency 1918system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency 1919system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency 1920system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency 1921system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency 1922system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency 1923system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency 1924system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency 1925system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency | 1920system.cpu1.l2cache.overall_mshr_miss_rate::total 0.263175 # mshr miss rate for overall accesses 1921system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average ReadReq mshr miss latency 1922system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average ReadReq mshr miss latency 1923system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average ReadReq mshr miss latency 1924system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066 # average ReadReq mshr miss latency 1925system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194 # average ReadReq mshr miss latency 1926system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average HardPFReq mshr miss latency 1927system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103 # average HardPFReq mshr miss latency 1928system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378 # average UpgradeReq mshr miss latency 1929system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378 # average UpgradeReq mshr miss latency 1930system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363 # average SCUpgradeReq mshr miss latency 1931system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363 # average SCUpgradeReq mshr miss latency 1932system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 255400 # average SCUpgradeFailReq mshr miss latency 1933system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 255400 # average SCUpgradeFailReq mshr miss latency 1934system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064 # average ReadExReq mshr miss latency 1935system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064 # average ReadExReq mshr miss latency 1936system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency 1937system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency 1938system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency 1939system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency 1940system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency 1941system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency 1942system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency 1943system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency 1944system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency 1945system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency 1946system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency |
| 1926system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1927system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1928system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1929system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1930system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1931system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1932system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1933system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1934system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1947system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1948system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1949system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1950system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1951system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1952system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1953system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1954system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1955system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1935system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution 1936system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution 1937system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution 1938system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution 1939system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution 1940system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution 1941system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 1942system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution 1943system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution 1944system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution 1945system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 1946system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 1947system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution 1948system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution 1949system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes) 1950system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes) 1951system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) 1952system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes) 1953system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes) 1954system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes) 1955system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes) 1956system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) 1957system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes) 1958system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes) 1959system.cpu1.toL2Bus.snoops 818999 # Total snoops (count) 1960system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram 1961system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram 1962system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram | 1956system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution 1957system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution 1958system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution 1959system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution 1960system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution 1961system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution 1962system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1963system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution 1964system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution 1965system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution 1966system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 1967system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution 1968system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution 1969system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution 1970system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) 1971system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) 1972system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) 1973system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) 1974system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) 1975system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) 1976system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) 1977system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) 1978system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) 1979system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) 1980system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) 1981system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram 1982system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram 1983system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram |
| 1963system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1964system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1965system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1966system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1967system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1968system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1984system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1985system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1986system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1987system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1988system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1989system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1969system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram 1970system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram | 1990system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram 1991system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram |
| 1971system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1972system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1973system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1992system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1993system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1994system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1974system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram 1975system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks) | 1995system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram 1996system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) |
| 1976system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1997system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1977system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks) | 1998system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) |
| 1978system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1999system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1979system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks) | 2000system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) |
| 1980system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2001system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1981system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks) | 2002system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) |
| 1982system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2003system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1983system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks) | 2004system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) |
| 1984system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2005system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1985system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks) | 2006system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) |
| 1986system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2007system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1987system.iobus.trans_dist::ReadReq 31019 # Transaction distribution 1988system.iobus.trans_dist::ReadResp 31019 # Transaction distribution 1989system.iobus.trans_dist::WriteReq 59407 # Transaction distribution 1990system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1991system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution 1992system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) | 2008system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2009system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2010system.iobus.trans_dist::WriteReq 59437 # Transaction distribution 2011system.iobus.trans_dist::WriteResp 23213 # Transaction distribution 2012system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2013system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) |
| 1993system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1994system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1995system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1996system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1997system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 1998system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1999system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2000system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2005system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2006system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2007system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2008system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2009system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2010system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2011system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2012system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2014system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2015system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2016system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2017system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2018system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 2019system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2020system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2021system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2026system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2027system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2028system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2029system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2030system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2031system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2032system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2033system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2013system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) | 2034system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) |
| 2014system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) 2015system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) | 2035system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) 2036system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) |
| 2016system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) 2017system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) | 2037system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) 2038system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) |
| 2018system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2019system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2020system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2021system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2022system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) 2023system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2024system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2025system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2030system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2031system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2032system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2033system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2034system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2035system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2036system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2037system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2039system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2040system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2041system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2042system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2043system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) 2044system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2045system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2046system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 2051system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2052system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2053system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2054system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2055system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2056system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2057system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2058system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2038system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) | 2059system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) |
| 2039system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) 2040system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) | 2060system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) 2061system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) |
| 2041system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) 2042system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) | 2062system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) 2063system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) |
| 2043system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2044system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2045system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2046system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2047system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2048system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2049system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2050system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2074system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2075system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2076system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2077system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2078system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2079system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2080system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2081system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2064system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2065system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2066system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2067system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2068system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2069system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2070system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2071system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 2095system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2096system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2097system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2098system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2099system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2100system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2101system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2102system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2082system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks) | 2103system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) |
| 2083system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2084system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2085system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2104system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2105system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2106system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2086system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) | 2107system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) |
| 2087system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2108system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2088system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks) | 2109system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) |
| 2089system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2110system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2090system.iocache.tags.replacements 36443 # number of replacements 2091system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use | 2111system.iocache.tags.replacements 36459 # number of replacements 2112system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use |
| 2092system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2113system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2093system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. | 2114system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. |
| 2094system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 2115system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 2095system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit. 2096system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor 2097system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy 2098system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy | 2116system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. 2117system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor 2118system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy 2119system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy |
| 2099system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2100system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2101system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2120system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2121system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2122system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2102system.iocache.tags.tag_accesses 328557 # Number of tag accesses 2103system.iocache.tags.data_accesses 328557 # Number of data accesses 2104system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2105system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits | 2123system.iocache.tags.tag_accesses 328293 # Number of tag accesses 2124system.iocache.tags.data_accesses 328293 # Number of data accesses |
| 2106system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2107system.iocache.ReadReq_misses::total 253 # number of ReadReq misses | 2125system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2126system.iocache.ReadReq_misses::total 253 # number of ReadReq misses |
| 2108system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses 2109system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses | 2127system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 2128system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
| 2110system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2111system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2112system.iocache.overall_misses::realview.ide 253 # number of overall misses 2113system.iocache.overall_misses::total 253 # number of overall misses | 2129system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2130system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2131system.iocache.overall_misses::realview.ide 253 # number of overall misses 2132system.iocache.overall_misses::total 253 # number of overall misses |
| 2114system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles 2115system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles 2116system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles 2117system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles 2118system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles 2119system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles | 2133system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles 2134system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles 2135system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles 2136system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles 2137system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles 2138system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles 2139system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles 2140system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles |
| 2120system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2121system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) | 2141system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2142system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) |
| 2122system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) 2123system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) | 2143system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 2144system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 2124system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2125system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2126system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2127system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2128system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2129system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 2145system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2146system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2147system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2148system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2149system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2150system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 2130system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses 2131system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses | 2151system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2152system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
| 2132system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2133system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2134system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2135system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2153system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2154system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2155system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2156system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2136system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency 2137system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency 2138system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2139system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency 2140system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2141system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency 2142system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 2157system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency 2158system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency 2159system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency 2160system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency 2161system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency 2162system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency 2163system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency 2164system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency 2165system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked |
| 2143system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2166system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2144system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 2167system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked |
| 2145system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2168system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2146system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 2169system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked |
| 2147system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2170system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2148system.iocache.fast_writes 36224 # number of fast writes performed | 2171system.iocache.fast_writes 0 # number of fast writes performed |
| 2149system.iocache.cache_copies 0 # number of cache copies performed | 2172system.iocache.cache_copies 0 # number of cache copies performed |
| 2173system.iocache.writebacks::writebacks 36206 # number of writebacks 2174system.iocache.writebacks::total 36206 # number of writebacks |
|
| 2150system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2151system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses | 2175system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2176system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses |
| 2177system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 2178system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
|
| 2152system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2153system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2154system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2155system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses | 2179system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2180system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2181system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2182system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses |
| 2156system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles 2157system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles 2158system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles 2159system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles 2160system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles 2161system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles 2162system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles 2163system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles | 2183system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles 2184system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles 2185system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles 2186system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles 2187system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles 2188system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles 2189system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles 2190system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles |
| 2164system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2165system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 2191system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2192system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 2193system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2194system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
|
| 2166system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2167system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2168system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2169system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2195system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2196system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2197system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2198system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2170system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency 2171system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency 2172system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2173system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2174system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2175system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency 2176system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2177system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency | 2199system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency 2200system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency 2201system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency 2202system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency 2203system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency 2204system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency 2205system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency 2206system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency |
| 2178system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2207system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2179system.l2c.tags.replacements 132935 # number of replacements 2180system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use 2181system.l2c.tags.total_refs 488817 # Total number of references to valid blocks. 2182system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks. 2183system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks. | 2208system.l2c.tags.replacements 132552 # number of replacements 2209system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use 2210system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. 2211system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. 2212system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. |
| 2184system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 2213system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 2185system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor 2186system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor 2187system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor 2188system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor 2189system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor 2190system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor 2191system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor 2192system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor 2193system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor 2194system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor 2195system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor 2196system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy | 2214system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor 2215system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor 2216system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor 2217system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor 2218system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor 2219system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor 2220system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor 2221system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor 2222system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor 2223system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor 2224system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor 2225system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy |
| 2197system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy 2198system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy | 2226system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy 2227system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy |
| 2199system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy 2200system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy 2201system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy | 2228system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy 2229system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy 2230system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy |
| 2202system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy 2203system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy | 2231system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy 2232system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy |
| 2204system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy 2205system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy 2206system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy 2207system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy 2208system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id 2209system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 2210system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id 2211system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 2212system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id 2213system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id 2214system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 2215system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 2216system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 2217system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id 2218system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id 2219system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id 2220system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 2221system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id 2222system.l2c.tags.tag_accesses 6143442 # Number of tag accesses 2223system.l2c.tags.data_accesses 6143442 # Number of data accesses 2224system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits 2225system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits 2226system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits 2227system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits 2228system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits 2229system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits 2230system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits 2231system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits 2232system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits 2233system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits 2234system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits 2235system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits 2236system.l2c.Writeback_hits::total 240423 # number of Writeback hits 2237system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits 2238system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits 2239system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits 2240system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits 2241system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits 2242system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits 2243system.l2c.ReadExReq_hits::cpu0.data 4104 # number of ReadExReq hits 2244system.l2c.ReadExReq_hits::cpu1.data 2566 # number of ReadExReq hits 2245system.l2c.ReadExReq_hits::total 6670 # number of ReadExReq hits 2246system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits 2247system.l2c.demand_hits::cpu0.itb.walker 155 # number of demand (read+write) hits 2248system.l2c.demand_hits::cpu0.inst 10201 # number of demand (read+write) hits 2249system.l2c.demand_hits::cpu0.data 33543 # number of demand (read+write) hits 2250system.l2c.demand_hits::cpu0.l2cache.prefetcher 168037 # number of demand (read+write) hits 2251system.l2c.demand_hits::cpu1.dtb.walker 53 # number of demand (read+write) hits 2252system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits 2253system.l2c.demand_hits::cpu1.inst 4112 # number of demand (read+write) hits 2254system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits 2255system.l2c.demand_hits::cpu1.l2cache.prefetcher 47653 # number of demand (read+write) hits 2256system.l2c.demand_hits::total 276883 # number of demand (read+write) hits 2257system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits 2258system.l2c.overall_hits::cpu0.itb.walker 155 # number of overall hits 2259system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits 2260system.l2c.overall_hits::cpu0.data 33543 # number of overall hits 2261system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits 2262system.l2c.overall_hits::cpu1.dtb.walker 53 # number of overall hits 2263system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits 2264system.l2c.overall_hits::cpu1.inst 4112 # number of overall hits 2265system.l2c.overall_hits::cpu1.data 12939 # number of overall hits 2266system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits 2267system.l2c.overall_hits::total 276883 # number of overall hits | 2233system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy 2234system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy 2235system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy 2236system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy 2237system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id 2238system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2239system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id 2240system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id 2241system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id 2242system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id 2243system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2244system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2245system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 2246system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id 2247system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id 2248system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id 2249system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id 2250system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2251system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id 2252system.l2c.tags.tag_accesses 6110572 # Number of tag accesses 2253system.l2c.tags.data_accesses 6110572 # Number of data accesses 2254system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits 2255system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits 2256system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits 2257system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits 2258system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits 2259system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits 2260system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits 2261system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits 2262system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits 2263system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits 2264system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits 2265system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits 2266system.l2c.Writeback_hits::total 239712 # number of Writeback hits 2267system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits 2268system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits 2269system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits 2270system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits 2271system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits 2272system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits 2273system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits 2274system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits 2275system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits 2276system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits 2277system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits 2278system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits 2279system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits 2280system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits 2281system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits 2282system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits 2283system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits 2284system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits 2285system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits 2286system.l2c.demand_hits::total 274257 # number of demand (read+write) hits 2287system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits 2288system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits 2289system.l2c.overall_hits::cpu0.inst 7661 # number of overall hits 2290system.l2c.overall_hits::cpu0.data 25477 # number of overall hits 2291system.l2c.overall_hits::cpu0.l2cache.prefetcher 138574 # number of overall hits 2292system.l2c.overall_hits::cpu1.dtb.walker 103 # number of overall hits 2293system.l2c.overall_hits::cpu1.itb.walker 107 # number of overall hits 2294system.l2c.overall_hits::cpu1.inst 6377 # number of overall hits 2295system.l2c.overall_hits::cpu1.data 20183 # number of overall hits 2296system.l2c.overall_hits::cpu1.l2cache.prefetcher 75612 # number of overall hits 2297system.l2c.overall_hits::total 274257 # number of overall hits |
| 2268system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses 2269system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 2298system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses 2299system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 2270system.l2c.ReadReq_misses::cpu0.inst 3124 # number of ReadReq misses 2271system.l2c.ReadReq_misses::cpu0.data 6991 # number of ReadReq misses 2272system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150306 # number of ReadReq misses 2273system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses | 2300system.l2c.ReadReq_misses::cpu0.inst 3079 # number of ReadReq misses 2301system.l2c.ReadReq_misses::cpu0.data 6828 # number of ReadReq misses 2302system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 144642 # number of ReadReq misses 2303system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses |
| 2274system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses | 2304system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses |
| 2275system.l2c.ReadReq_misses::cpu1.inst 786 # number of ReadReq misses 2276system.l2c.ReadReq_misses::cpu1.data 1400 # number of ReadReq misses 2277system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq misses 2278system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses 2279system.l2c.UpgradeReq_misses::cpu0.data 8554 # number of UpgradeReq misses 2280system.l2c.UpgradeReq_misses::cpu1.data 4191 # number of UpgradeReq misses 2281system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses 2282system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses 2283system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # number of SCUpgradeReq misses 2284system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses 2285system.l2c.ReadExReq_misses::cpu0.data 6191 # number of ReadExReq misses 2286system.l2c.ReadExReq_misses::cpu1.data 5553 # number of ReadExReq misses 2287system.l2c.ReadExReq_misses::total 11744 # number of ReadExReq misses | 2305system.l2c.ReadReq_misses::cpu1.inst 831 # number of ReadReq misses 2306system.l2c.ReadReq_misses::cpu1.data 1568 # number of ReadReq misses 2307system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 26632 # number of ReadReq misses 2308system.l2c.ReadReq_misses::total 183594 # number of ReadReq misses 2309system.l2c.UpgradeReq_misses::cpu0.data 7063 # number of UpgradeReq misses 2310system.l2c.UpgradeReq_misses::cpu1.data 5704 # number of UpgradeReq misses 2311system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses 2312system.l2c.SCUpgradeReq_misses::cpu0.data 818 # number of SCUpgradeReq misses 2313system.l2c.SCUpgradeReq_misses::cpu1.data 1393 # number of SCUpgradeReq misses 2314system.l2c.SCUpgradeReq_misses::total 2211 # number of SCUpgradeReq misses 2315system.l2c.ReadExReq_misses::cpu0.data 6032 # number of ReadExReq misses 2316system.l2c.ReadExReq_misses::cpu1.data 5664 # number of ReadExReq misses 2317system.l2c.ReadExReq_misses::total 11696 # number of ReadExReq misses |
| 2288system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 2289system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 2318system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 2319system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
| 2290system.l2c.demand_misses::cpu0.inst 3124 # number of demand (read+write) misses 2291system.l2c.demand_misses::cpu0.data 13182 # number of demand (read+write) misses 2292system.l2c.demand_misses::cpu0.l2cache.prefetcher 150306 # number of demand (read+write) misses 2293system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses | 2320system.l2c.demand_misses::cpu0.inst 3079 # number of demand (read+write) misses 2321system.l2c.demand_misses::cpu0.data 12860 # number of demand (read+write) misses 2322system.l2c.demand_misses::cpu0.l2cache.prefetcher 144642 # number of demand (read+write) misses 2323system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses |
| 2294system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses | 2324system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses |
| 2295system.l2c.demand_misses::cpu1.inst 786 # number of demand (read+write) misses 2296system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses 2297system.l2c.demand_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) misses 2298system.l2c.demand_misses::total 195660 # number of demand (read+write) misses | 2325system.l2c.demand_misses::cpu1.inst 831 # number of demand (read+write) misses 2326system.l2c.demand_misses::cpu1.data 7232 # number of demand (read+write) misses 2327system.l2c.demand_misses::cpu1.l2cache.prefetcher 26632 # number of demand (read+write) misses 2328system.l2c.demand_misses::total 195290 # number of demand (read+write) misses |
| 2299system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 2300system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses | 2329system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 2330system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
| 2301system.l2c.overall_misses::cpu0.inst 3124 # number of overall misses 2302system.l2c.overall_misses::cpu0.data 13182 # number of overall misses 2303system.l2c.overall_misses::cpu0.l2cache.prefetcher 150306 # number of overall misses 2304system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses | 2331system.l2c.overall_misses::cpu0.inst 3079 # number of overall misses 2332system.l2c.overall_misses::cpu0.data 12860 # number of overall misses 2333system.l2c.overall_misses::cpu0.l2cache.prefetcher 144642 # number of overall misses 2334system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses |
| 2305system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses | 2335system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses |
| 2306system.l2c.overall_misses::cpu1.inst 786 # number of overall misses 2307system.l2c.overall_misses::cpu1.data 6953 # number of overall misses 2308system.l2c.overall_misses::cpu1.l2cache.prefetcher 21296 # number of overall misses 2309system.l2c.overall_misses::total 195660 # number of overall misses | 2336system.l2c.overall_misses::cpu1.inst 831 # number of overall misses 2337system.l2c.overall_misses::cpu1.data 7232 # number of overall misses 2338system.l2c.overall_misses::cpu1.l2cache.prefetcher 26632 # number of overall misses 2339system.l2c.overall_misses::total 195290 # number of overall misses |
| 2310system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 598250 # number of ReadReq miss cycles 2311system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles | 2340system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 598250 # number of ReadReq miss cycles 2341system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles |
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| 2316system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles | 2346system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles |
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| 2336system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles | 2366system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles |
| 2337system.l2c.demand_miss_latency::cpu1.inst 71055248 # number of demand (read+write) miss cycles 2338system.l2c.demand_miss_latency::cpu1.data 522722930 # number of demand (read+write) miss cycles 2339system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of demand (read+write) miss cycles 2340system.l2c.demand_miss_latency::total 19282942905 # number of demand (read+write) miss cycles | 2367system.l2c.demand_miss_latency::cpu1.inst 76052499 # number of demand (read+write) miss cycles 2368system.l2c.demand_miss_latency::cpu1.data 539757394 # number of demand (read+write) miss cycles 2369system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2969532817 # number of demand (read+write) miss cycles 2370system.l2c.demand_miss_latency::total 19267940888 # number of demand (read+write) miss cycles |
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| 2343system.l2c.overall_miss_latency::cpu0.inst 271876998 # number of overall miss cycles 2344system.l2c.overall_miss_latency::cpu0.data 1061951136 # number of overall miss cycles 2345system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of overall miss cycles 2346system.l2c.overall_miss_latency::cpu1.dtb.walker 223500 # number of overall miss cycles | 2373system.l2c.overall_miss_latency::cpu0.inst 268856499 # number of overall miss cycles 2374system.l2c.overall_miss_latency::cpu0.data 1042103408 # number of overall miss cycles 2375system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14370591021 # number of overall miss cycles 2376system.l2c.overall_miss_latency::cpu1.dtb.walker 299500 # number of overall miss cycles |
| 2347system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles | 2377system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles |
| 2348system.l2c.overall_miss_latency::cpu1.inst 71055248 # number of overall miss cycles 2349system.l2c.overall_miss_latency::cpu1.data 522722930 # number of overall miss cycles 2350system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of overall miss cycles 2351system.l2c.overall_miss_latency::total 19282942905 # number of overall miss cycles 2352system.l2c.ReadReq_accesses::cpu0.dtb.walker 154 # number of ReadReq accesses(hits+misses) 2353system.l2c.ReadReq_accesses::cpu0.itb.walker 156 # number of ReadReq accesses(hits+misses) 2354system.l2c.ReadReq_accesses::cpu0.inst 13325 # number of ReadReq accesses(hits+misses) 2355system.l2c.ReadReq_accesses::cpu0.data 36430 # number of ReadReq accesses(hits+misses) 2356system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318343 # number of ReadReq accesses(hits+misses) 2357system.l2c.ReadReq_accesses::cpu1.dtb.walker 56 # number of ReadReq accesses(hits+misses) 2358system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) 2359system.l2c.ReadReq_accesses::cpu1.inst 4898 # number of ReadReq accesses(hits+misses) 2360system.l2c.ReadReq_accesses::cpu1.data 11773 # number of ReadReq accesses(hits+misses) 2361system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68949 # number of ReadReq accesses(hits+misses) 2362system.l2c.ReadReq_accesses::total 454129 # number of ReadReq accesses(hits+misses) 2363system.l2c.Writeback_accesses::writebacks 240423 # number of Writeback accesses(hits+misses) 2364system.l2c.Writeback_accesses::total 240423 # number of Writeback accesses(hits+misses) 2365system.l2c.UpgradeReq_accesses::cpu0.data 18187 # number of UpgradeReq accesses(hits+misses) 2366system.l2c.UpgradeReq_accesses::cpu1.data 5191 # number of UpgradeReq accesses(hits+misses) 2367system.l2c.UpgradeReq_accesses::total 23378 # number of UpgradeReq accesses(hits+misses) 2368system.l2c.SCUpgradeReq_accesses::cpu0.data 1140 # number of SCUpgradeReq accesses(hits+misses) 2369system.l2c.SCUpgradeReq_accesses::cpu1.data 1430 # number of SCUpgradeReq accesses(hits+misses) 2370system.l2c.SCUpgradeReq_accesses::total 2570 # number of SCUpgradeReq accesses(hits+misses) 2371system.l2c.ReadExReq_accesses::cpu0.data 10295 # number of ReadExReq accesses(hits+misses) 2372system.l2c.ReadExReq_accesses::cpu1.data 8119 # number of ReadExReq accesses(hits+misses) 2373system.l2c.ReadExReq_accesses::total 18414 # number of ReadExReq accesses(hits+misses) 2374system.l2c.demand_accesses::cpu0.dtb.walker 154 # number of demand (read+write) accesses 2375system.l2c.demand_accesses::cpu0.itb.walker 156 # number of demand (read+write) accesses 2376system.l2c.demand_accesses::cpu0.inst 13325 # number of demand (read+write) accesses 2377system.l2c.demand_accesses::cpu0.data 46725 # number of demand (read+write) accesses 2378system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318343 # number of demand (read+write) accesses 2379system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses 2380system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses 2381system.l2c.demand_accesses::cpu1.inst 4898 # number of demand (read+write) accesses 2382system.l2c.demand_accesses::cpu1.data 19892 # number of demand (read+write) accesses 2383system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68949 # number of demand (read+write) accesses 2384system.l2c.demand_accesses::total 472543 # number of demand (read+write) accesses 2385system.l2c.overall_accesses::cpu0.dtb.walker 154 # number of overall (read+write) accesses 2386system.l2c.overall_accesses::cpu0.itb.walker 156 # number of overall (read+write) accesses 2387system.l2c.overall_accesses::cpu0.inst 13325 # number of overall (read+write) accesses 2388system.l2c.overall_accesses::cpu0.data 46725 # number of overall (read+write) accesses 2389system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318343 # number of overall (read+write) accesses 2390system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses 2391system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses 2392system.l2c.overall_accesses::cpu1.inst 4898 # number of overall (read+write) accesses 2393system.l2c.overall_accesses::cpu1.data 19892 # number of overall (read+write) accesses 2394system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68949 # number of overall (read+write) accesses 2395system.l2c.overall_accesses::total 472543 # number of overall (read+write) accesses 2396system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for ReadReq accesses 2397system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006410 # miss rate for ReadReq accesses 2398system.l2c.ReadReq_miss_rate::cpu0.inst 0.234447 # miss rate for ReadReq accesses 2399system.l2c.ReadReq_miss_rate::cpu0.data 0.191902 # miss rate for ReadReq accesses 2400system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for ReadReq accesses 2401system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for ReadReq accesses 2402system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.022222 # miss rate for ReadReq accesses 2403system.l2c.ReadReq_miss_rate::cpu1.inst 0.160474 # miss rate for ReadReq accesses 2404system.l2c.ReadReq_miss_rate::cpu1.data 0.118916 # miss rate for ReadReq accesses 2405system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for ReadReq accesses 2406system.l2c.ReadReq_miss_rate::total 0.404986 # miss rate for ReadReq accesses 2407system.l2c.UpgradeReq_miss_rate::cpu0.data 0.470336 # miss rate for UpgradeReq accesses 2408system.l2c.UpgradeReq_miss_rate::cpu1.data 0.807359 # miss rate for UpgradeReq accesses 2409system.l2c.UpgradeReq_miss_rate::total 0.545171 # miss rate for UpgradeReq accesses 2410system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783333 # miss rate for SCUpgradeReq accesses 2411system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.904196 # miss rate for SCUpgradeReq accesses 2412system.l2c.SCUpgradeReq_miss_rate::total 0.850584 # miss rate for SCUpgradeReq accesses 2413system.l2c.ReadExReq_miss_rate::cpu0.data 0.601360 # miss rate for ReadExReq accesses 2414system.l2c.ReadExReq_miss_rate::cpu1.data 0.683951 # miss rate for ReadExReq accesses 2415system.l2c.ReadExReq_miss_rate::total 0.637776 # miss rate for ReadExReq accesses 2416system.l2c.demand_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for demand accesses 2417system.l2c.demand_miss_rate::cpu0.itb.walker 0.006410 # miss rate for demand accesses 2418system.l2c.demand_miss_rate::cpu0.inst 0.234447 # miss rate for demand accesses 2419system.l2c.demand_miss_rate::cpu0.data 0.282119 # miss rate for demand accesses 2420system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for demand accesses 2421system.l2c.demand_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for demand accesses 2422system.l2c.demand_miss_rate::cpu1.itb.walker 0.022222 # miss rate for demand accesses 2423system.l2c.demand_miss_rate::cpu1.inst 0.160474 # miss rate for demand accesses 2424system.l2c.demand_miss_rate::cpu1.data 0.349538 # miss rate for demand accesses 2425system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for demand accesses 2426system.l2c.demand_miss_rate::total 0.414058 # miss rate for demand accesses 2427system.l2c.overall_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for overall accesses 2428system.l2c.overall_miss_rate::cpu0.itb.walker 0.006410 # miss rate for overall accesses 2429system.l2c.overall_miss_rate::cpu0.inst 0.234447 # miss rate for overall accesses 2430system.l2c.overall_miss_rate::cpu0.data 0.282119 # miss rate for overall accesses 2431system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for overall accesses 2432system.l2c.overall_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for overall accesses 2433system.l2c.overall_miss_rate::cpu1.itb.walker 0.022222 # miss rate for overall accesses 2434system.l2c.overall_miss_rate::cpu1.inst 0.160474 # miss rate for overall accesses 2435system.l2c.overall_miss_rate::cpu1.data 0.349538 # miss rate for overall accesses 2436system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for overall accesses 2437system.l2c.overall_miss_rate::total 0.414058 # miss rate for overall accesses | 2378system.l2c.overall_miss_latency::cpu1.inst 76052499 # number of overall miss cycles 2379system.l2c.overall_miss_latency::cpu1.data 539757394 # number of overall miss cycles 2380system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2969532817 # number of overall miss cycles 2381system.l2c.overall_miss_latency::total 19267940888 # number of overall miss cycles 2382system.l2c.ReadReq_accesses::cpu0.dtb.walker 91 # number of ReadReq accesses(hits+misses) 2383system.l2c.ReadReq_accesses::cpu0.itb.walker 81 # number of ReadReq accesses(hits+misses) 2384system.l2c.ReadReq_accesses::cpu0.inst 10740 # number of ReadReq accesses(hits+misses) 2385system.l2c.ReadReq_accesses::cpu0.data 28622 # number of ReadReq accesses(hits+misses) 2386system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 283216 # number of ReadReq accesses(hits+misses) 2387system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses) 2388system.l2c.ReadReq_accesses::cpu1.itb.walker 108 # number of ReadReq accesses(hits+misses) 2389system.l2c.ReadReq_accesses::cpu1.inst 7208 # number of ReadReq accesses(hits+misses) 2390system.l2c.ReadReq_accesses::cpu1.data 18860 # number of ReadReq accesses(hits+misses) 2391system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 102244 # number of ReadReq accesses(hits+misses) 2392system.l2c.ReadReq_accesses::total 451277 # number of ReadReq accesses(hits+misses) 2393system.l2c.Writeback_accesses::writebacks 239712 # number of Writeback accesses(hits+misses) 2394system.l2c.Writeback_accesses::total 239712 # number of Writeback accesses(hits+misses) 2395system.l2c.UpgradeReq_accesses::cpu0.data 15944 # number of UpgradeReq accesses(hits+misses) 2396system.l2c.UpgradeReq_accesses::cpu1.data 7119 # number of UpgradeReq accesses(hits+misses) 2397system.l2c.UpgradeReq_accesses::total 23063 # number of UpgradeReq accesses(hits+misses) 2398system.l2c.SCUpgradeReq_accesses::cpu0.data 1031 # number of SCUpgradeReq accesses(hits+misses) 2399system.l2c.SCUpgradeReq_accesses::cpu1.data 1541 # number of SCUpgradeReq accesses(hits+misses) 2400system.l2c.SCUpgradeReq_accesses::total 2572 # number of SCUpgradeReq accesses(hits+misses) 2401system.l2c.ReadExReq_accesses::cpu0.data 9715 # number of ReadExReq accesses(hits+misses) 2402system.l2c.ReadExReq_accesses::cpu1.data 8555 # number of ReadExReq accesses(hits+misses) 2403system.l2c.ReadExReq_accesses::total 18270 # number of ReadExReq accesses(hits+misses) 2404system.l2c.demand_accesses::cpu0.dtb.walker 91 # number of demand (read+write) accesses 2405system.l2c.demand_accesses::cpu0.itb.walker 81 # number of demand (read+write) accesses 2406system.l2c.demand_accesses::cpu0.inst 10740 # number of demand (read+write) accesses 2407system.l2c.demand_accesses::cpu0.data 38337 # number of demand (read+write) accesses 2408system.l2c.demand_accesses::cpu0.l2cache.prefetcher 283216 # number of demand (read+write) accesses 2409system.l2c.demand_accesses::cpu1.dtb.walker 107 # number of demand (read+write) accesses 2410system.l2c.demand_accesses::cpu1.itb.walker 108 # number of demand (read+write) accesses 2411system.l2c.demand_accesses::cpu1.inst 7208 # number of demand (read+write) accesses 2412system.l2c.demand_accesses::cpu1.data 27415 # number of demand (read+write) accesses 2413system.l2c.demand_accesses::cpu1.l2cache.prefetcher 102244 # number of demand (read+write) accesses 2414system.l2c.demand_accesses::total 469547 # number of demand (read+write) accesses 2415system.l2c.overall_accesses::cpu0.dtb.walker 91 # number of overall (read+write) accesses 2416system.l2c.overall_accesses::cpu0.itb.walker 81 # number of overall (read+write) accesses 2417system.l2c.overall_accesses::cpu0.inst 10740 # number of overall (read+write) accesses 2418system.l2c.overall_accesses::cpu0.data 38337 # number of overall (read+write) accesses 2419system.l2c.overall_accesses::cpu0.l2cache.prefetcher 283216 # number of overall (read+write) accesses 2420system.l2c.overall_accesses::cpu1.dtb.walker 107 # number of overall (read+write) accesses 2421system.l2c.overall_accesses::cpu1.itb.walker 108 # number of overall (read+write) accesses 2422system.l2c.overall_accesses::cpu1.inst 7208 # number of overall (read+write) accesses 2423system.l2c.overall_accesses::cpu1.data 27415 # number of overall (read+write) accesses 2424system.l2c.overall_accesses::cpu1.l2cache.prefetcher 102244 # number of overall (read+write) accesses 2425system.l2c.overall_accesses::total 469547 # number of overall (read+write) accesses 2426system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for ReadReq accesses 2427system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012346 # miss rate for ReadReq accesses 2428system.l2c.ReadReq_miss_rate::cpu0.inst 0.286685 # miss rate for ReadReq accesses 2429system.l2c.ReadReq_miss_rate::cpu0.data 0.238558 # miss rate for ReadReq accesses 2430system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for ReadReq accesses 2431system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for ReadReq accesses 2432system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.009259 # miss rate for ReadReq accesses 2433system.l2c.ReadReq_miss_rate::cpu1.inst 0.115289 # miss rate for ReadReq accesses 2434system.l2c.ReadReq_miss_rate::cpu1.data 0.083139 # miss rate for ReadReq accesses 2435system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for ReadReq accesses 2436system.l2c.ReadReq_miss_rate::total 0.406832 # miss rate for ReadReq accesses 2437system.l2c.UpgradeReq_miss_rate::cpu0.data 0.442988 # miss rate for UpgradeReq accesses 2438system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801236 # miss rate for UpgradeReq accesses 2439system.l2c.UpgradeReq_miss_rate::total 0.553571 # miss rate for UpgradeReq accesses 2440system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.793404 # miss rate for SCUpgradeReq accesses 2441system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.903958 # miss rate for SCUpgradeReq accesses 2442system.l2c.SCUpgradeReq_miss_rate::total 0.859642 # miss rate for SCUpgradeReq accesses 2443system.l2c.ReadExReq_miss_rate::cpu0.data 0.620896 # miss rate for ReadExReq accesses 2444system.l2c.ReadExReq_miss_rate::cpu1.data 0.662069 # miss rate for ReadExReq accesses 2445system.l2c.ReadExReq_miss_rate::total 0.640175 # miss rate for ReadExReq accesses 2446system.l2c.demand_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for demand accesses 2447system.l2c.demand_miss_rate::cpu0.itb.walker 0.012346 # miss rate for demand accesses 2448system.l2c.demand_miss_rate::cpu0.inst 0.286685 # miss rate for demand accesses 2449system.l2c.demand_miss_rate::cpu0.data 0.335446 # miss rate for demand accesses 2450system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for demand accesses 2451system.l2c.demand_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for demand accesses 2452system.l2c.demand_miss_rate::cpu1.itb.walker 0.009259 # miss rate for demand accesses 2453system.l2c.demand_miss_rate::cpu1.inst 0.115289 # miss rate for demand accesses 2454system.l2c.demand_miss_rate::cpu1.data 0.263797 # miss rate for demand accesses 2455system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for demand accesses 2456system.l2c.demand_miss_rate::total 0.415912 # miss rate for demand accesses 2457system.l2c.overall_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for overall accesses 2458system.l2c.overall_miss_rate::cpu0.itb.walker 0.012346 # miss rate for overall accesses 2459system.l2c.overall_miss_rate::cpu0.inst 0.286685 # miss rate for overall accesses 2460system.l2c.overall_miss_rate::cpu0.data 0.335446 # miss rate for overall accesses 2461system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for overall accesses 2462system.l2c.overall_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for overall accesses 2463system.l2c.overall_miss_rate::cpu1.itb.walker 0.009259 # miss rate for overall accesses 2464system.l2c.overall_miss_rate::cpu1.inst 0.115289 # miss rate for overall accesses 2465system.l2c.overall_miss_rate::cpu1.data 0.263797 # miss rate for overall accesses 2466system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for overall accesses 2467system.l2c.overall_miss_rate::total 0.415912 # miss rate for overall accesses |
| 2438system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency 2439system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 2468system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency 2469system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
| 2440system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476 # average ReadReq miss latency 2441system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858 # average ReadReq miss latency 2442system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average ReadReq miss latency 2443system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency | 2470system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87319.421565 # average ReadReq miss latency 2471system.l2c.ReadReq_avg_miss_latency::cpu0.data 82510.215290 # average ReadReq miss latency 2472system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average ReadReq miss latency 2473system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74875 # average ReadReq miss latency |
| 2444system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency | 2474system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency |
| 2445system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880 # average ReadReq miss latency 2446system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286 # average ReadReq miss latency 2447system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average ReadReq miss latency 2448system.l2c.ReadReq_avg_miss_latency::total 99979.728990 # average ReadReq miss latency 2449system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1087.516367 # average UpgradeReq miss latency 2450system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2280.861608 # average UpgradeReq miss latency 2451system.l2c.UpgradeReq_avg_miss_latency::total 1479.929855 # average UpgradeReq miss latency 2452system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1441.707727 # average SCUpgradeReq miss latency 2453system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1682.836040 # average SCUpgradeReq miss latency 2454system.l2c.SCUpgradeReq_avg_miss_latency::total 1584.333028 # average SCUpgradeReq miss latency 2455system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529 # average ReadExReq miss latency 2456system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377 # average ReadExReq miss latency 2457system.l2c.ReadExReq_avg_miss_latency::total 76215.179496 # average ReadExReq miss latency | 2475system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91519.252708 # average ReadReq miss latency 2476system.l2c.ReadReq_avg_miss_latency::cpu1.data 83887.116709 # average ReadReq miss latency 2477system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average ReadReq miss latency 2478system.l2c.ReadReq_avg_miss_latency::total 100117.622771 # average ReadReq miss latency 2479system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 808.192553 # average UpgradeReq miss latency 2480system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2202.571178 # average UpgradeReq miss latency 2481system.l2c.UpgradeReq_avg_miss_latency::total 1431.168638 # average UpgradeReq miss latency 2482system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.435208 # average SCUpgradeReq miss latency 2483system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1660.732950 # average SCUpgradeReq miss latency 2484system.l2c.SCUpgradeReq_avg_miss_latency::total 1470.089100 # average SCUpgradeReq miss latency 2485system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79364.001658 # average ReadExReq miss latency 2486system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72073.162959 # average ReadExReq miss latency 2487system.l2c.ReadExReq_avg_miss_latency::total 75833.280865 # average ReadExReq miss latency |
| 2458system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency 2459system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2488system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency 2489system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2460system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency 2461system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency 2462system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency 2463system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency | 2490system.l2c.demand_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency 2491system.l2c.demand_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency 2492system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency 2493system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency |
| 2464system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency | 2494system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency |
| 2465system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency 2466system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency 2467system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency 2468system.l2c.demand_avg_miss_latency::total 98553.321604 # average overall miss latency | 2495system.l2c.demand_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency 2496system.l2c.demand_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency 2497system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency 2498system.l2c.demand_avg_miss_latency::total 98663.223350 # average overall miss latency |
| 2469system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency 2470system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 2499system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency 2500system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
| 2471system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency 2472system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency 2473system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency 2474system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency | 2501system.l2c.overall_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency 2502system.l2c.overall_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency 2503system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency 2504system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency |
| 2475system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency | 2505system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency |
| 2476system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency 2477system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency 2478system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency 2479system.l2c.overall_avg_miss_latency::total 98553.321604 # average overall miss latency 2480system.l2c.blocked_cycles::no_mshrs 370 # number of cycles access was blocked | 2506system.l2c.overall_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency 2507system.l2c.overall_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency 2508system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency 2509system.l2c.overall_avg_miss_latency::total 98663.223350 # average overall miss latency 2510system.l2c.blocked_cycles::no_mshrs 6 # number of cycles access was blocked |
| 2481system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2511system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2482system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked | 2512system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked |
| 2483system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 2513system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2484system.l2c.avg_blocked_cycles::no_mshrs 46.250000 # average number of cycles each access was blocked | 2514system.l2c.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked |
| 2485system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2486system.l2c.fast_writes 0 # number of fast writes performed 2487system.l2c.cache_copies 0 # number of cache copies performed | 2515system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2516system.l2c.fast_writes 0 # number of fast writes performed 2517system.l2c.cache_copies 0 # number of cache copies performed |
| 2488system.l2c.writebacks::writebacks 99922 # number of writebacks 2489system.l2c.writebacks::total 99922 # number of writebacks | 2518system.l2c.writebacks::writebacks 99681 # number of writebacks 2519system.l2c.writebacks::total 99681 # number of writebacks |
| 2490system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits | 2520system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits |
| 2491system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits | 2521system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits 2522system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits |
| 2492system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits | 2523system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits |
| 2493system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits | 2524system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2525system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits |
| 2494system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits | 2526system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits |
| 2495system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 2527system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 2528system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits |
| 2496system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses 2497system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses | 2529system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses 2530system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
| 2498system.l2c.ReadReq_mshr_misses::cpu0.inst 3124 # number of ReadReq MSHR misses 2499system.l2c.ReadReq_mshr_misses::cpu0.data 6991 # number of ReadReq MSHR misses 2500system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of ReadReq MSHR misses 2501system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses | 2531system.l2c.ReadReq_mshr_misses::cpu0.inst 3079 # number of ReadReq MSHR misses 2532system.l2c.ReadReq_mshr_misses::cpu0.data 6828 # number of ReadReq MSHR misses 2533system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 144641 # number of ReadReq MSHR misses 2534system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses |
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| 2558system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles 2559system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles | 2591system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles 2592system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles |
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| 2564system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles | 2597system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles |
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| 2569system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles 2570system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles | 2602system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles 2603system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles |
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| 2580system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles | 2613system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles |
| 2581system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796922003 # number of ReadReq MSHR uncacheable cycles | 2614system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4790227503 # number of ReadReq MSHR uncacheable cycles |
| 2582system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles | 2615system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles |
| 2583system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814310000 # number of ReadReq MSHR uncacheable cycles 2584system.l2c.ReadReq_mshr_uncacheable_latency::total 6097036003 # number of ReadReq MSHR uncacheable cycles 2585system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540062000 # number of WriteReq MSHR uncacheable cycles 2586system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712612000 # number of WriteReq MSHR uncacheable cycles 2587system.l2c.WriteReq_mshr_uncacheable_latency::total 4252674000 # number of WriteReq MSHR uncacheable cycles | 2616system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 820437000 # number of ReadReq MSHR uncacheable cycles 2617system.l2c.ReadReq_mshr_uncacheable_latency::total 6096468503 # number of ReadReq MSHR uncacheable cycles 2618system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3529697001 # number of WriteReq MSHR uncacheable cycles 2619system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 722659000 # number of WriteReq MSHR uncacheable cycles 2620system.l2c.WriteReq_mshr_uncacheable_latency::total 4252356001 # number of WriteReq MSHR uncacheable cycles |
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| 2590system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles | 2623system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles |
| 2591system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles 2592system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles 2593system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses 2594system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses 2595system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses 2596system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses 2597system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses 2598system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses 2599system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses 2600system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses 2601system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses 2602system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses 2603system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses 2604system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses 2605system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses 2606system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses 2607system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses 2608system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses 2609system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses 2610system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses 2611system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses 2612system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses 2613system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses 2614system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses 2615system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses 2616system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses 2617system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses 2618system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses 2619system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses 2620system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses 2621system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses 2622system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses 2623system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses 2624system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses 2625system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses 2626system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses 2627system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses 2628system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses 2629system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses 2630system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses 2631system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses 2632system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses 2633system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses 2634system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses | 2624system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1543096000 # number of overall MSHR uncacheable cycles 2625system.l2c.overall_mshr_uncacheable_latency::total 10348824504 # number of overall MSHR uncacheable cycles 2626system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.087912 # mshr miss rate for ReadReq accesses 2627system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012346 # mshr miss rate for ReadReq accesses 2628system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.286685 # mshr miss rate for ReadReq accesses 2629system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.238558 # mshr miss rate for ReadReq accesses 2630system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510709 # mshr miss rate for ReadReq accesses 2631system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037383 # mshr miss rate for ReadReq accesses 2632system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009259 # mshr miss rate for ReadReq accesses 2633system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.115289 # mshr miss rate for ReadReq accesses 2634system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083139 # mshr miss rate for ReadReq accesses 2635system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.260465 # mshr miss rate for ReadReq accesses 2636system.l2c.ReadReq_mshr_miss_rate::total 0.406828 # mshr miss rate for ReadReq accesses 2637system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.442988 # mshr miss rate for UpgradeReq accesses 2638system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801236 # mshr miss rate for UpgradeReq accesses 2639system.l2c.UpgradeReq_mshr_miss_rate::total 0.553571 # mshr miss rate for UpgradeReq accesses 2640system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793404 # mshr miss rate for SCUpgradeReq accesses 2641system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.903958 # mshr miss rate for SCUpgradeReq accesses 2642system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.859642 # mshr miss rate for SCUpgradeReq accesses 2643system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.620896 # mshr miss rate for ReadExReq accesses 2644system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.662069 # mshr miss rate for ReadExReq accesses 2645system.l2c.ReadExReq_mshr_miss_rate::total 0.640175 # mshr miss rate for ReadExReq accesses 2646system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.087912 # mshr miss rate for demand accesses 2647system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012346 # mshr miss rate for demand accesses 2648system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286685 # mshr miss rate for demand accesses 2649system.l2c.demand_mshr_miss_rate::cpu0.data 0.335446 # mshr miss rate for demand accesses 2650system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510709 # mshr miss rate for demand accesses 2651system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.037383 # mshr miss rate for demand accesses 2652system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009259 # mshr miss rate for demand accesses 2653system.l2c.demand_mshr_miss_rate::cpu1.inst 0.115289 # mshr miss rate for demand accesses 2654system.l2c.demand_mshr_miss_rate::cpu1.data 0.263797 # mshr miss rate for demand accesses 2655system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.260465 # mshr miss rate for demand accesses 2656system.l2c.demand_mshr_miss_rate::total 0.415907 # mshr miss rate for demand accesses 2657system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.087912 # mshr miss rate for overall accesses 2658system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012346 # mshr miss rate for overall accesses 2659system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286685 # mshr miss rate for overall accesses 2660system.l2c.overall_mshr_miss_rate::cpu0.data 0.335446 # mshr miss rate for overall accesses 2661system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.510709 # mshr miss rate for overall accesses 2662system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.037383 # mshr miss rate for overall accesses 2663system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009259 # mshr miss rate for overall accesses 2664system.l2c.overall_mshr_miss_rate::cpu1.inst 0.115289 # mshr miss rate for overall accesses 2665system.l2c.overall_mshr_miss_rate::cpu1.data 0.263797 # mshr miss rate for overall accesses 2666system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.260465 # mshr miss rate for overall accesses 2667system.l2c.overall_mshr_miss_rate::total 0.415907 # mshr miss rate for overall accesses |
| 2635system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency 2636system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 2668system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency 2669system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 2637system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency 2638system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency 2639system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency | 2670system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average ReadReq mshr miss latency 2671system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70082.930580 # average ReadReq mshr miss latency 2672system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average ReadReq mshr miss latency |
| 2640system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2641system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency | 2673system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2674system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency |
| 2642system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency 2643system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency 2644system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency 2645system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency 2646system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency 2647system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency 2648system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency 2649system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency 2650system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency 2651system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency 2652system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency 2653system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency 2654system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency | 2675system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average ReadReq mshr miss latency 2676system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546 # average ReadReq mshr miss latency 2677system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average ReadReq mshr miss latency 2678system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986 # average ReadReq mshr miss latency 2679system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146 # average UpgradeReq mshr miss latency 2680system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884 # average UpgradeReq mshr miss latency 2681system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660 # average UpgradeReq mshr miss latency 2682system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550 # average SCUpgradeReq mshr miss latency 2683system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency 2684system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency 2685system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency 2686system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency 2687system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency |
| 2655system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency 2656system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 2688system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency 2689system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 2657system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency 2658system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency 2659system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency | 2690system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency 2691system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency 2692system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency |
| 2660system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2661system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency | 2693system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2694system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency |
| 2662system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency 2663system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency 2664system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency 2665system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency | 2695system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency 2696system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency 2697system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency 2698system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency |
| 2666system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency 2667system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 2699system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency 2700system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 2668system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency 2669system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency 2670system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency | 2701system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency 2702system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency 2703system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency |
| 2671system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2672system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency | 2704system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2705system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency |
| 2673system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency 2674system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency 2675system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency 2676system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency | 2706system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency 2707system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency 2708system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency 2709system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency |
| 2677system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2678system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2679system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2680system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2681system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2682system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2683system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2684system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2685system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2686system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2687system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2688system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2689system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2690system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 2710system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2711system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2712system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2713system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2714system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2715system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2716system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2717system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2718system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2719system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2720system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2721system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2722system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2723system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2691system.membus.trans_dist::ReadReq 228475 # Transaction distribution 2692system.membus.trans_dist::ReadResp 228474 # Transaction distribution 2693system.membus.trans_dist::WriteReq 31175 # Transaction distribution 2694system.membus.trans_dist::WriteResp 31175 # Transaction distribution 2695system.membus.trans_dist::Writeback 99922 # Transaction distribution | 2724system.membus.trans_dist::ReadReq 228161 # Transaction distribution 2725system.membus.trans_dist::ReadResp 228160 # Transaction distribution 2726system.membus.trans_dist::WriteReq 31188 # Transaction distribution 2727system.membus.trans_dist::WriteResp 31188 # Transaction distribution 2728system.membus.trans_dist::Writeback 135887 # Transaction distribution |
| 2696system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2697system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 2729system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2730system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 2698system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution 2699system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution 2700system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution | 2731system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution 2732system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution 2733system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution |
| 2701system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution | 2734system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution |
| 2702system.membus.trans_dist::ReadExReq 28459 # Transaction distribution 2703system.membus.trans_dist::ReadExResp 11563 # Transaction distribution 2704system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) | 2735system.membus.trans_dist::ReadExReq 28446 # Transaction distribution 2736system.membus.trans_dist::ReadExResp 11501 # Transaction distribution 2737system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) |
| 2705system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 2738system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 2706system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes) 2707system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes) 2708system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes) 2709system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) 2710system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) 2711system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes) 2712system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) | 2739system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) 2740system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) 2741system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) 2742system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) 2743system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) 2744system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) 2745system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) |
| 2713system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) | 2746system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) |
| 2714system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes) 2715system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes) 2716system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes) 2717system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 2718system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 2719system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes) 2720system.membus.snoops 129134 # Total snoops (count) 2721system.membus.snoop_fanout::samples 475892 # Request fanout histogram | 2747system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) 2748system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) 2749system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) 2750system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) 2751system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) 2752system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) 2753system.membus.snoops 129157 # Total snoops (count) 2754system.membus.snoop_fanout::samples 511174 # Request fanout histogram |
| 2722system.membus.snoop_fanout::mean 1 # Request fanout histogram 2723system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2724system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2725system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2755system.membus.snoop_fanout::mean 1 # Request fanout histogram 2756system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2757system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2758system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2726system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram | 2759system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram |
| 2727system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2728system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2729system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2730system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 2760system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2761system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2762system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2763system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 2731system.membus.snoop_fanout::total 475892 # Request fanout histogram 2732system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks) | 2764system.membus.snoop_fanout::total 511174 # Request fanout histogram 2765system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) |
| 2733system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2734system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 2735system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2766system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2767system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 2768system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2736system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks) | 2769system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) |
| 2737system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2770system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2738system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks) | 2771system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) |
| 2739system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) | 2772system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
| 2740system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks) | 2773system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) |
| 2741system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 2774system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 2742system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks) | 2775system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) |
| 2743system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2744system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2745system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2746system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2747system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2748system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2749system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2750system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2767system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2768system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2769system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2770system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2771system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2772system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2773system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2774system.realview.ethernet.droppedPackets 0 # number of packets dropped | 2776system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2777system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2778system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2779system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2780system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2781system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2782system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2783system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 2800system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2801system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2802system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2803system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2804system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2805system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2806system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2807system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 2775system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution 2776system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution 2777system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution 2778system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution 2779system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution 2780system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 2781system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution 2782system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution 2783system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution 2784system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution 2785system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 2786system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution 2787system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution 2788system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes) 2789system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes) 2790system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes) 2791system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes) 2792system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes) 2793system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes) 2794system.toL2Bus.snoops 305031 # Total snoops (count) 2795system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram 2796system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram 2797system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram | 2808system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution 2809system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution 2810system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution 2811system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution 2812system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution 2813system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2814system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution 2815system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution 2816system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution 2817system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 2818system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution 2819system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution 2820system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution 2821system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) 2822system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) 2823system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) 2824system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) 2825system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) 2826system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) 2827system.toL2Bus.snoops 304478 # Total snoops (count) 2828system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram 2829system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram 2830system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram |
| 2798system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2799system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2831system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2832system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2800system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram 2801system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram | 2833system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram 2834system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram |
| 2802system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2803system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2804system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2835system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2836system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2837system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2805system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram 2806system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks) | 2838system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram 2839system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) |
| 2807system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2808system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 2809system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2840system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2841system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 2842system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2810system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks) | 2843system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) |
| 2811system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 2844system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 2812system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks) | 2845system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) |
| 2813system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2814 2815---------- End Simulation Statistics ---------- | 2846system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2847 2848---------- End Simulation Statistics ---------- |