| stats.txt (10517:ba51f8572571) | stats.txt (10535:4ccec5baf82c) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.866923 # Number of seconds simulated 4sim_ticks 2866923142000 # Number of ticks simulated 5final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.866913 # Number of seconds simulated 4sim_ticks 2866913114000 # Number of ticks simulated 5final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 699616 # Simulator instruction rate (inst/s) 8host_op_rate 846245 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15203294122 # Simulator tick rate (ticks/s) 10host_mem_usage 599680 # Number of bytes of host memory used 11host_seconds 188.57 # Real time elapsed on the host 12sim_insts 131928295 # Number of instructions simulated 13sim_ops 159578500 # Number of ops (including micro ops) simulated | 7host_inst_rate 786450 # Simulator instruction rate (inst/s) 8host_op_rate 951292 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17090693254 # Simulator tick rate (ticks/s) 10host_mem_usage 609256 # Number of bytes of host memory used 11host_seconds 167.75 # Real time elapsed on the host 12sim_insts 131924636 # Number of instructions simulated 13sim_ops 159576421 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | |
| 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory 32system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory | 23system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 35system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory 36system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 34system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 35system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory |
| 37system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 39system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory | 38system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory |
| 42system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory | 41system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory |
| 44system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory 46system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory 49system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory | 43system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory |
| 50system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 51system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 52system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory 53system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) | 51system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 52system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory |
| 54system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 56system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s) | 55system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 58system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 61system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s) | 60system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 69system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 72system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s) | 71system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s) 72system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s) |
| 75system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 74system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 77system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s) | 76system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s) |
| 80system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 79system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 82system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 205337 # Number of read requests accepted 87system.physmem.writeReqs 140504 # Number of write requests accepted 88system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue 92system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue | 81system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 205263 # Number of read requests accepted 87system.physmem.writeReqs 140582 # Number of write requests accepted 88system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue 92system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue |
| 96system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one | 96system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one |
| 97system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 12897 # Per bank write bursts 99system.physmem.perBankRdBursts::1 12279 # Per bank write bursts 100system.physmem.perBankRdBursts::2 13044 # Per bank write bursts 101system.physmem.perBankRdBursts::3 12666 # Per bank write bursts 102system.physmem.perBankRdBursts::4 21207 # Per bank write bursts 103system.physmem.perBankRdBursts::5 12512 # Per bank write bursts 104system.physmem.perBankRdBursts::6 12819 # Per bank write bursts 105system.physmem.perBankRdBursts::7 13070 # Per bank write bursts 106system.physmem.perBankRdBursts::8 12092 # Per bank write bursts 107system.physmem.perBankRdBursts::9 12100 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12291 # Per bank write bursts 109system.physmem.perBankRdBursts::11 10982 # Per bank write bursts 110system.physmem.perBankRdBursts::12 11837 # Per bank write bursts 111system.physmem.perBankRdBursts::13 12135 # Per bank write bursts 112system.physmem.perBankRdBursts::14 11741 # Per bank write bursts 113system.physmem.perBankRdBursts::15 11403 # Per bank write bursts 114system.physmem.perBankWrBursts::0 8736 # Per bank write bursts 115system.physmem.perBankWrBursts::1 8619 # Per bank write bursts 116system.physmem.perBankWrBursts::2 9216 # Per bank write bursts 117system.physmem.perBankWrBursts::3 8724 # Per bank write bursts 118system.physmem.perBankWrBursts::4 8630 # Per bank write bursts 119system.physmem.perBankWrBursts::5 8715 # Per bank write bursts 120system.physmem.perBankWrBursts::6 8820 # Per bank write bursts 121system.physmem.perBankWrBursts::7 8946 # Per bank write bursts 122system.physmem.perBankWrBursts::8 8394 # Per bank write bursts 123system.physmem.perBankWrBursts::9 8545 # Per bank write bursts 124system.physmem.perBankWrBursts::10 8627 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8114 # Per bank write bursts 126system.physmem.perBankWrBursts::12 8397 # Per bank write bursts 127system.physmem.perBankWrBursts::13 8288 # Per bank write bursts 128system.physmem.perBankWrBursts::14 8182 # Per bank write bursts 129system.physmem.perBankWrBursts::15 7606 # Per bank write bursts | 97system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 12846 # Per bank write bursts 99system.physmem.perBankRdBursts::1 12299 # Per bank write bursts 100system.physmem.perBankRdBursts::2 13037 # Per bank write bursts 101system.physmem.perBankRdBursts::3 12736 # Per bank write bursts 102system.physmem.perBankRdBursts::4 21227 # Per bank write bursts 103system.physmem.perBankRdBursts::5 12513 # Per bank write bursts 104system.physmem.perBankRdBursts::6 12853 # Per bank write bursts 105system.physmem.perBankRdBursts::7 12957 # Per bank write bursts 106system.physmem.perBankRdBursts::8 12050 # Per bank write bursts 107system.physmem.perBankRdBursts::9 12106 # Per bank write bursts 108system.physmem.perBankRdBursts::10 12270 # Per bank write bursts 109system.physmem.perBankRdBursts::11 11010 # Per bank write bursts 110system.physmem.perBankRdBursts::12 11804 # Per bank write bursts 111system.physmem.perBankRdBursts::13 12158 # Per bank write bursts 112system.physmem.perBankRdBursts::14 11709 # Per bank write bursts 113system.physmem.perBankRdBursts::15 11437 # Per bank write bursts 114system.physmem.perBankWrBursts::0 8735 # Per bank write bursts 115system.physmem.perBankWrBursts::1 8638 # Per bank write bursts 116system.physmem.perBankWrBursts::2 9213 # Per bank write bursts 117system.physmem.perBankWrBursts::3 8824 # Per bank write bursts 118system.physmem.perBankWrBursts::4 8594 # Per bank write bursts 119system.physmem.perBankWrBursts::5 8713 # Per bank write bursts 120system.physmem.perBankWrBursts::6 8840 # Per bank write bursts 121system.physmem.perBankWrBursts::7 8875 # Per bank write bursts 122system.physmem.perBankWrBursts::8 8399 # Per bank write bursts 123system.physmem.perBankWrBursts::9 8546 # Per bank write bursts 124system.physmem.perBankWrBursts::10 8611 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8118 # Per bank write bursts 126system.physmem.perBankWrBursts::12 8409 # Per bank write bursts 127system.physmem.perBankWrBursts::13 8327 # Per bank write bursts 128system.physmem.perBankWrBursts::14 8185 # Per bank write bursts 129system.physmem.perBankWrBursts::15 7610 # Per bank write bursts |
| 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 131system.physmem.numWrRetry 7 # Number of times write queue was full causing retry | 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 131system.physmem.numWrRetry 7 # Number of times write queue was full causing retry |
| 132system.physmem.totGap 2866922767000 # Total gap between requests | 132system.physmem.totGap 2866912757000 # Total gap between requests |
| 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 9742 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 0 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) | 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 9742 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 0 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 139system.physmem.readPktSize::6 195567 # Read request sizes (log2) | 139system.physmem.readPktSize::6 195493 # Read request sizes (log2) |
| 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) | 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 146system.physmem.writePktSize::6 136068 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see | 146system.physmem.writePktSize::6 136146 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see | 194system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see |
| 238system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see | 238system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see |
| 239system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes | 239system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes | 261system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes |
| 263system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads | 263system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads |
| 288system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads | 288system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads |
| 289system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads 301system.physmem.totQLat 6009454502 # Total ticks spent queuing 302system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM 303system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers 304system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst | 289system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads 297system.physmem.totQLat 5976562250 # Total ticks spent queuing 298system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM 299system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers 300system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst |
| 305system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 301system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 306system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst | 302system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst |
| 307system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s 308system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 309system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s | 303system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s 304system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 305system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s |
| 310system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s | 306system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s |
| 311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 312system.physmem.busUtil 0.06 # Data bus utilization in percentage 313system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 314system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 307system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 308system.physmem.busUtil 0.06 # Data bus utilization in percentage 309system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 310system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 315system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing 316system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing | 311system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing 312system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing |
| 317system.physmem.readRowHits 175010 # Number of row buffer hits during reads | 313system.physmem.readRowHits 175010 # Number of row buffer hits during reads |
| 318system.physmem.writeRowHits 85502 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes 321system.physmem.avgGap 8289713.39 # Average gap between requests 322system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined 323system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states 324system.physmem.memoryStateTime::REF 95732780000 # Time in different power states | 314system.physmem.writeRowHits 85700 # Number of row buffer hits during writes 315system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads 316system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes 317system.physmem.avgGap 8289588.56 # Average gap between requests 318system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined 319system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states 320system.physmem.memoryStateTime::REF 95732520000 # Time in different power states |
| 325system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 321system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 326system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states | 322system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states |
| 327system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 323system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 328system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ) 329system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ) 330system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ) 331system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ) 332system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ) 333system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ) 334system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ) 335system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ) 336system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ) 337system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ) 338system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ) 339system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ) 340system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ) 341system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ) 342system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ) 343system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ) 344system.physmem.averagePower::0 669.491656 # Core power per rank (mW) 345system.physmem.averagePower::1 669.352997 # Core power per rank (mW) | 324system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ) 325system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ) 326system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ) 327system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ) 328system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ) 329system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ) 330system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ) 331system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ) 332system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ) 333system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ) 334system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ) 335system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ) 336system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ) 337system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ) 338system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ) 339system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ) 340system.physmem.averagePower::0 669.485397 # Core power per rank (mW) 341system.physmem.averagePower::1 669.364885 # Core power per rank (mW) |
| 346system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) | 342system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 348system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 350system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 351system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 359system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) |
| 364system.membus.trans_dist::ReadReq 228669 # Transaction distribution 365system.membus.trans_dist::ReadResp 228668 # Transaction distribution 366system.membus.trans_dist::WriteReq 31179 # Transaction distribution 367system.membus.trans_dist::WriteResp 31179 # Transaction distribution 368system.membus.trans_dist::Writeback 99844 # Transaction distribution 369system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 370system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 371system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution 372system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution 373system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution 374system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 375system.membus.trans_dist::ReadExReq 28316 # Transaction distribution 376system.membus.trans_dist::ReadExResp 11444 # Transaction distribution 377system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) 378system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 379system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes) 380system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes) 381system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes) 382system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) 383system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) 384system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes) 385system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) 386system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 387system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes) 388system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes) 389system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes) 390system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 391system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 392system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes) 393system.membus.snoops 128959 # Total snoops (count) 394system.membus.snoop_fanout::samples 475734 # Request fanout histogram 395system.membus.snoop_fanout::mean 1 # Request fanout histogram 396system.membus.snoop_fanout::stdev 0 # Request fanout histogram 397system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 398system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 399system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram 400system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 401system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 402system.membus.snoop_fanout::min_value 1 # Request fanout histogram 403system.membus.snoop_fanout::max_value 1 # Request fanout histogram 404system.membus.snoop_fanout::total 475734 # Request fanout histogram 405system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks) 406system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 407system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 408system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 409system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks) 410system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 411system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks) 412system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 413system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks) 414system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 415system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks) 416system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 417system.cpu_clk_domain.clock 500 # Clock period in ticks 418system.l2c.tags.replacements 132855 # number of replacements 419system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use 420system.l2c.tags.total_refs 486769 # Total number of references to valid blocks. 421system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks. 422system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks. 423system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 424system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor 432system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor 433system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor 434system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor 435system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy 439system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy 440system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy 442system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy 444system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy 445system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy 446system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy 447system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id 448system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 449system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id 453system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 454system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 455system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id 456system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id 457system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id 458system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id 459system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 460system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id 461system.l2c.tags.tag_accesses 6123027 # Number of tag accesses 462system.l2c.tags.data_accesses 6123027 # Number of data accesses 463system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits 470system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits 471system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits 472system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits 473system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits 474system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits 475system.l2c.Writeback_hits::total 239796 # number of Writeback hits 476system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits 477system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits 478system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits 479system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits 480system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits 481system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits 482system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits 483system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits 484system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits 485system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits 492system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits 493system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits 494system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits 495system.l2c.demand_hits::total 274907 # number of demand (read+write) hits 496system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits 497system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits 498system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits 499system.l2c.overall_hits::cpu0.data 33021 # number of overall hits 500system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits 501system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits 502system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits 503system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits 504system.l2c.overall_hits::cpu1.data 12797 # number of overall hits 505system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits 506system.l2c.overall_hits::total 274907 # number of overall hits 507system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses 508system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 509system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses 511system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 513system.l2c.ReadReq_misses::cpu1.itb.walker 1 # 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number of overall (read+write) accesses 630system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses 631system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses 632system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses 633system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses 634system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses 635system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses 636system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses 637system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses 638system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses 639system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses 640system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # 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miss rate for demand accesses 665system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses 666system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses 671system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses 672system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses 673system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses 674system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses 675system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses 676system.l2c.overall_miss_rate::total 0.415882 # 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number of ReadReq MSHR uncacheable cycles 820system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796970001 # number of ReadReq MSHR uncacheable cycles 821system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles 822system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814272500 # number of ReadReq MSHR uncacheable cycles 823system.l2c.ReadReq_mshr_uncacheable_latency::total 6097046501 # number of ReadReq MSHR uncacheable cycles 824system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540071000 # number of WriteReq MSHR uncacheable cycles 825system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712688499 # number of WriteReq MSHR uncacheable cycles 826system.l2c.WriteReq_mshr_uncacheable_latency::total 4252759499 # number of WriteReq MSHR uncacheable cycles 827system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles 828system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337041001 # number of overall MSHR uncacheable cycles 829system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles 830system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526960999 # number of overall MSHR uncacheable cycles 831system.l2c.overall_mshr_uncacheable_latency::total 10349806000 # number of overall MSHR uncacheable cycles 832system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for ReadReq accesses 833system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for ReadReq accesses 834system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for ReadReq accesses 835system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.194648 # mshr miss rate for ReadReq accesses 836system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for ReadReq accesses 837system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for ReadReq accesses 838system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses 839system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for ReadReq accesses 840system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120999 # mshr miss rate for ReadReq accesses 841system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for ReadReq accesses 842system.l2c.ReadReq_mshr_miss_rate::total 0.407020 # mshr miss rate for ReadReq accesses 843system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.468098 # mshr miss rate for UpgradeReq accesses 844system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.820316 # mshr miss rate for UpgradeReq accesses 845system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses 846system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.780337 # mshr miss rate for SCUpgradeReq accesses 847system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.896575 # mshr miss rate for SCUpgradeReq accesses 848system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845886 # mshr miss rate for SCUpgradeReq accesses 849system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595289 # mshr miss rate for ReadExReq accesses 850system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.685430 # mshr miss rate for ReadExReq accesses 851system.l2c.ReadExReq_mshr_miss_rate::total 0.634834 # mshr miss rate for ReadExReq accesses 852system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for demand accesses 853system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for demand accesses 854system.l2c.demand_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for demand accesses 855system.l2c.demand_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for demand accesses 856system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for demand accesses 857system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for demand accesses 858system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses 859system.l2c.demand_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for demand accesses 860system.l2c.demand_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for demand accesses 861system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for demand accesses 862system.l2c.demand_mshr_miss_rate::total 0.415880 # mshr miss rate for demand accesses 863system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for overall accesses 864system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for overall accesses 865system.l2c.overall_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for overall accesses 866system.l2c.overall_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for overall accesses 867system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for overall accesses 868system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for overall accesses 869system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses 870system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses 871system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses 872system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for overall accesses 873system.l2c.overall_mshr_miss_rate::total 0.415880 # mshr miss rate for overall accesses 874system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average ReadReq mshr miss latency 875system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 876system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average ReadReq mshr miss latency 877system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69416.248423 # average ReadReq mshr miss latency 878system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average ReadReq mshr miss latency 879system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency 880system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency 881system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency 882system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency 883system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency 884system.l2c.ReadReq_avg_mshr_miss_latency::total 87699.200225 # average ReadReq mshr miss latency 885system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency 886system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency 887system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency 888system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency 889system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency 890system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency 891system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68004.146010 # average ReadExReq mshr miss latency 892system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59507.325036 # average ReadExReq mshr miss latency 893system.l2c.ReadExReq_avg_mshr_miss_latency::total 63979.490017 # average ReadExReq mshr miss latency 894system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency 895system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 896system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency 897system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency 898system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency 899system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency 900system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 901system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency 902system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency 903system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency 904system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency 905system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency 906system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 907system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency 908system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency 909system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency 910system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency 911system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 912system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency 913system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency 914system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency 915system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency 916system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 917system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 918system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 919system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 920system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 921system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 922system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 923system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 924system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 925system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 926system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 927system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 928system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 929system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 930system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 931system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 932system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 933system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 934system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 935system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 936system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 937system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 938system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 939system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 940system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 941system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 942system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 943system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 944system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 945system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 946system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 947system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 948system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 949system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 950system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 951system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 952system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 953system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 954system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 955system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 956system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 957system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 958system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 959system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 960system.realview.ethernet.droppedPackets 0 # number of packets dropped | |
| 961system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 962system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 963system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 964system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 965system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 966system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 360system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 361system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 362system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 363system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 364system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 365system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 967system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution 968system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution 969system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution 970system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution 971system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution 972system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 973system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution 974system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution 975system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution 976system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution 977system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 978system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution 979system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution 980system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes) 981system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes) 982system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes) 983system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes) 984system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes) 985system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes) 986system.toL2Bus.snoops 304794 # Total snoops (count) 987system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram 988system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram 989system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram 990system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 991system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 992system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram 993system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram 994system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 995system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 996system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 997system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram 998system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks) 999system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1000system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 1001system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1002system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks) 1003system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1004system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks) 1005system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1006system.iobus.trans_dist::ReadReq 31019 # Transaction distribution 1007system.iobus.trans_dist::ReadResp 31019 # Transaction distribution 1008system.iobus.trans_dist::WriteReq 59414 # Transaction distribution 1009system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1010system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution 1011system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1012system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1013system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1014system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1015system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1016system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 1017system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1018system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1019system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1024system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1025system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1027system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1028system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1029system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1030system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1031system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1032system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) 1033system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) 1034system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 1037system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1038system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1039system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1040system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1041system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) 1042system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1043system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1044system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1052system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1054system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1055system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1056system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1057system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) 1058system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) 1059system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) 1060system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) 1061system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 1062system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1063system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 1064system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1065system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1066system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1067system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1068system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1069system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1070system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1071system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) 1072system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1073system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1074system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1075system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1076system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1077system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1078system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1079system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1080system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1081system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1082system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1083system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1084system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1085system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1086system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1087system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1088system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1090system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1092system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1093system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1094system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1096system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1097system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1098system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1099system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1100system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1101system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks) 1102system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1103system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1104system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1105system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) 1106system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1107system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks) 1108system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 366system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 1109system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1110system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1111system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1112system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1113system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1114system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1115system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1116system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1124system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1125system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1126system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1127system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1128system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1129system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1130system.cpu0.dtb.inst_hits 0 # ITB inst hits 1131system.cpu0.dtb.inst_misses 0 # ITB inst misses | 367system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 368system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 369system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 370system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 371system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 372system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 373system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 374system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 382system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 388system.cpu0.dtb.inst_hits 0 # ITB inst hits 389system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1132system.cpu0.dtb.read_hits 24351510 # DTB read hits 1133system.cpu0.dtb.read_misses 6410 # DTB read misses 1134system.cpu0.dtb.write_hits 18124813 # DTB write hits 1135system.cpu0.dtb.write_misses 1105 # DTB write misses | 390system.cpu0.dtb.read_hits 24351477 # DTB read hits 391system.cpu0.dtb.read_misses 6408 # DTB read misses 392system.cpu0.dtb.write_hits 18124986 # DTB write hits 393system.cpu0.dtb.write_misses 1114 # DTB write misses |
| 1136system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1137system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1138system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1139system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 394system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 395system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 396system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 397system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1140system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB | 398system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB |
| 1141system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 399system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1142system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch | 400system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch |
| 1143system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1144system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 401system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 402system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 1145system.cpu0.dtb.read_accesses 24357920 # DTB read accesses 1146system.cpu0.dtb.write_accesses 18125918 # DTB write accesses | 403system.cpu0.dtb.read_accesses 24357885 # DTB read accesses 404system.cpu0.dtb.write_accesses 18126100 # DTB write accesses |
| 1147system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 405system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1148system.cpu0.dtb.hits 42476323 # DTB hits 1149system.cpu0.dtb.misses 7515 # DTB misses 1150system.cpu0.dtb.accesses 42483838 # DTB accesses | 406system.cpu0.dtb.hits 42476463 # DTB hits 407system.cpu0.dtb.misses 7522 # DTB misses 408system.cpu0.dtb.accesses 42483985 # DTB accesses |
| 1151system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1152system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1153system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1154system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1155system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1156system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1157system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1158system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1164system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1165system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1166system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1167system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1168system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1169system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1170system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1171system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 409system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 410system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 411system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 412system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 413system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 414system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 415system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 416system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 422system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 423system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 424system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 425system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 426system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 427system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 428system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 429system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1172system.cpu0.itb.inst_hits 115065468 # ITB inst hits 1173system.cpu0.itb.inst_misses 3349 # ITB inst misses | 430system.cpu0.itb.inst_hits 115065570 # ITB inst hits 431system.cpu0.itb.inst_misses 3350 # ITB inst misses |
| 1174system.cpu0.itb.read_hits 0 # DTB read hits 1175system.cpu0.itb.read_misses 0 # DTB read misses 1176system.cpu0.itb.write_hits 0 # DTB write hits 1177system.cpu0.itb.write_misses 0 # DTB write misses 1178system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1179system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1180system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1181system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 432system.cpu0.itb.read_hits 0 # DTB read hits 433system.cpu0.itb.read_misses 0 # DTB read misses 434system.cpu0.itb.write_hits 0 # DTB write hits 435system.cpu0.itb.write_misses 0 # DTB write misses 436system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 437system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 438system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 439system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1182system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB | 440system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB |
| 1183system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1184system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1185system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1186system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1187system.cpu0.itb.read_accesses 0 # DTB read accesses 1188system.cpu0.itb.write_accesses 0 # DTB write accesses | 441system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 442system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 443system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 445system.cpu0.itb.read_accesses 0 # DTB read accesses 446system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1189system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses 1190system.cpu0.itb.hits 115065468 # DTB hits 1191system.cpu0.itb.misses 3349 # DTB misses 1192system.cpu0.itb.accesses 115068817 # DTB accesses 1193system.cpu0.numCycles 5733846284 # number of cpu cycles simulated | 447system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses 448system.cpu0.itb.hits 115065570 # DTB hits 449system.cpu0.itb.misses 3350 # DTB misses 450system.cpu0.itb.accesses 115068920 # DTB accesses 451system.cpu0.numCycles 5733826228 # number of cpu cycles simulated |
| 1194system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1195system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 452system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 453system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1196system.cpu0.committedInsts 111421342 # Number of instructions committed 1197system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed 1198system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses | 454system.cpu0.committedInsts 111421445 # Number of instructions committed 455system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed 456system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses |
| 1199system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses | 457system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses |
| 1200system.cpu0.num_func_calls 12527292 # number of times a function call or return occured 1201system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls 1202system.cpu0.num_int_insts 119417138 # number of integer instructions | 458system.cpu0.num_func_calls 12527454 # number of times a function call or return occured 459system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls 460system.cpu0.num_int_insts 119418221 # number of integer instructions |
| 1203system.cpu0.num_fp_insts 9755 # number of float instructions | 461system.cpu0.num_fp_insts 9755 # number of float instructions |
| 1204system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read 1205system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written | 462system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read 463system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written |
| 1206system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 1207system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 464system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 465system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 1208system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read 1209system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written 1210system.cpu0.num_mem_refs 43585643 # number of memory refs 1211system.cpu0.num_load_insts 24597805 # Number of load instructions 1212system.cpu0.num_store_insts 18987838 # Number of store instructions 1213system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles 1214system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles 1215system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles 1216system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles 1217system.cpu0.Branches 28215087 # Number of branches fetched | 466system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read 467system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written 468system.cpu0.num_mem_refs 43585923 # number of memory refs 469system.cpu0.num_load_insts 24597873 # Number of load instructions 470system.cpu0.num_store_insts 18988050 # Number of store instructions 471system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles 472system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles 473system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles 474system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles 475system.cpu0.Branches 28215151 # Number of branches fetched |
| 1218system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction | 476system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction |
| 1219system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction 1220system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction | 477system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction 478system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction |
| 1221system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction 1222system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction 1223system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction 1224system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction 1225system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction 1226system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction 1227system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction 1228system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 1236system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction 1237system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction 1238system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction 1239system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction 1240system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction 1241system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction 1242system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction 1243system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction | 479system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction 480system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction 481system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction 482system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction 483system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction 484system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction 485system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction 486system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 494system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction 495system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction 496system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction 497system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction 498system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction 499system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction 500system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction 501system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction |
| 1244system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction | 502system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction |
| 1245system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction 1246system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction 1247system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction | 503system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction 504system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction 505system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction |
| 1248system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction 1249system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction | 506system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction 507system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction |
| 1250system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1251system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 508system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 509system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1252system.cpu0.op_class::total 138425707 # Class of executed instruction | 510system.cpu0.op_class::total 138426785 # Class of executed instruction |
| 1253system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 511system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1254system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed 1255system.cpu0.icache.tags.replacements 1060721 # number of replacements 1256system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use 1257system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks. 1258system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks. 1259system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks. | 512system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed 513system.cpu0.dcache.tags.replacements 658574 # number of replacements 514system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use 515system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks. 516system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks. 517system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks. 518system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. 519system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor 520system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy 521system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy 522system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 523system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 524system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 525system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 526system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 527system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses 528system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses 529system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits 530system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits 531system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits 532system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits 533system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits 534system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits 535system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits 536system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits 537system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits 538system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits 539system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits 540system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits 541system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits 542system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits 543system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses 544system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses 545system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses 546system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses 547system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses 548system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses 549system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses 550system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses 551system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses 552system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses 553system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses 554system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses 555system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses 556system.cpu0.dcache.overall_misses::total 764106 # number of overall misses 557system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles 558system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles 559system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles 560system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles 561system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles 562system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles 563system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles 564system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles 565system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles 566system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles 567system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles 568system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles 569system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles 570system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles 571system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses) 572system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses) 573system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses) 574system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses) 575system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses) 576system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses) 577system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses) 578system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses) 579system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses) 580system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses) 581system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses 582system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses 583system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses 584system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses 585system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses 586system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses 587system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses 588system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses 589system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses 590system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses 591system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses 592system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses 593system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses 594system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses 595system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses 596system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses 597system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses 598system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses 599system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency 600system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency 601system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency 602system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency 603system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency 604system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency 605system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency 606system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency 607system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 608system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 609system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency 610system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency 611system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency 612system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency 613system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 614system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 616system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 617system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 618system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu0.dcache.fast_writes 0 # number of fast writes performed 620system.cpu0.dcache.cache_copies 0 # number of cache copies performed 621system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks 622system.cpu0.dcache.writebacks::total 483361 # number of writebacks 623system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits 624system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits 625system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits 626system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits 627system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits 628system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits 629system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits 630system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits 631system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses 632system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses 633system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses 634system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses 635system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses 636system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses 637system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses 638system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses 639system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses 640system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses 641system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses 642system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses 643system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses 644system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses 645system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles 646system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles 647system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles 648system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles 649system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles 650system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles 651system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles 652system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles 653system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles 654system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles 655system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles 656system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles 657system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles 658system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles 659system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles 660system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles 661system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles 662system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles 663system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles 664system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles 665system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles 666system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles 667system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses 668system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses 669system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses 670system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses 671system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses 672system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses 673system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses 674system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses 675system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses 676system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses 677system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses 678system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses 679system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses 680system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses 681system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency 682system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency 683system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency 684system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency 685system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency 686system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency 687system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency 688system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency 689system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency 690system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency 691system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 692system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 693system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency 694system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency 695system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency 696system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency 697system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 698system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 699system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 700system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 701system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 702system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 703system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 704system.cpu0.icache.tags.replacements 1061124 # number of replacements 705system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use 706system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks. 707system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks. 708system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks. |
| 1260system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. | 709system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. |
| 1261system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor | 710system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor |
| 1262system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 1263system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy 1264system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 711system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 712system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy 713system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1265system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 1266system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id | 714system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 715system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id |
| 1267system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id 1268system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 716system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id 717system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1269system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses 1270system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses 1271system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits 1272system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits 1273system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits 1274system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits 1275system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits 1276system.cpu0.icache.overall_hits::total 114004226 # number of overall hits 1277system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses 1278system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses 1279system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses 1280system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses 1281system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses 1282system.cpu0.icache.overall_misses::total 1061242 # number of overall misses 1283system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles 1284system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles 1285system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles 1286system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles 1287system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles 1288system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles 1289system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses) 1290system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses) 1291system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses 1292system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses 1293system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses 1294system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses 1295system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses 1296system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses 1297system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses 1298system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses 1299system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses 1300system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses 1301system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency 1302system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency 1303system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency 1304system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency 1305system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency 1306system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency | 718system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses 719system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses 720system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits 721system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits 722system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits 723system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits 724system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits 725system.cpu0.icache.overall_hits::total 114003925 # number of overall hits 726system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses 727system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses 728system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses 729system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses 730system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses 731system.cpu0.icache.overall_misses::total 1061645 # number of overall misses 732system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles 733system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles 734system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles 735system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles 736system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles 737system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles 738system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses) 739system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses) 740system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses 741system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses 742system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses 743system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses 744system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses 745system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses 746system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses 747system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses 748system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses 749system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses 750system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency 751system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency 752system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency 753system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency 754system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency 755system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency |
| 1307system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1308system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1309system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1310system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1311system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1312system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1313system.cpu0.icache.fast_writes 0 # number of fast writes performed 1314system.cpu0.icache.cache_copies 0 # number of cache copies performed | 756system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 762system.cpu0.icache.fast_writes 0 # number of fast writes performed 763system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1315system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses 1316system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses 1317system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses 1318system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses 1319system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses 1320system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses 1321system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles 1322system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles 1323system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles 1324system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles 1325system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles 1326system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles | 764system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses 765system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses 766system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses 767system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses 768system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # number of overall MSHR misses 769system.cpu0.icache.overall_mshr_misses::total 1061645 # number of overall MSHR misses 770system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407816003 # number of ReadReq MSHR miss cycles 771system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407816003 # number of ReadReq MSHR miss cycles 772system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407816003 # number of demand (read+write) MSHR miss cycles 773system.cpu0.icache.demand_mshr_miss_latency::total 7407816003 # number of demand (read+write) MSHR miss cycles 774system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407816003 # number of overall MSHR miss cycles 775system.cpu0.icache.overall_mshr_miss_latency::total 7407816003 # number of overall MSHR miss cycles |
| 1327system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 1328system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 1329system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 1330system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles | 776system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 777system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 778system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 779system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles |
| 1331system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses 1332system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses 1333system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses 1334system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses 1335system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses 1336system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses 1337system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency 1338system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency 1339system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency 1340system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency 1341system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency 1342system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency | 780system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses 781system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses 782system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses 783system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses 784system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses 785system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses 786system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency 787system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency 788system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency 789system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency 790system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency 791system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency |
| 1343system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1344system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1345system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1346system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1347system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 792system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 793system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 794system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 795system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 796system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1348system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified 1349system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr 1350system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache 1351system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue | 797system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified 798system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr 799system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache 800system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue |
| 1352system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 801system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1353system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated 1354system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued 1355system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page | 802system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated 803system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued 804system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page |
| 1356system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 805system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1357system.cpu0.l2cache.tags.replacements 355628 # number of replacements 1358system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use 1359system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks. 1360system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks. 1361system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks. 1362system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit. 1363system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor 1364system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor 1365system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor 1366system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor 1367system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor 1368system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor 1369system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy 1370system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy | 806system.cpu0.l2cache.tags.replacements 357554 # number of replacements 807system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use 808system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks. 809system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks. 810system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks. 811system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 812system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor 813system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor 814system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor 815system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor 816system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor 817system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor 818system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy 819system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy |
| 1371system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy | 820system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy |
| 1372system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy 1373system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy 1374system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy 1375system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy 1376system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id 1377system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1378system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id 1379system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id 1380system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id 1381system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id 1382system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id 1383system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id 1384system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1385system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1386system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 1387system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 1388system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id 1389system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id 1390system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id 1391system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id 1392system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 1393system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id 1394system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses 1395system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses 1396system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits 1397system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits 1398system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits 1399system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits 1400system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits 1401system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits 1402system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits 1403system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits 1404system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits 1405system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits 1406system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits 1407system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits 1408system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits 1409system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits 1410system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits 1411system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits 1412system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits 1413system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits 1414system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits 1415system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits 1416system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits 1417system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits 1418system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits 1419system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses 1420system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses 1421system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses 1422system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses 1423system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses 1424system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses 1425system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses 1426system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses 1427system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses | 821system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy 822system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy 823system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy 824system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy 825system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id 826system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 827system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id 828system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id 829system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id 830system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id 831system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id 832system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id 833system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 834system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 835system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 836system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id 837system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id 838system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id 839system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id 840system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 841system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id 842system.cpu0.l2cache.tags.tag_accesses 38013369 # Number of tag accesses 843system.cpu0.l2cache.tags.data_accesses 38013369 # Number of data accesses 844system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7065 # number of ReadReq hits 845system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3186 # number of ReadReq hits 846system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1046032 # number of ReadReq hits 847system.cpu0.l2cache.ReadReq_hits::cpu0.data 372434 # number of ReadReq hits 848system.cpu0.l2cache.ReadReq_hits::total 1428717 # number of ReadReq hits 849system.cpu0.l2cache.Writeback_hits::writebacks 483361 # number of Writeback hits 850system.cpu0.l2cache.Writeback_hits::total 483361 # number of Writeback hits 851system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10097 # number of UpgradeReq hits 852system.cpu0.l2cache.UpgradeReq_hits::total 10097 # number of UpgradeReq hits 853system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2054 # number of SCUpgradeReq hits 854system.cpu0.l2cache.SCUpgradeReq_hits::total 2054 # number of SCUpgradeReq hits 855system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212764 # number of ReadExReq hits 856system.cpu0.l2cache.ReadExReq_hits::total 212764 # number of ReadExReq hits 857system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7065 # number of demand (read+write) hits 858system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3186 # number of demand (read+write) hits 859system.cpu0.l2cache.demand_hits::cpu0.inst 1046032 # number of demand (read+write) hits 860system.cpu0.l2cache.demand_hits::cpu0.data 585198 # number of demand (read+write) hits 861system.cpu0.l2cache.demand_hits::total 1641481 # number of demand (read+write) hits 862system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7065 # number of overall hits 863system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3186 # number of overall hits 864system.cpu0.l2cache.overall_hits::cpu0.inst 1046032 # number of overall hits 865system.cpu0.l2cache.overall_hits::cpu0.data 585198 # number of overall hits 866system.cpu0.l2cache.overall_hits::total 1641481 # number of overall hits 867system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 284 # number of ReadReq misses 868system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 213 # number of ReadReq misses 869system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15613 # number of ReadReq misses 870system.cpu0.l2cache.ReadReq_misses::cpu0.data 83733 # number of ReadReq misses 871system.cpu0.l2cache.ReadReq_misses::total 99843 # number of ReadReq misses 872system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29803 # number of UpgradeReq misses 873system.cpu0.l2cache.UpgradeReq_misses::total 29803 # number of UpgradeReq misses 874system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19308 # number of SCUpgradeReq misses 875system.cpu0.l2cache.SCUpgradeReq_misses::total 19308 # number of SCUpgradeReq misses |
| 1428system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 1429system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses | 876system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 877system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses |
| 1430system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses 1431system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses 1432system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses 1433system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses 1434system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses 1435system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses 1436system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses 1437system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses 1438system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses 1439system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses 1440system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses 1441system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses 1442system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles 1443system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles 1444system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles 1445system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles 1446system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles 1447system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles 1448system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles 1449system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles 1450system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles 1451system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles 1452system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles 1453system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles 1454system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles 1455system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles 1456system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles 1457system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles 1458system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles 1459system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles 1460system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles 1461system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles 1462system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles 1463system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles 1464system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles 1465system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses) 1466system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses) 1467system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses) 1468system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses) 1469system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses) 1470system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses) 1471system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses) 1472system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses) 1473system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses) 1474system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses) 1475system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses) | 878system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44911 # number of ReadExReq misses 879system.cpu0.l2cache.ReadExReq_misses::total 44911 # number of ReadExReq misses 880system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 284 # number of demand (read+write) misses 881system.cpu0.l2cache.demand_misses::cpu0.itb.walker 213 # number of demand (read+write) misses 882system.cpu0.l2cache.demand_misses::cpu0.inst 15613 # number of demand (read+write) misses 883system.cpu0.l2cache.demand_misses::cpu0.data 128644 # number of demand (read+write) misses 884system.cpu0.l2cache.demand_misses::total 144754 # number of demand (read+write) misses 885system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 284 # number of overall misses 886system.cpu0.l2cache.overall_misses::cpu0.itb.walker 213 # number of overall misses 887system.cpu0.l2cache.overall_misses::cpu0.inst 15613 # number of overall misses 888system.cpu0.l2cache.overall_misses::cpu0.data 128644 # number of overall misses 889system.cpu0.l2cache.overall_misses::total 144754 # number of overall misses 890system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6608000 # number of ReadReq miss cycles 891system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4758500 # number of ReadReq miss cycles 892system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598124482 # number of ReadReq miss cycles 893system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2271341908 # number of ReadReq miss cycles 894system.cpu0.l2cache.ReadReq_miss_latency::total 2880832890 # number of ReadReq miss cycles 895system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522877259 # number of UpgradeReq miss cycles 896system.cpu0.l2cache.UpgradeReq_miss_latency::total 522877259 # number of UpgradeReq miss cycles 897system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377985887 # number of SCUpgradeReq miss cycles 898system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377985887 # number of SCUpgradeReq miss cycles 899system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1224995 # number of SCUpgradeFailReq miss cycles 900system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1224995 # number of SCUpgradeFailReq miss cycles 901system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513514605 # number of ReadExReq miss cycles 902system.cpu0.l2cache.ReadExReq_miss_latency::total 1513514605 # number of ReadExReq miss cycles 903system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6608000 # number of demand (read+write) miss cycles 904system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4758500 # number of demand (read+write) miss cycles 905system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598124482 # number of demand (read+write) miss cycles 906system.cpu0.l2cache.demand_miss_latency::cpu0.data 3784856513 # number of demand (read+write) miss cycles 907system.cpu0.l2cache.demand_miss_latency::total 4394347495 # number of demand (read+write) miss cycles 908system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6608000 # number of overall miss cycles 909system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4758500 # number of overall miss cycles 910system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598124482 # number of overall miss cycles 911system.cpu0.l2cache.overall_miss_latency::cpu0.data 3784856513 # number of overall miss cycles 912system.cpu0.l2cache.overall_miss_latency::total 4394347495 # number of overall miss cycles 913system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7349 # number of ReadReq accesses(hits+misses) 914system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3399 # number of ReadReq accesses(hits+misses) 915system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061645 # number of ReadReq accesses(hits+misses) 916system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456167 # number of ReadReq accesses(hits+misses) 917system.cpu0.l2cache.ReadReq_accesses::total 1528560 # number of ReadReq accesses(hits+misses) 918system.cpu0.l2cache.Writeback_accesses::writebacks 483361 # number of Writeback accesses(hits+misses) 919system.cpu0.l2cache.Writeback_accesses::total 483361 # number of Writeback accesses(hits+misses) 920system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39900 # number of UpgradeReq accesses(hits+misses) 921system.cpu0.l2cache.UpgradeReq_accesses::total 39900 # number of UpgradeReq accesses(hits+misses) 922system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21362 # number of SCUpgradeReq accesses(hits+misses) 923system.cpu0.l2cache.SCUpgradeReq_accesses::total 21362 # number of SCUpgradeReq accesses(hits+misses) |
| 1476system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1477system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) | 924system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 925system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) |
| 1478system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses) 1479system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses) 1480system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses 1481system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses 1482system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses 1483system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses 1484system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses 1485system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses 1486system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses 1487system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses 1488system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses 1489system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses 1490system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses 1491system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses 1492system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses 1493system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses 1494system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses 1495system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses 1496system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses 1497system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses 1498system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses | 926system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257675 # number of ReadExReq accesses(hits+misses) 927system.cpu0.l2cache.ReadExReq_accesses::total 257675 # number of ReadExReq accesses(hits+misses) 928system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7349 # number of demand (read+write) accesses 929system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3399 # number of demand (read+write) accesses 930system.cpu0.l2cache.demand_accesses::cpu0.inst 1061645 # number of demand (read+write) accesses 931system.cpu0.l2cache.demand_accesses::cpu0.data 713842 # number of demand (read+write) accesses 932system.cpu0.l2cache.demand_accesses::total 1786235 # number of demand (read+write) accesses 933system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7349 # number of overall (read+write) accesses 934system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3399 # number of overall (read+write) accesses 935system.cpu0.l2cache.overall_accesses::cpu0.inst 1061645 # number of overall (read+write) accesses 936system.cpu0.l2cache.overall_accesses::cpu0.data 713842 # number of overall (read+write) accesses 937system.cpu0.l2cache.overall_accesses::total 1786235 # number of overall (read+write) accesses 938system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for ReadReq accesses 939system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.062665 # miss rate for ReadReq accesses 940system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014706 # miss rate for ReadReq accesses 941system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183558 # miss rate for ReadReq accesses 942system.cpu0.l2cache.ReadReq_miss_rate::total 0.065318 # miss rate for ReadReq accesses 943system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.746942 # miss rate for UpgradeReq accesses 944system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.746942 # miss rate for UpgradeReq accesses 945system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.903848 # miss rate for SCUpgradeReq accesses 946system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.903848 # miss rate for SCUpgradeReq accesses |
| 1499system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1500system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 947system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 948system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1501system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses 1502system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses 1503system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses 1504system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses 1505system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses 1506system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses 1507system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses 1508system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses 1509system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses 1510system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses 1511system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses 1512system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses 1513system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency 1514system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency 1515system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency 1516system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency 1517system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency 1518system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency 1519system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency 1520system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency 1521system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency 1522system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency 1523system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency 1524system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency 1525system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency 1526system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency 1527system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency 1528system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency 1529system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency 1530system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency 1531system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency 1532system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency 1533system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency 1534system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency 1535system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency 1536system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked | 949system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174293 # miss rate for ReadExReq accesses 950system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174293 # miss rate for ReadExReq accesses 951system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for demand accesses 952system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.062665 # miss rate for demand accesses 953system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014706 # miss rate for demand accesses 954system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180214 # miss rate for demand accesses 955system.cpu0.l2cache.demand_miss_rate::total 0.081039 # miss rate for demand accesses 956system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for overall accesses 957system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.062665 # miss rate for overall accesses 958system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014706 # miss rate for overall accesses 959system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180214 # miss rate for overall accesses 960system.cpu0.l2cache.overall_miss_rate::total 0.081039 # miss rate for overall accesses 961system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average ReadReq miss latency 962system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22340.375587 # average ReadReq miss latency 963system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38309.388458 # average ReadReq miss latency 964system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27126.006568 # average ReadReq miss latency 965system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28853.629098 # average ReadReq miss latency 966system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17544.450525 # average UpgradeReq miss latency 967system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525 # average UpgradeReq miss latency 968system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312 # average SCUpgradeReq miss latency 969system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19576.646312 # average SCUpgradeReq miss latency 970system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 153124.375000 # average SCUpgradeFailReq miss latency 971system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 153124.375000 # average SCUpgradeFailReq miss latency 972system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33700.309612 # average ReadExReq miss latency 973system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33700.309612 # average ReadExReq miss latency 974system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency 975system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency 976system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency 977system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency 978system.cpu0.l2cache.demand_avg_miss_latency::total 30357.347604 # average overall miss latency 979system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency 980system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency 981system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency 982system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency 983system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604 # average overall miss latency 984system.cpu0.l2cache.blocked_cycles::no_mshrs 6544 # number of cycles access was blocked |
| 1537system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 985system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1538system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked | 986system.cpu0.l2cache.blocked::no_mshrs 99 # number of cycles access was blocked |
| 1539system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 987system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1540system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked | 988system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 66.101010 # average number of cycles each access was blocked |
| 1541system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1542system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1543system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 989system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 990system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 991system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1544system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks 1545system.cpu0.l2cache.writebacks::total 204753 # number of writebacks 1546system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits 1547system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits 1548system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits 1549system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits 1550system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits 1551system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits 1552system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits 1553system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits 1554system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits 1555system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits 1556system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits 1557system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses 1558system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses 1559system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses 1560system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses 1561system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses 1562system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses 1563system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses 1564system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses 1565system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses 1566system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses 1567system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses | 992system.cpu0.l2cache.writebacks::writebacks 205226 # number of writebacks 993system.cpu0.l2cache.writebacks::total 205226 # number of writebacks 994system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2290 # number of ReadReq MSHR hits 995system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2728 # number of ReadReq MSHR hits 996system.cpu0.l2cache.ReadReq_mshr_hits::total 5018 # number of ReadReq MSHR hits 997system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits 998system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits 999system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2290 # number of demand (read+write) MSHR hits 1000system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3938 # number of demand (read+write) MSHR hits 1001system.cpu0.l2cache.demand_mshr_hits::total 6228 # number of demand (read+write) MSHR hits 1002system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2290 # number of overall MSHR hits 1003system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3938 # number of overall MSHR hits 1004system.cpu0.l2cache.overall_mshr_hits::total 6228 # number of overall MSHR hits 1005system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 284 # number of ReadReq MSHR misses 1006system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 213 # number of ReadReq MSHR misses 1007system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13323 # number of ReadReq MSHR misses 1008system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 81005 # number of ReadReq MSHR misses 1009system.cpu0.l2cache.ReadReq_mshr_misses::total 94825 # number of ReadReq MSHR misses 1010system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of HardPFReq MSHR misses 1011system.cpu0.l2cache.HardPFReq_mshr_misses::total 445317 # number of HardPFReq MSHR misses 1012system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29803 # number of UpgradeReq MSHR misses 1013system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29803 # number of UpgradeReq MSHR misses 1014system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19308 # number of SCUpgradeReq MSHR misses 1015system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19308 # number of SCUpgradeReq MSHR misses |
| 1568system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1569system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses | 1016system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1017system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses |
| 1570system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses 1571system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses 1572system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses 1573system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses 1574system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses 1575system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses 1576system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses 1577system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses 1578system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses 1579system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses 1580system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses 1581system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses 1582system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses 1583system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles 1584system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles 1585system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles 1586system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles 1587system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles 1588system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles 1589system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles 1590system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # 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number of demand (read+write) MSHR miss cycles 1600system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles 1601system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles 1602system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles 1603system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles 1604system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles 1605system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles 1606system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles 1607system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles 1608system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles | 1018system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43701 # number of ReadExReq MSHR misses 1019system.cpu0.l2cache.ReadExReq_mshr_misses::total 43701 # number of ReadExReq MSHR misses 1020system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 284 # number of demand (read+write) MSHR misses 1021system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 213 # number of demand (read+write) MSHR misses 1022system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13323 # number of demand (read+write) MSHR misses 1023system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124706 # number of demand (read+write) MSHR misses 1024system.cpu0.l2cache.demand_mshr_misses::total 138526 # number of demand (read+write) MSHR misses 1025system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 284 # number of overall MSHR misses 1026system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 213 # number of overall MSHR misses 1027system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13323 # number of overall MSHR misses 1028system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124706 # number of overall MSHR misses 1029system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of overall MSHR misses 1030system.cpu0.l2cache.overall_mshr_misses::total 583843 # number of overall MSHR misses 1031system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of ReadReq MSHR miss cycles 1032system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3267500 # number of ReadReq MSHR miss cycles 1033system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457593766 # number of ReadReq MSHR miss cycles 1034system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1665461966 # number of ReadReq MSHR miss cycles 1035system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2130941732 # number of ReadReq MSHR miss cycles 1036system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of HardPFReq MSHR miss cycles 1037system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17831693567 # number of HardPFReq MSHR miss cycles 1038system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489548028 # number of UpgradeReq MSHR miss cycles 1039system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489548028 # number of UpgradeReq MSHR miss cycles 1040system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261537598 # number of SCUpgradeReq MSHR miss cycles 1041system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261537598 # number of SCUpgradeReq MSHR miss cycles 1042system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 965995 # number of SCUpgradeFailReq MSHR miss cycles 1043system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 965995 # number of SCUpgradeFailReq MSHR miss cycles 1044system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080387358 # number of ReadExReq MSHR miss cycles 1045system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080387358 # number of ReadExReq MSHR miss cycles 1046system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4618500 # 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number of overall MSHR miss cycles 1056system.cpu0.l2cache.overall_mshr_miss_latency::total 21043022657 # number of overall MSHR miss cycles |
| 1609system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles | 1057system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles |
| 1610system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles 1611system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles 1612system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles 1613system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles | 1058system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328411497 # number of ReadReq MSHR uncacheable cycles 1059system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975619997 # number of ReadReq MSHR uncacheable cycles 1060system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3986952006 # number of WriteReq MSHR uncacheable cycles 1061system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3986952006 # number of WriteReq MSHR uncacheable cycles |
| 1614system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles | 1062system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles |
| 1615system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles 1616system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles 1617system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses 1618system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses 1619system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses 1620system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses 1621system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses | 1063system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315363503 # number of overall MSHR uncacheable cycles 1064system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962572003 # number of overall MSHR uncacheable cycles 1065system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for ReadReq accesses 1066system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for ReadReq accesses 1067system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for ReadReq accesses 1068system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177578 # mshr miss rate for ReadReq accesses 1069system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062036 # mshr miss rate for ReadReq accesses |
| 1622system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1623system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1070system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1071system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1624system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses 1625system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses 1626system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses 1627system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses | 1072system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.746942 # mshr miss rate for UpgradeReq accesses 1073system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.746942 # mshr miss rate for UpgradeReq accesses 1074system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.903848 # mshr miss rate for SCUpgradeReq accesses 1075system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.903848 # mshr miss rate for SCUpgradeReq accesses |
| 1628system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1629system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1076system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1077system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1630system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses 1631system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses 1632system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses 1633system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses 1634system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses 1635system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses 1636system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses 1637system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses 1638system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses 1639system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses 1640system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses | 1078system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses 1079system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses 1080system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses 1081system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses 1082system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for demand accesses 1083system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for demand accesses 1084system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077552 # mshr miss rate for demand accesses 1085system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses 1086system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses 1087system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses 1088system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses |
| 1641system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1089system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1642system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses 1643system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency 1644system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency 1645system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency 1646system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency 1647system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency 1648system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency 1649system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency 1650system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency 1651system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency 1652system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency 1653system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency 1654system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency 1655system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency 1656system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency 1657system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency 1658system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency 1659system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency 1660system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency 1661system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency 1662system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency 1663system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency 1664system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency 1665system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency 1666system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency 1667system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency 1668system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency | 1090system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses 1091system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency 1092system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency 1093system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency 1094system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency 1095system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency 1096system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency 1097system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency 1098system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency 1099system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency 1100system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency 1101system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency 1102system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency 1103system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency 1104system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency 1105system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency 1106system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency 1107system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency 1108system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency 1109system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency 1110system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency 1111system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency 1112system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency 1113system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency 1114system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency 1115system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency 1116system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency |
| 1669system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1670system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1671system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1672system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1673system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1674system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1675system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1676system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1677system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1117system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1118system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1119system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1120system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1121system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1122system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1123system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1124system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1125system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1678system.cpu0.dcache.tags.replacements 659666 # number of replacements 1679system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use 1680system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks. 1681system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks. 1682system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks. 1683system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. 1684system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor 1685system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy 1686system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy 1687system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1688system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 1689system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 1690system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id 1691system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1692system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses 1693system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses 1694system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits 1695system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits 1696system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits 1697system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits 1698system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits 1699system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits 1700system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits 1701system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits 1702system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits 1703system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits 1704system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits 1705system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits 1706system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits 1707system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits 1708system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses 1709system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses 1710system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses 1711system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses 1712system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses 1713system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses 1714system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses 1715system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses 1716system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses 1717system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses 1718system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses 1719system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses 1720system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses 1721system.cpu0.dcache.overall_misses::total 765091 # number of overall misses 1722system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles 1723system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles 1724system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles 1725system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles 1726system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles 1727system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles 1728system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles 1729system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles 1730system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles 1731system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles 1732system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles 1733system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles 1734system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles 1735system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles 1736system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses) 1737system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses) 1738system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses) 1739system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses) 1740system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses) 1741system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses) 1742system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses) 1743system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses) 1744system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses) 1745system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses) 1746system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses 1747system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses 1748system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses 1749system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses 1750system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses 1751system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses 1752system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses 1753system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses 1754system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses 1755system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses 1756system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses 1757system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses 1758system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses 1759system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses 1760system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses 1761system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses 1762system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses 1763system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses 1764system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency 1765system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency 1766system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency 1767system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency 1768system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency 1769system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency 1770system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency 1771system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency 1772system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1773system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1774system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency 1775system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency 1776system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency 1777system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency 1778system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1779system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1780system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1781system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1782system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1783system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1784system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1785system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1786system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks 1787system.cpu0.dcache.writebacks::total 484431 # number of writebacks 1788system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits 1789system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits 1790system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits 1791system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits 1792system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits 1793system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits 1794system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits 1795system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits 1796system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses 1797system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses 1798system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses 1799system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses 1800system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses 1801system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses 1802system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses 1803system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses 1804system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses 1805system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses 1806system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses 1807system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses 1808system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses 1809system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses 1810system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles 1811system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles 1812system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles 1813system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles 1814system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles 1815system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles 1816system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles 1817system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles 1818system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles 1819system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles 1820system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles 1821system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles 1822system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles 1823system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles 1824system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles 1825system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles 1826system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles 1827system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles 1828system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles 1829system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles 1830system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles 1831system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles 1832system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses 1833system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses 1834system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses 1835system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses 1836system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses 1837system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses 1838system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses 1839system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses 1840system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses 1841system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses 1842system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses 1843system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses 1844system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses 1845system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses 1846system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency 1847system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency 1848system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency 1849system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency 1850system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency 1851system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency 1852system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency 1853system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency 1854system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency 1855system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency 1856system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1857system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1858system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency 1859system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency 1860system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency 1861system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency 1862system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1863system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1864system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1865system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1866system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1867system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1868system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1869system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution 1870system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution 1871system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution 1872system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution 1873system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution 1874system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution | 1126system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution 1127system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution 1128system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution 1129system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution 1130system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution 1131system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution |
| 1875system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution | 1132system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution |
| 1876system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution 1877system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution 1878system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution 1879system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution | 1133system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution 1134system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution 1135system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution 1136system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution |
| 1880system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution | 1137system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution |
| 1881system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution 1882system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution 1883system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes) 1884system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes) 1885system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes) 1886system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes) 1887system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes) 1888system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes) 1889system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes) 1890system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes) 1891system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes) 1892system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes) 1893system.cpu0.toL2Bus.snoops 985271 # Total snoops (count) 1894system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram 1895system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram 1896system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram | 1138system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution 1139system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution 1140system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes) 1141system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes) 1142system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes) 1143system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes) 1144system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes) 1145system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes) 1146system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes) 1147system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes) 1148system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes) 1149system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes) 1150system.cpu0.toL2Bus.snoops 988296 # Total snoops (count) 1151system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram 1152system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram 1153system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram |
| 1897system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1898system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1899system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1900system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1901system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1902system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1154system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1155system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1156system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1157system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1158system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1159system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1903system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram 1904system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram | 1160system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram 1161system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram |
| 1905system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1906system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1907system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1162system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1163system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1164system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1908system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram 1909system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks) | 1165system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram 1166system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks) |
| 1910system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1167system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1911system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks) | 1168system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks) |
| 1912system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1169system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1913system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks) | 1170system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks) |
| 1914system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1171system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1915system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks) | 1172system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks) |
| 1916system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1173system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1917system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) | 1174system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) |
| 1918system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1175system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1919system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks) | 1176system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks) |
| 1920system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1921system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1922system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1923system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1924system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1925system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1926system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1927system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1936system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1937system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1938system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1939system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1940system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1941system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1942system.cpu1.dtb.inst_hits 0 # ITB inst hits 1943system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1177system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1178system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1179system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1180system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1181system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1182system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1183system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1184system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1193system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1194system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1195system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1196system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1197system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1198system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1199system.cpu1.dtb.inst_hits 0 # ITB inst hits 1200system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1944system.cpu1.dtb.read_hits 4826536 # DTB read hits 1945system.cpu1.dtb.read_misses 2746 # DTB read misses 1946system.cpu1.dtb.write_hits 4130096 # DTB write hits 1947system.cpu1.dtb.write_misses 525 # DTB write misses | 1201system.cpu1.dtb.read_hits 4826061 # DTB read hits 1202system.cpu1.dtb.read_misses 2744 # DTB read misses 1203system.cpu1.dtb.write_hits 4130169 # DTB write hits 1204system.cpu1.dtb.write_misses 524 # DTB write misses |
| 1948system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1949system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1950system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1951system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1952system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB 1953system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1205system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1206system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1207system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1208system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1209system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB 1210system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1954system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch | 1211system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch |
| 1955system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1956system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions | 1212system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1213system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions |
| 1957system.cpu1.dtb.read_accesses 4829282 # DTB read accesses 1958system.cpu1.dtb.write_accesses 4130621 # DTB write accesses | 1214system.cpu1.dtb.read_accesses 4828805 # DTB read accesses 1215system.cpu1.dtb.write_accesses 4130693 # DTB write accesses |
| 1959system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1216system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1960system.cpu1.dtb.hits 8956632 # DTB hits 1961system.cpu1.dtb.misses 3271 # DTB misses 1962system.cpu1.dtb.accesses 8959903 # DTB accesses | 1217system.cpu1.dtb.hits 8956230 # DTB hits 1218system.cpu1.dtb.misses 3268 # DTB misses 1219system.cpu1.dtb.accesses 8959498 # DTB accesses |
| 1963system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1964system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1965system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1966system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1967system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1968system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1969system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1970system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1976system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1977system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1978system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1979system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1980system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1981system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1982system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1983system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1220system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1221system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1222system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1223system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1224system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1225system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1226system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1227system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1233system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1234system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1235system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1236system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1237system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1238system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1239system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1240system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1984system.cpu1.itb.inst_hits 20887785 # ITB inst hits | 1241system.cpu1.itb.inst_hits 20883965 # ITB inst hits |
| 1985system.cpu1.itb.inst_misses 1747 # ITB inst misses 1986system.cpu1.itb.read_hits 0 # DTB read hits 1987system.cpu1.itb.read_misses 0 # DTB read misses 1988system.cpu1.itb.write_hits 0 # DTB write hits 1989system.cpu1.itb.write_misses 0 # DTB write misses 1990system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1991system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1992system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1993system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1994system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB 1995system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1996system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1997system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1998system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1999system.cpu1.itb.read_accesses 0 # DTB read accesses 2000system.cpu1.itb.write_accesses 0 # DTB write accesses | 1242system.cpu1.itb.inst_misses 1747 # ITB inst misses 1243system.cpu1.itb.read_hits 0 # DTB read hits 1244system.cpu1.itb.read_misses 0 # DTB read misses 1245system.cpu1.itb.write_hits 0 # DTB write hits 1246system.cpu1.itb.write_misses 0 # DTB write misses 1247system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1248system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1249system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1250system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1251system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB 1252system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1253system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1254system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1255system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1256system.cpu1.itb.read_accesses 0 # DTB read accesses 1257system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 2001system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses 2002system.cpu1.itb.hits 20887785 # DTB hits | 1258system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses 1259system.cpu1.itb.hits 20883965 # DTB hits |
| 2003system.cpu1.itb.misses 1747 # DTB misses | 1260system.cpu1.itb.misses 1747 # DTB misses |
| 2004system.cpu1.itb.accesses 20889532 # DTB accesses 2005system.cpu1.numCycles 5732937622 # number of cpu cycles simulated | 1261system.cpu1.itb.accesses 20885712 # DTB accesses 1262system.cpu1.numCycles 5732918807 # number of cpu cycles simulated |
| 2006system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2007system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1263system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1264system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2008system.cpu1.committedInsts 20506953 # Number of instructions committed 2009system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed 2010system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses | 1265system.cpu1.committedInsts 20503191 # Number of instructions committed 1266system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed 1267system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses |
| 2011system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses | 1268system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses |
| 2012system.cpu1.num_func_calls 1209546 # number of times a function call or return occured 2013system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls 2014system.cpu1.num_int_insts 22187475 # number of integer instructions | 1269system.cpu1.num_func_calls 1209330 # number of times a function call or return occured 1270system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls 1271system.cpu1.num_int_insts 22184707 # number of integer instructions |
| 2015system.cpu1.num_fp_insts 1792 # number of float instructions | 1272system.cpu1.num_fp_insts 1792 # number of float instructions |
| 2016system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read 2017system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written | 1273system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read 1274system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written |
| 2018system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 2019system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written | 1275system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 1276system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written |
| 2020system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read 2021system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written 2022system.cpu1.num_mem_refs 9246104 # number of memory refs 2023system.cpu1.num_load_insts 4945808 # Number of load instructions 2024system.cpu1.num_store_insts 4300296 # Number of store instructions 2025system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles 2026system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles 2027system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles 2028system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles 2029system.cpu1.Branches 3892449 # Number of branches fetched | 1277system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read 1278system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written 1279system.cpu1.num_mem_refs 9245671 # number of memory refs 1280system.cpu1.num_load_insts 4945342 # Number of load instructions 1281system.cpu1.num_store_insts 4300329 # Number of store instructions 1282system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles 1283system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles 1284system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles 1285system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles 1286system.cpu1.Branches 3891928 # Number of branches fetched |
| 2030system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction | 1287system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction |
| 2031system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction 2032system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction | 1288system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction 1289system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction |
| 2033system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction 2034system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction 2035system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction 2036system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction 2037system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction 2038system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction 2039system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction 2040system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 2048system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction 2049system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction 2050system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction 2051system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction 2052system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction 2053system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction 2054system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction 2055system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction | 1290system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction 1291system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction 1292system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction 1293system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction 1294system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction 1295system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction 1296system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction 1297system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 1305system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction 1306system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction 1307system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction 1308system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction 1309system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction 1310system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction 1311system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction 1312system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction |
| 2056system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction | 1313system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction |
| 2057system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction 2058system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction 2059system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction | 1314system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction 1315system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction 1316system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction |
| 2060system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction 2061system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction | 1317system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction 1318system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction |
| 2062system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2063system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1319system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1320system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 2064system.cpu1.op_class::total 25300005 # Class of executed instruction | 1321system.cpu1.op_class::total 25296825 # Class of executed instruction |
| 2065system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1322system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2066system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed 2067system.cpu1.icache.tags.replacements 565422 # number of replacements 2068system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use 2069system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks. 2070system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks. 2071system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks. 2072system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit. 2073system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor | 1323system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed 1324system.cpu1.dcache.tags.replacements 218952 # number of replacements 1325system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use 1326system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks. 1327system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks. 1328system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks. 1329system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. 1330system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor 1331system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy 1332system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy 1333system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id 1334system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id 1335system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id 1336system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id 1337system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses 1338system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses 1339system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits 1340system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits 1341system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits 1342system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits 1343system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits 1344system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits 1345system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits 1346system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits 1347system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits 1348system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits 1349system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits 1350system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits 1351system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits 1352system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits 1353system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses 1354system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses 1355system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses 1356system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses 1357system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses 1358system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses 1359system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses 1360system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses 1361system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses 1362system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses 1363system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses 1364system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses 1365system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses 1366system.cpu1.dcache.overall_misses::total 293221 # number of overall misses 1367system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles 1368system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles 1369system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles 1370system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles 1371system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles 1372system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles 1373system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles 1374system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles 1375system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles 1376system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles 1377system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles 1378system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles 1379system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles 1380system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles 1381system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses) 1382system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses) 1383system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses) 1384system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses) 1385system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses) 1386system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses) 1387system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses) 1388system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses) 1389system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses) 1390system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses) 1391system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses 1392system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses 1393system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses 1394system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses 1395system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses 1396system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses 1397system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses 1398system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses 1399system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses 1400system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses 1401system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses 1402system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses 1403system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses 1404system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses 1405system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses 1406system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses 1407system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses 1408system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses 1409system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency 1410system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency 1411system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency 1412system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency 1413system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency 1414system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency 1415system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency 1416system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency 1417system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1418system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1419system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605 # average overall miss latency 1420system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605 # average overall miss latency 1421system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122 # average overall miss latency 1422system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122 # average overall miss latency 1423system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1424system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1425system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1426system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1427system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1428system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1429system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1430system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1431system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks 1432system.cpu1.dcache.writebacks::total 135060 # number of writebacks 1433system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits 1434system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits 1435system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits 1436system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 1437system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # number of LoadLockedReq MSHR hits 1438system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12325 # number of LoadLockedReq MSHR hits 1439system.cpu1.dcache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits 1440system.cpu1.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits 1441system.cpu1.dcache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits 1442system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits 1443system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154894 # number of ReadReq MSHR misses 1444system.cpu1.dcache.ReadReq_mshr_misses::total 154894 # number of ReadReq MSHR misses 1445system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103785 # number of WriteReq MSHR misses 1446system.cpu1.dcache.WriteReq_mshr_misses::total 103785 # number of WriteReq MSHR misses 1447system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33053 # number of SoftPFReq MSHR misses 1448system.cpu1.dcache.SoftPFReq_mshr_misses::total 33053 # number of SoftPFReq MSHR misses 1449system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5608 # number of LoadLockedReq MSHR misses 1450system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5608 # number of LoadLockedReq MSHR misses 1451system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23205 # number of StoreCondReq MSHR misses 1452system.cpu1.dcache.StoreCondReq_mshr_misses::total 23205 # number of StoreCondReq MSHR misses 1453system.cpu1.dcache.demand_mshr_misses::cpu1.data 258679 # number of demand (read+write) MSHR misses 1454system.cpu1.dcache.demand_mshr_misses::total 258679 # number of demand (read+write) MSHR misses 1455system.cpu1.dcache.overall_mshr_misses::cpu1.data 291732 # number of overall MSHR misses 1456system.cpu1.dcache.overall_mshr_misses::total 291732 # number of overall MSHR misses 1457system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1899677974 # number of ReadReq MSHR miss cycles 1458system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1899677974 # number of ReadReq MSHR miss cycles 1459system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2055753168 # number of WriteReq MSHR miss cycles 1460system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2055753168 # number of WriteReq MSHR miss cycles 1461system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496489496 # number of SoftPFReq MSHR miss cycles 1462system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496489496 # number of SoftPFReq MSHR miss cycles 1463system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84032750 # number of LoadLockedReq MSHR miss cycles 1464system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84032750 # number of LoadLockedReq MSHR miss cycles 1465system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490566779 # number of StoreCondReq MSHR miss cycles 1466system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490566779 # number of StoreCondReq MSHR miss cycles 1467system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1599500 # number of StoreCondFailReq MSHR miss cycles 1468system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1599500 # number of StoreCondFailReq MSHR miss cycles 1469system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3955431142 # number of demand (read+write) MSHR miss cycles 1470system.cpu1.dcache.demand_mshr_miss_latency::total 3955431142 # number of demand (read+write) MSHR miss cycles 1471system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4451920638 # number of overall MSHR miss cycles 1472system.cpu1.dcache.overall_mshr_miss_latency::total 4451920638 # number of overall MSHR miss cycles 1473system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961065499 # number of ReadReq MSHR uncacheable cycles 1474system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961065499 # number of ReadReq MSHR uncacheable cycles 1475system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382997 # number of WriteReq MSHR uncacheable cycles 1476system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382997 # number of WriteReq MSHR uncacheable cycles 1477system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794448496 # number of overall MSHR uncacheable cycles 1478system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794448496 # number of overall MSHR uncacheable cycles 1479system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033549 # mshr miss rate for ReadReq accesses 1480system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033549 # mshr miss rate for ReadReq accesses 1481system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025803 # mshr miss rate for WriteReq accesses 1482system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025803 # mshr miss rate for WriteReq accesses 1483system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.336038 # mshr miss rate for SoftPFReq accesses 1484system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.336038 # mshr miss rate for SoftPFReq accesses 1485system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053352 # mshr miss rate for LoadLockedReq accesses 1486system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses 1487system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225635 # mshr miss rate for StoreCondReq accesses 1488system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225635 # mshr miss rate for StoreCondReq accesses 1489system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses 1490system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses 1491system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033388 # mshr miss rate for overall accesses 1492system.cpu1.dcache.overall_mshr_miss_rate::total 0.033388 # mshr miss rate for overall accesses 1493system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178 # average ReadReq mshr miss latency 1494system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency 1495system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215 # average WriteReq mshr miss latency 1496system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215 # average WriteReq mshr miss latency 1497system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587 # average SoftPFReq mshr miss latency 1498system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587 # average SoftPFReq mshr miss latency 1499system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency 1500system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency 1501system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency 1502system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency 1503system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1504system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1505system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency 1506system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency 1507system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency 1508system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency 1509system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1510system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1511system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1512system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1513system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1514system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1516system.cpu1.icache.tags.replacements 565004 # number of replacements 1517system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use 1518system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks. 1519system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks. 1520system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks. 1521system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. 1522system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor |
| 2074system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy 2075system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy 2076system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2077system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id | 1523system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy 1524system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy 1525system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1526system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id |
| 2078system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id 2079system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id | 1527system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id 1528system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id |
| 2080system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1529system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2081system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses 2082system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses 2083system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits 2084system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits 2085system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits 2086system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits 2087system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits 2088system.cpu1.icache.overall_hits::total 20321845 # number of overall hits 2089system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses 2090system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses 2091system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses 2092system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses 2093system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses 2094system.cpu1.icache.overall_misses::total 565935 # number of overall misses 2095system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles 2096system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles 2097system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles 2098system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles 2099system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles 2100system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles 2101system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses) 2102system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses) 2103system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses 2104system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses 2105system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses 2106system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses 2107system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses 2108system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses 2109system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses 2110system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses 2111system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses 2112system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses 2113system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency 2114system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency 2115system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency 2116system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency 2117system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency 2118system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency | 1530system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses 1531system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses 1532system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits 1533system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits 1534system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits 1535system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits 1536system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits 1537system.cpu1.icache.overall_hits::total 20318443 # number of overall hits 1538system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses 1539system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses 1540system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses 1541system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses 1542system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses 1543system.cpu1.icache.overall_misses::total 565517 # number of overall misses 1544system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles 1545system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles 1546system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles 1547system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles 1548system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles 1549system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles 1550system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses) 1551system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses) 1552system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses 1553system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses 1554system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses 1555system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses 1556system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses 1557system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses 1558system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses 1559system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses 1560system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses 1561system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses 1562system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency 1563system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency 1564system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency 1565system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency 1566system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency 1567system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency |
| 2119system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2120system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2121system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2122system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2123system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2124system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2125system.cpu1.icache.fast_writes 0 # number of fast writes performed 2126system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1568system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1569system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1570system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1571system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1572system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1573system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1574system.cpu1.icache.fast_writes 0 # number of fast writes performed 1575system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2127system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses 2128system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses 2129system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses 2130system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses 2131system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses 2132system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses 2133system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles 2134system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles 2135system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles 2136system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles 2137system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles 2138system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles | 1576system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses 1577system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses 1578system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses 1579system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses 1580system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses 1581system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses 1582system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles 1583system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles 1584system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles 1585system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles 1586system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles 1587system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles |
| 2139system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles 2140system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles 2141system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles 2142system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles | 1588system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles 1589system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles 1590system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles 1591system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles |
| 2143system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses 2144system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses 2145system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses 2146system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses 2147system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses 2148system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses 2149system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency 2150system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency 2151system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency 2152system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency 2153system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency 2154system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency | 1592system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses 1593system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses 1594system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses 1595system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses 1596system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses 1597system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses 1598system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency 1599system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency 1600system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency 1601system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency 1602system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency 1603system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency |
| 2155system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2156system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2157system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2158system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2159system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1604system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1605system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1606system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1607system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1608system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2160system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified 2161system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr 2162system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache 2163system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue | 1609system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified 1610system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr 1611system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache 1612system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue |
| 2164system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1613system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 2165system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated 2166system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued 2167system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page | 1614system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated 1615system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued 1616system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page |
| 2168system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1617system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 2169system.cpu1.l2cache.tags.replacements 85170 # number of replacements 2170system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use 2171system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks. 2172system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks. 2173system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks. 2174system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2175system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor 2176system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor 2177system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor 2178system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor 2179system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor 2180system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor 2181system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy 2182system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy 2183system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy 2184system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy 2185system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy 2186system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy 2187system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy 2188system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id 2189system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id 2190system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id 2191system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id 2192system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id 2193system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id | 1618system.cpu1.l2cache.tags.replacements 85089 # number of replacements 1619system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use 1620system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks. 1621system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks. 1622system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks. 1623system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit. 1624system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor 1625system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor 1626system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor 1627system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor 1628system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor 1629system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor 1630system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy 1631system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 1632system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy 1633system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy 1634system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy 1635system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy 1636system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy 1637system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id 1638system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1639system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id 1640system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id 1641system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id 1642system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id |
| 2194system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id | 1643system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id |
| 2195system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 2196system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 2197system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id 2198system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id 2199system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id 2200system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 2201system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id 2202system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses 2203system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses 2204system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits 2205system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits 2206system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits 2207system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits 2208system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits 2209system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits 2210system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits 2211system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits 2212system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits 2213system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits 2214system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits 2215system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits 2216system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits 2217system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits 2218system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits 2219system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits 2220system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits 2221system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits 2222system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits 2223system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits 2224system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits 2225system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits 2226system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits 2227system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses 2228system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses 2229system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses 2230system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses 2231system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses 2232system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses 2233system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses 2234system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses 2235system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses 2236system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 2237system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 2238system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses 2239system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses 2240system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses 2241system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses 2242system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses 2243system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses 2244system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses 2245system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses 2246system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses 2247system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses 2248system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses 2249system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses 2250system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles 2251system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles 2252system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles 2253system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles 2254system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles 2255system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles 2256system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles 2257system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles 2258system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles 2259system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles 2260system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles 2261system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles 2262system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles 2263system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles 2264system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles 2265system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles 2266system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles 2267system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles 2268system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles 2269system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles 2270system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles 2271system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles 2272system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles 2273system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses) 2274system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses) 2275system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses) 2276system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses) 2277system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses) 2278system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses) 2279system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses) 2280system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses) 2281system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses) 2282system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses) 2283system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses) 2284system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 2285system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 2286system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses) 2287system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses) 2288system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses 2289system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses 2290system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses 2291system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses 2292system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses 2293system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses 2294system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses 2295system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses 2296system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses 2297system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses 2298system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses 2299system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses 2300system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses 2301system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses 2302system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses 2303system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses 2304system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses 2305system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses 2306system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses | 1644system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1645system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id 1646system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id 1647system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id 1648system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id 1649system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1650system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id 1651system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses 1652system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses 1653system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits 1654system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits 1655system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits 1656system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits 1657system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits 1658system.cpu1.l2cache.Writeback_hits::writebacks 135060 # number of Writeback hits 1659system.cpu1.l2cache.Writeback_hits::total 135060 # number of Writeback hits 1660system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1609 # number of UpgradeReq hits 1661system.cpu1.l2cache.UpgradeReq_hits::total 1609 # number of UpgradeReq hits 1662system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 861 # number of SCUpgradeReq hits 1663system.cpu1.l2cache.SCUpgradeReq_hits::total 861 # number of SCUpgradeReq hits 1664system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39179 # number of ReadExReq hits 1665system.cpu1.l2cache.ReadExReq_hits::total 39179 # number of ReadExReq hits 1666system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2996 # number of demand (read+write) hits 1667system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1704 # number of demand (read+write) hits 1668system.cpu1.l2cache.demand_hits::cpu1.inst 559876 # number of demand (read+write) hits 1669system.cpu1.l2cache.demand_hits::cpu1.data 162423 # number of demand (read+write) hits 1670system.cpu1.l2cache.demand_hits::total 726999 # number of demand (read+write) hits 1671system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2996 # number of overall hits 1672system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1704 # number of overall hits 1673system.cpu1.l2cache.overall_hits::cpu1.inst 559876 # number of overall hits 1674system.cpu1.l2cache.overall_hits::cpu1.data 162423 # number of overall hits 1675system.cpu1.l2cache.overall_hits::total 726999 # number of overall hits 1676system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses 1677system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses 1678system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5641 # number of ReadReq misses 1679system.cpu1.l2cache.ReadReq_misses::cpu1.data 70311 # number of ReadReq misses 1680system.cpu1.l2cache.ReadReq_misses::total 76567 # number of ReadReq misses 1681system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29399 # number of UpgradeReq misses 1682system.cpu1.l2cache.UpgradeReq_misses::total 29399 # number of UpgradeReq misses 1683system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22337 # number of SCUpgradeReq misses 1684system.cpu1.l2cache.SCUpgradeReq_misses::total 22337 # number of SCUpgradeReq misses 1685system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses 1686system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1687system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33598 # number of ReadExReq misses 1688system.cpu1.l2cache.ReadExReq_misses::total 33598 # number of ReadExReq misses 1689system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses 1690system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses 1691system.cpu1.l2cache.demand_misses::cpu1.inst 5641 # number of demand (read+write) misses 1692system.cpu1.l2cache.demand_misses::cpu1.data 103909 # number of demand (read+write) misses 1693system.cpu1.l2cache.demand_misses::total 110165 # number of demand (read+write) misses 1694system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses 1695system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses 1696system.cpu1.l2cache.overall_misses::cpu1.inst 5641 # number of overall misses 1697system.cpu1.l2cache.overall_misses::cpu1.data 103909 # number of overall misses 1698system.cpu1.l2cache.overall_misses::total 110165 # number of overall misses 1699system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6952000 # number of ReadReq miss cycles 1700system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5546000 # number of ReadReq miss cycles 1701system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192723218 # number of ReadReq miss cycles 1702system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1546712890 # number of ReadReq miss cycles 1703system.cpu1.l2cache.ReadReq_miss_latency::total 1751934108 # number of ReadReq miss cycles 1704system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537154147 # number of UpgradeReq miss cycles 1705system.cpu1.l2cache.UpgradeReq_miss_latency::total 537154147 # number of UpgradeReq miss cycles 1706system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436854563 # number of SCUpgradeReq miss cycles 1707system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436854563 # number of SCUpgradeReq miss cycles 1708system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1562500 # number of SCUpgradeFailReq miss cycles 1709system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1562500 # number of SCUpgradeFailReq miss cycles 1710system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1072389357 # number of ReadExReq miss cycles 1711system.cpu1.l2cache.ReadExReq_miss_latency::total 1072389357 # number of ReadExReq miss cycles 1712system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6952000 # number of demand (read+write) miss cycles 1713system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5546000 # number of demand (read+write) miss cycles 1714system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192723218 # number of demand (read+write) miss cycles 1715system.cpu1.l2cache.demand_miss_latency::cpu1.data 2619102247 # number of demand (read+write) miss cycles 1716system.cpu1.l2cache.demand_miss_latency::total 2824323465 # number of demand (read+write) miss cycles 1717system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6952000 # number of overall miss cycles 1718system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5546000 # number of overall miss cycles 1719system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192723218 # number of overall miss cycles 1720system.cpu1.l2cache.overall_miss_latency::cpu1.data 2619102247 # number of overall miss cycles 1721system.cpu1.l2cache.overall_miss_latency::total 2824323465 # number of overall miss cycles 1722system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3334 # number of ReadReq accesses(hits+misses) 1723system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) 1724system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565517 # number of ReadReq accesses(hits+misses) 1725system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193555 # number of ReadReq accesses(hits+misses) 1726system.cpu1.l2cache.ReadReq_accesses::total 764387 # number of ReadReq accesses(hits+misses) 1727system.cpu1.l2cache.Writeback_accesses::writebacks 135060 # number of Writeback accesses(hits+misses) 1728system.cpu1.l2cache.Writeback_accesses::total 135060 # number of Writeback accesses(hits+misses) 1729system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31008 # number of UpgradeReq accesses(hits+misses) 1730system.cpu1.l2cache.UpgradeReq_accesses::total 31008 # number of UpgradeReq accesses(hits+misses) 1731system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23198 # number of SCUpgradeReq accesses(hits+misses) 1732system.cpu1.l2cache.SCUpgradeReq_accesses::total 23198 # number of SCUpgradeReq accesses(hits+misses) 1733system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1734system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1735system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72777 # number of ReadExReq accesses(hits+misses) 1736system.cpu1.l2cache.ReadExReq_accesses::total 72777 # number of ReadExReq accesses(hits+misses) 1737system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3334 # number of demand (read+write) accesses 1738system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses 1739system.cpu1.l2cache.demand_accesses::cpu1.inst 565517 # number of demand (read+write) accesses 1740system.cpu1.l2cache.demand_accesses::cpu1.data 266332 # number of demand (read+write) accesses 1741system.cpu1.l2cache.demand_accesses::total 837164 # number of demand (read+write) accesses 1742system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3334 # number of overall (read+write) accesses 1743system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses 1744system.cpu1.l2cache.overall_accesses::cpu1.inst 565517 # number of overall (read+write) accesses 1745system.cpu1.l2cache.overall_accesses::cpu1.data 266332 # number of overall (read+write) accesses 1746system.cpu1.l2cache.overall_accesses::total 837164 # number of overall (read+write) accesses 1747system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for ReadReq accesses 1748system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.139828 # miss rate for ReadReq accesses 1749system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009975 # miss rate for ReadReq accesses 1750system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363261 # miss rate for ReadReq accesses 1751system.cpu1.l2cache.ReadReq_miss_rate::total 0.100168 # miss rate for ReadReq accesses 1752system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.948110 # miss rate for UpgradeReq accesses 1753system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.948110 # miss rate for UpgradeReq accesses 1754system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962885 # miss rate for SCUpgradeReq accesses 1755system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962885 # miss rate for SCUpgradeReq accesses |
| 2307system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2308system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1756system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1757system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2309system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses 2310system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses 2311system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses 2312system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses 2313system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses 2314system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses 2315system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses 2316system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses 2317system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses 2318system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses 2319system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses 2320system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses 2321system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency 2322system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency 2323system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency 2324system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency 2325system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency 2326system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency 2327system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency 2328system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency 2329system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency 2330system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency 2331system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency 2332system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency 2333system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency 2334system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency 2335system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency 2336system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency 2337system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency 2338system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency 2339system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency 2340system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency 2341system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency 2342system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency 2343system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency 2344system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked | 1758system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.461657 # miss rate for ReadExReq accesses 1759system.cpu1.l2cache.ReadExReq_miss_rate::total 0.461657 # miss rate for ReadExReq accesses 1760system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for demand accesses 1761system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.139828 # miss rate for demand accesses 1762system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009975 # miss rate for demand accesses 1763system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.390148 # miss rate for demand accesses 1764system.cpu1.l2cache.demand_miss_rate::total 0.131593 # miss rate for demand accesses 1765system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for overall accesses 1766system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.139828 # miss rate for overall accesses 1767system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009975 # miss rate for overall accesses 1768system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.390148 # miss rate for overall accesses 1769system.cpu1.l2cache.overall_miss_rate::total 0.131593 # miss rate for overall accesses 1770system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average ReadReq miss latency 1771system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650 # average ReadReq miss latency 1772system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758 # average ReadReq miss latency 1773system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730 # average ReadReq miss latency 1774system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830 # average ReadReq miss latency 1775system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686 # average UpgradeReq miss latency 1776system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686 # average UpgradeReq miss latency 1777system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151 # average SCUpgradeReq miss latency 1778system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151 # average SCUpgradeReq miss latency 1779system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714 # average SCUpgradeFailReq miss latency 1780system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714 # average SCUpgradeFailReq miss latency 1781system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807 # average ReadExReq miss latency 1782system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807 # average ReadExReq miss latency 1783system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency 1784system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency 1785system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency 1786system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency 1787system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046 # average overall miss latency 1788system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency 1789system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency 1790system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency 1791system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency 1792system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046 # average overall miss latency 1793system.cpu1.l2cache.blocked_cycles::no_mshrs 1642 # number of cycles access was blocked |
| 2345system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1794system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2346system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked | 1795system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked |
| 2347system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1796system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2348system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked | 1797system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.914286 # average number of cycles each access was blocked |
| 2349system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2350system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2351system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1798system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1799system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1800system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2352system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks 2353system.cpu1.l2cache.writebacks::total 35043 # number of writebacks 2354system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits 2355system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits 2356system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits 2357system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits 2358system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits 2359system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits 2360system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits 2361system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits 2362system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits 2363system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits 2364system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits 2365system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses 2366system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses 2367system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses 2368system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses 2369system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses 2370system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses 2371system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses 2372system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses 2373system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses 2374system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # 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number of demand (read+write) MSHR misses 2385system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses 2386system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses 2387system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses 2388system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses 2389system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses 2390system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses 2391system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles 2392system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles 2393system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles 2394system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # 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number of overall MSHR miss cycles 2413system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles 2414system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles 2415system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles 2416system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles | 1801system.cpu1.l2cache.writebacks::writebacks 35198 # number of writebacks 1802system.cpu1.l2cache.writebacks::total 35198 # number of writebacks 1803system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 739 # number of ReadReq MSHR hits 1804system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 100 # number of ReadReq MSHR hits 1805system.cpu1.l2cache.ReadReq_mshr_hits::total 839 # number of ReadReq MSHR hits 1806system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 193 # number of ReadExReq MSHR hits 1807system.cpu1.l2cache.ReadExReq_mshr_hits::total 193 # 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number of demand (read+write) MSHR miss cycles 1858system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1873474823 # number of demand (read+write) MSHR miss cycles 1859system.cpu1.l2cache.demand_mshr_miss_latency::total 2025569848 # number of demand (read+write) MSHR miss cycles 1860system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of overall MSHR miss cycles 1861system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3607000 # number of overall MSHR miss cycles 1862system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143902025 # number of overall MSHR miss cycles 1863system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1873474823 # number of overall MSHR miss cycles 1864system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of overall MSHR miss cycles 1865system.cpu1.l2cache.overall_mshr_miss_latency::total 5272959486 # number of overall MSHR miss cycles |
| 2417system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles | 1866system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles |
| 2418system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles 2419system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles 2420system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles 2421system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles | 1867system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles 1868system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles 1869system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles 1870system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles |
| 2422system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles | 1871system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles |
| 2423system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles 2424system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles 2425system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses 2426system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses 2427system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses 2428system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses 2429system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses | 1872system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles 1873system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles 1874system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses 1875system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses 1876system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses 1877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses 1878system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses |
| 2430system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2431system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1879system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1880system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2432system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses 2433system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses 2434system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses 2435system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses | 1881system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses 1882system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses 1883system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses 1884system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses |
| 2436system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2437system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1885system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1886system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2438system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses 2439system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses 2440system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses 2441system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses 2442system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses 2443system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses 2444system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses 2445system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses 2446system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses 2447system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses 2448system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses | 1887system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses 1888system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses 1889system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses 1890system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses 1891system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses 1892system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses 1893system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses 1894system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses 1895system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses 1896system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses 1897system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses |
| 2449system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1898system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2450system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses 2451system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency 2452system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency 2453system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency 2454system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency 2455system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency 2456system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency 2457system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency 2458system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency 2459system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency 2460system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency 2461system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency 2462system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency 2463system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency 2464system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency 2465system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency 2466system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency 2467system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency 2468system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency 2469system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency 2470system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency 2471system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency 2472system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency 2473system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency 2474system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency 2475system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency 2476system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency | 1899system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses 1900system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency 1901system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency 1902system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency 1903system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency 1904system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency 1905system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency 1906system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency 1907system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency 1908system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency 1909system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency 1910system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency 1911system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency 1912system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency 1913system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency 1914system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency 1915system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency 1916system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency 1917system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency 1918system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency 1919system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency 1920system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency 1921system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency 1922system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency 1923system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency 1924system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency 1925system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency |
| 2477system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2478system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2479system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2480system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2481system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2482system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2483system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2484system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2485system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1926system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1927system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1928system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1929system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1930system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1931system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1932system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1933system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1934system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2486system.cpu1.dcache.tags.replacements 218971 # number of replacements 2487system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use 2488system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks. 2489system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks. 2490system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks. 2491system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit. 2492system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor 2493system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy 2494system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy 2495system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id 2496system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id 2497system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id 2498system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id 2499system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses 2500system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses 2501system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits 2502system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits 2503system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits 2504system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits 2505system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits 2506system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits 2507system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits 2508system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits 2509system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits 2510system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits 2511system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits 2512system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits 2513system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits 2514system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits 2515system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses 2516system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses 2517system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses 2518system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses 2519system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses 2520system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses 2521system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses 2522system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses 2523system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses 2524system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses 2525system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses 2526system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses 2527system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses 2528system.cpu1.dcache.overall_misses::total 293049 # number of overall misses 2529system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles 2530system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles 2531system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles 2532system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles 2533system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles 2534system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles 2535system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles 2536system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles 2537system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles 2538system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles 2539system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles 2540system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles 2541system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles 2542system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles 2543system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses) 2544system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses) 2545system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses) 2546system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses) 2547system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses) 2548system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses) 2549system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses) 2550system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses) 2551system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses) 2552system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses) 2553system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses 2554system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses 2555system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses 2556system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses 2557system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses 2558system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses 2559system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses 2560system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses 2561system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses 2562system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses 2563system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses 2564system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses 2565system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses 2566system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses 2567system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses 2568system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses 2569system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses 2570system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses 2571system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency 2572system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency 2573system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency 2574system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency 2575system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency 2576system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency 2577system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency 2578system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency 2579system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2580system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2581system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency 2582system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency 2583system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency 2584system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency 2585system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2586system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2587system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2588system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2589system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2590system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2591system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2592system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2593system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks 2594system.cpu1.dcache.writebacks::total 134894 # number of writebacks 2595system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits 2596system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits 2597system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits 2598system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits 2599system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits 2600system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits 2601system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits 2602system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits 2603system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses 2604system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses 2605system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses 2606system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses 2607system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses 2608system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses 2609system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses 2610system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses 2611system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses 2612system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses 2613system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses 2614system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses 2615system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses 2616system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses 2617system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles 2618system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles 2619system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles 2620system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles 2621system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles 2622system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles 2623system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles 2624system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles 2625system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles 2626system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles 2627system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles 2628system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles 2629system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles 2630system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles 2631system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles 2632system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles 2633system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles 2634system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles 2635system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles 2636system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles 2637system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles 2638system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles 2639system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses 2640system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses 2641system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses 2642system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses 2643system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses 2644system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses 2645system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses 2646system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses 2647system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses 2648system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses 2649system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses 2650system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses 2651system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses 2652system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses 2653system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency 2654system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency 2655system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency 2656system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency 2657system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency 2658system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency 2659system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency 2660system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency 2661system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency 2662system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency 2663system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2664system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2665system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency 2666system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency 2667system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency 2668system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency 2669system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2670system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2671system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2672system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2673system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2674system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2675system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2676system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution 2677system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution 2678system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution 2679system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution 2680system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution 2681system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution | 1935system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution 1936system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution 1937system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution 1938system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution 1939system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution 1940system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution |
| 2682system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution | 1941system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution |
| 2683system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution 2684system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution 2685system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution | 1942system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution 1943system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution 1944system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution |
| 2686system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 2687system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution | 1945system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 1946system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution |
| 2688system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution 2689system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution 2690system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes) 2691system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes) 2692system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes) 2693system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes) 2694system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes) 2695system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes) 2696system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes) 2697system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes) 2698system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes) 2699system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes) 2700system.cpu1.toL2Bus.snoops 817024 # Total snoops (count) 2701system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram 2702system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram 2703system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram | 1947system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution 1948system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution 1949system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes) 1950system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes) 1951system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) 1952system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes) 1953system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes) 1954system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes) 1955system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes) 1956system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) 1957system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes) 1958system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes) 1959system.cpu1.toL2Bus.snoops 818999 # Total snoops (count) 1960system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram 1961system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram 1962system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram |
| 2704system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2705system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2706system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2707system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2708system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2709system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1963system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1964system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1965system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1966system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1967system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1968system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 2710system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram 2711system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram | 1969system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram 1970system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram |
| 2712system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2713system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2714system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1971system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1972system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1973system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 2715system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram 2716system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks) | 1974system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram 1975system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks) |
| 2717system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1976system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2718system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks) | 1977system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks) |
| 2719system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1978system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2720system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks) | 1979system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks) |
| 2721system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1980system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2722system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks) | 1981system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks) |
| 2723system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1982system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2724system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) | 1983system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks) |
| 2725system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1984system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2726system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks) | 1985system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks) |
| 2727system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1986system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2728system.iocache.tags.replacements 36427 # number of replacements 2729system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use 2730system.iocache.tags.total_refs 16 # Total number of references to valid blocks. 2731system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks. 2732system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. 2733system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit. 2734system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor 2735system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy 2736system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy | 1987system.iobus.trans_dist::ReadReq 31019 # Transaction distribution 1988system.iobus.trans_dist::ReadResp 31019 # Transaction distribution 1989system.iobus.trans_dist::WriteReq 59407 # Transaction distribution 1990system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1991system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution 1992system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1993system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1994system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1995system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1996system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1997system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 1998system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1999system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2000system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2001system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2002system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2003system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2004system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2005system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2006system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2007system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2008system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2009system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2010system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2011system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2012system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2013system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) 2014system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) 2015system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) 2016system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) 2017system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 2018system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2019system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2020system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2021system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2022system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) 2023system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2024system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2025system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2026system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2027system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2028system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2029system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2030system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2031system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2032system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2033system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2034system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 2035system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2036system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 2037system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2038system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) 2039system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) 2040system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) 2041system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) 2042system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) 2043system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2044system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) 2045system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2046system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 2047system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2048system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 2049system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2050system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 2051system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 2052system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) 2053system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2054system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 2055system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2056system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2057system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2058system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2059system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2060system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2061system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2062system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 2063system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2064system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2065system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2066system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 2067system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2068system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 2069system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2070system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 2071system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2072system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 2073system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2074system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 2075system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2076system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 2077system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2078system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 2079system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2080system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 2081system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2082system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks) 2083system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2084system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2085system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2086system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) 2087system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2088system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks) 2089system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2090system.iocache.tags.replacements 36443 # number of replacements 2091system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use 2092system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2093system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. 2094system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2095system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit. 2096system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor 2097system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy 2098system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy |
| 2737system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2738system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2739system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2099system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2100system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2101system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2740system.iocache.tags.tag_accesses 328485 # Number of tag accesses 2741system.iocache.tags.data_accesses 328485 # Number of data accesses | 2102system.iocache.tags.tag_accesses 328557 # Number of tag accesses 2103system.iocache.tags.data_accesses 328557 # Number of data accesses |
| 2742system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2743system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2744system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2745system.iocache.ReadReq_misses::total 253 # number of ReadReq misses | 2104system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2105system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2106system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2107system.iocache.ReadReq_misses::total 253 # number of ReadReq misses |
| 2746system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses 2747system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses | 2108system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses 2109system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses |
| 2748system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2749system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2750system.iocache.overall_misses::realview.ide 253 # number of overall misses 2751system.iocache.overall_misses::total 253 # number of overall misses | 2110system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2111system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2112system.iocache.overall_misses::realview.ide 253 # number of overall misses 2113system.iocache.overall_misses::total 253 # number of overall misses |
| 2752system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles 2753system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles 2754system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles 2755system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles 2756system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles 2757system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles | 2114system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles 2115system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles 2116system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles 2117system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles 2118system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles 2119system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles |
| 2758system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2759system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) | 2120system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2121system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) |
| 2760system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses) 2761system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses) | 2122system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) 2123system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) |
| 2762system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2763system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2764system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2765system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2766system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2767system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 2124system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2125system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2126system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2127system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2128system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2129system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 2768system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses 2769system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses | 2130system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses 2131system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses |
| 2770system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2771system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2772system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2773system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2132system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2133system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2134system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2135system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2774system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency 2775system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency 2776system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency 2777system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency 2778system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency 2779system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency | 2136system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency 2137system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency 2138system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2139system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency 2140system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2141system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency |
| 2780system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2781system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2782system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2783system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2784system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2785system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2786system.iocache.fast_writes 36224 # number of fast writes performed 2787system.iocache.cache_copies 0 # number of cache copies performed 2788system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2789system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses 2790system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2791system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2792system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2793system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses | 2142system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2143system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2144system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2145system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2146system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2147system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2148system.iocache.fast_writes 36224 # number of fast writes performed 2149system.iocache.cache_copies 0 # number of cache copies performed 2150system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2151system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses 2152system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2153system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2154system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2155system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses |
| 2794system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles 2795system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles 2796system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles 2797system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles 2798system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles 2799system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles 2800system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles 2801system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles | 2156system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles 2157system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles 2158system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles 2159system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles 2160system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles 2161system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles 2162system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles 2163system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles |
| 2802system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2803system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2804system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2805system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2806system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2807system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2164system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2165system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2166system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2167system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2168system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2169system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2808system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency 2809system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency | 2170system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency 2171system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency |
| 2810system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2811system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency | 2172system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2173system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 2812system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency 2813system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency 2814system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency 2815system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency | 2174system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2175system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency 2176system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2177system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency |
| 2816system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2178system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2179system.l2c.tags.replacements 132935 # number of replacements 2180system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use 2181system.l2c.tags.total_refs 488817 # Total number of references to valid blocks. 2182system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks. 2183system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks. 2184system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2185system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor 2186system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor 2187system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor 2188system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor 2189system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor 2190system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor 2191system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor 2192system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor 2193system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor 2194system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor 2195system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor 2196system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy 2197system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy 2198system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2199system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy 2200system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy 2201system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy 2202system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy 2203system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 2204system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy 2205system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy 2206system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy 2207system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy 2208system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id 2209system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 2210system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id 2211system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id 2212system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id 2213system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id 2214system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 2215system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 2216system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id 2217system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id 2218system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id 2219system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id 2220system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 2221system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id 2222system.l2c.tags.tag_accesses 6143442 # Number of tag accesses 2223system.l2c.tags.data_accesses 6143442 # Number of data accesses 2224system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits 2225system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits 2226system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits 2227system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits 2228system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits 2229system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits 2230system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits 2231system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits 2232system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits 2233system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits 2234system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits 2235system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits 2236system.l2c.Writeback_hits::total 240423 # number of Writeback hits 2237system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits 2238system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits 2239system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits 2240system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits 2241system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits 2242system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits 2243system.l2c.ReadExReq_hits::cpu0.data 4104 # number of ReadExReq hits 2244system.l2c.ReadExReq_hits::cpu1.data 2566 # number of ReadExReq hits 2245system.l2c.ReadExReq_hits::total 6670 # number of ReadExReq hits 2246system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits 2247system.l2c.demand_hits::cpu0.itb.walker 155 # number of demand (read+write) hits 2248system.l2c.demand_hits::cpu0.inst 10201 # number of demand (read+write) hits 2249system.l2c.demand_hits::cpu0.data 33543 # number of demand (read+write) hits 2250system.l2c.demand_hits::cpu0.l2cache.prefetcher 168037 # number of demand (read+write) hits 2251system.l2c.demand_hits::cpu1.dtb.walker 53 # number of demand (read+write) hits 2252system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits 2253system.l2c.demand_hits::cpu1.inst 4112 # number of demand (read+write) hits 2254system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits 2255system.l2c.demand_hits::cpu1.l2cache.prefetcher 47653 # number of demand (read+write) hits 2256system.l2c.demand_hits::total 276883 # number of demand (read+write) hits 2257system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits 2258system.l2c.overall_hits::cpu0.itb.walker 155 # number of overall hits 2259system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits 2260system.l2c.overall_hits::cpu0.data 33543 # number of overall hits 2261system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits 2262system.l2c.overall_hits::cpu1.dtb.walker 53 # number of overall hits 2263system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits 2264system.l2c.overall_hits::cpu1.inst 4112 # number of overall hits 2265system.l2c.overall_hits::cpu1.data 12939 # number of overall hits 2266system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits 2267system.l2c.overall_hits::total 276883 # number of overall hits 2268system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses 2269system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 2270system.l2c.ReadReq_misses::cpu0.inst 3124 # number of ReadReq misses 2271system.l2c.ReadReq_misses::cpu0.data 6991 # number of ReadReq misses 2272system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150306 # number of ReadReq misses 2273system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 2274system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 2275system.l2c.ReadReq_misses::cpu1.inst 786 # number of ReadReq misses 2276system.l2c.ReadReq_misses::cpu1.data 1400 # number of ReadReq misses 2277system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq misses 2278system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses 2279system.l2c.UpgradeReq_misses::cpu0.data 8554 # number of UpgradeReq misses 2280system.l2c.UpgradeReq_misses::cpu1.data 4191 # number of UpgradeReq misses 2281system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses 2282system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses 2283system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # number of SCUpgradeReq misses 2284system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses 2285system.l2c.ReadExReq_misses::cpu0.data 6191 # number of ReadExReq misses 2286system.l2c.ReadExReq_misses::cpu1.data 5553 # number of ReadExReq misses 2287system.l2c.ReadExReq_misses::total 11744 # number of ReadExReq misses 2288system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 2289system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 2290system.l2c.demand_misses::cpu0.inst 3124 # number of demand (read+write) misses 2291system.l2c.demand_misses::cpu0.data 13182 # number of demand (read+write) misses 2292system.l2c.demand_misses::cpu0.l2cache.prefetcher 150306 # number of demand (read+write) misses 2293system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 2294system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 2295system.l2c.demand_misses::cpu1.inst 786 # number of demand (read+write) misses 2296system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses 2297system.l2c.demand_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) misses 2298system.l2c.demand_misses::total 195660 # number of demand (read+write) misses 2299system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 2300system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 2301system.l2c.overall_misses::cpu0.inst 3124 # number of overall misses 2302system.l2c.overall_misses::cpu0.data 13182 # number of overall misses 2303system.l2c.overall_misses::cpu0.l2cache.prefetcher 150306 # number of overall misses 2304system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 2305system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 2306system.l2c.overall_misses::cpu1.inst 786 # number of overall misses 2307system.l2c.overall_misses::cpu1.data 6953 # number of overall misses 2308system.l2c.overall_misses::cpu1.l2cache.prefetcher 21296 # number of overall misses 2309system.l2c.overall_misses::total 195660 # number of overall misses 2310system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 598250 # number of ReadReq miss cycles 2311system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles 2312system.l2c.ReadReq_miss_latency::cpu0.inst 271876998 # number of ReadReq miss cycles 2313system.l2c.ReadReq_miss_latency::cpu0.data 570375499 # number of ReadReq miss cycles 2314system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of ReadReq miss cycles 2315system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 223500 # number of ReadReq miss cycles 2316system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 2317system.l2c.ReadReq_miss_latency::cpu1.inst 71055248 # number of ReadReq miss cycles 2318system.l2c.ReadReq_miss_latency::cpu1.data 119227499 # number of ReadReq miss cycles 2319system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of ReadReq miss cycles 2320system.l2c.ReadReq_miss_latency::total 18387871837 # number of ReadReq miss cycles 2321system.l2c.UpgradeReq_miss_latency::cpu0.data 9302615 # number of UpgradeReq miss cycles 2322system.l2c.UpgradeReq_miss_latency::cpu1.data 9559091 # number of UpgradeReq miss cycles 2323system.l2c.UpgradeReq_miss_latency::total 18861706 # number of UpgradeReq miss cycles 2324system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1287445 # number of SCUpgradeReq miss cycles 2325system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2175907 # number of SCUpgradeReq miss cycles 2326system.l2c.SCUpgradeReq_miss_latency::total 3463352 # number of SCUpgradeReq miss cycles 2327system.l2c.ReadExReq_miss_latency::cpu0.data 491575637 # number of ReadExReq miss cycles 2328system.l2c.ReadExReq_miss_latency::cpu1.data 403495431 # number of ReadExReq miss cycles 2329system.l2c.ReadExReq_miss_latency::total 895071068 # number of ReadExReq miss cycles 2330system.l2c.demand_miss_latency::cpu0.dtb.walker 598250 # number of demand (read+write) miss cycles 2331system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles 2332system.l2c.demand_miss_latency::cpu0.inst 271876998 # number of demand (read+write) miss cycles 2333system.l2c.demand_miss_latency::cpu0.data 1061951136 # number of demand (read+write) miss cycles 2334system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of demand (read+write) miss cycles 2335system.l2c.demand_miss_latency::cpu1.dtb.walker 223500 # number of demand (read+write) miss cycles 2336system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 2337system.l2c.demand_miss_latency::cpu1.inst 71055248 # number of demand (read+write) miss cycles 2338system.l2c.demand_miss_latency::cpu1.data 522722930 # number of demand (read+write) miss cycles 2339system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of demand (read+write) miss cycles 2340system.l2c.demand_miss_latency::total 19282942905 # number of demand (read+write) miss cycles 2341system.l2c.overall_miss_latency::cpu0.dtb.walker 598250 # number of overall miss cycles 2342system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles 2343system.l2c.overall_miss_latency::cpu0.inst 271876998 # number of overall miss cycles 2344system.l2c.overall_miss_latency::cpu0.data 1061951136 # number of overall miss cycles 2345system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of overall miss cycles 2346system.l2c.overall_miss_latency::cpu1.dtb.walker 223500 # number of overall miss cycles 2347system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 2348system.l2c.overall_miss_latency::cpu1.inst 71055248 # number of overall miss cycles 2349system.l2c.overall_miss_latency::cpu1.data 522722930 # number of overall miss cycles 2350system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of overall miss cycles 2351system.l2c.overall_miss_latency::total 19282942905 # number of overall miss cycles 2352system.l2c.ReadReq_accesses::cpu0.dtb.walker 154 # number of ReadReq accesses(hits+misses) 2353system.l2c.ReadReq_accesses::cpu0.itb.walker 156 # number of ReadReq accesses(hits+misses) 2354system.l2c.ReadReq_accesses::cpu0.inst 13325 # number of ReadReq accesses(hits+misses) 2355system.l2c.ReadReq_accesses::cpu0.data 36430 # number of ReadReq accesses(hits+misses) 2356system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318343 # number of ReadReq accesses(hits+misses) 2357system.l2c.ReadReq_accesses::cpu1.dtb.walker 56 # number of ReadReq accesses(hits+misses) 2358system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses) 2359system.l2c.ReadReq_accesses::cpu1.inst 4898 # number of ReadReq accesses(hits+misses) 2360system.l2c.ReadReq_accesses::cpu1.data 11773 # number of ReadReq accesses(hits+misses) 2361system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68949 # number of ReadReq accesses(hits+misses) 2362system.l2c.ReadReq_accesses::total 454129 # number of ReadReq accesses(hits+misses) 2363system.l2c.Writeback_accesses::writebacks 240423 # number of Writeback accesses(hits+misses) 2364system.l2c.Writeback_accesses::total 240423 # number of Writeback accesses(hits+misses) 2365system.l2c.UpgradeReq_accesses::cpu0.data 18187 # number of UpgradeReq accesses(hits+misses) 2366system.l2c.UpgradeReq_accesses::cpu1.data 5191 # number of UpgradeReq accesses(hits+misses) 2367system.l2c.UpgradeReq_accesses::total 23378 # number of UpgradeReq accesses(hits+misses) 2368system.l2c.SCUpgradeReq_accesses::cpu0.data 1140 # number of SCUpgradeReq accesses(hits+misses) 2369system.l2c.SCUpgradeReq_accesses::cpu1.data 1430 # number of SCUpgradeReq accesses(hits+misses) 2370system.l2c.SCUpgradeReq_accesses::total 2570 # number of SCUpgradeReq accesses(hits+misses) 2371system.l2c.ReadExReq_accesses::cpu0.data 10295 # number of ReadExReq accesses(hits+misses) 2372system.l2c.ReadExReq_accesses::cpu1.data 8119 # number of ReadExReq accesses(hits+misses) 2373system.l2c.ReadExReq_accesses::total 18414 # number of ReadExReq accesses(hits+misses) 2374system.l2c.demand_accesses::cpu0.dtb.walker 154 # number of demand (read+write) accesses 2375system.l2c.demand_accesses::cpu0.itb.walker 156 # number of demand (read+write) accesses 2376system.l2c.demand_accesses::cpu0.inst 13325 # number of demand (read+write) accesses 2377system.l2c.demand_accesses::cpu0.data 46725 # number of demand (read+write) accesses 2378system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318343 # number of demand (read+write) accesses 2379system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses 2380system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses 2381system.l2c.demand_accesses::cpu1.inst 4898 # number of demand (read+write) accesses 2382system.l2c.demand_accesses::cpu1.data 19892 # number of demand (read+write) accesses 2383system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68949 # number of demand (read+write) accesses 2384system.l2c.demand_accesses::total 472543 # number of demand (read+write) accesses 2385system.l2c.overall_accesses::cpu0.dtb.walker 154 # number of overall (read+write) accesses 2386system.l2c.overall_accesses::cpu0.itb.walker 156 # number of overall (read+write) accesses 2387system.l2c.overall_accesses::cpu0.inst 13325 # number of overall (read+write) accesses 2388system.l2c.overall_accesses::cpu0.data 46725 # number of overall (read+write) accesses 2389system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318343 # number of overall (read+write) accesses 2390system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses 2391system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses 2392system.l2c.overall_accesses::cpu1.inst 4898 # number of overall (read+write) accesses 2393system.l2c.overall_accesses::cpu1.data 19892 # number of overall (read+write) accesses 2394system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68949 # number of overall (read+write) accesses 2395system.l2c.overall_accesses::total 472543 # number of overall (read+write) accesses 2396system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for ReadReq accesses 2397system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006410 # miss rate for ReadReq accesses 2398system.l2c.ReadReq_miss_rate::cpu0.inst 0.234447 # miss rate for ReadReq accesses 2399system.l2c.ReadReq_miss_rate::cpu0.data 0.191902 # miss rate for ReadReq accesses 2400system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for ReadReq accesses 2401system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for ReadReq accesses 2402system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.022222 # miss rate for ReadReq accesses 2403system.l2c.ReadReq_miss_rate::cpu1.inst 0.160474 # miss rate for ReadReq accesses 2404system.l2c.ReadReq_miss_rate::cpu1.data 0.118916 # miss rate for ReadReq accesses 2405system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for ReadReq accesses 2406system.l2c.ReadReq_miss_rate::total 0.404986 # miss rate for ReadReq accesses 2407system.l2c.UpgradeReq_miss_rate::cpu0.data 0.470336 # miss rate for UpgradeReq accesses 2408system.l2c.UpgradeReq_miss_rate::cpu1.data 0.807359 # miss rate for UpgradeReq accesses 2409system.l2c.UpgradeReq_miss_rate::total 0.545171 # miss rate for UpgradeReq accesses 2410system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783333 # miss rate for SCUpgradeReq accesses 2411system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.904196 # miss rate for SCUpgradeReq accesses 2412system.l2c.SCUpgradeReq_miss_rate::total 0.850584 # miss rate for SCUpgradeReq accesses 2413system.l2c.ReadExReq_miss_rate::cpu0.data 0.601360 # miss rate for ReadExReq accesses 2414system.l2c.ReadExReq_miss_rate::cpu1.data 0.683951 # miss rate for ReadExReq accesses 2415system.l2c.ReadExReq_miss_rate::total 0.637776 # miss rate for ReadExReq accesses 2416system.l2c.demand_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for demand accesses 2417system.l2c.demand_miss_rate::cpu0.itb.walker 0.006410 # miss rate for demand accesses 2418system.l2c.demand_miss_rate::cpu0.inst 0.234447 # miss rate for demand accesses 2419system.l2c.demand_miss_rate::cpu0.data 0.282119 # miss rate for demand accesses 2420system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for demand accesses 2421system.l2c.demand_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for demand accesses 2422system.l2c.demand_miss_rate::cpu1.itb.walker 0.022222 # miss rate for demand accesses 2423system.l2c.demand_miss_rate::cpu1.inst 0.160474 # miss rate for demand accesses 2424system.l2c.demand_miss_rate::cpu1.data 0.349538 # miss rate for demand accesses 2425system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for demand accesses 2426system.l2c.demand_miss_rate::total 0.414058 # miss rate for demand accesses 2427system.l2c.overall_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for overall accesses 2428system.l2c.overall_miss_rate::cpu0.itb.walker 0.006410 # miss rate for overall accesses 2429system.l2c.overall_miss_rate::cpu0.inst 0.234447 # miss rate for overall accesses 2430system.l2c.overall_miss_rate::cpu0.data 0.282119 # miss rate for overall accesses 2431system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for overall accesses 2432system.l2c.overall_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for overall accesses 2433system.l2c.overall_miss_rate::cpu1.itb.walker 0.022222 # miss rate for overall accesses 2434system.l2c.overall_miss_rate::cpu1.inst 0.160474 # miss rate for overall accesses 2435system.l2c.overall_miss_rate::cpu1.data 0.349538 # miss rate for overall accesses 2436system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for overall accesses 2437system.l2c.overall_miss_rate::total 0.414058 # miss rate for overall accesses 2438system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency 2439system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 2440system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476 # average ReadReq miss latency 2441system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858 # average ReadReq miss latency 2442system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average ReadReq miss latency 2443system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency 2444system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 2445system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880 # average ReadReq miss latency 2446system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286 # average ReadReq miss latency 2447system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average ReadReq miss latency 2448system.l2c.ReadReq_avg_miss_latency::total 99979.728990 # average ReadReq miss latency 2449system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1087.516367 # average UpgradeReq miss latency 2450system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2280.861608 # average UpgradeReq miss latency 2451system.l2c.UpgradeReq_avg_miss_latency::total 1479.929855 # average UpgradeReq miss latency 2452system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1441.707727 # average SCUpgradeReq miss latency 2453system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1682.836040 # average SCUpgradeReq miss latency 2454system.l2c.SCUpgradeReq_avg_miss_latency::total 1584.333028 # average SCUpgradeReq miss latency 2455system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529 # average ReadExReq miss latency 2456system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377 # average ReadExReq miss latency 2457system.l2c.ReadExReq_avg_miss_latency::total 76215.179496 # average ReadExReq miss latency 2458system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency 2459system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2460system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency 2461system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency 2462system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency 2463system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency 2464system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 2465system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency 2466system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency 2467system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency 2468system.l2c.demand_avg_miss_latency::total 98553.321604 # average overall miss latency 2469system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency 2470system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 2471system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency 2472system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency 2473system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency 2474system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency 2475system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 2476system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency 2477system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency 2478system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency 2479system.l2c.overall_avg_miss_latency::total 98553.321604 # average overall miss latency 2480system.l2c.blocked_cycles::no_mshrs 370 # number of cycles access was blocked 2481system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2482system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 2483system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2484system.l2c.avg_blocked_cycles::no_mshrs 46.250000 # average number of cycles each access was blocked 2485system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2486system.l2c.fast_writes 0 # number of fast writes performed 2487system.l2c.cache_copies 0 # number of cache copies performed 2488system.l2c.writebacks::writebacks 99922 # number of writebacks 2489system.l2c.writebacks::total 99922 # number of writebacks 2490system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits 2491system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 2492system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2493system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 2494system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits 2495system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 2496system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses 2497system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses 2498system.l2c.ReadReq_mshr_misses::cpu0.inst 3124 # number of ReadReq MSHR misses 2499system.l2c.ReadReq_mshr_misses::cpu0.data 6991 # number of ReadReq MSHR misses 2500system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of ReadReq MSHR misses 2501system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses 2502system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 2503system.l2c.ReadReq_mshr_misses::cpu1.inst 786 # number of ReadReq MSHR misses 2504system.l2c.ReadReq_mshr_misses::cpu1.data 1400 # number of ReadReq MSHR misses 2505system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq MSHR misses 2506system.l2c.ReadReq_mshr_misses::total 183915 # number of ReadReq MSHR misses 2507system.l2c.UpgradeReq_mshr_misses::cpu0.data 8554 # number of UpgradeReq MSHR misses 2508system.l2c.UpgradeReq_mshr_misses::cpu1.data 4191 # number of UpgradeReq MSHR misses 2509system.l2c.UpgradeReq_mshr_misses::total 12745 # number of UpgradeReq MSHR misses 2510system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 893 # number of SCUpgradeReq MSHR misses 2511system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1293 # number of SCUpgradeReq MSHR misses 2512system.l2c.SCUpgradeReq_mshr_misses::total 2186 # number of SCUpgradeReq MSHR misses 2513system.l2c.ReadExReq_mshr_misses::cpu0.data 6191 # number of ReadExReq MSHR misses 2514system.l2c.ReadExReq_mshr_misses::cpu1.data 5553 # number of ReadExReq MSHR misses 2515system.l2c.ReadExReq_mshr_misses::total 11744 # number of ReadExReq MSHR misses 2516system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses 2517system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 2518system.l2c.demand_mshr_misses::cpu0.inst 3124 # number of demand (read+write) MSHR misses 2519system.l2c.demand_mshr_misses::cpu0.data 13182 # number of demand (read+write) MSHR misses 2520system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of demand (read+write) MSHR misses 2521system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses 2522system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 2523system.l2c.demand_mshr_misses::cpu1.inst 786 # number of demand (read+write) MSHR misses 2524system.l2c.demand_mshr_misses::cpu1.data 6953 # number of demand (read+write) MSHR misses 2525system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) MSHR misses 2526system.l2c.demand_mshr_misses::total 195659 # number of demand (read+write) MSHR misses 2527system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses 2528system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 2529system.l2c.overall_mshr_misses::cpu0.inst 3124 # number of overall MSHR misses 2530system.l2c.overall_mshr_misses::cpu0.data 13182 # number of overall MSHR misses 2531system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of overall MSHR misses 2532system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses 2533system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 2534system.l2c.overall_mshr_misses::cpu1.inst 786 # number of overall MSHR misses 2535system.l2c.overall_mshr_misses::cpu1.data 6953 # number of overall MSHR misses 2536system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of overall MSHR misses 2537system.l2c.overall_mshr_misses::total 195659 # number of overall MSHR misses 2538system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 498750 # number of ReadReq MSHR miss cycles 2539system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles 2540system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233055498 # number of ReadReq MSHR miss cycles 2541system.l2c.ReadReq_mshr_miss_latency::cpu0.data 483422499 # number of ReadReq MSHR miss cycles 2542system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of ReadReq MSHR miss cycles 2543system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 187500 # number of ReadReq MSHR miss cycles 2544system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 2545system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 61295748 # number of ReadReq MSHR miss cycles 2546system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101745999 # number of ReadReq MSHR miss cycles 2547system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of ReadReq MSHR miss cycles 2548system.l2c.ReadReq_mshr_miss_latency::total 16105922337 # number of ReadReq MSHR miss cycles 2549system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86281499 # number of UpgradeReq MSHR miss cycles 2550system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42154679 # number of UpgradeReq MSHR miss cycles 2551system.l2c.UpgradeReq_mshr_miss_latency::total 128436178 # number of UpgradeReq MSHR miss cycles 2552system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8967891 # number of SCUpgradeReq MSHR miss cycles 2553system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12981791 # number of SCUpgradeReq MSHR miss cycles 2554system.l2c.SCUpgradeReq_mshr_miss_latency::total 21949682 # number of SCUpgradeReq MSHR miss cycles 2555system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 414199861 # number of ReadExReq MSHR miss cycles 2556system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 333199069 # number of ReadExReq MSHR miss cycles 2557system.l2c.ReadExReq_mshr_miss_latency::total 747398930 # number of ReadExReq MSHR miss cycles 2558system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles 2559system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 2560system.l2c.demand_mshr_miss_latency::cpu0.inst 233055498 # number of demand (read+write) MSHR miss cycles 2561system.l2c.demand_mshr_miss_latency::cpu0.data 897622360 # number of demand (read+write) MSHR miss cycles 2562system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of demand (read+write) MSHR miss cycles 2563system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 187500 # number of demand (read+write) MSHR miss cycles 2564system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 2565system.l2c.demand_mshr_miss_latency::cpu1.inst 61295748 # number of demand (read+write) MSHR miss cycles 2566system.l2c.demand_mshr_miss_latency::cpu1.data 434945068 # number of demand (read+write) MSHR miss cycles 2567system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of demand (read+write) MSHR miss cycles 2568system.l2c.demand_mshr_miss_latency::total 16853321267 # number of demand (read+write) MSHR miss cycles 2569system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles 2570system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles 2571system.l2c.overall_mshr_miss_latency::cpu0.inst 233055498 # number of overall MSHR miss cycles 2572system.l2c.overall_mshr_miss_latency::cpu0.data 897622360 # number of overall MSHR miss cycles 2573system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of overall MSHR miss cycles 2574system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187500 # number of overall MSHR miss cycles 2575system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 2576system.l2c.overall_mshr_miss_latency::cpu1.inst 61295748 # number of overall MSHR miss cycles 2577system.l2c.overall_mshr_miss_latency::cpu1.data 434945068 # number of overall MSHR miss cycles 2578system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of overall MSHR miss cycles 2579system.l2c.overall_mshr_miss_latency::total 16853321267 # number of overall MSHR miss cycles 2580system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles 2581system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796922003 # number of ReadReq MSHR uncacheable cycles 2582system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles 2583system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814310000 # number of ReadReq MSHR uncacheable cycles 2584system.l2c.ReadReq_mshr_uncacheable_latency::total 6097036003 # number of ReadReq MSHR uncacheable cycles 2585system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540062000 # number of WriteReq MSHR uncacheable cycles 2586system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712612000 # number of WriteReq MSHR uncacheable cycles 2587system.l2c.WriteReq_mshr_uncacheable_latency::total 4252674000 # number of WriteReq MSHR uncacheable cycles 2588system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles 2589system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8336984003 # number of overall MSHR uncacheable cycles 2590system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles 2591system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles 2592system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles 2593system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses 2594system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses 2595system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses 2596system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses 2597system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses 2598system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses 2599system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses 2600system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses 2601system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses 2602system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses 2603system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses 2604system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses 2605system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses 2606system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses 2607system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses 2608system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses 2609system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses 2610system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses 2611system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses 2612system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses 2613system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses 2614system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses 2615system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses 2616system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses 2617system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses 2618system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses 2619system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses 2620system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses 2621system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses 2622system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses 2623system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses 2624system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses 2625system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses 2626system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses 2627system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses 2628system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses 2629system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses 2630system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses 2631system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses 2632system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses 2633system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses 2634system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses 2635system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency 2636system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 2637system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency 2638system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency 2639system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency 2640system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency 2641system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 2642system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency 2643system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency 2644system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency 2645system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency 2646system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency 2647system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency 2648system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency 2649system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency 2650system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency 2651system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency 2652system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency 2653system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency 2654system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency 2655system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency 2656system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2657system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency 2658system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency 2659system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency 2660system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2661system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 2662system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency 2663system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency 2664system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency 2665system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency 2666system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency 2667system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 2668system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency 2669system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency 2670system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency 2671system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency 2672system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 2673system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency 2674system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency 2675system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency 2676system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency 2677system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2678system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2679system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2680system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2681system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2682system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 2683system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2684system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2685system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 2686system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 2687system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2688system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2689system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2690system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2691system.membus.trans_dist::ReadReq 228475 # Transaction distribution 2692system.membus.trans_dist::ReadResp 228474 # Transaction distribution 2693system.membus.trans_dist::WriteReq 31175 # Transaction distribution 2694system.membus.trans_dist::WriteResp 31175 # Transaction distribution 2695system.membus.trans_dist::Writeback 99922 # Transaction distribution 2696system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 2697system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 2698system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution 2699system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution 2700system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution 2701system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution 2702system.membus.trans_dist::ReadExReq 28459 # Transaction distribution 2703system.membus.trans_dist::ReadExResp 11563 # Transaction distribution 2704system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) 2705system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2706system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes) 2707system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes) 2708system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes) 2709system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) 2710system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) 2711system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes) 2712system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) 2713system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2714system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes) 2715system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes) 2716system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes) 2717system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 2718system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 2719system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes) 2720system.membus.snoops 129134 # Total snoops (count) 2721system.membus.snoop_fanout::samples 475892 # Request fanout histogram 2722system.membus.snoop_fanout::mean 1 # Request fanout histogram 2723system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2724system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2725system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2726system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram 2727system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2728system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2729system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2730system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2731system.membus.snoop_fanout::total 475892 # Request fanout histogram 2732system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks) 2733system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2734system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) 2735system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2736system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks) 2737system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2738system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks) 2739system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 2740system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks) 2741system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 2742system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks) 2743system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2744system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2745system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2746system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2747system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2748system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2749system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2750system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2751system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2752system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2753system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2754system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2755system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2756system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2757system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2758system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2759system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2760system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2761system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2762system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2763system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2764system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2765system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2766system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2767system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2768system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2769system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2770system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2771system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2772system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2773system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2774system.realview.ethernet.droppedPackets 0 # number of packets dropped 2775system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution 2776system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution 2777system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution 2778system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution 2779system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution 2780system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 2781system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution 2782system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution 2783system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution 2784system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution 2785system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 2786system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution 2787system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution 2788system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes) 2789system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes) 2790system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes) 2791system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes) 2792system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes) 2793system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes) 2794system.toL2Bus.snoops 305031 # Total snoops (count) 2795system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram 2796system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram 2797system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram 2798system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2799system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2800system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram 2801system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram 2802system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2803system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2804system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2805system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram 2806system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks) 2807system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2808system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 2809system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2810system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks) 2811system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 2812system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks) 2813system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
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| 2817 2818---------- End Simulation Statistics ---------- | 2814 2815---------- End Simulation Statistics ---------- |