| stats.txt (10513:ca4438b6e39a) | stats.txt (10517:ba51f8572571) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.866929 # Number of seconds simulated 4sim_ticks 2866929256000 # Number of ticks simulated 5final_tick 2866929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.866923 # Number of seconds simulated 4sim_ticks 2866923142000 # Number of ticks simulated 5final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 703930 # Simulator instruction rate (inst/s) 8host_op_rate 851474 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15295798763 # Simulator tick rate (ticks/s) 10host_mem_usage 599572 # Number of bytes of host memory used 11host_seconds 187.43 # Real time elapsed on the host 12sim_insts 131939289 # Number of instructions simulated 13sim_ops 159593891 # Number of ops (including micro ops) simulated | 7host_inst_rate 699616 # Simulator instruction rate (inst/s) 8host_op_rate 846245 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15203294122 # Simulator tick rate (ticks/s) 10host_mem_usage 599680 # Number of bytes of host memory used 11host_seconds 188.57 # Real time elapsed on the host 12sim_insts 131928295 # Number of instructions simulated 13sim_ops 159578500 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) | |
| 34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 35system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory |
| 36system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
| 37system.physmem.bytes_read::cpu0.inst 234148 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 830144 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu0.l2cache.prefetcher 9620672 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory |
| 41system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory | 23system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory |
| 43system.physmem.bytes_read::cpu1.data 440928 # Number of bytes read from this memory 44system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365312 # Number of bytes read from this memory 45system.physmem.bytes_read::total 12542872 # Number of bytes read from this memory 46system.physmem.bytes_inst_read::cpu0.inst 234148 # Number of instructions bytes read from this memory | 25system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory 27system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory |
| 47system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory | 29system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory |
| 48system.physmem.bytes_inst_read::total 284024 # Number of instructions bytes read from this memory 49system.physmem.bytes_written::writebacks 6392960 # Number of bytes written to this memory | 30system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory |
| 50system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 51system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 52system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 32system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 53system.physmem.bytes_written::total 8729040 # Number of bytes written to this memory | 35system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory |
| 54system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 36system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 55system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory |
| 56system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory | 38system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
| 57system.physmem.num_reads::cpu0.inst 12112 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu0.data 13497 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu0.l2cache.prefetcher 150323 # Number of read requests responded to by this memory 60system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory | 39system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory |
| 61system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 62system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory | 43system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory |
| 63system.physmem.num_reads::cpu1.data 6913 # Number of read requests responded to by this memory 64system.physmem.num_reads::cpu1.l2cache.prefetcher 21333 # Number of read requests responded to by this memory 65system.physmem.num_reads::total 205140 # Number of read requests responded to by this memory 66system.physmem.num_writes::writebacks 99890 # Number of write requests responded to by this memory | 45system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory 46system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory |
| 67system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 68system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 69system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 49system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 51system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 70system.physmem.num_writes::total 140550 # Number of write requests responded to by this memory | 52system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory |
| 71system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) |
| 72system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) | 54system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) |
| 73system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) | 55system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) |
| 74system.physmem.bw_read::cpu0.inst 81672 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_read::cpu0.data 289559 # Total read bandwidth from this memory (bytes/s) 76system.physmem.bw_read::cpu0.l2cache.prefetcher 3355741 # Total read bandwidth from this memory (bytes/s) 77system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) | 56system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s) |
| 78system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 79system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) | 60system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) |
| 80system.physmem.bw_read::cpu1.data 153798 # Total read bandwidth from this memory (bytes/s) 81system.physmem.bw_read::cpu1.l2cache.prefetcher 476228 # Total read bandwidth from this memory (bytes/s) 82system.physmem.bw_read::total 4375020 # Total read bandwidth from this memory (bytes/s) 83system.physmem.bw_inst_read::cpu0.inst 81672 # Instruction read bandwidth from this memory (bytes/s) | 62system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s) |
| 84system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) | 66system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) |
| 85system.physmem.bw_inst_read::total 99069 # Instruction read bandwidth from this memory (bytes/s) 86system.physmem.bw_write::writebacks 2229898 # Write bandwidth from this memory (bytes/s) 87system.physmem.bw_write::realview.ide 808648 # Write bandwidth from this memory (bytes/s) | 67system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s) 68system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s) |
| 88system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 89system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 70system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 90system.physmem.bw_write::total 3044735 # Write bandwidth from this memory (bytes/s) 91system.physmem.bw_total::writebacks 2229898 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::realview.ide 808983 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) | 72system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) |
| 94system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) | 76system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) |
| 95system.physmem.bw_total::cpu0.inst 81672 # Total bandwidth to/from this memory (bytes/s) 96system.physmem.bw_total::cpu0.data 295734 # Total bandwidth to/from this memory (bytes/s) 97system.physmem.bw_total::cpu0.l2cache.prefetcher 3355741 # Total bandwidth to/from this memory (bytes/s) 98system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) | 77system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s) |
| 99system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 100system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) | 81system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) |
| 101system.physmem.bw_total::cpu1.data 153812 # Total bandwidth to/from this memory (bytes/s) 102system.physmem.bw_total::cpu1.l2cache.prefetcher 476228 # Total bandwidth to/from this memory (bytes/s) 103system.physmem.bw_total::total 7419755 # Total bandwidth to/from this memory (bytes/s) 104system.physmem.readReqs 205141 # Number of read requests accepted 105system.physmem.writeReqs 140550 # Number of write requests accepted 106system.physmem.readBursts 205141 # Number of DRAM read bursts, including those serviced by the write queue 107system.physmem.writeBursts 140550 # Number of DRAM write bursts, including those merged in the write queue 108system.physmem.bytesReadDRAM 13114752 # Total number of bytes read from DRAM 109system.physmem.bytesReadWrQ 14272 # Total number of bytes read from write queue 110system.physmem.bytesWritten 8743552 # Total number of bytes written to DRAM 111system.physmem.bytesReadSys 12542936 # Total read bytes from the system interface side 112system.physmem.bytesWrittenSys 8729040 # Total written bytes from the system interface side 113system.physmem.servicedByWrQ 223 # Number of DRAM read bursts serviced by the write queue 114system.physmem.mergedWrBursts 3913 # Number of DRAM write bursts merged with an existing one 115system.physmem.neitherReadNorWriteReqs 15151 # Number of requests that are neither read nor write 116system.physmem.perBankRdBursts::0 12845 # Per bank write bursts 117system.physmem.perBankRdBursts::1 12298 # Per bank write bursts 118system.physmem.perBankRdBursts::2 13022 # Per bank write bursts 119system.physmem.perBankRdBursts::3 12754 # Per bank write bursts 120system.physmem.perBankRdBursts::4 21257 # Per bank write bursts 121system.physmem.perBankRdBursts::5 12515 # Per bank write bursts 122system.physmem.perBankRdBursts::6 12829 # Per bank write bursts 123system.physmem.perBankRdBursts::7 12945 # Per bank write bursts 124system.physmem.perBankRdBursts::8 12057 # Per bank write bursts | 83system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.readReqs 205337 # Number of read requests accepted 87system.physmem.writeReqs 140504 # Number of write requests accepted 88system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue 89system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue 90system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM 91system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue 92system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM 93system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side 94system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side 95system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue 96system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one 97system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write 98system.physmem.perBankRdBursts::0 12897 # Per bank write bursts 99system.physmem.perBankRdBursts::1 12279 # Per bank write bursts 100system.physmem.perBankRdBursts::2 13044 # Per bank write bursts 101system.physmem.perBankRdBursts::3 12666 # Per bank write bursts 102system.physmem.perBankRdBursts::4 21207 # Per bank write bursts 103system.physmem.perBankRdBursts::5 12512 # Per bank write bursts 104system.physmem.perBankRdBursts::6 12819 # Per bank write bursts 105system.physmem.perBankRdBursts::7 13070 # Per bank write bursts 106system.physmem.perBankRdBursts::8 12092 # Per bank write bursts |
| 125system.physmem.perBankRdBursts::9 12100 # Per bank write bursts | 107system.physmem.perBankRdBursts::9 12100 # Per bank write bursts |
| 126system.physmem.perBankRdBursts::10 12212 # Per bank write bursts 127system.physmem.perBankRdBursts::11 11004 # Per bank write bursts 128system.physmem.perBankRdBursts::12 11810 # Per bank write bursts 129system.physmem.perBankRdBursts::13 12145 # Per bank write bursts 130system.physmem.perBankRdBursts::14 11734 # Per bank write bursts 131system.physmem.perBankRdBursts::15 11391 # Per bank write bursts 132system.physmem.perBankWrBursts::0 8757 # Per bank write bursts 133system.physmem.perBankWrBursts::1 8655 # Per bank write bursts 134system.physmem.perBankWrBursts::2 9184 # Per bank write bursts 135system.physmem.perBankWrBursts::3 8823 # Per bank write bursts 136system.physmem.perBankWrBursts::4 8606 # Per bank write bursts 137system.physmem.perBankWrBursts::5 8736 # Per bank write bursts 138system.physmem.perBankWrBursts::6 8840 # Per bank write bursts 139system.physmem.perBankWrBursts::7 8881 # Per bank write bursts 140system.physmem.perBankWrBursts::8 8404 # Per bank write bursts 141system.physmem.perBankWrBursts::9 8549 # Per bank write bursts 142system.physmem.perBankWrBursts::10 8595 # Per bank write bursts 143system.physmem.perBankWrBursts::11 8133 # Per bank write bursts 144system.physmem.perBankWrBursts::12 8369 # Per bank write bursts 145system.physmem.perBankWrBursts::13 8306 # Per bank write bursts 146system.physmem.perBankWrBursts::14 8199 # Per bank write bursts 147system.physmem.perBankWrBursts::15 7581 # Per bank write bursts | 108system.physmem.perBankRdBursts::10 12291 # Per bank write bursts 109system.physmem.perBankRdBursts::11 10982 # Per bank write bursts 110system.physmem.perBankRdBursts::12 11837 # Per bank write bursts 111system.physmem.perBankRdBursts::13 12135 # Per bank write bursts 112system.physmem.perBankRdBursts::14 11741 # Per bank write bursts 113system.physmem.perBankRdBursts::15 11403 # Per bank write bursts 114system.physmem.perBankWrBursts::0 8736 # Per bank write bursts 115system.physmem.perBankWrBursts::1 8619 # Per bank write bursts 116system.physmem.perBankWrBursts::2 9216 # Per bank write bursts 117system.physmem.perBankWrBursts::3 8724 # Per bank write bursts 118system.physmem.perBankWrBursts::4 8630 # Per bank write bursts 119system.physmem.perBankWrBursts::5 8715 # Per bank write bursts 120system.physmem.perBankWrBursts::6 8820 # Per bank write bursts 121system.physmem.perBankWrBursts::7 8946 # Per bank write bursts 122system.physmem.perBankWrBursts::8 8394 # Per bank write bursts 123system.physmem.perBankWrBursts::9 8545 # Per bank write bursts 124system.physmem.perBankWrBursts::10 8627 # Per bank write bursts 125system.physmem.perBankWrBursts::11 8114 # Per bank write bursts 126system.physmem.perBankWrBursts::12 8397 # Per bank write bursts 127system.physmem.perBankWrBursts::13 8288 # Per bank write bursts 128system.physmem.perBankWrBursts::14 8182 # Per bank write bursts 129system.physmem.perBankWrBursts::15 7606 # Per bank write bursts |
| 148system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 149system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 150system.physmem.totGap 2866928814500 # Total gap between requests | 131system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 132system.physmem.totGap 2866922767000 # Total gap between requests |
| 151system.physmem.readPktSize::0 0 # Read request sizes (log2) 152system.physmem.readPktSize::1 0 # Read request sizes (log2) 153system.physmem.readPktSize::2 9742 # Read request sizes (log2) 154system.physmem.readPktSize::3 28 # Read request sizes (log2) 155system.physmem.readPktSize::4 0 # Read request sizes (log2) 156system.physmem.readPktSize::5 0 # Read request sizes (log2) | 133system.physmem.readPktSize::0 0 # Read request sizes (log2) 134system.physmem.readPktSize::1 0 # Read request sizes (log2) 135system.physmem.readPktSize::2 9742 # Read request sizes (log2) 136system.physmem.readPktSize::3 28 # Read request sizes (log2) 137system.physmem.readPktSize::4 0 # Read request sizes (log2) 138system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 157system.physmem.readPktSize::6 195371 # Read request sizes (log2) | 139system.physmem.readPktSize::6 195567 # Read request sizes (log2) |
| 158system.physmem.writePktSize::0 0 # Write request sizes (log2) 159system.physmem.writePktSize::1 0 # Write request sizes (log2) 160system.physmem.writePktSize::2 4436 # Write request sizes (log2) 161system.physmem.writePktSize::3 0 # Write request sizes (log2) 162system.physmem.writePktSize::4 0 # Write request sizes (log2) 163system.physmem.writePktSize::5 0 # Write request sizes (log2) | 140system.physmem.writePktSize::0 0 # Write request sizes (log2) 141system.physmem.writePktSize::1 0 # Write request sizes (log2) 142system.physmem.writePktSize::2 4436 # Write request sizes (log2) 143system.physmem.writePktSize::3 0 # Write request sizes (log2) 144system.physmem.writePktSize::4 0 # Write request sizes (log2) 145system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 164system.physmem.writePktSize::6 136114 # Write request sizes (log2) 165system.physmem.rdQLenPdf::0 121124 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::1 21708 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::2 13339 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::3 11204 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::4 9572 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::5 8231 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::6 7040 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::7 6218 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::8 5357 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::9 501 # What read queue length does an incoming req see | 146system.physmem.writePktSize::6 136068 # Write request sizes (log2) 147system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see |
| 175system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see | 157system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see |
| 176system.physmem.rdQLenPdf::11 142 # What read queue length does an incoming req see | 158system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see |
| 177system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see | 159system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see |
| 178system.physmem.rdQLenPdf::13 64 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::15 26 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see | 160system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see |
| 183system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 190system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 204system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 165system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 212system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::16 3287 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::17 4176 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::18 5630 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::19 6226 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::21 7608 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::22 8446 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::23 9168 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::24 10203 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::25 9843 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::26 9504 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::27 9253 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::28 9714 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::30 7664 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::31 7594 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::32 7157 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::33 408 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::34 309 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::39 181 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::41 152 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::43 141 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see 246system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::50 77 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see 249system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see 250system.physmem.wrQLenPdf::53 41 # What write queue length does an incoming req see 251system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see 252system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see 253system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see 254system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see 255system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see 256system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see 257system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see 258system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see 259system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see 260system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 261system.physmem.bytesPerActivate::samples 80974 # Bytes accessed per row activation 262system.physmem.bytesPerActivate::mean 269.941463 # Bytes accessed per row activation 263system.physmem.bytesPerActivate::gmean 151.852686 # Bytes accessed per row activation 264system.physmem.bytesPerActivate::stdev 318.869933 # Bytes accessed per row activation 265system.physmem.bytesPerActivate::0-127 39277 48.51% 48.51% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::128-255 16073 19.85% 68.36% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::256-383 6267 7.74% 76.09% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::384-511 3406 4.21% 80.30% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::512-639 3201 3.95% 84.25% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::640-767 1947 2.40% 86.66% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::768-895 1140 1.41% 88.07% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::896-1023 1004 1.24% 89.31% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::1024-1151 8659 10.69% 100.00% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::total 80974 # Bytes accessed per row activation 275system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes 276system.physmem.rdPerTurnAround::mean 30.475461 # Reads before turning the bus around for writes 277system.physmem.rdPerTurnAround::stdev 574.843547 # Reads before turning the bus around for writes 278system.physmem.rdPerTurnAround::0-2047 6723 99.99% 99.99% # Reads before turning the bus around for writes 279system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 280system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes 281system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::mean 20.317965 # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::gmean 18.827449 # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::stdev 11.656598 # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::16-19 5486 81.59% 81.59% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::20-23 426 6.34% 87.92% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::24-27 82 1.22% 89.14% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::28-31 201 2.99% 92.13% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::32-35 197 2.93% 95.06% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::36-39 21 0.31% 95.37% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::40-43 19 0.28% 95.66% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::44-47 16 0.24% 95.90% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::48-51 29 0.43% 96.33% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::52-55 5 0.07% 96.40% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::56-59 4 0.06% 96.46% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::60-63 3 0.04% 96.51% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::64-67 175 2.60% 99.11% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::68-71 8 0.12% 99.23% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::72-75 7 0.10% 99.33% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::76-79 4 0.06% 99.39% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::80-83 7 0.10% 99.49% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::88-91 2 0.03% 99.55% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::96-99 6 0.09% 99.64% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::104-107 1 0.01% 99.69% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::108-111 2 0.03% 99.72% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::112-115 4 0.06% 99.78% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::116-119 3 0.04% 99.82% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 314system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 315system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads 316system.physmem.totQLat 5972474500 # Total ticks spent queuing 317system.physmem.totMemAccLat 9814687000 # Total ticks spent from burst creation until serviced by the DRAM 318system.physmem.totBusLat 1024590000 # Total ticks spent in databus transfers 319system.physmem.avgQLat 29145.68 # Average queueing delay per DRAM burst | 194system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see 243system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation 246system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation 257system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads 301system.physmem.totQLat 6009454502 # Total ticks spent queuing 302system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM 303system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers 304system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst |
| 320system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 305system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 321system.physmem.avgMemAccLat 47895.68 # Average memory access latency per DRAM burst 322system.physmem.avgRdBW 4.57 # Average DRAM read bandwidth in MiByte/s | 306system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst 307system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s |
| 323system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 324system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s 325system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s 326system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 327system.physmem.busUtil 0.06 # Data bus utilization in percentage 328system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 329system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 308system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 309system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s 310system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s 311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 312system.physmem.busUtil 0.06 # Data bus utilization in percentage 313system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 314system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 330system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing 331system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing 332system.physmem.readRowHits 175001 # Number of row buffer hits during reads 333system.physmem.writeRowHits 85560 # Number of row buffer hits during writes 334system.physmem.readRowHitRate 85.40 # Row buffer hit rate for reads 335system.physmem.writeRowHitRate 62.62 # Row buffer hit rate for writes 336system.physmem.avgGap 8293327.90 # Average gap between requests 337system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined 338system.physmem.memoryStateTime::IDLE 2731384342500 # Time in different power states 339system.physmem.memoryStateTime::REF 95733040000 # Time in different power states | 315system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing 316system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing 317system.physmem.readRowHits 175010 # Number of row buffer hits during reads 318system.physmem.writeRowHits 85502 # Number of row buffer hits during writes 319system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads 320system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes 321system.physmem.avgGap 8289713.39 # Average gap between requests 322system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined 323system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states 324system.physmem.memoryStateTime::REF 95732780000 # Time in different power states |
| 340system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 325system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 341system.physmem.memoryStateTime::ACT 39811853000 # Time in different power states | 326system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states |
| 342system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 327system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 343system.physmem.actEnergy::0 323167320 # Energy for activate commands per rank (pJ) 344system.physmem.actEnergy::1 288996120 # Energy for activate commands per rank (pJ) 345system.physmem.preEnergy::0 176331375 # Energy for precharge commands per rank (pJ) 346system.physmem.preEnergy::1 157686375 # Energy for precharge commands per rank (pJ) 347system.physmem.readEnergy::0 861627000 # Energy for read commands per rank (pJ) 348system.physmem.readEnergy::1 736725600 # Energy for read commands per rank (pJ) 349system.physmem.writeEnergy::0 456723360 # Energy for write commands per rank (pJ) 350system.physmem.writeEnergy::1 428561280 # Energy for write commands per rank (pJ) 351system.physmem.refreshEnergy::0 187253826240 # Energy for refresh commands per rank (pJ) 352system.physmem.refreshEnergy::1 187253826240 # Energy for refresh commands per rank (pJ) 353system.physmem.actBackEnergy::0 82374692850 # Energy for active background per rank (pJ) 354system.physmem.actBackEnergy::1 81185757210 # Energy for active background per rank (pJ) 355system.physmem.preBackEnergy::0 1647898682250 # Energy for precharge background per rank (pJ) 356system.physmem.preBackEnergy::1 1648941608250 # Energy for precharge background per rank (pJ) 357system.physmem.totalEnergy::0 1919345050395 # Total energy per rank (pJ) 358system.physmem.totalEnergy::1 1918993161075 # Total energy per rank (pJ) 359system.physmem.averagePower::0 669.477790 # Core power per rank (mW) 360system.physmem.averagePower::1 669.355049 # Core power per rank (mW) 361system.membus.trans_dist::ReadReq 228441 # Transaction distribution 362system.membus.trans_dist::ReadResp 228440 # Transaction distribution 363system.membus.trans_dist::WriteReq 31177 # Transaction distribution 364system.membus.trans_dist::WriteResp 31177 # Transaction distribution 365system.membus.trans_dist::Writeback 99890 # Transaction distribution | 328system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ) 329system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ) 330system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ) 331system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ) 332system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ) 333system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ) 334system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ) 335system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ) 336system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ) 337system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ) 338system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ) 339system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ) 340system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ) 341system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ) 342system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ) 343system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ) 344system.physmem.averagePower::0 669.491656 # Core power per rank (mW) 345system.physmem.averagePower::1 669.352997 # Core power per rank (mW) 346system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 349system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 350system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 351system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 352system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 353system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 354system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 355system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 359system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 362system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 363system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 364system.membus.trans_dist::ReadReq 228669 # Transaction distribution 365system.membus.trans_dist::ReadResp 228668 # Transaction distribution 366system.membus.trans_dist::WriteReq 31179 # Transaction distribution 367system.membus.trans_dist::WriteResp 31179 # Transaction distribution 368system.membus.trans_dist::Writeback 99844 # Transaction distribution |
| 366system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 367system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 369system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 370system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 368system.membus.trans_dist::UpgradeReq 85859 # Transaction distribution 369system.membus.trans_dist::SCUpgradeReq 41212 # Transaction distribution 370system.membus.trans_dist::UpgradeResp 15151 # Transaction distribution 371system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 372system.membus.trans_dist::ReadExReq 28398 # Transaction distribution 373system.membus.trans_dist::ReadExResp 11478 # Transaction distribution | 371system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution 372system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution 373system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution 374system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 375system.membus.trans_dist::ReadExReq 28316 # Transaction distribution 376system.membus.trans_dist::ReadExResp 11444 # Transaction distribution |
| 374system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) | 377system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) |
| 375system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) 376system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14560 # Packet count per connected master and slave (bytes) 377system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678158 # Packet count per connected master and slave (bytes) 378system.membus.pkt_count_system.l2c.mem_side::total 800720 # Packet count per connected master and slave (bytes) | 378system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 379system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes) 380system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes) 381system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes) |
| 379system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) 380system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) | 382system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) 383system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) |
| 381system.membus.pkt_count::total 873436 # Packet count per connected master and slave (bytes) | 384system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes) |
| 382system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) | 385system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) |
| 383system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) 384system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29120 # Cumulative packet size per connected master and slave (bytes) 385system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18952616 # Cumulative packet size per connected master and slave (bytes) 386system.membus.pkt_size_system.l2c.mem_side::total 19144659 # Cumulative packet size per connected master and slave (bytes) | 386system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 387system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes) 388system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes) 389system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes) |
| 387system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 388system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) | 390system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 391system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) |
| 389system.membus.pkt_size::total 21463955 # Cumulative packet size per connected master and slave (bytes) 390system.membus.snoops 129081 # Total snoops (count) 391system.membus.snoop_fanout::samples 475718 # Request fanout histogram | 392system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes) 393system.membus.snoops 128959 # Total snoops (count) 394system.membus.snoop_fanout::samples 475734 # Request fanout histogram |
| 392system.membus.snoop_fanout::mean 1 # Request fanout histogram 393system.membus.snoop_fanout::stdev 0 # Request fanout histogram 394system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 395system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 395system.membus.snoop_fanout::mean 1 # Request fanout histogram 396system.membus.snoop_fanout::stdev 0 # Request fanout histogram 397system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 398system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 396system.membus.snoop_fanout::1 475718 100.00% 100.00% # Request fanout histogram | 399system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram |
| 397system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 398system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 399system.membus.snoop_fanout::min_value 1 # Request fanout histogram 400system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 400system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 401system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 402system.membus.snoop_fanout::min_value 1 # Request fanout histogram 403system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 401system.membus.snoop_fanout::total 475718 # Request fanout histogram 402system.membus.reqLayer0.occupancy 88161999 # Layer occupancy (ticks) | 404system.membus.snoop_fanout::total 475734 # Request fanout histogram 405system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks) |
| 403system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 406system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 404system.membus.reqLayer1.occupancy 20500 # Layer occupancy (ticks) | 407system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) |
| 405system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 408system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 406system.membus.reqLayer2.occupancy 12079498 # Layer occupancy (ticks) | 409system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks) |
| 407system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 410system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 408system.membus.reqLayer5.occupancy 1514580499 # Layer occupancy (ticks) | 411system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks) |
| 409system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) | 412system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
| 410system.membus.respLayer2.occupancy 1969894164 # Layer occupancy (ticks) | 413system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks) |
| 411system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 414system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 412system.membus.respLayer3.occupancy 38592409 # Layer occupancy (ticks) | 415system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks) |
| 413system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 414system.cpu_clk_domain.clock 500 # Clock period in ticks | 416system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 417system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 415system.l2c.tags.replacements 132728 # number of replacements 416system.l2c.tags.tagsinuse 64199.829322 # Cycle average of tags in use 417system.l2c.tags.total_refs 489645 # Total number of references to valid blocks. 418system.l2c.tags.sampled_refs 197292 # Sample count of references to valid blocks. 419system.l2c.tags.avg_refs 2.481829 # Average number of references to valid blocks. | 418system.l2c.tags.replacements 132855 # number of replacements 419system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use 420system.l2c.tags.total_refs 486769 # Total number of references to valid blocks. 421system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks. 422system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks. |
| 420system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 423system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 421system.l2c.tags.occ_blocks::writebacks 12574.713731 # Average occupied blocks per requestor 422system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.829645 # Average occupied blocks per requestor 423system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043526 # Average occupied blocks per requestor 424system.l2c.tags.occ_blocks::cpu0.inst 1158.059566 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu0.data 1408.624866 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.540569 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007801 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu1.inst 536.338892 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu1.data 908.008157 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8820.200180 # Average occupied blocks per requestor 432system.l2c.tags.occ_percent::writebacks 0.191875 # Average percentage of cache occupancy | 424system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor 432system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor 433system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor 434system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor 435system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy |
| 433system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy | 436system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy |
| 434system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 435system.l2c.tags.occ_percent::cpu0.inst 0.017671 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu0.data 0.021494 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.591834 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000039 # Average percentage of cache occupancy | 437system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy 439system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy 440system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy |
| 439system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy | 442system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy |
| 440system.l2c.tags.occ_percent::cpu1.inst 0.008184 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::cpu1.data 0.013855 # Average percentage of cache occupancy 442system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134586 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::total 0.979612 # Average percentage of cache occupancy 444system.l2c.tags.occ_task_id_blocks::1022 44718 # Occupied blocks per task id 445system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 446system.l2c.tags.occ_task_id_blocks::1024 19841 # Occupied blocks per task id 447system.l2c.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id 448system.l2c.tags.age_task_id_blocks_1022::3 5098 # Occupied blocks per task id 449system.l2c.tags.age_task_id_blocks_1022::4 39452 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id | 443system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy 444system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy 445system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy 446system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy 447system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id 448system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 449system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id 453system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 454system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id |
| 453system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id | 455system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id |
| 454system.l2c.tags.age_task_id_blocks_1024::3 1574 # Occupied blocks per task id 455system.l2c.tags.age_task_id_blocks_1024::4 18054 # Occupied blocks per task id 456system.l2c.tags.occ_task_id_percent::1022 0.682343 # Percentage of cache occupancy per task id 457system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 458system.l2c.tags.occ_task_id_percent::1024 0.302750 # Percentage of cache occupancy per task id 459system.l2c.tags.tag_accesses 6148253 # Number of tag accesses 460system.l2c.tags.data_accesses 6148253 # Number of data accesses 461system.l2c.ReadReq_hits::cpu0.dtb.walker 127 # number of ReadReq hits 462system.l2c.ReadReq_hits::cpu0.itb.walker 159 # number of ReadReq hits 463system.l2c.ReadReq_hits::cpu0.inst 10419 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.data 29225 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168428 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu1.dtb.walker 62 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.inst 4147 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.data 10318 # number of ReadReq hits 470system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47800 # number of ReadReq hits 471system.l2c.ReadReq_hits::total 270735 # number of ReadReq hits 472system.l2c.Writeback_hits::writebacks 240561 # number of Writeback hits 473system.l2c.Writeback_hits::total 240561 # number of Writeback hits 474system.l2c.UpgradeReq_hits::cpu0.data 9666 # number of UpgradeReq hits 475system.l2c.UpgradeReq_hits::cpu1.data 1017 # number of UpgradeReq hits 476system.l2c.UpgradeReq_hits::total 10683 # number of UpgradeReq hits 477system.l2c.SCUpgradeReq_hits::cpu0.data 240 # number of SCUpgradeReq hits 478system.l2c.SCUpgradeReq_hits::cpu1.data 136 # number of SCUpgradeReq hits 479system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits 480system.l2c.ReadExReq_hits::cpu0.data 4189 # number of ReadExReq hits 481system.l2c.ReadExReq_hits::cpu1.data 2493 # number of ReadExReq hits 482system.l2c.ReadExReq_hits::total 6682 # number of ReadExReq hits 483system.l2c.demand_hits::cpu0.dtb.walker 127 # number of demand (read+write) hits 484system.l2c.demand_hits::cpu0.itb.walker 159 # number of demand (read+write) hits 485system.l2c.demand_hits::cpu0.inst 10419 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.data 33414 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu0.l2cache.prefetcher 168428 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu1.dtb.walker 62 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.inst 4147 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.data 12811 # number of demand (read+write) hits 492system.l2c.demand_hits::cpu1.l2cache.prefetcher 47800 # number of demand (read+write) hits 493system.l2c.demand_hits::total 277417 # number of demand (read+write) hits 494system.l2c.overall_hits::cpu0.dtb.walker 127 # number of overall hits 495system.l2c.overall_hits::cpu0.itb.walker 159 # number of overall hits 496system.l2c.overall_hits::cpu0.inst 10419 # number of overall hits 497system.l2c.overall_hits::cpu0.data 33414 # number of overall hits 498system.l2c.overall_hits::cpu0.l2cache.prefetcher 168428 # number of overall hits 499system.l2c.overall_hits::cpu1.dtb.walker 62 # number of overall hits 500system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits 501system.l2c.overall_hits::cpu1.inst 4147 # number of overall hits 502system.l2c.overall_hits::cpu1.data 12811 # number of overall hits 503system.l2c.overall_hits::cpu1.l2cache.prefetcher 47800 # number of overall hits 504system.l2c.overall_hits::total 277417 # number of overall hits 505system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses | 456system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id 457system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id 458system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id 459system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 460system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id 461system.l2c.tags.tag_accesses 6123027 # Number of tag accesses 462system.l2c.tags.data_accesses 6123027 # Number of data accesses 463system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits 470system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits 471system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits 472system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits 473system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits 474system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits 475system.l2c.Writeback_hits::total 239796 # number of Writeback hits 476system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits 477system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits 478system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits 479system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits 480system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits 481system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits 482system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits 483system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits 484system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits 485system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits 492system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits 493system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits 494system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits 495system.l2c.demand_hits::total 274907 # number of demand (read+write) hits 496system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits 497system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits 498system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits 499system.l2c.overall_hits::cpu0.data 33021 # number of overall hits 500system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits 501system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits 502system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits 503system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits 504system.l2c.overall_hits::cpu1.data 12797 # number of overall hits 505system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits 506system.l2c.overall_hits::total 274907 # number of overall hits 507system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses |
| 506system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses | 508system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
| 507system.l2c.ReadReq_misses::cpu0.inst 3095 # number of ReadReq misses 508system.l2c.ReadReq_misses::cpu0.data 6926 # number of ReadReq misses 509system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses | 509system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses 511system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses |
| 511system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses | 513system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 514system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses |
| 513system.l2c.ReadReq_misses::cpu1.data 1418 # number of ReadReq misses 514system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq misses 515system.l2c.ReadReq_misses::total 183878 # number of ReadReq misses 516system.l2c.UpgradeReq_misses::cpu0.data 8558 # number of UpgradeReq misses 517system.l2c.UpgradeReq_misses::cpu1.data 4221 # number of UpgradeReq misses 518system.l2c.UpgradeReq_misses::total 12779 # number of UpgradeReq misses 519system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses 520system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses 521system.l2c.SCUpgradeReq_misses::total 2199 # number of SCUpgradeReq misses 522system.l2c.ReadExReq_misses::cpu0.data 6118 # number of ReadExReq misses 523system.l2c.ReadExReq_misses::cpu1.data 5533 # number of ReadExReq misses 524system.l2c.ReadExReq_misses::total 11651 # number of ReadExReq misses 525system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses | 515system.l2c.ReadReq_misses::cpu1.data 1415 # number of ReadReq misses 516system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq misses 517system.l2c.ReadReq_misses::total 184109 # number of ReadReq misses 518system.l2c.UpgradeReq_misses::cpu0.data 8503 # number of UpgradeReq misses 519system.l2c.UpgradeReq_misses::cpu1.data 4264 # number of UpgradeReq misses 520system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses 521system.l2c.SCUpgradeReq_misses::cpu0.data 881 # number of SCUpgradeReq misses 522system.l2c.SCUpgradeReq_misses::cpu1.data 1309 # number of SCUpgradeReq misses 523system.l2c.SCUpgradeReq_misses::total 2190 # number of SCUpgradeReq misses 524system.l2c.ReadExReq_misses::cpu0.data 6116 # number of ReadExReq misses 525system.l2c.ReadExReq_misses::cpu1.data 5504 # number of ReadExReq misses 526system.l2c.ReadExReq_misses::total 11620 # number of ReadExReq misses 527system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses |
| 526system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses | 528system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
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| 533system.l2c.demand_misses::cpu1.data 6951 # number of demand (read+write) misses 534system.l2c.demand_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) misses 535system.l2c.demand_misses::total 195529 # number of demand (read+write) misses 536system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses | 535system.l2c.demand_misses::cpu1.data 6919 # number of demand (read+write) misses 536system.l2c.demand_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) misses 537system.l2c.demand_misses::total 195729 # number of demand (read+write) misses 538system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses |
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| 538system.l2c.overall_misses::cpu0.inst 3095 # number of overall misses 539system.l2c.overall_misses::cpu0.data 13044 # number of overall misses 540system.l2c.overall_misses::cpu0.l2cache.prefetcher 150324 # number of overall misses 541system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses | 540system.l2c.overall_misses::cpu0.inst 3114 # number of overall misses 541system.l2c.overall_misses::cpu0.data 13092 # number of overall misses 542system.l2c.overall_misses::cpu0.l2cache.prefetcher 150483 # number of overall misses 543system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses |
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| 544system.l2c.overall_misses::cpu1.data 6951 # number of overall misses 545system.l2c.overall_misses::cpu1.l2cache.prefetcher 21333 # number of overall misses 546system.l2c.overall_misses::total 195529 # number of overall misses 547system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 510000 # number of ReadReq miss cycles | 546system.l2c.overall_misses::cpu1.data 6919 # number of overall misses 547system.l2c.overall_misses::cpu1.l2cache.prefetcher 21339 # number of overall misses 548system.l2c.overall_misses::total 195729 # number of overall misses 549system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 706500 # number of ReadReq miss cycles |
| 548system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles | 550system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles |
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| 569system.l2c.demand_miss_latency::cpu0.inst 268587999 # number of demand (read+write) miss cycles 570system.l2c.demand_miss_latency::cpu0.data 1048933389 # number of demand (read+write) miss cycles 571system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of demand (read+write) miss cycles 572system.l2c.demand_miss_latency::cpu1.dtb.walker 328000 # number of demand (read+write) miss cycles 573system.l2c.demand_miss_latency::cpu1.itb.walker 94250 # number of demand (read+write) miss cycles 574system.l2c.demand_miss_latency::cpu1.inst 70493000 # number of demand (read+write) miss cycles 575system.l2c.demand_miss_latency::cpu1.data 527090436 # number of demand (read+write) miss cycles 576system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of demand (read+write) miss cycles 577system.l2c.demand_miss_latency::total 19269350900 # number of demand (read+write) miss cycles 578system.l2c.overall_miss_latency::cpu0.dtb.walker 510000 # number of overall miss cycles | 571system.l2c.demand_miss_latency::cpu0.inst 269607250 # number of demand (read+write) miss cycles 572system.l2c.demand_miss_latency::cpu0.data 1063341890 # number of demand (read+write) miss cycles 573system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of demand (read+write) miss cycles 574system.l2c.demand_miss_latency::cpu1.dtb.walker 266750 # number of demand (read+write) miss cycles 575system.l2c.demand_miss_latency::cpu1.itb.walker 88750 # number of demand (read+write) miss cycles 576system.l2c.demand_miss_latency::cpu1.inst 69445999 # number of demand (read+write) miss cycles 577system.l2c.demand_miss_latency::cpu1.data 520050931 # number of demand (read+write) miss cycles 578system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of demand (read+write) miss cycles 579system.l2c.demand_miss_latency::total 19319712175 # number of demand (read+write) miss cycles 580system.l2c.overall_miss_latency::cpu0.dtb.walker 706500 # number of overall miss cycles |
| 579system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles | 581system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles |
| 580system.l2c.overall_miss_latency::cpu0.inst 268587999 # number of overall miss cycles 581system.l2c.overall_miss_latency::cpu0.data 1048933389 # number of overall miss cycles 582system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of overall miss cycles 583system.l2c.overall_miss_latency::cpu1.dtb.walker 328000 # number of overall miss cycles 584system.l2c.overall_miss_latency::cpu1.itb.walker 94250 # number of overall miss cycles 585system.l2c.overall_miss_latency::cpu1.inst 70493000 # number of overall miss cycles 586system.l2c.overall_miss_latency::cpu1.data 527090436 # number of overall miss cycles 587system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of overall miss cycles 588system.l2c.overall_miss_latency::total 19269350900 # number of overall miss cycles 589system.l2c.ReadReq_accesses::cpu0.dtb.walker 134 # number of ReadReq accesses(hits+misses) 590system.l2c.ReadReq_accesses::cpu0.itb.walker 160 # number of ReadReq accesses(hits+misses) 591system.l2c.ReadReq_accesses::cpu0.inst 13514 # number of ReadReq accesses(hits+misses) 592system.l2c.ReadReq_accesses::cpu0.data 36151 # number of ReadReq accesses(hits+misses) 593system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318752 # number of ReadReq accesses(hits+misses) 594system.l2c.ReadReq_accesses::cpu1.dtb.walker 66 # number of ReadReq accesses(hits+misses) 595system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::cpu1.inst 4916 # number of ReadReq accesses(hits+misses) 597system.l2c.ReadReq_accesses::cpu1.data 11736 # number of ReadReq accesses(hits+misses) 598system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69133 # number of ReadReq accesses(hits+misses) 599system.l2c.ReadReq_accesses::total 454613 # number of ReadReq accesses(hits+misses) 600system.l2c.Writeback_accesses::writebacks 240561 # number of Writeback accesses(hits+misses) 601system.l2c.Writeback_accesses::total 240561 # number of Writeback accesses(hits+misses) 602system.l2c.UpgradeReq_accesses::cpu0.data 18224 # number of UpgradeReq accesses(hits+misses) 603system.l2c.UpgradeReq_accesses::cpu1.data 5238 # number of UpgradeReq accesses(hits+misses) 604system.l2c.UpgradeReq_accesses::total 23462 # number of UpgradeReq accesses(hits+misses) | 582system.l2c.overall_miss_latency::cpu0.inst 269607250 # number of overall miss cycles 583system.l2c.overall_miss_latency::cpu0.data 1063341890 # number of overall miss cycles 584system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of overall miss cycles 585system.l2c.overall_miss_latency::cpu1.dtb.walker 266750 # number of overall miss cycles 586system.l2c.overall_miss_latency::cpu1.itb.walker 88750 # number of overall miss cycles 587system.l2c.overall_miss_latency::cpu1.inst 69445999 # number of overall miss cycles 588system.l2c.overall_miss_latency::cpu1.data 520050931 # number of overall miss cycles 589system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of overall miss cycles 590system.l2c.overall_miss_latency::total 19319712175 # number of overall miss cycles 591system.l2c.ReadReq_accesses::cpu0.dtb.walker 146 # number of ReadReq accesses(hits+misses) 592system.l2c.ReadReq_accesses::cpu0.itb.walker 134 # number of ReadReq accesses(hits+misses) 593system.l2c.ReadReq_accesses::cpu0.inst 13324 # number of ReadReq accesses(hits+misses) 594system.l2c.ReadReq_accesses::cpu0.data 35839 # number of ReadReq accesses(hits+misses) 595system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 317069 # number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::cpu1.dtb.walker 52 # number of ReadReq accesses(hits+misses) 597system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) 598system.l2c.ReadReq_accesses::cpu1.inst 4966 # number of ReadReq accesses(hits+misses) 599system.l2c.ReadReq_accesses::cpu1.data 11686 # number of ReadReq accesses(hits+misses) 600system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69069 # number of ReadReq accesses(hits+misses) 601system.l2c.ReadReq_accesses::total 452332 # number of ReadReq accesses(hits+misses) 602system.l2c.Writeback_accesses::writebacks 239796 # number of Writeback accesses(hits+misses) 603system.l2c.Writeback_accesses::total 239796 # number of Writeback accesses(hits+misses) 604system.l2c.UpgradeReq_accesses::cpu0.data 18165 # number of UpgradeReq accesses(hits+misses) 605system.l2c.UpgradeReq_accesses::cpu1.data 5198 # number of UpgradeReq accesses(hits+misses) 606system.l2c.UpgradeReq_accesses::total 23363 # number of UpgradeReq accesses(hits+misses) |
| 605system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses) | 607system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses) |
| 606system.l2c.SCUpgradeReq_accesses::cpu1.data 1446 # number of SCUpgradeReq accesses(hits+misses) 607system.l2c.SCUpgradeReq_accesses::total 2575 # number of SCUpgradeReq accesses(hits+misses) 608system.l2c.ReadExReq_accesses::cpu0.data 10307 # number of ReadExReq accesses(hits+misses) 609system.l2c.ReadExReq_accesses::cpu1.data 8026 # number of ReadExReq accesses(hits+misses) 610system.l2c.ReadExReq_accesses::total 18333 # number of ReadExReq accesses(hits+misses) 611system.l2c.demand_accesses::cpu0.dtb.walker 134 # number of demand (read+write) accesses 612system.l2c.demand_accesses::cpu0.itb.walker 160 # number of demand (read+write) accesses 613system.l2c.demand_accesses::cpu0.inst 13514 # number of demand (read+write) accesses 614system.l2c.demand_accesses::cpu0.data 46458 # number of demand (read+write) accesses 615system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318752 # number of demand (read+write) accesses 616system.l2c.demand_accesses::cpu1.dtb.walker 66 # number of demand (read+write) accesses 617system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses 618system.l2c.demand_accesses::cpu1.inst 4916 # number of demand (read+write) accesses 619system.l2c.demand_accesses::cpu1.data 19762 # number of demand (read+write) accesses 620system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69133 # number of demand (read+write) accesses 621system.l2c.demand_accesses::total 472946 # number of demand (read+write) accesses 622system.l2c.overall_accesses::cpu0.dtb.walker 134 # number of overall (read+write) accesses 623system.l2c.overall_accesses::cpu0.itb.walker 160 # number of overall (read+write) accesses 624system.l2c.overall_accesses::cpu0.inst 13514 # number of overall (read+write) accesses 625system.l2c.overall_accesses::cpu0.data 46458 # number of overall (read+write) accesses 626system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318752 # number of overall (read+write) accesses 627system.l2c.overall_accesses::cpu1.dtb.walker 66 # number of overall (read+write) accesses 628system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses 629system.l2c.overall_accesses::cpu1.inst 4916 # number of overall (read+write) accesses 630system.l2c.overall_accesses::cpu1.data 19762 # number of overall (read+write) accesses 631system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69133 # number of overall (read+write) accesses 632system.l2c.overall_accesses::total 472946 # number of overall (read+write) accesses 633system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for ReadReq accesses 634system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006250 # miss rate for ReadReq accesses 635system.l2c.ReadReq_miss_rate::cpu0.inst 0.229022 # miss rate for ReadReq accesses 636system.l2c.ReadReq_miss_rate::cpu0.data 0.191585 # miss rate for ReadReq accesses 637system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for ReadReq accesses 638system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for ReadReq accesses 639system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses 640system.l2c.ReadReq_miss_rate::cpu1.inst 0.156428 # miss rate for ReadReq accesses 641system.l2c.ReadReq_miss_rate::cpu1.data 0.120825 # miss rate for ReadReq accesses 642system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for ReadReq accesses 643system.l2c.ReadReq_miss_rate::total 0.404471 # miss rate for ReadReq accesses 644system.l2c.UpgradeReq_miss_rate::cpu0.data 0.469601 # miss rate for UpgradeReq accesses 645system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805842 # miss rate for UpgradeReq accesses 646system.l2c.UpgradeReq_miss_rate::total 0.544668 # miss rate for UpgradeReq accesses 647system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787422 # miss rate for SCUpgradeReq accesses 648system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.905947 # miss rate for SCUpgradeReq accesses 649system.l2c.SCUpgradeReq_miss_rate::total 0.853981 # miss rate for SCUpgradeReq accesses 650system.l2c.ReadExReq_miss_rate::cpu0.data 0.593577 # miss rate for ReadExReq accesses 651system.l2c.ReadExReq_miss_rate::cpu1.data 0.689385 # miss rate for ReadExReq accesses 652system.l2c.ReadExReq_miss_rate::total 0.635521 # miss rate for ReadExReq accesses 653system.l2c.demand_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for demand accesses 654system.l2c.demand_miss_rate::cpu0.itb.walker 0.006250 # miss rate for demand accesses 655system.l2c.demand_miss_rate::cpu0.inst 0.229022 # miss rate for demand accesses 656system.l2c.demand_miss_rate::cpu0.data 0.280770 # miss rate for demand accesses 657system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for demand accesses 658system.l2c.demand_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for demand accesses 659system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses 660system.l2c.demand_miss_rate::cpu1.inst 0.156428 # miss rate for demand accesses 661system.l2c.demand_miss_rate::cpu1.data 0.351736 # miss rate for demand accesses 662system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for demand accesses 663system.l2c.demand_miss_rate::total 0.413428 # miss rate for demand accesses 664system.l2c.overall_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for overall accesses 665system.l2c.overall_miss_rate::cpu0.itb.walker 0.006250 # miss rate for overall accesses 666system.l2c.overall_miss_rate::cpu0.inst 0.229022 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.data 0.280770 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses 671system.l2c.overall_miss_rate::cpu1.inst 0.156428 # miss rate for overall accesses 672system.l2c.overall_miss_rate::cpu1.data 0.351736 # miss rate for overall accesses 673system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for overall accesses 674system.l2c.overall_miss_rate::total 0.413428 # miss rate for overall accesses 675system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average ReadReq miss latency | 608system.l2c.SCUpgradeReq_accesses::cpu1.data 1460 # number of SCUpgradeReq accesses(hits+misses) 609system.l2c.SCUpgradeReq_accesses::total 2589 # number of SCUpgradeReq accesses(hits+misses) 610system.l2c.ReadExReq_accesses::cpu0.data 10274 # number of ReadExReq accesses(hits+misses) 611system.l2c.ReadExReq_accesses::cpu1.data 8030 # number of ReadExReq accesses(hits+misses) 612system.l2c.ReadExReq_accesses::total 18304 # number of ReadExReq accesses(hits+misses) 613system.l2c.demand_accesses::cpu0.dtb.walker 146 # number of demand (read+write) accesses 614system.l2c.demand_accesses::cpu0.itb.walker 134 # number of demand (read+write) accesses 615system.l2c.demand_accesses::cpu0.inst 13324 # number of demand (read+write) accesses 616system.l2c.demand_accesses::cpu0.data 46113 # number of demand (read+write) accesses 617system.l2c.demand_accesses::cpu0.l2cache.prefetcher 317069 # number of demand (read+write) accesses 618system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses 619system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses 620system.l2c.demand_accesses::cpu1.inst 4966 # number of demand (read+write) accesses 621system.l2c.demand_accesses::cpu1.data 19716 # number of demand (read+write) accesses 622system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69069 # number of demand (read+write) accesses 623system.l2c.demand_accesses::total 470636 # number of demand (read+write) accesses 624system.l2c.overall_accesses::cpu0.dtb.walker 146 # number of overall (read+write) accesses 625system.l2c.overall_accesses::cpu0.itb.walker 134 # number of overall (read+write) accesses 626system.l2c.overall_accesses::cpu0.inst 13324 # number of overall (read+write) accesses 627system.l2c.overall_accesses::cpu0.data 46113 # number of overall (read+write) accesses 628system.l2c.overall_accesses::cpu0.l2cache.prefetcher 317069 # number of overall (read+write) accesses 629system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses 630system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses 631system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses 632system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses 633system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses 634system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses 635system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses 636system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses 637system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses 638system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses 639system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses 640system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for ReadReq accesses 641system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses 642system.l2c.ReadReq_miss_rate::cpu1.inst 0.154853 # miss rate for ReadReq accesses 643system.l2c.ReadReq_miss_rate::cpu1.data 0.121085 # miss rate for ReadReq accesses 644system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for ReadReq accesses 645system.l2c.ReadReq_miss_rate::total 0.407022 # miss rate for ReadReq accesses 646system.l2c.UpgradeReq_miss_rate::cpu0.data 0.468098 # miss rate for UpgradeReq accesses 647system.l2c.UpgradeReq_miss_rate::cpu1.data 0.820316 # miss rate for UpgradeReq accesses 648system.l2c.UpgradeReq_miss_rate::total 0.546462 # miss rate for UpgradeReq accesses 649system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.780337 # miss rate for SCUpgradeReq accesses 650system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.896575 # miss rate for SCUpgradeReq accesses 651system.l2c.SCUpgradeReq_miss_rate::total 0.845886 # miss rate for SCUpgradeReq accesses 652system.l2c.ReadExReq_miss_rate::cpu0.data 0.595289 # miss rate for ReadExReq accesses 653system.l2c.ReadExReq_miss_rate::cpu1.data 0.685430 # miss rate for ReadExReq accesses 654system.l2c.ReadExReq_miss_rate::total 0.634834 # miss rate for ReadExReq accesses 655system.l2c.demand_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for demand accesses 656system.l2c.demand_miss_rate::cpu0.itb.walker 0.007463 # miss rate for demand accesses 657system.l2c.demand_miss_rate::cpu0.inst 0.233714 # miss rate for demand accesses 658system.l2c.demand_miss_rate::cpu0.data 0.283911 # miss rate for demand accesses 659system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for demand accesses 660system.l2c.demand_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for demand accesses 661system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses 662system.l2c.demand_miss_rate::cpu1.inst 0.154853 # miss rate for demand accesses 663system.l2c.demand_miss_rate::cpu1.data 0.350933 # miss rate for demand accesses 664system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for demand accesses 665system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses 666system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses 671system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses 672system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses 673system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses 674system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses 675system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses 676system.l2c.overall_miss_rate::total 0.415882 # miss rate for overall accesses 677system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average ReadReq miss latency |
| 676system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency | 678system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency |
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| 696system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 698system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
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| 707system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency | 709system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency |
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| 718system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 720system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 719system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked | 721system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked |
| 720system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 722system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
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mshr miss rate for overall accesses 870system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses 871system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses 872system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for overall accesses 873system.l2c.overall_mshr_miss_rate::total 0.415880 # mshr miss rate for overall accesses 874system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average ReadReq mshr miss latency |
| 867system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 875system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 868system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average ReadReq mshr miss latency 869system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665 # average ReadReq mshr miss latency 870system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average ReadReq mshr miss latency 871system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average ReadReq mshr miss latency 872system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average ReadReq mshr miss latency 873system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average ReadReq mshr miss latency 874system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453 # average ReadReq mshr miss latency 875system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average ReadReq mshr miss latency 876system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816 # average ReadReq mshr miss latency 877system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533 # average UpgradeReq mshr miss latency 878system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922 # average UpgradeReq mshr miss latency 879system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676 # average UpgradeReq mshr miss latency 880system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423 # average SCUpgradeReq mshr miss latency 881system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733 # average SCUpgradeReq mshr miss latency 882system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852 # average SCUpgradeReq mshr miss latency 883system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099 # average ReadExReq mshr miss latency 884system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940 # average ReadExReq mshr miss latency 885system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831 # average ReadExReq mshr miss latency 886system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency | 876system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average ReadReq mshr miss latency 877system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69416.248423 # average ReadReq mshr miss latency 878system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average ReadReq mshr miss latency 879system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency 880system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency 881system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency 882system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency 883system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency 884system.l2c.ReadReq_avg_mshr_miss_latency::total 87699.200225 # average ReadReq mshr miss latency 885system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency 886system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency 887system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency 888system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency 889system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency 890system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency 891system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68004.146010 # average ReadExReq mshr miss latency 892system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59507.325036 # average ReadExReq mshr miss latency 893system.l2c.ReadExReq_avg_mshr_miss_latency::total 63979.490017 # average ReadExReq mshr miss latency 894system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency |
| 887system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 895system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 888system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency 889system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency 890system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency 891system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency 892system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency 893system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency 894system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency 895system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency 896system.l2c.demand_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency 897system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency | 896system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency 897system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency 898system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency 899system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency 900system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 901system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency 902system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency 903system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency 904system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency 905system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency |
| 898system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 906system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 899system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency 900system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency 901system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency 902system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency 903system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency 904system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency 905system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency 906system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency 907system.l2c.overall_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency | 907system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency 908system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency 909system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency 910system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency 911system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency 912system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency 913system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency 914system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency 915system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency |
| 908system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 910system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 911system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 912system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 913system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 914system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 915system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 35 unchanged lines hidden (view full) --- 951system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 952system.realview.ethernet.droppedPackets 0 # number of packets dropped 953system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 954system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 955system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 956system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 957system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 958system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 916system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 917system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 918system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 919system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 920system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 921system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 922system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 923system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 35 unchanged lines hidden (view full) --- 959system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 960system.realview.ethernet.droppedPackets 0 # number of packets dropped 961system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 962system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 963system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 964system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 965system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 966system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 959system.toL2Bus.trans_dist::ReadReq 633918 # Transaction distribution 960system.toL2Bus.trans_dist::ReadResp 633902 # Transaction distribution 961system.toL2Bus.trans_dist::WriteReq 31177 # Transaction distribution 962system.toL2Bus.trans_dist::WriteResp 31177 # Transaction distribution 963system.toL2Bus.trans_dist::Writeback 240561 # Transaction distribution 964system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 965system.toL2Bus.trans_dist::UpgradeReq 96369 # Transaction distribution 966system.toL2Bus.trans_dist::SCUpgradeReq 41588 # Transaction distribution 967system.toL2Bus.trans_dist::UpgradeResp 137957 # Transaction distribution 968system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 969system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 970system.toL2Bus.trans_dist::ReadExReq 39943 # Transaction distribution 971system.toL2Bus.trans_dist::ReadExResp 39943 # Transaction distribution 972system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1258028 # Packet count per connected master and slave (bytes) 973system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 400059 # Packet count per connected master and slave (bytes) 974system.toL2Bus.pkt_count::total 1658087 # Packet count per connected master and slave (bytes) 975system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37640280 # Cumulative packet size per connected master and slave (bytes) 976system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8288315 # Cumulative packet size per connected master and slave (bytes) 977system.toL2Bus.pkt_size::total 45928595 # Cumulative packet size per connected master and slave (bytes) 978system.toL2Bus.snoops 305065 # Total snoops (count) 979system.toL2Bus.snoop_fanout::samples 1044371 # Request fanout histogram 980system.toL2Bus.snoop_fanout::mean 1.034928 # Request fanout histogram 981system.toL2Bus.snoop_fanout::stdev 0.183598 # Request fanout histogram | 967system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution 968system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution 969system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution 970system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution 971system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution 972system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 973system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution 974system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution 975system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution 976system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution 977system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 978system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution 979system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution 980system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes) 981system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes) 982system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes) 983system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes) 984system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes) 985system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes) 986system.toL2Bus.snoops 304794 # Total snoops (count) 987system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram 988system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram 989system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram |
| 982system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 983system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 990system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 991system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 984system.toL2Bus.snoop_fanout::1 1007893 96.51% 96.51% # Request fanout histogram 985system.toL2Bus.snoop_fanout::2 36478 3.49% 100.00% # Request fanout histogram | 992system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram 993system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram |
| 986system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 987system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 988system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 994system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 995system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 996system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 989system.toL2Bus.snoop_fanout::total 1044371 # Request fanout histogram 990system.toL2Bus.reqLayer0.occupancy 1521180751 # Layer occupancy (ticks) | 997system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram 998system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks) |
| 991system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 992system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 993system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 999system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1000system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 1001system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 994system.toL2Bus.respLayer0.occupancy 2136308825 # Layer occupancy (ticks) | 1002system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks) |
| 995system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1003system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 996system.toL2Bus.respLayer1.occupancy 850635338 # Layer occupancy (ticks) | 1004system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks) |
| 997system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 998system.iobus.trans_dist::ReadReq 31019 # Transaction distribution 999system.iobus.trans_dist::ReadResp 31019 # Transaction distribution | 1005system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1006system.iobus.trans_dist::ReadReq 31019 # Transaction distribution 1007system.iobus.trans_dist::ReadResp 31019 # Transaction distribution |
| 1000system.iobus.trans_dist::WriteReq 59408 # Transaction distribution | 1008system.iobus.trans_dist::WriteReq 59414 # Transaction distribution |
| 1001system.iobus.trans_dist::WriteResp 59440 # Transaction distribution | 1009system.iobus.trans_dist::WriteResp 59440 # Transaction distribution |
| 1002system.iobus.trans_dist::WriteInvalidateReq 32 # Transaction distribution | 1010system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution |
| 1003system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1005system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1007system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1008system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 1009system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1010system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 1085system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1086system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1087system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1088system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1090system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1092system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1011system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1012system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1013system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1014system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1015system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1016system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 1017system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1018system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 1093system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1094system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1096system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1097system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1098system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1099system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1100system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1093system.iobus.reqLayer27.occupancy 326676322 # Layer occupancy (ticks) | 1101system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks) |
| 1094system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1096system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1097system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) 1098system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1102system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1103system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1104system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1105system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) 1106system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1099system.iobus.respLayer3.occupancy 36842591 # Layer occupancy (ticks) | 1107system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks) |
| 1100system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1101system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1102system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1103system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1104system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1105system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1106system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1107system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1116system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1117system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1118system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1119system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1120system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1121system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1122system.cpu0.dtb.inst_hits 0 # ITB inst hits 1123system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1108system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1109system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1110system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1111system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1112system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1113system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1114system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1115system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1124system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1125system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1126system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1127system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1128system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1129system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1130system.cpu0.dtb.inst_hits 0 # ITB inst hits 1131system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1124system.cpu0.dtb.read_hits 24353899 # DTB read hits 1125system.cpu0.dtb.read_misses 6408 # DTB read misses 1126system.cpu0.dtb.write_hits 18126722 # DTB write hits 1127system.cpu0.dtb.write_misses 1115 # DTB write misses | 1132system.cpu0.dtb.read_hits 24351510 # DTB read hits 1133system.cpu0.dtb.read_misses 6410 # DTB read misses 1134system.cpu0.dtb.write_hits 18124813 # DTB write hits 1135system.cpu0.dtb.write_misses 1105 # DTB write misses |
| 1128system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1129system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1130system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1131system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1136system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1137system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1138system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1139system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1132system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB | 1140system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB |
| 1133system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1141system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1134system.cpu0.dtb.prefetch_faults 1442 # Number of TLB faults due to prefetch | 1142system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch |
| 1135system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1136system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 1143system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1144system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 1137system.cpu0.dtb.read_accesses 24360307 # DTB read accesses 1138system.cpu0.dtb.write_accesses 18127837 # DTB write accesses | 1145system.cpu0.dtb.read_accesses 24357920 # DTB read accesses 1146system.cpu0.dtb.write_accesses 18125918 # DTB write accesses |
| 1139system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1147system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1140system.cpu0.dtb.hits 42480621 # DTB hits 1141system.cpu0.dtb.misses 7523 # DTB misses 1142system.cpu0.dtb.accesses 42488144 # DTB accesses | 1148system.cpu0.dtb.hits 42476323 # DTB hits 1149system.cpu0.dtb.misses 7515 # DTB misses 1150system.cpu0.dtb.accesses 42483838 # DTB accesses |
| 1143system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1144system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1145system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1146system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1147system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1148system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1149system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1150system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1156system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1157system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1158system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1159system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1160system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1161system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1162system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1163system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1151system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1152system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1153system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1154system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1155system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1156system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1157system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1158system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1164system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1165system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1166system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1167system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1168system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1169system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1170system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1171system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1164system.cpu0.itb.inst_hits 115074724 # ITB inst hits 1165system.cpu0.itb.inst_misses 3350 # ITB inst misses | 1172system.cpu0.itb.inst_hits 115065468 # ITB inst hits 1173system.cpu0.itb.inst_misses 3349 # ITB inst misses |
| 1166system.cpu0.itb.read_hits 0 # DTB read hits 1167system.cpu0.itb.read_misses 0 # DTB read misses 1168system.cpu0.itb.write_hits 0 # DTB write hits 1169system.cpu0.itb.write_misses 0 # DTB write misses 1170system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1171system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1172system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1173system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 1174system.cpu0.itb.read_hits 0 # DTB read hits 1175system.cpu0.itb.read_misses 0 # DTB read misses 1176system.cpu0.itb.write_hits 0 # DTB write hits 1177system.cpu0.itb.write_misses 0 # DTB write misses 1178system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1179system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1180system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1181system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1174system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB | 1182system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB |
| 1175system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1176system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1177system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1178system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1179system.cpu0.itb.read_accesses 0 # DTB read accesses 1180system.cpu0.itb.write_accesses 0 # DTB write accesses | 1183system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1184system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1185system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1186system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1187system.cpu0.itb.read_accesses 0 # DTB read accesses 1188system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1181system.cpu0.itb.inst_accesses 115078074 # ITB inst accesses 1182system.cpu0.itb.hits 115074724 # DTB hits 1183system.cpu0.itb.misses 3350 # DTB misses 1184system.cpu0.itb.accesses 115078074 # DTB accesses 1185system.cpu0.numCycles 5733858512 # number of cpu cycles simulated | 1189system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses 1190system.cpu0.itb.hits 115065468 # DTB hits 1191system.cpu0.itb.misses 3349 # DTB misses 1192system.cpu0.itb.accesses 115068817 # DTB accesses 1193system.cpu0.numCycles 5733846284 # number of cpu cycles simulated |
| 1186system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1187system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1194system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1195system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1188system.cpu0.committedInsts 111430460 # Number of instructions committed 1189system.cpu0.committedOps 134719109 # Number of ops (including micro ops) committed 1190system.cpu0.num_int_alu_accesses 119427816 # Number of integer alu accesses | 1196system.cpu0.committedInsts 111421342 # Number of instructions committed 1197system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed 1198system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses |
| 1191system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses | 1199system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses |
| 1192system.cpu0.num_func_calls 12527987 # number of times a function call or return occured 1193system.cpu0.num_conditional_control_insts 14980229 # number of instructions that are conditional controls 1194system.cpu0.num_int_insts 119427816 # number of integer instructions | 1200system.cpu0.num_func_calls 12527292 # number of times a function call or return occured 1201system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls 1202system.cpu0.num_int_insts 119417138 # number of integer instructions |
| 1195system.cpu0.num_fp_insts 9755 # number of float instructions | 1203system.cpu0.num_fp_insts 9755 # number of float instructions |
| 1196system.cpu0.num_int_register_reads 220379706 # number of times the integer registers were read 1197system.cpu0.num_int_register_writes 83050844 # number of times the integer registers were written | 1204system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read 1205system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written |
| 1198system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 1199system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 1206system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 1207system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 1200system.cpu0.num_cc_register_reads 488414813 # number of times the CC registers were read 1201system.cpu0.num_cc_register_writes 49991768 # number of times the CC registers were written 1202system.cpu0.num_mem_refs 43590115 # number of memory refs 1203system.cpu0.num_load_insts 24600281 # Number of load instructions 1204system.cpu0.num_store_insts 18989834 # Number of store instructions 1205system.cpu0.num_idle_cycles 5477713409.888090 # Number of idle cycles 1206system.cpu0.num_busy_cycles 256145102.111911 # Number of busy cycles | 1208system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read 1209system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written 1210system.cpu0.num_mem_refs 43585643 # number of memory refs 1211system.cpu0.num_load_insts 24597805 # Number of load instructions 1212system.cpu0.num_store_insts 18987838 # Number of store instructions 1213system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles 1214system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles |
| 1207system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles 1208system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles | 1215system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles 1216system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles |
| 1209system.cpu0.Branches 28216928 # Number of branches fetched | 1217system.cpu0.Branches 28215087 # Number of branches fetched |
| 1210system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction | 1218system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction |
| 1211system.cpu0.op_class::IntAlu 94734127 68.43% 68.43% # Class of executed instruction 1212system.cpu0.op_class::IntMult 104105 0.08% 68.51% # Class of executed instruction | 1219system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction 1220system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction |
| 1213system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction 1214system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction 1215system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction 1216system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction 1217system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction 1218system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction 1219system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction 1220system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 1228system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction 1229system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction 1230system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction 1231system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction 1232system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction 1233system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction 1234system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction 1235system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction | 1221system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction 1222system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction 1223system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction 1224system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction 1225system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction 1226system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction 1227system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction 1228system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 1236system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction 1237system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction 1238system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction 1239system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction 1240system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction 1241system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction 1242system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction 1243system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction |
| 1236system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction | 1244system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction |
| 1237system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction 1238system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction 1239system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction | 1245system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction 1246system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction 1247system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction |
| 1240system.cpu0.op_class::MemRead 24600281 17.77% 86.28% # Class of executed instruction 1241system.cpu0.op_class::MemWrite 18989834 13.72% 100.00% # Class of executed instruction | 1248system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction 1249system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction |
| 1242system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1243system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1250system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1251system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1244system.cpu0.op_class::total 138438000 # Class of executed instruction | 1252system.cpu0.op_class::total 138425707 # Class of executed instruction |
| 1245system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1253system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1246system.cpu0.kern.inst.quiesce 2074 # number of quiesce instructions executed 1247system.cpu0.icache.tags.replacements 1061133 # number of replacements 1248system.cpu0.icache.tags.tagsinuse 511.483144 # Cycle average of tags in use 1249system.cpu0.icache.tags.total_refs 114013070 # Total number of references to valid blocks. 1250system.cpu0.icache.tags.sampled_refs 1061645 # Sample count of references to valid blocks. 1251system.cpu0.icache.tags.avg_refs 107.392838 # Average number of references to valid blocks. 1252system.cpu0.icache.tags.warmup_cycle 12807152500 # Cycle when the warmup percentage was hit. 1253system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483144 # Average occupied blocks per requestor | 1254system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed 1255system.cpu0.icache.tags.replacements 1060721 # number of replacements 1256system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use 1257system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks. 1258system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks. 1259system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks. 1260system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. 1261system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor |
| 1254system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 1255system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy 1256system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1257system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 1258system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id 1259system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id 1260system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1262system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 1263system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy 1264system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1265system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 1266system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id 1267system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id 1268system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1261system.cpu0.icache.tags.tag_accesses 231211102 # Number of tag accesses 1262system.cpu0.icache.tags.data_accesses 231211102 # Number of data accesses 1263system.cpu0.icache.ReadReq_hits::cpu0.inst 114013070 # number of ReadReq hits 1264system.cpu0.icache.ReadReq_hits::total 114013070 # number of ReadReq hits 1265system.cpu0.icache.demand_hits::cpu0.inst 114013070 # number of demand (read+write) hits 1266system.cpu0.icache.demand_hits::total 114013070 # number of demand (read+write) hits 1267system.cpu0.icache.overall_hits::cpu0.inst 114013070 # number of overall hits 1268system.cpu0.icache.overall_hits::total 114013070 # number of overall hits 1269system.cpu0.icache.ReadReq_misses::cpu0.inst 1061654 # number of ReadReq misses 1270system.cpu0.icache.ReadReq_misses::total 1061654 # number of ReadReq misses 1271system.cpu0.icache.demand_misses::cpu0.inst 1061654 # number of demand (read+write) misses 1272system.cpu0.icache.demand_misses::total 1061654 # number of demand (read+write) misses 1273system.cpu0.icache.overall_misses::cpu0.inst 1061654 # number of overall misses 1274system.cpu0.icache.overall_misses::total 1061654 # number of overall misses 1275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000777256 # number of ReadReq miss cycles 1276system.cpu0.icache.ReadReq_miss_latency::total 9000777256 # number of ReadReq miss cycles 1277system.cpu0.icache.demand_miss_latency::cpu0.inst 9000777256 # number of demand (read+write) miss cycles 1278system.cpu0.icache.demand_miss_latency::total 9000777256 # number of demand (read+write) miss cycles 1279system.cpu0.icache.overall_miss_latency::cpu0.inst 9000777256 # number of overall miss cycles 1280system.cpu0.icache.overall_miss_latency::total 9000777256 # number of overall miss cycles 1281system.cpu0.icache.ReadReq_accesses::cpu0.inst 115074724 # number of ReadReq accesses(hits+misses) 1282system.cpu0.icache.ReadReq_accesses::total 115074724 # number of ReadReq accesses(hits+misses) 1283system.cpu0.icache.demand_accesses::cpu0.inst 115074724 # number of demand (read+write) accesses 1284system.cpu0.icache.demand_accesses::total 115074724 # number of demand (read+write) accesses 1285system.cpu0.icache.overall_accesses::cpu0.inst 115074724 # number of overall (read+write) accesses 1286system.cpu0.icache.overall_accesses::total 115074724 # number of overall (read+write) accesses 1287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses 1288system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses 1289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses 1290system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses 1291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses 1292system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses 1293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.070309 # average ReadReq miss latency 1294system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.070309 # average ReadReq miss latency 1295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency 1296system.cpu0.icache.demand_avg_miss_latency::total 8478.070309 # average overall miss latency 1297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency 1298system.cpu0.icache.overall_avg_miss_latency::total 8478.070309 # average overall miss latency | 1269system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses 1270system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses 1271system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits 1272system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits 1273system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits 1274system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits 1275system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits 1276system.cpu0.icache.overall_hits::total 114004226 # number of overall hits 1277system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses 1278system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses 1279system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses 1280system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses 1281system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses 1282system.cpu0.icache.overall_misses::total 1061242 # number of overall misses 1283system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles 1284system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles 1285system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles 1286system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles 1287system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles 1288system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles 1289system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses) 1290system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses) 1291system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses 1292system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses 1293system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses 1294system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses 1295system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses 1296system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses 1297system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses 1298system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses 1299system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses 1300system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses 1301system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency 1302system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency 1303system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency 1304system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency 1305system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency 1306system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency |
| 1299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1305system.cpu0.icache.fast_writes 0 # number of fast writes performed 1306system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1307system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1308system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1309system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1310system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1311system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1312system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1313system.cpu0.icache.fast_writes 0 # number of fast writes performed 1314system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1307system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061654 # number of ReadReq MSHR misses 1308system.cpu0.icache.ReadReq_mshr_misses::total 1061654 # number of ReadReq MSHR misses 1309system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061654 # number of demand (read+write) MSHR misses 1310system.cpu0.icache.demand_mshr_misses::total 1061654 # number of demand (read+write) MSHR misses 1311system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061654 # number of overall MSHR misses 1312system.cpu0.icache.overall_mshr_misses::total 1061654 # number of overall MSHR misses 1313system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407609744 # number of ReadReq MSHR miss cycles 1314system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407609744 # number of ReadReq MSHR miss cycles 1315system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407609744 # number of demand (read+write) MSHR miss cycles 1316system.cpu0.icache.demand_mshr_miss_latency::total 7407609744 # number of demand (read+write) MSHR miss cycles 1317system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407609744 # number of overall MSHR miss cycles 1318system.cpu0.icache.overall_mshr_miss_latency::total 7407609744 # number of overall MSHR miss cycles 1319system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719278000 # number of ReadReq MSHR uncacheable cycles 1320system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719278000 # number of ReadReq MSHR uncacheable cycles 1321system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719278000 # number of overall MSHR uncacheable cycles 1322system.cpu0.icache.overall_mshr_uncacheable_latency::total 719278000 # number of overall MSHR uncacheable cycles 1323system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses 1324system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses 1325system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses 1326system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses 1327system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses 1328system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses 1329system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average ReadReq mshr miss latency 1330system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.423665 # average ReadReq mshr miss latency 1331system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency 1332system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency 1333system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency 1334system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency | 1315system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses 1316system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses 1317system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses 1318system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses 1319system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses 1320system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses 1321system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles 1322system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles 1323system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles 1324system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles 1325system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles 1326system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles 1327system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles 1328system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles 1329system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles 1330system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles 1331system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses 1332system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses 1333system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses 1334system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses 1335system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses 1336system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses 1337system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency 1338system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency 1339system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency 1340system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency 1341system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency 1342system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency |
| 1335system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1336system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1337system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1338system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1339system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1343system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1344system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1345system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1346system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1347system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1340system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923568 # number of hwpf identified 1341system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 227909 # number of hwpf that were already in mshr 1342system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9246862 # number of hwpf that were already in the cache 1343system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 529 # number of hwpf that were already in the prefetch queue | 1348system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified 1349system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr 1350system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache 1351system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue |
| 1344system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1352system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1345system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 49 # number of hwpf removed because MSHR allocated 1346system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 448219 # number of hwpf issued 1347system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778472 # number of hwpf spanning a virtual page | 1353system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated 1354system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued 1355system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page |
| 1348system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1356system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1349system.cpu0.l2cache.tags.replacements 358131 # number of replacements 1350system.cpu0.l2cache.tags.tagsinuse 16113.840521 # Cycle average of tags in use 1351system.cpu0.l2cache.tags.total_refs 1936015 # Total number of references to valid blocks. 1352system.cpu0.l2cache.tags.sampled_refs 374364 # Sample count of references to valid blocks. 1353system.cpu0.l2cache.tags.avg_refs 5.171477 # Average number of references to valid blocks. 1354system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1355system.cpu0.l2cache.tags.occ_blocks::writebacks 6748.405331 # Average occupied blocks per requestor 1356system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.298352 # Average occupied blocks per requestor 1357system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.117074 # Average occupied blocks per requestor 1358system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 799.968206 # Average occupied blocks per requestor 1359system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1087.232896 # Average occupied blocks per requestor 1360system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7475.818663 # Average occupied blocks per requestor 1361system.cpu0.l2cache.tags.occ_percent::writebacks 0.411890 # Average percentage of cache occupancy 1362system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000140 # Average percentage of cache occupancy 1363system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy 1364system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048826 # Average percentage of cache occupancy 1365system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.066359 # Average percentage of cache occupancy 1366system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.456288 # Average percentage of cache occupancy 1367system.cpu0.l2cache.tags.occ_percent::total 0.983511 # Average percentage of cache occupancy 1368system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7939 # Occupied blocks per task id 1369system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 1370system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8291 # Occupied blocks per task id | 1357system.cpu0.l2cache.tags.replacements 355628 # number of replacements 1358system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use 1359system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks. 1360system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks. 1361system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks. 1362system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit. 1363system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor 1364system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor 1365system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor 1366system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor 1367system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor 1368system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor 1369system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy 1370system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy 1371system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 1372system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy 1373system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy 1374system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy 1375system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy 1376system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id 1377system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1378system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id |
| 1371system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id | 1379system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id |
| 1372system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 127 # Occupied blocks per task id 1373system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1966 # Occupied blocks per task id 1374system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4890 # Occupied blocks per task id 1375system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 915 # Occupied blocks per task id 1376system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id | 1380system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id 1381system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id 1382system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id 1383system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id 1384system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id |
| 1377system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 1385system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 1378system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 1379system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id 1380system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2895 # Occupied blocks per task id 1381system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4675 # Occupied blocks per task id 1382system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id 1383system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.484558 # Percentage of cache occupancy per task id 1384system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 1385system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.506042 # Percentage of cache occupancy per task id 1386system.cpu0.l2cache.tags.tag_accesses 38026831 # Number of tag accesses 1387system.cpu0.l2cache.tags.data_accesses 38026831 # Number of data accesses 1388system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 6990 # number of ReadReq hits 1389system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3189 # number of ReadReq hits 1390system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045942 # number of ReadReq hits 1391system.cpu0.l2cache.ReadReq_hits::cpu0.data 372788 # number of ReadReq hits 1392system.cpu0.l2cache.ReadReq_hits::total 1428909 # number of ReadReq hits 1393system.cpu0.l2cache.Writeback_hits::writebacks 483936 # number of Writeback hits 1394system.cpu0.l2cache.Writeback_hits::total 483936 # number of Writeback hits 1395system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10087 # number of UpgradeReq hits 1396system.cpu0.l2cache.UpgradeReq_hits::total 10087 # number of UpgradeReq hits 1397system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2033 # number of SCUpgradeReq hits 1398system.cpu0.l2cache.SCUpgradeReq_hits::total 2033 # number of SCUpgradeReq hits 1399system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212805 # number of ReadExReq hits 1400system.cpu0.l2cache.ReadExReq_hits::total 212805 # number of ReadExReq hits 1401system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 6990 # number of demand (read+write) hits 1402system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3189 # number of demand (read+write) hits 1403system.cpu0.l2cache.demand_hits::cpu0.inst 1045942 # number of demand (read+write) hits 1404system.cpu0.l2cache.demand_hits::cpu0.data 585593 # number of demand (read+write) hits 1405system.cpu0.l2cache.demand_hits::total 1641714 # number of demand (read+write) hits 1406system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 6990 # number of overall hits 1407system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3189 # number of overall hits 1408system.cpu0.l2cache.overall_hits::cpu0.inst 1045942 # number of overall hits 1409system.cpu0.l2cache.overall_hits::cpu0.data 585593 # number of overall hits 1410system.cpu0.l2cache.overall_hits::total 1641714 # number of overall hits 1411system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 263 # number of ReadReq misses 1412system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 219 # number of ReadReq misses 1413system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15712 # number of ReadReq misses 1414system.cpu0.l2cache.ReadReq_misses::cpu0.data 83577 # number of ReadReq misses 1415system.cpu0.l2cache.ReadReq_misses::total 99771 # number of ReadReq misses 1416system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29878 # number of UpgradeReq misses 1417system.cpu0.l2cache.UpgradeReq_misses::total 29878 # number of UpgradeReq misses 1418system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19321 # number of SCUpgradeReq misses 1419system.cpu0.l2cache.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses 1420system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 1421system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1422system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44921 # number of ReadExReq misses 1423system.cpu0.l2cache.ReadExReq_misses::total 44921 # number of ReadExReq misses 1424system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 263 # number of demand (read+write) misses 1425system.cpu0.l2cache.demand_misses::cpu0.itb.walker 219 # number of demand (read+write) misses 1426system.cpu0.l2cache.demand_misses::cpu0.inst 15712 # number of demand (read+write) misses 1427system.cpu0.l2cache.demand_misses::cpu0.data 128498 # number of demand (read+write) misses 1428system.cpu0.l2cache.demand_misses::total 144692 # number of demand (read+write) misses 1429system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 263 # number of overall misses 1430system.cpu0.l2cache.overall_misses::cpu0.itb.walker 219 # number of overall misses 1431system.cpu0.l2cache.overall_misses::cpu0.inst 15712 # number of overall misses 1432system.cpu0.l2cache.overall_misses::cpu0.data 128498 # number of overall misses 1433system.cpu0.l2cache.overall_misses::total 144692 # number of overall misses 1434system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6061000 # number of ReadReq miss cycles 1435system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4899500 # number of ReadReq miss cycles 1436system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598206723 # number of ReadReq miss cycles 1437system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2260687668 # number of ReadReq miss cycles 1438system.cpu0.l2cache.ReadReq_miss_latency::total 2869854891 # number of ReadReq miss cycles 1439system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 524614292 # number of UpgradeReq miss cycles 1440system.cpu0.l2cache.UpgradeReq_miss_latency::total 524614292 # number of UpgradeReq miss cycles 1441system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377658880 # number of SCUpgradeReq miss cycles 1442system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377658880 # number of SCUpgradeReq miss cycles 1443system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1333497 # number of SCUpgradeFailReq miss cycles 1444system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1333497 # number of SCUpgradeFailReq miss cycles 1445system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1506710587 # number of ReadExReq miss cycles 1446system.cpu0.l2cache.ReadExReq_miss_latency::total 1506710587 # number of ReadExReq miss cycles 1447system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6061000 # number of demand (read+write) miss cycles 1448system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4899500 # number of demand (read+write) miss cycles 1449system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598206723 # number of demand (read+write) miss cycles 1450system.cpu0.l2cache.demand_miss_latency::cpu0.data 3767398255 # number of demand (read+write) miss cycles 1451system.cpu0.l2cache.demand_miss_latency::total 4376565478 # number of demand (read+write) miss cycles 1452system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6061000 # number of overall miss cycles 1453system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4899500 # number of overall miss cycles 1454system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598206723 # number of overall miss cycles 1455system.cpu0.l2cache.overall_miss_latency::cpu0.data 3767398255 # number of overall miss cycles 1456system.cpu0.l2cache.overall_miss_latency::total 4376565478 # number of overall miss cycles 1457system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7253 # number of ReadReq accesses(hits+misses) 1458system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3408 # number of ReadReq accesses(hits+misses) 1459system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061654 # number of ReadReq accesses(hits+misses) 1460system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456365 # number of ReadReq accesses(hits+misses) 1461system.cpu0.l2cache.ReadReq_accesses::total 1528680 # number of ReadReq accesses(hits+misses) 1462system.cpu0.l2cache.Writeback_accesses::writebacks 483936 # number of Writeback accesses(hits+misses) 1463system.cpu0.l2cache.Writeback_accesses::total 483936 # number of Writeback accesses(hits+misses) 1464system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39965 # number of UpgradeReq accesses(hits+misses) 1465system.cpu0.l2cache.UpgradeReq_accesses::total 39965 # number of UpgradeReq accesses(hits+misses) 1466system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21354 # number of SCUpgradeReq accesses(hits+misses) 1467system.cpu0.l2cache.SCUpgradeReq_accesses::total 21354 # number of SCUpgradeReq accesses(hits+misses) 1468system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1469system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1470system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257726 # number of ReadExReq accesses(hits+misses) 1471system.cpu0.l2cache.ReadExReq_accesses::total 257726 # number of ReadExReq accesses(hits+misses) 1472system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7253 # number of demand (read+write) accesses 1473system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3408 # number of demand (read+write) accesses 1474system.cpu0.l2cache.demand_accesses::cpu0.inst 1061654 # number of demand (read+write) accesses 1475system.cpu0.l2cache.demand_accesses::cpu0.data 714091 # number of demand (read+write) accesses 1476system.cpu0.l2cache.demand_accesses::total 1786406 # number of demand (read+write) accesses 1477system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7253 # number of overall (read+write) accesses 1478system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3408 # number of overall (read+write) accesses 1479system.cpu0.l2cache.overall_accesses::cpu0.inst 1061654 # number of overall (read+write) accesses 1480system.cpu0.l2cache.overall_accesses::cpu0.data 714091 # number of overall (read+write) accesses 1481system.cpu0.l2cache.overall_accesses::total 1786406 # number of overall (read+write) accesses 1482system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for ReadReq accesses 1483system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064261 # miss rate for ReadReq accesses 1484system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014800 # miss rate for ReadReq accesses 1485system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183136 # miss rate for ReadReq accesses 1486system.cpu0.l2cache.ReadReq_miss_rate::total 0.065266 # miss rate for ReadReq accesses 1487system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.747604 # miss rate for UpgradeReq accesses 1488system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.747604 # miss rate for UpgradeReq accesses 1489system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.904795 # miss rate for SCUpgradeReq accesses 1490system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.904795 # miss rate for SCUpgradeReq accesses | 1386system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 1387system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 1388system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id 1389system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id 1390system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id 1391system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id 1392system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 1393system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id 1394system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses 1395system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses 1396system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits 1397system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits 1398system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits 1399system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits 1400system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits 1401system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits 1402system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits 1403system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits 1404system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits 1405system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits 1406system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits 1407system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits 1408system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits 1409system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits 1410system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits 1411system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits 1412system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits 1413system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits 1414system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits 1415system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits 1416system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits 1417system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits 1418system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits 1419system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses 1420system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses 1421system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses 1422system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses 1423system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses 1424system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses 1425system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses 1426system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses 1427system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses 1428system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses 1429system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 1430system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses 1431system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses 1432system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses 1433system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses 1434system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses 1435system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses 1436system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses 1437system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses 1438system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses 1439system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses 1440system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses 1441system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses 1442system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles 1443system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles 1444system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles 1445system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles 1446system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles 1447system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles 1448system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles 1449system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles 1450system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles 1451system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles 1452system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles 1453system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles 1454system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles 1455system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles 1456system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles 1457system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles 1458system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles 1459system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles 1460system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles 1461system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles 1462system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles 1463system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles 1464system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles 1465system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses) 1466system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses) 1467system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses) 1468system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses) 1469system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses) 1470system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses) 1471system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses) 1472system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses) 1473system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses) 1474system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses) 1475system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses) 1476system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1477system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1478system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses) 1479system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses) 1480system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses 1481system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses 1482system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses 1483system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses 1484system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses 1485system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses 1486system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses 1487system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses 1488system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses 1489system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses 1490system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses 1491system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses 1492system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses 1493system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses 1494system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses 1495system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses 1496system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses 1497system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses 1498system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses |
| 1491system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1492system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1499system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1500system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1493system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174298 # miss rate for ReadExReq accesses 1494system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174298 # miss rate for ReadExReq accesses 1495system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for demand accesses 1496system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064261 # miss rate for demand accesses 1497system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014800 # miss rate for demand accesses 1498system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179946 # miss rate for demand accesses 1499system.cpu0.l2cache.demand_miss_rate::total 0.080996 # miss rate for demand accesses 1500system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for overall accesses 1501system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064261 # miss rate for overall accesses 1502system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014800 # miss rate for overall accesses 1503system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179946 # miss rate for overall accesses 1504system.cpu0.l2cache.overall_miss_rate::total 0.080996 # miss rate for overall accesses 1505system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average ReadReq miss latency 1506system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22372.146119 # average ReadReq miss latency 1507system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38073.238480 # average ReadReq miss latency 1508system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27049.160271 # average ReadReq miss latency 1509system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28764.419430 # average ReadReq miss latency 1510system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17558.547828 # average UpgradeReq miss latency 1511system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828 # average UpgradeReq miss latency 1512system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350 # average SCUpgradeReq miss latency 1513system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.549350 # average SCUpgradeReq miss latency 1514system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190499.571429 # average SCUpgradeFailReq miss latency 1515system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190499.571429 # average SCUpgradeFailReq miss latency 1516system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177 # average ReadExReq miss latency 1517system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33541.341177 # average ReadExReq miss latency 1518system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency 1519system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency 1520system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency 1521system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency 1522system.cpu0.l2cache.demand_avg_miss_latency::total 30247.459970 # average overall miss latency 1523system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency 1524system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency 1525system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency 1526system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency 1527system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970 # average overall miss latency 1528system.cpu0.l2cache.blocked_cycles::no_mshrs 5815 # number of cycles access was blocked | 1501system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses 1502system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses 1503system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses 1504system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses 1505system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses 1506system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses 1507system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses 1508system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses 1509system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses 1510system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses 1511system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses 1512system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses 1513system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency 1514system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency 1515system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency 1516system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency 1517system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency 1518system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency 1519system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency 1520system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency 1521system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency 1522system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency 1523system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency 1524system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency 1525system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency 1526system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency 1527system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency 1528system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency 1529system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency 1530system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency 1531system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency 1532system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency 1533system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency 1534system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency 1535system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency 1536system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked |
| 1529system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1537system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1530system.cpu0.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked | 1538system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked |
| 1531system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1539system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1532system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 76.513158 # average number of cycles each access was blocked | 1540system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked |
| 1533system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1534system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1535system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1541system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1542system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1543system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1536system.cpu0.l2cache.writebacks::writebacks 205462 # number of writebacks 1537system.cpu0.l2cache.writebacks::total 205462 # number of writebacks 1538system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2206 # number of ReadReq MSHR hits 1539system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2737 # number of ReadReq MSHR hits 1540system.cpu0.l2cache.ReadReq_mshr_hits::total 4943 # number of ReadReq MSHR hits 1541system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1219 # number of ReadExReq MSHR hits 1542system.cpu0.l2cache.ReadExReq_mshr_hits::total 1219 # number of ReadExReq MSHR hits 1543system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2206 # number of demand (read+write) MSHR hits 1544system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3956 # number of demand (read+write) MSHR hits 1545system.cpu0.l2cache.demand_mshr_hits::total 6162 # number of demand (read+write) MSHR hits 1546system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2206 # number of overall MSHR hits 1547system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3956 # number of overall MSHR hits 1548system.cpu0.l2cache.overall_mshr_hits::total 6162 # number of overall MSHR hits 1549system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 263 # number of ReadReq MSHR misses 1550system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 219 # number of ReadReq MSHR misses 1551system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13506 # number of ReadReq MSHR misses 1552system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80840 # number of ReadReq MSHR misses 1553system.cpu0.l2cache.ReadReq_mshr_misses::total 94828 # number of ReadReq MSHR misses 1554system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of HardPFReq MSHR misses 1555system.cpu0.l2cache.HardPFReq_mshr_misses::total 448214 # number of HardPFReq MSHR misses 1556system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29878 # number of UpgradeReq MSHR misses 1557system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29878 # number of UpgradeReq MSHR misses 1558system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19321 # number of SCUpgradeReq MSHR misses 1559system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19321 # number of SCUpgradeReq MSHR misses 1560system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1561system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1562system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43702 # number of ReadExReq MSHR misses 1563system.cpu0.l2cache.ReadExReq_mshr_misses::total 43702 # number of ReadExReq MSHR misses 1564system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 263 # number of demand (read+write) MSHR misses 1565system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 219 # number of demand (read+write) MSHR misses 1566system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13506 # number of demand (read+write) MSHR misses 1567system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124542 # number of demand (read+write) MSHR misses 1568system.cpu0.l2cache.demand_mshr_misses::total 138530 # number of demand (read+write) MSHR misses 1569system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 263 # number of overall MSHR misses 1570system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 219 # number of overall MSHR misses 1571system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13506 # number of overall MSHR misses 1572system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124542 # number of overall MSHR misses 1573system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of overall MSHR misses 1574system.cpu0.l2cache.overall_mshr_misses::total 586744 # number of overall MSHR misses 1575system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of ReadReq MSHR miss cycles 1576system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3366500 # number of ReadReq MSHR miss cycles 1577system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457538021 # number of ReadReq MSHR miss cycles 1578system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1656533968 # number of ReadReq MSHR miss cycles 1579system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2121657489 # number of ReadReq MSHR miss cycles 1580system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of HardPFReq MSHR miss cycles 1581system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17785493022 # number of HardPFReq MSHR miss cycles 1582system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 490939499 # number of UpgradeReq MSHR miss cycles 1583system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 490939499 # number of UpgradeReq MSHR miss cycles 1584system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261550596 # number of SCUpgradeReq MSHR miss cycles 1585system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261550596 # number of SCUpgradeReq MSHR miss cycles 1586system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1060497 # number of SCUpgradeFailReq MSHR miss cycles 1587system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1060497 # number of SCUpgradeFailReq MSHR miss cycles 1588system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1074359119 # number of ReadExReq MSHR miss cycles 1589system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1074359119 # number of ReadExReq MSHR miss cycles 1590system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of demand (read+write) MSHR miss cycles 1591system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3366500 # number of demand (read+write) MSHR miss cycles 1592system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457538021 # number of demand (read+write) MSHR miss cycles 1593system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2730893087 # number of demand (read+write) MSHR miss cycles 1594system.cpu0.l2cache.demand_mshr_miss_latency::total 3196016608 # number of demand (read+write) MSHR miss cycles 1595system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of overall MSHR miss cycles 1596system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3366500 # number of overall MSHR miss cycles 1597system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457538021 # number of overall MSHR miss cycles 1598system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2730893087 # number of overall MSHR miss cycles 1599system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of overall MSHR miss cycles 1600system.cpu0.l2cache.overall_mshr_miss_latency::total 20981509630 # number of overall MSHR miss cycles 1601system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647388500 # number of ReadReq MSHR uncacheable cycles 1602system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328873750 # number of ReadReq MSHR uncacheable cycles 1603system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5976262250 # number of ReadReq MSHR uncacheable cycles 1604system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987021005 # number of WriteReq MSHR uncacheable cycles 1605system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987021005 # number of WriteReq MSHR uncacheable cycles 1606system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647388500 # number of overall MSHR uncacheable cycles 1607system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315894755 # number of overall MSHR uncacheable cycles 1608system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9963283255 # number of overall MSHR uncacheable cycles 1609system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for ReadReq accesses 1610system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for ReadReq accesses 1611system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for ReadReq accesses 1612system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177139 # mshr miss rate for ReadReq accesses 1613system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062033 # mshr miss rate for ReadReq accesses | 1544system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks 1545system.cpu0.l2cache.writebacks::total 204753 # number of writebacks 1546system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits 1547system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits 1548system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits 1549system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits 1550system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits 1551system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits 1552system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits 1553system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits 1554system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits 1555system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits 1556system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits 1557system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses 1558system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses 1559system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses 1560system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses 1561system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses 1562system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses 1563system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses 1564system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses 1565system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses 1566system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses 1567system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses 1568system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses 1569system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 1570system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses 1571system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses 1572system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses 1573system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses 1574system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses 1575system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses 1576system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses 1577system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses 1578system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses 1579system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses 1580system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses 1581system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses 1582system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses 1583system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles 1584system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles 1585system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles 1586system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles 1587system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles 1588system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles 1589system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles 1590system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # number of UpgradeReq MSHR miss cycles 1591system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489027550 # number of UpgradeReq MSHR miss cycles 1592system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261183602 # number of SCUpgradeReq MSHR miss cycles 1593system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261183602 # number of SCUpgradeReq MSHR miss cycles 1594system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1027996 # number of SCUpgradeFailReq MSHR miss cycles 1595system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1027996 # number of SCUpgradeFailReq MSHR miss cycles 1596system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080146893 # number of ReadExReq MSHR miss cycles 1597system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080146893 # number of ReadExReq MSHR miss cycles 1598system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of demand (read+write) MSHR miss cycles 1599system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2974500 # number of demand (read+write) MSHR miss cycles 1600system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles 1601system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles 1602system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles 1603system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles 1604system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles 1605system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles 1606system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles 1607system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles 1608system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles 1609system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles 1610system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles 1611system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles 1612system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles 1613system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles 1614system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles 1615system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles 1616system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles 1617system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses 1618system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses 1619system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses 1620system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses 1621system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses |
| 1614system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1615system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1622system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1623system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1616system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.747604 # mshr miss rate for UpgradeReq accesses 1617system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.747604 # mshr miss rate for UpgradeReq accesses 1618system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.904795 # mshr miss rate for SCUpgradeReq accesses 1619system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.904795 # mshr miss rate for SCUpgradeReq accesses | 1624system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses 1625system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses 1626system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses 1627system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses |
| 1620system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1621system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1628system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1629system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1622system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169568 # mshr miss rate for ReadExReq accesses 1623system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169568 # mshr miss rate for ReadExReq accesses 1624system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for demand accesses 1625system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for demand accesses 1626system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for demand accesses 1627system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for demand accesses 1628system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077547 # mshr miss rate for demand accesses 1629system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for overall accesses 1630system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for overall accesses 1631system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for overall accesses 1632system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for overall accesses | 1630system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses 1631system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses 1632system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses 1633system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses 1634system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses 1635system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses 1636system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses 1637system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses 1638system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses 1639system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses 1640system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses |
| 1633system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1641system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1634system.cpu0.l2cache.overall_mshr_miss_rate::total 0.328449 # mshr miss rate for overall accesses 1635system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average ReadReq mshr miss latency 1636system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average ReadReq mshr miss latency 1637system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average ReadReq mshr miss latency 1638system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706 # average ReadReq mshr miss latency 1639system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980 # average ReadReq mshr miss latency 1640system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average HardPFReq mshr miss latency 1641system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539 # average HardPFReq mshr miss latency 1642system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283 # average UpgradeReq mshr miss latency 1643system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283 # average UpgradeReq mshr miss latency 1644system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849 # average SCUpgradeReq mshr miss latency 1645system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849 # average SCUpgradeReq mshr miss latency 1646system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429 # average SCUpgradeFailReq mshr miss latency 1647system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429 # average SCUpgradeFailReq mshr miss latency 1648system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750 # average ReadExReq mshr miss latency 1649system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750 # average ReadExReq mshr miss latency 1650system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency 1651system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency 1652system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency 1653system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency 1654system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873 # average overall mshr miss latency 1655system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency 1656system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency 1657system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency 1658system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency 1659system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average overall mshr miss latency 1660system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154 # average overall mshr miss latency | 1642system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses 1643system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency 1644system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency 1645system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency 1646system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency 1647system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency 1648system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency 1649system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency 1650system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency 1651system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency 1652system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency 1653system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency 1654system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency 1655system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency 1656system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency 1657system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency 1658system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency 1659system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency 1660system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency 1661system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency 1662system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency 1663system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency 1664system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency 1665system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency 1666system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency 1667system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency 1668system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency |
| 1661system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1662system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1663system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1664system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1665system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1666system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1667system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1668system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1669system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1669system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1670system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1671system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1672system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1673system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1674system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1675system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1676system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1677system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1670system.cpu0.dcache.tags.replacements 658799 # number of replacements 1671system.cpu0.dcache.tags.tagsinuse 485.164758 # Cycle average of tags in use 1672system.cpu0.dcache.tags.total_refs 41683742 # Total number of references to valid blocks. 1673system.cpu0.dcache.tags.sampled_refs 659311 # Sample count of references to valid blocks. 1674system.cpu0.dcache.tags.avg_refs 63.223186 # Average number of references to valid blocks. 1675system.cpu0.dcache.tags.warmup_cycle 1016179000 # Cycle when the warmup percentage was hit. 1676system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.164758 # Average occupied blocks per requestor 1677system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947587 # Average percentage of cache occupancy 1678system.cpu0.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy | 1678system.cpu0.dcache.tags.replacements 659666 # number of replacements 1679system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use 1680system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks. 1681system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks. 1682system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks. 1683system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. 1684system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor 1685system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy 1686system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy |
| 1679system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1687system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1680system.cpu0.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 1681system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 1682system.cpu0.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id | 1688system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 1689system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 1690system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id |
| 1683system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1691system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1684system.cpu0.dcache.tags.tag_accesses 85573160 # Number of tag accesses 1685system.cpu0.dcache.tags.data_accesses 85573160 # Number of data accesses 1686system.cpu0.dcache.ReadReq_hits::cpu0.data 23155425 # number of ReadReq hits 1687system.cpu0.dcache.ReadReq_hits::total 23155425 # number of ReadReq hits 1688system.cpu0.dcache.WriteReq_hits::cpu0.data 17431620 # number of WriteReq hits 1689system.cpu0.dcache.WriteReq_hits::total 17431620 # number of WriteReq hits 1690system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323179 # number of SoftPFReq hits 1691system.cpu0.dcache.SoftPFReq_hits::total 323179 # number of SoftPFReq hits 1692system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358328 # number of LoadLockedReq hits 1693system.cpu0.dcache.LoadLockedReq_hits::total 358328 # number of LoadLockedReq hits 1694system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353864 # number of StoreCondReq hits 1695system.cpu0.dcache.StoreCondReq_hits::total 353864 # number of StoreCondReq hits 1696system.cpu0.dcache.demand_hits::cpu0.data 40587045 # number of demand (read+write) hits 1697system.cpu0.dcache.demand_hits::total 40587045 # number of demand (read+write) hits 1698system.cpu0.dcache.overall_hits::cpu0.data 40910224 # number of overall hits 1699system.cpu0.dcache.overall_hits::total 40910224 # number of overall hits 1700system.cpu0.dcache.ReadReq_misses::cpu0.data 360428 # number of ReadReq misses 1701system.cpu0.dcache.ReadReq_misses::total 360428 # number of ReadReq misses 1702system.cpu0.dcache.WriteReq_misses::cpu0.data 297691 # number of WriteReq misses 1703system.cpu0.dcache.WriteReq_misses::total 297691 # number of WriteReq misses 1704system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106192 # number of SoftPFReq misses 1705system.cpu0.dcache.SoftPFReq_misses::total 106192 # number of SoftPFReq misses 1706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21416 # number of LoadLockedReq misses 1707system.cpu0.dcache.LoadLockedReq_misses::total 21416 # number of LoadLockedReq misses 1708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses 1709system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses 1710system.cpu0.dcache.demand_misses::cpu0.data 658119 # number of demand (read+write) misses 1711system.cpu0.dcache.demand_misses::total 658119 # number of demand (read+write) misses 1712system.cpu0.dcache.overall_misses::cpu0.data 764311 # number of overall misses 1713system.cpu0.dcache.overall_misses::total 764311 # number of overall misses 1714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4473033768 # number of ReadReq miss cycles 1715system.cpu0.dcache.ReadReq_miss_latency::total 4473033768 # number of ReadReq miss cycles 1716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4445222415 # number of WriteReq miss cycles 1717system.cpu0.dcache.WriteReq_miss_latency::total 4445222415 # number of WriteReq miss cycles 1718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335592501 # number of LoadLockedReq miss cycles 1719system.cpu0.dcache.LoadLockedReq_miss_latency::total 335592501 # number of LoadLockedReq miss cycles 1720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473344116 # number of StoreCondReq miss cycles 1721system.cpu0.dcache.StoreCondReq_miss_latency::total 473344116 # number of StoreCondReq miss cycles 1722system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1450500 # number of StoreCondFailReq miss cycles 1723system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1450500 # number of StoreCondFailReq miss cycles 1724system.cpu0.dcache.demand_miss_latency::cpu0.data 8918256183 # number of demand (read+write) miss cycles 1725system.cpu0.dcache.demand_miss_latency::total 8918256183 # number of demand (read+write) miss cycles 1726system.cpu0.dcache.overall_miss_latency::cpu0.data 8918256183 # number of overall miss cycles 1727system.cpu0.dcache.overall_miss_latency::total 8918256183 # number of overall miss cycles 1728system.cpu0.dcache.ReadReq_accesses::cpu0.data 23515853 # number of ReadReq accesses(hits+misses) 1729system.cpu0.dcache.ReadReq_accesses::total 23515853 # number of ReadReq accesses(hits+misses) 1730system.cpu0.dcache.WriteReq_accesses::cpu0.data 17729311 # number of WriteReq accesses(hits+misses) 1731system.cpu0.dcache.WriteReq_accesses::total 17729311 # number of WriteReq accesses(hits+misses) 1732system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429371 # number of SoftPFReq accesses(hits+misses) 1733system.cpu0.dcache.SoftPFReq_accesses::total 429371 # number of SoftPFReq accesses(hits+misses) 1734system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379744 # number of LoadLockedReq accesses(hits+misses) 1735system.cpu0.dcache.LoadLockedReq_accesses::total 379744 # number of LoadLockedReq accesses(hits+misses) 1736system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375234 # number of StoreCondReq accesses(hits+misses) 1737system.cpu0.dcache.StoreCondReq_accesses::total 375234 # number of StoreCondReq accesses(hits+misses) 1738system.cpu0.dcache.demand_accesses::cpu0.data 41245164 # number of demand (read+write) accesses 1739system.cpu0.dcache.demand_accesses::total 41245164 # number of demand (read+write) accesses 1740system.cpu0.dcache.overall_accesses::cpu0.data 41674535 # number of overall (read+write) accesses 1741system.cpu0.dcache.overall_accesses::total 41674535 # number of overall (read+write) accesses 1742system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015327 # miss rate for ReadReq accesses 1743system.cpu0.dcache.ReadReq_miss_rate::total 0.015327 # miss rate for ReadReq accesses 1744system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016791 # miss rate for WriteReq accesses 1745system.cpu0.dcache.WriteReq_miss_rate::total 0.016791 # miss rate for WriteReq accesses 1746system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247320 # miss rate for SoftPFReq accesses 1747system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247320 # miss rate for SoftPFReq accesses 1748system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056396 # miss rate for LoadLockedReq accesses 1749system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056396 # miss rate for LoadLockedReq accesses 1750system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses 1751system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses 1752system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015956 # miss rate for demand accesses 1753system.cpu0.dcache.demand_miss_rate::total 0.015956 # miss rate for demand accesses 1754system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018340 # miss rate for overall accesses 1755system.cpu0.dcache.overall_miss_rate::total 0.018340 # miss rate for overall accesses 1756system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286 # average ReadReq miss latency 1757system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286 # average ReadReq miss latency 1758system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273 # average WriteReq miss latency 1759system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273 # average WriteReq miss latency 1760system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550 # average LoadLockedReq miss latency 1761system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550 # average LoadLockedReq miss latency 1762system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236 # average StoreCondReq miss latency 1763system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236 # average StoreCondReq miss latency | 1692system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses 1693system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses 1694system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits 1695system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits 1696system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits 1697system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits 1698system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits 1699system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits 1700system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits 1701system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits 1702system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits 1703system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits 1704system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits 1705system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits 1706system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits 1707system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits 1708system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses 1709system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses 1710system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses 1711system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses 1712system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses 1713system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses 1714system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses 1715system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses 1716system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses 1717system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses 1718system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses 1719system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses 1720system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses 1721system.cpu0.dcache.overall_misses::total 765091 # number of overall misses 1722system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles 1723system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles 1724system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles 1725system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles 1726system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles 1727system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles 1728system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles 1729system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles 1730system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles 1731system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles 1732system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles 1733system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles 1734system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles 1735system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles 1736system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses) 1737system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses) 1738system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses) 1739system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses) 1740system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses) 1741system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses) 1742system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses) 1743system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses) 1744system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses) 1745system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses) 1746system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses 1747system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses 1748system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses 1749system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses 1750system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses 1751system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses 1752system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses 1753system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses 1754system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses 1755system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses 1756system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses 1757system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses 1758system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses 1759system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses 1760system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses 1761system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses 1762system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses 1763system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses 1764system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency 1765system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency 1766system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency 1767system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency 1768system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency 1769system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency 1770system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency 1771system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency |
| 1764system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1765system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1772system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1773system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1766system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089 # average overall miss latency 1767system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089 # average overall miss latency 1768system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370 # average overall miss latency 1769system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370 # average overall miss latency | 1774system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency 1775system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency 1776system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency 1777system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency |
| 1770system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1771system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1772system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1773system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1774system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1775system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1776system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1777system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1778system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1779system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1780system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1781system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1782system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1783system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1784system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1785system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1778system.cpu0.dcache.writebacks::writebacks 483937 # number of writebacks 1779system.cpu0.dcache.writebacks::total 483937 # number of writebacks 1780system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7364 # number of ReadReq MSHR hits 1781system.cpu0.dcache.ReadReq_mshr_hits::total 7364 # number of ReadReq MSHR hits 1782system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15075 # number of LoadLockedReq MSHR hits 1783system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15075 # number of LoadLockedReq MSHR hits 1784system.cpu0.dcache.demand_mshr_hits::cpu0.data 7364 # number of demand (read+write) MSHR hits 1785system.cpu0.dcache.demand_mshr_hits::total 7364 # number of demand (read+write) MSHR hits 1786system.cpu0.dcache.overall_mshr_hits::cpu0.data 7364 # number of overall MSHR hits 1787system.cpu0.dcache.overall_mshr_hits::total 7364 # number of overall MSHR hits 1788system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353064 # number of ReadReq MSHR misses 1789system.cpu0.dcache.ReadReq_mshr_misses::total 353064 # number of ReadReq MSHR misses 1790system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297691 # number of WriteReq MSHR misses 1791system.cpu0.dcache.WriteReq_mshr_misses::total 297691 # number of WriteReq MSHR misses 1792system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96960 # number of SoftPFReq MSHR misses 1793system.cpu0.dcache.SoftPFReq_mshr_misses::total 96960 # number of SoftPFReq MSHR misses 1794system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6341 # number of LoadLockedReq MSHR misses 1795system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6341 # number of LoadLockedReq MSHR misses 1796system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21361 # number of StoreCondReq MSHR misses 1797system.cpu0.dcache.StoreCondReq_mshr_misses::total 21361 # number of StoreCondReq MSHR misses 1798system.cpu0.dcache.demand_mshr_misses::cpu0.data 650755 # number of demand (read+write) MSHR misses 1799system.cpu0.dcache.demand_mshr_misses::total 650755 # number of demand (read+write) MSHR misses 1800system.cpu0.dcache.overall_mshr_misses::cpu0.data 747715 # number of overall MSHR misses 1801system.cpu0.dcache.overall_mshr_misses::total 747715 # number of overall MSHR misses 1802system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3674066732 # number of ReadReq MSHR miss cycles 1803system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3674066732 # number of ReadReq MSHR miss cycles 1804system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3839615585 # number of WriteReq MSHR miss cycles 1805system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3839615585 # number of WriteReq MSHR miss cycles 1806system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1190903244 # number of SoftPFReq MSHR miss cycles 1807system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1190903244 # number of SoftPFReq MSHR miss cycles 1808system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89864249 # number of LoadLockedReq MSHR miss cycles 1809system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89864249 # number of LoadLockedReq MSHR miss cycles 1810system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429815884 # number of StoreCondReq MSHR miss cycles 1811system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429815884 # number of StoreCondReq MSHR miss cycles 1812system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1372500 # number of StoreCondFailReq MSHR miss cycles 1813system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1372500 # number of StoreCondFailReq MSHR miss cycles 1814system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7513682317 # number of demand (read+write) MSHR miss cycles 1815system.cpu0.dcache.demand_mshr_miss_latency::total 7513682317 # number of demand (read+write) MSHR miss cycles 1816system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8704585561 # number of overall MSHR miss cycles 1817system.cpu0.dcache.overall_mshr_miss_latency::total 8704585561 # number of overall MSHR miss cycles 1818system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564939750 # number of ReadReq MSHR uncacheable cycles 1819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564939750 # number of ReadReq MSHR uncacheable cycles 1820system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183945995 # number of WriteReq MSHR uncacheable cycles 1821system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183945995 # number of WriteReq MSHR uncacheable cycles 1822system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748885745 # number of overall MSHR uncacheable cycles 1823system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748885745 # number of overall MSHR uncacheable cycles 1824system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015014 # mshr miss rate for ReadReq accesses 1825system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015014 # mshr miss rate for ReadReq accesses 1826system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016791 # mshr miss rate for WriteReq accesses 1827system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016791 # mshr miss rate for WriteReq accesses 1828system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225819 # mshr miss rate for SoftPFReq accesses 1829system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225819 # mshr miss rate for SoftPFReq accesses 1830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016698 # mshr miss rate for LoadLockedReq accesses 1831system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016698 # mshr miss rate for LoadLockedReq accesses 1832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056927 # mshr miss rate for StoreCondReq accesses 1833system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056927 # mshr miss rate for StoreCondReq accesses 1834system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015778 # mshr miss rate for demand accesses 1835system.cpu0.dcache.demand_mshr_miss_rate::total 0.015778 # mshr miss rate for demand accesses 1836system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017942 # mshr miss rate for overall accesses 1837system.cpu0.dcache.overall_mshr_miss_rate::total 0.017942 # mshr miss rate for overall accesses 1838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371 # average ReadReq mshr miss latency 1839system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371 # average ReadReq mshr miss latency 1840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148 # average WriteReq mshr miss latency 1841system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148 # average WriteReq mshr miss latency 1842system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946 # average SoftPFReq mshr miss latency 1843system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946 # average SoftPFReq mshr miss latency 1844system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445 # average LoadLockedReq mshr miss latency 1845system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445 # average LoadLockedReq mshr miss latency 1846system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460 # average StoreCondReq mshr miss latency 1847system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460 # average StoreCondReq mshr miss latency | 1786system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks 1787system.cpu0.dcache.writebacks::total 484431 # number of writebacks 1788system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits 1789system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits 1790system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits 1791system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits 1792system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits 1793system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits 1794system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits 1795system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits 1796system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses 1797system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses 1798system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses 1799system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses 1800system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses 1801system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses 1802system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses 1803system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses 1804system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses 1805system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses 1806system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses 1807system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses 1808system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses 1809system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses 1810system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles 1811system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles 1812system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles 1813system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles 1814system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles 1815system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles 1816system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles 1817system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles 1818system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles 1819system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles 1820system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles 1821system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles 1822system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles 1823system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles 1824system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles 1825system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles 1826system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles 1827system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles 1828system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles 1829system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles 1830system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles 1831system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles 1832system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses 1833system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses 1834system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses 1835system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses 1836system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses 1837system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses 1838system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses 1839system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses 1840system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses 1841system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses 1842system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses 1843system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses 1844system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses 1845system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses 1846system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency 1847system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency 1848system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency 1849system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency 1850system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency 1851system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency 1852system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency 1853system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency 1854system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency 1855system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency |
| 1848system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1849system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1856system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1857system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1850system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018 # average overall mshr miss latency 1851system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018 # average overall mshr miss latency 1852system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101 # average overall mshr miss latency 1853system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101 # average overall mshr miss latency | 1858system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency 1859system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency 1860system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency 1861system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency |
| 1854system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1855system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1856system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1857system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1858system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1859system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1860system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1862system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1863system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1864system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1865system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1866system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1867system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1868system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1861system.cpu0.toL2Bus.trans_dist::ReadReq 1734717 # Transaction distribution 1862system.cpu0.toL2Bus.trans_dist::ReadResp 1628862 # Transaction distribution 1863system.cpu0.toL2Bus.trans_dist::WriteReq 26256 # Transaction distribution 1864system.cpu0.toL2Bus.trans_dist::WriteResp 26256 # Transaction distribution 1865system.cpu0.toL2Bus.trans_dist::Writeback 483936 # Transaction distribution 1866system.cpu0.toL2Bus.trans_dist::HardPFReq 598763 # Transaction distribution 1867system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1868system.cpu0.toL2Bus.trans_dist::UpgradeReq 81012 # Transaction distribution 1869system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43653 # Transaction distribution 1870system.cpu0.toL2Bus.trans_dist::UpgradeResp 101651 # Transaction distribution 1871system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 1872system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 1873system.cpu0.toL2Bus.trans_dist::ReadExReq 279403 # Transaction distribution 1874system.cpu0.toL2Bus.trans_dist::ReadExResp 269117 # Transaction distribution 1875system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141354 # Packet count per connected master and slave (bytes) 1876system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2250253 # Packet count per connected master and slave (bytes) 1877system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9809 # Packet count per connected master and slave (bytes) 1878system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 20976 # Packet count per connected master and slave (bytes) 1879system.cpu0.toL2Bus.pkt_count::total 4422392 # Packet count per connected master and slave (bytes) 1880system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981948 # Cumulative packet size per connected master and slave (bytes) 1881system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80932636 # Cumulative packet size per connected master and slave (bytes) 1882system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13632 # Cumulative packet size per connected master and slave (bytes) 1883system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29012 # Cumulative packet size per connected master and slave (bytes) 1884system.cpu0.toL2Bus.pkt_size::total 148957228 # Cumulative packet size per connected master and slave (bytes) 1885system.cpu0.toL2Bus.snoops 991588 # Total snoops (count) 1886system.cpu0.toL2Bus.snoop_fanout::samples 3219253 # Request fanout histogram 1887system.cpu0.toL2Bus.snoop_fanout::mean 5.272771 # Request fanout histogram 1888system.cpu0.toL2Bus.snoop_fanout::stdev 0.445384 # Request fanout histogram | 1869system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution 1870system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution 1871system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution 1872system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution 1873system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution 1874system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution 1875system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 1876system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution 1877system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution 1878system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution 1879system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 1880system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 1881system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution 1882system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution 1883system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes) 1884system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes) 1885system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes) 1886system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes) 1887system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes) 1888system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes) 1889system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes) 1890system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes) 1891system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes) 1892system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes) 1893system.cpu0.toL2Bus.snoops 985271 # Total snoops (count) 1894system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram 1895system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram 1896system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram |
| 1889system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1890system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1891system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1892system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1893system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1894system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1897system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1898system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1899system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1900system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1901system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1902system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1895system.cpu0.toL2Bus.snoop_fanout::5 2341135 72.72% 72.72% # Request fanout histogram 1896system.cpu0.toL2Bus.snoop_fanout::6 878118 27.28% 100.00% # Request fanout histogram | 1903system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram 1904system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram |
| 1897system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1898system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1899system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1905system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1906system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1907system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1900system.cpu0.toL2Bus.snoop_fanout::total 3219253 # Request fanout histogram 1901system.cpu0.toL2Bus.reqLayer0.occupancy 1700320883 # Layer occupancy (ticks) | 1908system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram 1909system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks) |
| 1902system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1910system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1903system.cpu0.toL2Bus.snoopLayer0.occupancy 115643997 # Layer occupancy (ticks) | 1911system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks) |
| 1904system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1912system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1905system.cpu0.toL2Bus.respLayer0.occupancy 1603955756 # Layer occupancy (ticks) | 1913system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks) |
| 1906system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1914system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1907system.cpu0.toL2Bus.respLayer1.occupancy 1150860061 # Layer occupancy (ticks) | 1915system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks) |
| 1908system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1916system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1909system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) | 1917system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) |
| 1910system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1918system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1911system.cpu0.toL2Bus.respLayer3.occupancy 13723500 # Layer occupancy (ticks) | 1919system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks) |
| 1912system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1913system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1914system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1915system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1916system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1917system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1918system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1919system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1928system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1929system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1930system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1931system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1932system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1933system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1934system.cpu1.dtb.inst_hits 0 # ITB inst hits 1935system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1920system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1921system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1922system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1923system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1924system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1925system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1926system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1927system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1936system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1937system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1938system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1939system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1940system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1941system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1942system.cpu1.dtb.inst_hits 0 # ITB inst hits 1943system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1936system.cpu1.dtb.read_hits 4827395 # DTB read hits 1937system.cpu1.dtb.read_misses 2744 # DTB read misses 1938system.cpu1.dtb.write_hits 4131070 # DTB write hits 1939system.cpu1.dtb.write_misses 524 # DTB write misses | 1944system.cpu1.dtb.read_hits 4826536 # DTB read hits 1945system.cpu1.dtb.read_misses 2746 # DTB read misses 1946system.cpu1.dtb.write_hits 4130096 # DTB write hits 1947system.cpu1.dtb.write_misses 525 # DTB write misses |
| 1940system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1941system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1942system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1943system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1944system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB 1945system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1948system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1949system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1950system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1951system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1952system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB 1953system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1946system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch | 1954system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch |
| 1947system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1948system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions | 1955system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1956system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions |
| 1949system.cpu1.dtb.read_accesses 4830139 # DTB read accesses 1950system.cpu1.dtb.write_accesses 4131594 # DTB write accesses | 1957system.cpu1.dtb.read_accesses 4829282 # DTB read accesses 1958system.cpu1.dtb.write_accesses 4130621 # DTB write accesses |
| 1951system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1959system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1952system.cpu1.dtb.hits 8958465 # DTB hits 1953system.cpu1.dtb.misses 3268 # DTB misses 1954system.cpu1.dtb.accesses 8961733 # DTB accesses | 1960system.cpu1.dtb.hits 8956632 # DTB hits 1961system.cpu1.dtb.misses 3271 # DTB misses 1962system.cpu1.dtb.accesses 8959903 # DTB accesses |
| 1955system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1956system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1957system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1958system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1959system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1960system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1961system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1962system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1968system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1969system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1970system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1971system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1972system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1973system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1974system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1975system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1963system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1964system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1965system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1966system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1967system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1968system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1969system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1970system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1976system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1977system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1978system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1979system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1980system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1981system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1982system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1983system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1976system.cpu1.itb.inst_hits 20889672 # ITB inst hits | 1984system.cpu1.itb.inst_hits 20887785 # ITB inst hits |
| 1977system.cpu1.itb.inst_misses 1747 # ITB inst misses 1978system.cpu1.itb.read_hits 0 # DTB read hits 1979system.cpu1.itb.read_misses 0 # DTB read misses 1980system.cpu1.itb.write_hits 0 # DTB write hits 1981system.cpu1.itb.write_misses 0 # DTB write misses 1982system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1983system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1984system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1985system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1986system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB 1987system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1988system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1989system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1990system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1991system.cpu1.itb.read_accesses 0 # DTB read accesses 1992system.cpu1.itb.write_accesses 0 # DTB write accesses | 1985system.cpu1.itb.inst_misses 1747 # ITB inst misses 1986system.cpu1.itb.read_hits 0 # DTB read hits 1987system.cpu1.itb.read_misses 0 # DTB read misses 1988system.cpu1.itb.write_hits 0 # DTB write hits 1989system.cpu1.itb.write_misses 0 # DTB write misses 1990system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1991system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1992system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1993system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1994system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB 1995system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1996system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1997system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1998system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1999system.cpu1.itb.read_accesses 0 # DTB read accesses 2000system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1993system.cpu1.itb.inst_accesses 20891419 # ITB inst accesses 1994system.cpu1.itb.hits 20889672 # DTB hits | 2001system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses 2002system.cpu1.itb.hits 20887785 # DTB hits |
| 1995system.cpu1.itb.misses 1747 # DTB misses | 2003system.cpu1.itb.misses 1747 # DTB misses |
| 1996system.cpu1.itb.accesses 20891419 # DTB accesses 1997system.cpu1.numCycles 5732950771 # number of cpu cycles simulated | 2004system.cpu1.itb.accesses 20889532 # DTB accesses 2005system.cpu1.numCycles 5732937622 # number of cpu cycles simulated |
| 1998system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1999system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 2006system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 2007system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 2000system.cpu1.committedInsts 20508829 # Number of instructions committed 2001system.cpu1.committedOps 24874782 # Number of ops (including micro ops) committed 2002system.cpu1.num_int_alu_accesses 22190598 # Number of integer alu accesses | 2008system.cpu1.committedInsts 20506953 # Number of instructions committed 2009system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed 2010system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses |
| 2003system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses | 2011system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses |
| 2004system.cpu1.num_func_calls 1209607 # number of times a function call or return occured 2005system.cpu1.num_conditional_control_insts 2572400 # number of instructions that are conditional controls 2006system.cpu1.num_int_insts 22190598 # number of integer instructions | 2012system.cpu1.num_func_calls 1209546 # number of times a function call or return occured 2013system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls 2014system.cpu1.num_int_insts 22187475 # number of integer instructions |
| 2007system.cpu1.num_fp_insts 1792 # number of float instructions | 2015system.cpu1.num_fp_insts 1792 # number of float instructions |
| 2008system.cpu1.num_int_register_reads 39855869 # number of times the integer registers were read 2009system.cpu1.num_int_register_writes 15449003 # number of times the integer registers were written | 2016system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read 2017system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written |
| 2010system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 2011system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written | 2018system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 2019system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written |
| 2012system.cpu1.num_cc_register_reads 90462747 # number of times the CC registers were read 2013system.cpu1.num_cc_register_writes 8862782 # number of times the CC registers were written 2014system.cpu1.num_mem_refs 9247846 # number of memory refs 2015system.cpu1.num_load_insts 4946569 # Number of load instructions 2016system.cpu1.num_store_insts 4301277 # Number of store instructions 2017system.cpu1.num_idle_cycles 5671538888.273010 # Number of idle cycles 2018system.cpu1.num_busy_cycles 61411882.726990 # Number of busy cycles 2019system.cpu1.not_idle_fraction 0.010712 # Percentage of non-idle cycles 2020system.cpu1.idle_fraction 0.989288 # Percentage of idle cycles 2021system.cpu1.Branches 3892747 # Number of branches fetched | 2020system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read 2021system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written 2022system.cpu1.num_mem_refs 9246104 # number of memory refs 2023system.cpu1.num_load_insts 4945808 # Number of load instructions 2024system.cpu1.num_store_insts 4300296 # Number of store instructions 2025system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles 2026system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles 2027system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles 2028system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles 2029system.cpu1.Branches 3892449 # Number of branches fetched |
| 2022system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction | 2030system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction |
| 2023system.cpu1.op_class::IntAlu 16017837 63.30% 63.30% # Class of executed instruction 2024system.cpu1.op_class::IntMult 33571 0.13% 63.44% # Class of executed instruction | 2031system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction 2032system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction |
| 2025system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction 2026system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction 2027system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction 2028system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction 2029system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction 2030system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction 2031system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction 2032system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 2040system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction 2041system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction 2042system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction 2043system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction 2044system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction 2045system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction 2046system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction 2047system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction | 2033system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction 2034system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction 2035system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction 2036system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction 2037system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction 2038system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction 2039system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction 2040system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 2048system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction 2049system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction 2050system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction 2051system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction 2052system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction 2053system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction 2054system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction 2055system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction |
| 2048system.cpu1.op_class::SimdFloatMisc 4039 0.02% 63.45% # Class of executed instruction | 2056system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction |
| 2049system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction 2050system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction 2051system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction | 2057system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction 2058system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction 2059system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction |
| 2052system.cpu1.op_class::MemRead 4946569 19.55% 83.00% # Class of executed instruction 2053system.cpu1.op_class::MemWrite 4301277 17.00% 100.00% # Class of executed instruction | 2060system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction 2061system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction |
| 2054system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2055system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 2062system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2063system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 2056system.cpu1.op_class::total 25303360 # Class of executed instruction | 2064system.cpu1.op_class::total 25300005 # Class of executed instruction |
| 2057system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 2065system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2058system.cpu1.kern.inst.quiesce 2751 # number of quiesce instructions executed 2059system.cpu1.icache.tags.replacements 565233 # number of replacements 2060system.cpu1.icache.tags.tagsinuse 498.685358 # Cycle average of tags in use 2061system.cpu1.icache.tags.total_refs 20323921 # Total number of references to valid blocks. 2062system.cpu1.icache.tags.sampled_refs 565745 # Sample count of references to valid blocks. 2063system.cpu1.icache.tags.avg_refs 35.924173 # Average number of references to valid blocks. 2064system.cpu1.icache.tags.warmup_cycle 115078716000 # Cycle when the warmup percentage was hit. 2065system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.685358 # Average occupied blocks per requestor 2066system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973995 # Average percentage of cache occupancy 2067system.cpu1.icache.tags.occ_percent::total 0.973995 # Average percentage of cache occupancy | 2066system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed 2067system.cpu1.icache.tags.replacements 565422 # number of replacements 2068system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use 2069system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks. 2070system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks. 2071system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks. 2072system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit. 2073system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor 2074system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy 2075system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy |
| 2068system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2076system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2069system.cpu1.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id 2070system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id | 2077system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id 2078system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id |
| 2071system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 2072system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2079system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 2080system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2073system.cpu1.icache.tags.tag_accesses 42345080 # Number of tag accesses 2074system.cpu1.icache.tags.data_accesses 42345080 # Number of data accesses 2075system.cpu1.icache.ReadReq_hits::cpu1.inst 20323921 # number of ReadReq hits 2076system.cpu1.icache.ReadReq_hits::total 20323921 # number of ReadReq hits 2077system.cpu1.icache.demand_hits::cpu1.inst 20323921 # number of demand (read+write) hits 2078system.cpu1.icache.demand_hits::total 20323921 # number of demand (read+write) hits 2079system.cpu1.icache.overall_hits::cpu1.inst 20323921 # number of overall hits 2080system.cpu1.icache.overall_hits::total 20323921 # number of overall hits 2081system.cpu1.icache.ReadReq_misses::cpu1.inst 565746 # number of ReadReq misses 2082system.cpu1.icache.ReadReq_misses::total 565746 # number of ReadReq misses 2083system.cpu1.icache.demand_misses::cpu1.inst 565746 # number of demand (read+write) misses 2084system.cpu1.icache.demand_misses::total 565746 # number of demand (read+write) misses 2085system.cpu1.icache.overall_misses::cpu1.inst 565746 # number of overall misses 2086system.cpu1.icache.overall_misses::total 565746 # number of overall misses 2087system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4684636281 # number of ReadReq miss cycles 2088system.cpu1.icache.ReadReq_miss_latency::total 4684636281 # number of ReadReq miss cycles 2089system.cpu1.icache.demand_miss_latency::cpu1.inst 4684636281 # number of demand (read+write) miss cycles 2090system.cpu1.icache.demand_miss_latency::total 4684636281 # number of demand (read+write) miss cycles 2091system.cpu1.icache.overall_miss_latency::cpu1.inst 4684636281 # number of overall miss cycles 2092system.cpu1.icache.overall_miss_latency::total 4684636281 # number of overall miss cycles 2093system.cpu1.icache.ReadReq_accesses::cpu1.inst 20889667 # number of ReadReq accesses(hits+misses) 2094system.cpu1.icache.ReadReq_accesses::total 20889667 # number of ReadReq accesses(hits+misses) 2095system.cpu1.icache.demand_accesses::cpu1.inst 20889667 # number of demand (read+write) accesses 2096system.cpu1.icache.demand_accesses::total 20889667 # number of demand (read+write) accesses 2097system.cpu1.icache.overall_accesses::cpu1.inst 20889667 # number of overall (read+write) accesses 2098system.cpu1.icache.overall_accesses::total 20889667 # number of overall (read+write) accesses 2099system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027083 # miss rate for ReadReq accesses 2100system.cpu1.icache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses 2101system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027083 # miss rate for demand accesses 2102system.cpu1.icache.demand_miss_rate::total 0.027083 # miss rate for demand accesses 2103system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027083 # miss rate for overall accesses 2104system.cpu1.icache.overall_miss_rate::total 0.027083 # miss rate for overall accesses 2105system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8280.458511 # average ReadReq miss latency 2106system.cpu1.icache.ReadReq_avg_miss_latency::total 8280.458511 # average ReadReq miss latency 2107system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency 2108system.cpu1.icache.demand_avg_miss_latency::total 8280.458511 # average overall miss latency 2109system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency 2110system.cpu1.icache.overall_avg_miss_latency::total 8280.458511 # average overall miss latency | 2081system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses 2082system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses 2083system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits 2084system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits 2085system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits 2086system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits 2087system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits 2088system.cpu1.icache.overall_hits::total 20321845 # number of overall hits 2089system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses 2090system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses 2091system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses 2092system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses 2093system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses 2094system.cpu1.icache.overall_misses::total 565935 # number of overall misses 2095system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles 2096system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles 2097system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles 2098system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles 2099system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles 2100system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles 2101system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses) 2102system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses) 2103system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses 2104system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses 2105system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses 2106system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses 2107system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses 2108system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses 2109system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses 2110system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses 2111system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses 2112system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses 2113system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency 2114system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency 2115system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency 2116system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency 2117system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency 2118system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency |
| 2111system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2112system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2113system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2114system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2115system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2116system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2117system.cpu1.icache.fast_writes 0 # number of fast writes performed 2118system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2119system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2120system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2121system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2122system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2123system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2124system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2125system.cpu1.icache.fast_writes 0 # number of fast writes performed 2126system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2119system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565746 # number of ReadReq MSHR misses 2120system.cpu1.icache.ReadReq_mshr_misses::total 565746 # number of ReadReq MSHR misses 2121system.cpu1.icache.demand_mshr_misses::cpu1.inst 565746 # number of demand (read+write) MSHR misses 2122system.cpu1.icache.demand_mshr_misses::total 565746 # number of demand (read+write) MSHR misses 2123system.cpu1.icache.overall_mshr_misses::cpu1.inst 565746 # number of overall MSHR misses 2124system.cpu1.icache.overall_mshr_misses::total 565746 # number of overall MSHR misses 2125system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835844219 # number of ReadReq MSHR miss cycles 2126system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835844219 # number of ReadReq MSHR miss cycles 2127system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835844219 # number of demand (read+write) MSHR miss cycles 2128system.cpu1.icache.demand_mshr_miss_latency::total 3835844219 # number of demand (read+write) MSHR miss cycles 2129system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835844219 # number of overall MSHR miss cycles 2130system.cpu1.icache.overall_mshr_miss_latency::total 3835844219 # number of overall MSHR miss cycles 2131system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14025750 # number of ReadReq MSHR uncacheable cycles 2132system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14025750 # number of ReadReq MSHR uncacheable cycles 2133system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14025750 # number of overall MSHR uncacheable cycles 2134system.cpu1.icache.overall_mshr_uncacheable_latency::total 14025750 # number of overall MSHR uncacheable cycles 2135system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for ReadReq accesses 2136system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027083 # mshr miss rate for ReadReq accesses 2137system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for demand accesses 2138system.cpu1.icache.demand_mshr_miss_rate::total 0.027083 # mshr miss rate for demand accesses 2139system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for overall accesses 2140system.cpu1.icache.overall_mshr_miss_rate::total 0.027083 # mshr miss rate for overall accesses 2141system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average ReadReq mshr miss latency 2142system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6780.152611 # average ReadReq mshr miss latency 2143system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency 2144system.cpu1.icache.demand_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency 2145system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency 2146system.cpu1.icache.overall_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency | 2127system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses 2128system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses 2129system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses 2130system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses 2131system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses 2132system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses 2133system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles 2134system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles 2135system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles 2136system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles 2137system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles 2138system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles 2139system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles 2140system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles 2141system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles 2142system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles 2143system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses 2144system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses 2145system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses 2146system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses 2147system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses 2148system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses 2149system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency 2150system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency 2151system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency 2152system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency 2153system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency 2154system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency |
| 2147system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2148system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2149system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2150system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2151system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2155system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2156system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2157system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2158system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2159system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2152system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4613211 # number of hwpf identified 2153system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23452 # number of hwpf that were already in mshr 2154system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471751 # number of hwpf that were already in the cache 2155system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 253 # number of hwpf that were already in the prefetch queue | 2160system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified 2161system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr 2162system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache 2163system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue |
| 2156system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 2164system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 2157system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 21 # number of hwpf removed because MSHR allocated 2158system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 117734 # number of hwpf issued 2159system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522133 # number of hwpf spanning a virtual page | 2165system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated 2166system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued 2167system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page |
| 2160system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 2168system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 2161system.cpu1.l2cache.tags.replacements 85099 # number of replacements 2162system.cpu1.l2cache.tags.tagsinuse 15602.150946 # Cycle average of tags in use 2163system.cpu1.l2cache.tags.total_refs 830949 # Total number of references to valid blocks. 2164system.cpu1.l2cache.tags.sampled_refs 100297 # Sample count of references to valid blocks. 2165system.cpu1.l2cache.tags.avg_refs 8.284884 # Average number of references to valid blocks. 2166system.cpu1.l2cache.tags.warmup_cycle 2855978416500 # Cycle when the warmup percentage was hit. 2167system.cpu1.l2cache.tags.occ_blocks::writebacks 4730.109881 # Average occupied blocks per requestor 2168system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.755019 # Average occupied blocks per requestor 2169system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.314200 # Average occupied blocks per requestor 2170system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 871.040386 # Average occupied blocks per requestor 2171system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1529.848587 # Average occupied blocks per requestor 2172system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8465.082873 # Average occupied blocks per requestor 2173system.cpu1.l2cache.tags.occ_percent::writebacks 0.288703 # Average percentage of cache occupancy 2174system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000351 # Average percentage of cache occupancy 2175system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000019 # Average percentage of cache occupancy 2176system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053164 # Average percentage of cache occupancy 2177system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.093375 # Average percentage of cache occupancy 2178system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.516668 # Average percentage of cache occupancy 2179system.cpu1.l2cache.tags.occ_percent::total 0.952280 # Average percentage of cache occupancy 2180system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9308 # Occupied blocks per task id 2181system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 2182system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5882 # Occupied blocks per task id 2183system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id 2184system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1130 # Occupied blocks per task id 2185system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8114 # Occupied blocks per task id | 2169system.cpu1.l2cache.tags.replacements 85170 # number of replacements 2170system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use 2171system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks. 2172system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks. 2173system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks. 2174system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2175system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor 2176system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor 2177system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor 2178system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor 2179system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor 2180system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor 2181system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy 2182system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy 2183system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy 2184system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy 2185system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy 2186system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy 2187system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy 2188system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id 2189system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id 2190system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id 2191system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id 2192system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id 2193system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id |
| 2186system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id | 2194system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id |
| 2187system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 2188system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id 2189system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1134 # Occupied blocks per task id 2190system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4474 # Occupied blocks per task id 2191system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.568115 # Percentage of cache occupancy per task id 2192system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 2193system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359009 # Percentage of cache occupancy per task id 2194system.cpu1.l2cache.tags.tag_accesses 16690228 # Number of tag accesses 2195system.cpu1.l2cache.tags.data_accesses 16690228 # Number of data accesses 2196system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3013 # number of ReadReq hits 2197system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1699 # number of ReadReq hits 2198system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560147 # number of ReadReq hits 2199system.cpu1.l2cache.ReadReq_hits::cpu1.data 123235 # number of ReadReq hits 2200system.cpu1.l2cache.ReadReq_hits::total 688094 # number of ReadReq hits 2201system.cpu1.l2cache.Writeback_hits::writebacks 134926 # number of Writeback hits 2202system.cpu1.l2cache.Writeback_hits::total 134926 # number of Writeback hits 2203system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1530 # number of UpgradeReq hits 2204system.cpu1.l2cache.UpgradeReq_hits::total 1530 # number of UpgradeReq hits 2205system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 889 # number of SCUpgradeReq hits 2206system.cpu1.l2cache.SCUpgradeReq_hits::total 889 # number of SCUpgradeReq hits 2207system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39290 # number of ReadExReq hits 2208system.cpu1.l2cache.ReadExReq_hits::total 39290 # number of ReadExReq hits 2209system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3013 # number of demand (read+write) hits 2210system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1699 # number of demand (read+write) hits 2211system.cpu1.l2cache.demand_hits::cpu1.inst 560147 # number of demand (read+write) hits 2212system.cpu1.l2cache.demand_hits::cpu1.data 162525 # number of demand (read+write) hits 2213system.cpu1.l2cache.demand_hits::total 727384 # number of demand (read+write) hits 2214system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3013 # number of overall hits 2215system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1699 # number of overall hits 2216system.cpu1.l2cache.overall_hits::cpu1.inst 560147 # number of overall hits 2217system.cpu1.l2cache.overall_hits::cpu1.data 162525 # number of overall hits 2218system.cpu1.l2cache.overall_hits::total 727384 # number of overall hits 2219system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 347 # number of ReadReq misses | 2195system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 2196system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 2197system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id 2198system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id 2199system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id 2200system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 2201system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id 2202system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses 2203system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses 2204system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits 2205system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits 2206system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits 2207system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits 2208system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits 2209system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits 2210system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits 2211system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits 2212system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits 2213system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits 2214system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits 2215system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits 2216system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits 2217system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits 2218system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits 2219system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits 2220system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits 2221system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits 2222system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits 2223system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits 2224system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits 2225system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits 2226system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits 2227system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses |
| 2220system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses | 2228system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses |
| 2221system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5599 # number of ReadReq misses 2222system.cpu1.l2cache.ReadReq_misses::cpu1.data 70297 # number of ReadReq misses 2223system.cpu1.l2cache.ReadReq_misses::total 76525 # number of ReadReq misses 2224system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29432 # number of UpgradeReq misses 2225system.cpu1.l2cache.UpgradeReq_misses::total 29432 # number of UpgradeReq misses 2226system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22334 # number of SCUpgradeReq misses 2227system.cpu1.l2cache.SCUpgradeReq_misses::total 22334 # number of SCUpgradeReq misses 2228system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2229system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2230system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33500 # number of ReadExReq misses 2231system.cpu1.l2cache.ReadExReq_misses::total 33500 # number of ReadExReq misses 2232system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 347 # number of demand (read+write) misses | 2229system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses 2230system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses 2231system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses 2232system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses 2233system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses 2234system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses 2235system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses 2236system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 2237system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 2238system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses 2239system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses 2240system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses |
| 2233system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses | 2241system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses |
| 2234system.cpu1.l2cache.demand_misses::cpu1.inst 5599 # number of demand (read+write) misses 2235system.cpu1.l2cache.demand_misses::cpu1.data 103797 # number of demand (read+write) misses 2236system.cpu1.l2cache.demand_misses::total 110025 # number of demand (read+write) misses 2237system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 347 # number of overall misses | 2242system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses 2243system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses 2244system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses 2245system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses |
| 2238system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses | 2246system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses |
| 2239system.cpu1.l2cache.overall_misses::cpu1.inst 5599 # number of overall misses 2240system.cpu1.l2cache.overall_misses::cpu1.data 103797 # number of overall misses 2241system.cpu1.l2cache.overall_misses::total 110025 # number of overall misses 2242system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7263500 # number of ReadReq miss cycles 2243system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5687750 # number of ReadReq miss cycles 2244system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191326469 # number of ReadReq miss cycles 2245system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1549353898 # number of ReadReq miss cycles 2246system.cpu1.l2cache.ReadReq_miss_latency::total 1753631617 # number of ReadReq miss cycles 2247system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537113129 # number of UpgradeReq miss cycles 2248system.cpu1.l2cache.UpgradeReq_miss_latency::total 537113129 # number of UpgradeReq miss cycles 2249system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436542574 # number of SCUpgradeReq miss cycles 2250system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436542574 # number of SCUpgradeReq miss cycles 2251system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1696500 # number of SCUpgradeFailReq miss cycles 2252system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1696500 # number of SCUpgradeFailReq miss cycles 2253system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1074535378 # number of ReadExReq miss cycles 2254system.cpu1.l2cache.ReadExReq_miss_latency::total 1074535378 # number of ReadExReq miss cycles 2255system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7263500 # number of demand (read+write) miss cycles 2256system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5687750 # number of demand (read+write) miss cycles 2257system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191326469 # number of demand (read+write) miss cycles 2258system.cpu1.l2cache.demand_miss_latency::cpu1.data 2623889276 # number of demand (read+write) miss cycles 2259system.cpu1.l2cache.demand_miss_latency::total 2828166995 # number of demand (read+write) miss cycles 2260system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7263500 # number of overall miss cycles 2261system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5687750 # number of overall miss cycles 2262system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191326469 # number of overall miss cycles 2263system.cpu1.l2cache.overall_miss_latency::cpu1.data 2623889276 # number of overall miss cycles 2264system.cpu1.l2cache.overall_miss_latency::total 2828166995 # number of overall miss cycles 2265system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3360 # number of ReadReq accesses(hits+misses) 2266system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) 2267system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565746 # number of ReadReq accesses(hits+misses) 2268system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193532 # number of ReadReq accesses(hits+misses) 2269system.cpu1.l2cache.ReadReq_accesses::total 764619 # number of ReadReq accesses(hits+misses) 2270system.cpu1.l2cache.Writeback_accesses::writebacks 134926 # number of Writeback accesses(hits+misses) 2271system.cpu1.l2cache.Writeback_accesses::total 134926 # number of Writeback accesses(hits+misses) 2272system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30962 # number of UpgradeReq accesses(hits+misses) 2273system.cpu1.l2cache.UpgradeReq_accesses::total 30962 # number of UpgradeReq accesses(hits+misses) 2274system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23223 # number of SCUpgradeReq accesses(hits+misses) 2275system.cpu1.l2cache.SCUpgradeReq_accesses::total 23223 # number of SCUpgradeReq accesses(hits+misses) 2276system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2277system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2278system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72790 # number of ReadExReq accesses(hits+misses) 2279system.cpu1.l2cache.ReadExReq_accesses::total 72790 # number of ReadExReq accesses(hits+misses) 2280system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3360 # number of demand (read+write) accesses 2281system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses 2282system.cpu1.l2cache.demand_accesses::cpu1.inst 565746 # number of demand (read+write) accesses 2283system.cpu1.l2cache.demand_accesses::cpu1.data 266322 # number of demand (read+write) accesses 2284system.cpu1.l2cache.demand_accesses::total 837409 # number of demand (read+write) accesses 2285system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3360 # number of overall (read+write) accesses 2286system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses 2287system.cpu1.l2cache.overall_accesses::cpu1.inst 565746 # number of overall (read+write) accesses 2288system.cpu1.l2cache.overall_accesses::cpu1.data 266322 # number of overall (read+write) accesses 2289system.cpu1.l2cache.overall_accesses::total 837409 # number of overall (read+write) accesses 2290system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for ReadReq accesses 2291system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.142352 # miss rate for ReadReq accesses 2292system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009897 # miss rate for ReadReq accesses 2293system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363232 # miss rate for ReadReq accesses 2294system.cpu1.l2cache.ReadReq_miss_rate::total 0.100083 # miss rate for ReadReq accesses 2295system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950585 # miss rate for UpgradeReq accesses 2296system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950585 # miss rate for UpgradeReq accesses 2297system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961719 # miss rate for SCUpgradeReq accesses 2298system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961719 # miss rate for SCUpgradeReq accesses | 2247system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses 2248system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses 2249system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses 2250system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles 2251system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles 2252system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles 2253system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles 2254system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles 2255system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles 2256system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles 2257system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles 2258system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles 2259system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles 2260system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles 2261system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles 2262system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles 2263system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles 2264system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles 2265system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles 2266system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles 2267system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles 2268system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles 2269system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles 2270system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles 2271system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles 2272system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles 2273system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses) 2274system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses) 2275system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses) 2276system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses) 2277system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses) 2278system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses) 2279system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses) 2280system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses) 2281system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses) 2282system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses) 2283system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses) 2284system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 2285system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 2286system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses) 2287system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses) 2288system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses 2289system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses 2290system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses 2291system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses 2292system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses 2293system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses 2294system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses 2295system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses 2296system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses 2297system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses 2298system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses 2299system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses 2300system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses 2301system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses 2302system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses 2303system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses 2304system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses 2305system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses 2306system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses |
| 2299system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2300system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2307system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2308system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2301system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.460228 # miss rate for ReadExReq accesses 2302system.cpu1.l2cache.ReadExReq_miss_rate::total 0.460228 # miss rate for ReadExReq accesses 2303system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for demand accesses 2304system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.142352 # miss rate for demand accesses 2305system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009897 # miss rate for demand accesses 2306system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389742 # miss rate for demand accesses 2307system.cpu1.l2cache.demand_miss_rate::total 0.131387 # miss rate for demand accesses 2308system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for overall accesses 2309system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.142352 # miss rate for overall accesses 2310system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009897 # miss rate for overall accesses 2311system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389742 # miss rate for overall accesses 2312system.cpu1.l2cache.overall_miss_rate::total 0.131387 # miss rate for overall accesses 2313system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average ReadReq miss latency 2314system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241 # average ReadReq miss latency 2315system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954 # average ReadReq miss latency 2316system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059 # average ReadReq miss latency 2317system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287 # average ReadReq miss latency 2318system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874 # average UpgradeReq miss latency 2319system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874 # average UpgradeReq miss latency 2320system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952 # average SCUpgradeReq miss latency 2321system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952 # average SCUpgradeReq miss latency 2322system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 565500 # average SCUpgradeFailReq miss latency 2323system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 565500 # average SCUpgradeFailReq miss latency 2324system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925 # average ReadExReq miss latency 2325system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925 # average ReadExReq miss latency 2326system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency 2327system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency 2328system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency 2329system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency 2330system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053 # average overall miss latency 2331system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency 2332system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency 2333system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency 2334system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency 2335system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053 # average overall miss latency 2336system.cpu1.l2cache.blocked_cycles::no_mshrs 1025 # number of cycles access was blocked | 2309system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses 2310system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses 2311system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses 2312system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses 2313system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses 2314system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses 2315system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses 2316system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses 2317system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses 2318system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses 2319system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses 2320system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses 2321system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency 2322system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency 2323system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency 2324system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency 2325system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency 2326system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency 2327system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency 2328system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency 2329system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency 2330system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency 2331system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency 2332system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency 2333system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency 2334system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency 2335system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency 2336system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency 2337system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency 2338system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency 2339system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency 2340system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency 2341system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency 2342system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency 2343system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency 2344system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked |
| 2337system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2345system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2338system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked | 2346system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked |
| 2339system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2347system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2340system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.285714 # average number of cycles each access was blocked | 2348system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked |
| 2341system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2342system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2343system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2349system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2350system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2351system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2344system.cpu1.l2cache.writebacks::writebacks 35099 # number of writebacks 2345system.cpu1.l2cache.writebacks::total 35099 # number of writebacks 2346system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 685 # number of ReadReq MSHR hits 2347system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 96 # number of ReadReq MSHR hits 2348system.cpu1.l2cache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits 2349system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 214 # number of ReadExReq MSHR hits 2350system.cpu1.l2cache.ReadExReq_mshr_hits::total 214 # number of ReadExReq MSHR hits 2351system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 685 # number of demand (read+write) MSHR hits 2352system.cpu1.l2cache.demand_mshr_hits::cpu1.data 310 # number of demand (read+write) MSHR hits 2353system.cpu1.l2cache.demand_mshr_hits::total 995 # number of demand (read+write) MSHR hits 2354system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 685 # number of overall MSHR hits 2355system.cpu1.l2cache.overall_mshr_hits::cpu1.data 310 # number of overall MSHR hits 2356system.cpu1.l2cache.overall_mshr_hits::total 995 # number of overall MSHR hits 2357system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 347 # number of ReadReq MSHR misses | 2352system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks 2353system.cpu1.l2cache.writebacks::total 35043 # number of writebacks 2354system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits 2355system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits 2356system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits 2357system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits 2358system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits 2359system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits 2360system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits 2361system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits 2362system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits 2363system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits 2364system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits 2365system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses |
| 2358system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses | 2366system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses |
| 2359system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4914 # number of ReadReq MSHR misses 2360system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70201 # number of ReadReq MSHR misses 2361system.cpu1.l2cache.ReadReq_mshr_misses::total 75744 # number of ReadReq MSHR misses 2362system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of HardPFReq MSHR misses 2363system.cpu1.l2cache.HardPFReq_mshr_misses::total 117733 # number of HardPFReq MSHR misses 2364system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29432 # number of UpgradeReq MSHR misses 2365system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29432 # number of UpgradeReq MSHR misses 2366system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22334 # number of SCUpgradeReq MSHR misses 2367system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22334 # number of SCUpgradeReq MSHR misses 2368system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2369system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2370system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33286 # number of ReadExReq MSHR misses 2371system.cpu1.l2cache.ReadExReq_mshr_misses::total 33286 # number of ReadExReq MSHR misses 2372system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 347 # number of demand (read+write) MSHR misses | 2367system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses 2368system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses 2369system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses 2370system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses 2371system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses 2372system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses 2373system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses 2374system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # number of SCUpgradeReq MSHR misses 2375system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22356 # number of SCUpgradeReq MSHR misses 2376system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 2377system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 2378system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33253 # number of ReadExReq MSHR misses 2379system.cpu1.l2cache.ReadExReq_mshr_misses::total 33253 # number of ReadExReq MSHR misses 2380system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 333 # number of demand (read+write) MSHR misses |
| 2373system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses | 2381system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses |
| 2374system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4914 # number of demand (read+write) MSHR misses 2375system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103487 # number of demand (read+write) MSHR misses 2376system.cpu1.l2cache.demand_mshr_misses::total 109030 # number of demand (read+write) MSHR misses 2377system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 347 # number of overall MSHR misses | 2382system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4965 # number of demand (read+write) MSHR misses 2383system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103360 # number of demand (read+write) MSHR misses 2384system.cpu1.l2cache.demand_mshr_misses::total 108940 # number of demand (read+write) MSHR misses 2385system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses |
| 2378system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses | 2386system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses |
| 2379system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4914 # number of overall MSHR misses 2380system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103487 # number of overall MSHR misses 2381system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of overall MSHR misses 2382system.cpu1.l2cache.overall_mshr_misses::total 226763 # number of overall MSHR misses 2383system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of ReadReq MSHR miss cycles 2384system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3713250 # number of ReadReq MSHR miss cycles 2385system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143751774 # number of ReadReq MSHR miss cycles 2386system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1055636432 # number of ReadReq MSHR miss cycles 2387system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1207934956 # number of ReadReq MSHR miss cycles 2388system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of HardPFReq MSHR miss cycles 2389system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3298666709 # number of HardPFReq MSHR miss cycles 2390system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 431077198 # number of UpgradeReq MSHR miss cycles 2391system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 431077198 # number of UpgradeReq MSHR miss cycles 2392system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306544179 # number of SCUpgradeReq MSHR miss cycles 2393system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306544179 # number of SCUpgradeReq MSHR miss cycles 2394system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1430500 # number of SCUpgradeFailReq MSHR miss cycles 2395system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1430500 # number of SCUpgradeFailReq MSHR miss cycles 2396system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820609092 # number of ReadExReq MSHR miss cycles 2397system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820609092 # number of ReadExReq MSHR miss cycles 2398system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of demand (read+write) MSHR miss cycles 2399system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3713250 # number of demand (read+write) MSHR miss cycles 2400system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143751774 # number of demand (read+write) MSHR miss cycles 2401system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1876245524 # number of demand (read+write) MSHR miss cycles 2402system.cpu1.l2cache.demand_mshr_miss_latency::total 2028544048 # number of demand (read+write) MSHR miss cycles 2403system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of overall MSHR miss cycles 2404system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3713250 # number of overall MSHR miss cycles 2405system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143751774 # number of overall MSHR miss cycles 2406system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1876245524 # number of overall MSHR miss cycles 2407system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of overall MSHR miss cycles 2408system.cpu1.l2cache.overall_mshr_miss_latency::total 5327210757 # number of overall MSHR miss cycles 2409system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12612250 # number of ReadReq MSHR uncacheable cycles 2410system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916010500 # number of ReadReq MSHR uncacheable cycles 2411system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928622750 # number of ReadReq MSHR uncacheable cycles 2412system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796474001 # number of WriteReq MSHR uncacheable cycles 2413system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796474001 # number of WriteReq MSHR uncacheable cycles 2414system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12612250 # number of overall MSHR uncacheable cycles 2415system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712484501 # number of overall MSHR uncacheable cycles 2416system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725096751 # number of overall MSHR uncacheable cycles 2417system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for ReadReq accesses 2418system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for ReadReq accesses 2419system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for ReadReq accesses 2420system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362736 # mshr miss rate for ReadReq accesses 2421system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099061 # mshr miss rate for ReadReq accesses | 2387system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses 2388system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses 2389system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses 2390system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses 2391system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles 2392system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles 2393system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles 2394system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # number of ReadReq MSHR miss cycles 2395system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206735448 # number of ReadReq MSHR miss cycles 2396system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of HardPFReq MSHR miss cycles 2397system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3265998125 # number of HardPFReq MSHR miss cycles 2398system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430847649 # number of UpgradeReq MSHR miss cycles 2399system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430847649 # number of UpgradeReq MSHR miss cycles 2400system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306945673 # number of SCUpgradeReq MSHR miss cycles 2401system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306945673 # number of SCUpgradeReq MSHR miss cycles 2402system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1280500 # number of SCUpgradeFailReq MSHR miss cycles 2403system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1280500 # number of SCUpgradeFailReq MSHR miss cycles 2404system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 812696840 # number of ReadExReq MSHR miss cycles 2405system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 812696840 # number of ReadExReq MSHR miss cycles 2406system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of demand (read+write) MSHR miss cycles 2407system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3694250 # number of demand (read+write) MSHR miss cycles 2408system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143766018 # number of demand (read+write) MSHR miss cycles 2409system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1867420270 # number of demand (read+write) MSHR miss cycles 2410system.cpu1.l2cache.demand_mshr_miss_latency::total 2019432288 # number of demand (read+write) MSHR miss cycles 2411system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of overall MSHR miss cycles 2412system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3694250 # number of overall MSHR miss cycles 2413system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles 2414system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles 2415system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles 2416system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles 2417system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles 2418system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles 2419system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles 2420system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles 2421system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles 2422system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles 2423system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles 2424system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles 2425system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses 2426system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses 2427system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses 2428system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses 2429system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses |
| 2422system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2423system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2430system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2431system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2424system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950585 # mshr miss rate for UpgradeReq accesses 2425system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950585 # mshr miss rate for UpgradeReq accesses 2426system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961719 # mshr miss rate for SCUpgradeReq accesses 2427system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961719 # mshr miss rate for SCUpgradeReq accesses | 2432system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses 2433system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses 2434system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses 2435system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses |
| 2428system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2429system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2436system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2437system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2430system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457288 # mshr miss rate for ReadExReq accesses 2431system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457288 # mshr miss rate for ReadExReq accesses 2432system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for demand accesses 2433system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for demand accesses 2434system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for demand accesses 2435system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for demand accesses 2436system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130199 # mshr miss rate for demand accesses 2437system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for overall accesses 2438system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for overall accesses 2439system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for overall accesses 2440system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for overall accesses | 2438system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses 2439system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses 2440system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses 2441system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses 2442system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses 2443system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses 2444system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses 2445system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses 2446system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses 2447system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses 2448system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses |
| 2441system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2449system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2442system.cpu1.l2cache.overall_mshr_miss_rate::total 0.270791 # mshr miss rate for overall accesses 2443system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average ReadReq mshr miss latency 2444system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average ReadReq mshr miss latency 2445system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average ReadReq mshr miss latency 2446system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804 # average ReadReq mshr miss latency 2447system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229 # average ReadReq mshr miss latency 2448system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average HardPFReq mshr miss latency 2449system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732 # average HardPFReq mshr miss latency 2450system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907 # average UpgradeReq mshr miss latency 2451system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907 # average UpgradeReq mshr miss latency 2452system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046 # average SCUpgradeReq mshr miss latency 2453system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046 # average SCUpgradeReq mshr miss latency 2454system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333 # average SCUpgradeFailReq mshr miss latency 2455system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333 # average SCUpgradeFailReq mshr miss latency 2456system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418 # average ReadExReq mshr miss latency 2457system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418 # average ReadExReq mshr miss latency 2458system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency 2459system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency 2460system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency 2461system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency 2462system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108 # average overall mshr miss latency 2463system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency 2464system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency 2465system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency 2466system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency 2467system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average overall mshr miss latency 2468system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122 # average overall mshr miss latency | 2450system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses 2451system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency 2452system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency 2453system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency 2454system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency 2455system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency 2456system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency 2457system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency 2458system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency 2459system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency 2460system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency 2461system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency 2462system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency 2463system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency 2464system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency 2465system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency 2466system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency 2467system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency 2468system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency 2469system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency 2470system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency 2471system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency 2472system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency 2473system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency 2474system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency 2475system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency 2476system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency |
| 2469system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2470system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2471system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2472system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2473system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2474system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2475system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2476system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2477system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2477system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2478system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2479system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2480system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2481system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2482system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2483system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2484system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2485system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2478system.cpu1.dcache.tags.replacements 218932 # number of replacements 2479system.cpu1.dcache.tags.tagsinuse 479.958616 # Cycle average of tags in use 2480system.cpu1.dcache.tags.total_refs 8645395 # Total number of references to valid blocks. 2481system.cpu1.dcache.tags.sampled_refs 219287 # Sample count of references to valid blocks. 2482system.cpu1.dcache.tags.avg_refs 39.425023 # Average number of references to valid blocks. 2483system.cpu1.dcache.tags.warmup_cycle 104115576500 # Cycle when the warmup percentage was hit. 2484system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.958616 # Average occupied blocks per requestor 2485system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937419 # Average percentage of cache occupancy 2486system.cpu1.dcache.tags.occ_percent::total 0.937419 # Average percentage of cache occupancy 2487system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 2488system.cpu1.dcache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id 2489system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id 2490system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id 2491system.cpu1.dcache.tags.tag_accesses 18161929 # Number of tag accesses 2492system.cpu1.dcache.tags.data_accesses 18161929 # Number of data accesses 2493system.cpu1.dcache.ReadReq_hits::cpu1.data 4463105 # number of ReadReq hits 2494system.cpu1.dcache.ReadReq_hits::total 4463105 # number of ReadReq hits 2495system.cpu1.dcache.WriteReq_hits::cpu1.data 3919326 # number of WriteReq hits 2496system.cpu1.dcache.WriteReq_hits::total 3919326 # number of WriteReq hits 2497system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64192 # number of SoftPFReq hits 2498system.cpu1.dcache.SoftPFReq_hits::total 64192 # number of SoftPFReq hits 2499system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87200 # number of LoadLockedReq hits 2500system.cpu1.dcache.LoadLockedReq_hits::total 87200 # number of LoadLockedReq hits 2501system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79632 # number of StoreCondReq hits 2502system.cpu1.dcache.StoreCondReq_hits::total 79632 # number of StoreCondReq hits 2503system.cpu1.dcache.demand_hits::cpu1.data 8382431 # number of demand (read+write) hits 2504system.cpu1.dcache.demand_hits::total 8382431 # number of demand (read+write) hits 2505system.cpu1.dcache.overall_hits::cpu1.data 8446623 # number of overall hits 2506system.cpu1.dcache.overall_hits::total 8446623 # number of overall hits 2507system.cpu1.dcache.ReadReq_misses::cpu1.data 155171 # number of ReadReq misses 2508system.cpu1.dcache.ReadReq_misses::total 155171 # number of ReadReq misses 2509system.cpu1.dcache.WriteReq_misses::cpu1.data 103752 # number of WriteReq misses 2510system.cpu1.dcache.WriteReq_misses::total 103752 # number of WriteReq misses 2511system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34196 # number of SoftPFReq misses 2512system.cpu1.dcache.SoftPFReq_misses::total 34196 # number of SoftPFReq misses 2513system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17931 # number of LoadLockedReq misses 2514system.cpu1.dcache.LoadLockedReq_misses::total 17931 # number of LoadLockedReq misses 2515system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23276 # number of StoreCondReq misses 2516system.cpu1.dcache.StoreCondReq_misses::total 23276 # number of StoreCondReq misses 2517system.cpu1.dcache.demand_misses::cpu1.data 258923 # number of demand (read+write) misses 2518system.cpu1.dcache.demand_misses::total 258923 # number of demand (read+write) misses 2519system.cpu1.dcache.overall_misses::cpu1.data 293119 # number of overall misses 2520system.cpu1.dcache.overall_misses::total 293119 # number of overall misses 2521system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220270266 # number of ReadReq miss cycles 2522system.cpu1.dcache.ReadReq_miss_latency::total 2220270266 # number of ReadReq miss cycles 2523system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2272762314 # number of WriteReq miss cycles 2524system.cpu1.dcache.WriteReq_miss_latency::total 2272762314 # number of WriteReq miss cycles 2525system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325809000 # number of LoadLockedReq miss cycles 2526system.cpu1.dcache.LoadLockedReq_miss_latency::total 325809000 # number of LoadLockedReq miss cycles 2527system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538454705 # number of StoreCondReq miss cycles 2528system.cpu1.dcache.StoreCondReq_miss_latency::total 538454705 # number of StoreCondReq miss cycles 2529system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1810500 # number of StoreCondFailReq miss cycles 2530system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1810500 # number of StoreCondFailReq miss cycles 2531system.cpu1.dcache.demand_miss_latency::cpu1.data 4493032580 # number of demand (read+write) miss cycles 2532system.cpu1.dcache.demand_miss_latency::total 4493032580 # number of demand (read+write) miss cycles 2533system.cpu1.dcache.overall_miss_latency::cpu1.data 4493032580 # number of overall miss cycles 2534system.cpu1.dcache.overall_miss_latency::total 4493032580 # number of overall miss cycles 2535system.cpu1.dcache.ReadReq_accesses::cpu1.data 4618276 # number of ReadReq accesses(hits+misses) 2536system.cpu1.dcache.ReadReq_accesses::total 4618276 # number of ReadReq accesses(hits+misses) 2537system.cpu1.dcache.WriteReq_accesses::cpu1.data 4023078 # number of WriteReq accesses(hits+misses) 2538system.cpu1.dcache.WriteReq_accesses::total 4023078 # number of WriteReq accesses(hits+misses) 2539system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98388 # number of SoftPFReq accesses(hits+misses) 2540system.cpu1.dcache.SoftPFReq_accesses::total 98388 # number of SoftPFReq accesses(hits+misses) 2541system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105131 # number of LoadLockedReq accesses(hits+misses) 2542system.cpu1.dcache.LoadLockedReq_accesses::total 105131 # number of LoadLockedReq accesses(hits+misses) 2543system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102908 # number of StoreCondReq accesses(hits+misses) 2544system.cpu1.dcache.StoreCondReq_accesses::total 102908 # number of StoreCondReq accesses(hits+misses) 2545system.cpu1.dcache.demand_accesses::cpu1.data 8641354 # number of demand (read+write) accesses 2546system.cpu1.dcache.demand_accesses::total 8641354 # number of demand (read+write) accesses 2547system.cpu1.dcache.overall_accesses::cpu1.data 8739742 # number of overall (read+write) accesses 2548system.cpu1.dcache.overall_accesses::total 8739742 # number of overall (read+write) accesses 2549system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033599 # miss rate for ReadReq accesses 2550system.cpu1.dcache.ReadReq_miss_rate::total 0.033599 # miss rate for ReadReq accesses 2551system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025789 # miss rate for WriteReq accesses 2552system.cpu1.dcache.WriteReq_miss_rate::total 0.025789 # miss rate for WriteReq accesses 2553system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347563 # miss rate for SoftPFReq accesses 2554system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347563 # miss rate for SoftPFReq accesses 2555system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170559 # miss rate for LoadLockedReq accesses 2556system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170559 # miss rate for LoadLockedReq accesses 2557system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226183 # miss rate for StoreCondReq accesses 2558system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226183 # miss rate for StoreCondReq accesses 2559system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029963 # miss rate for demand accesses 2560system.cpu1.dcache.demand_miss_rate::total 0.029963 # miss rate for demand accesses 2561system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033539 # miss rate for overall accesses 2562system.cpu1.dcache.overall_miss_rate::total 0.033539 # miss rate for overall accesses 2563system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748 # average ReadReq miss latency 2564system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748 # average ReadReq miss latency 2565system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507 # average WriteReq miss latency 2566system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507 # average WriteReq miss latency 2567system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250 # average LoadLockedReq miss latency 2568system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250 # average LoadLockedReq miss latency 2569system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461 # average StoreCondReq miss latency 2570system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461 # average StoreCondReq miss latency | 2486system.cpu1.dcache.tags.replacements 218971 # number of replacements 2487system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use 2488system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks. 2489system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks. 2490system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks. 2491system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit. 2492system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor 2493system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy 2494system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy 2495system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id 2496system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id 2497system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id 2498system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id 2499system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses 2500system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses 2501system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits 2502system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits 2503system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits 2504system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits 2505system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits 2506system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits 2507system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits 2508system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits 2509system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits 2510system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits 2511system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits 2512system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits 2513system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits 2514system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits 2515system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses 2516system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses 2517system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses 2518system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses 2519system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses 2520system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses 2521system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses 2522system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses 2523system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses 2524system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses 2525system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses 2526system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses 2527system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses 2528system.cpu1.dcache.overall_misses::total 293049 # number of overall misses 2529system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles 2530system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles 2531system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles 2532system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles 2533system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles 2534system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles 2535system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles 2536system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles 2537system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles 2538system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles 2539system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles 2540system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles 2541system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles 2542system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles 2543system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses) 2544system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses) 2545system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses) 2546system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses) 2547system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses) 2548system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses) 2549system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses) 2550system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses) 2551system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses) 2552system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses) 2553system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses 2554system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses 2555system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses 2556system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses 2557system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses 2558system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses 2559system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses 2560system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses 2561system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses 2562system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses 2563system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses 2564system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses 2565system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses 2566system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses 2567system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses 2568system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses 2569system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses 2570system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses 2571system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency 2572system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency 2573system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency 2574system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency 2575system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency 2576system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency 2577system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency 2578system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency |
| 2571system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2572system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2579system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2580system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2573system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072 # average overall miss latency 2574system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072 # average overall miss latency 2575system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674 # average overall miss latency 2576system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674 # average overall miss latency | 2581system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency 2582system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency 2583system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency 2584system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency |
| 2577system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2578system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2579system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2580system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2581system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2582system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2583system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2584system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2585system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2586system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2587system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2588system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2589system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2590system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2591system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2592system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2585system.cpu1.dcache.writebacks::writebacks 134926 # number of writebacks 2586system.cpu1.dcache.writebacks::total 134926 # number of writebacks 2587system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits 2588system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits 2589system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12328 # number of LoadLockedReq MSHR hits 2590system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12328 # number of LoadLockedReq MSHR hits 2591system.cpu1.dcache.demand_mshr_hits::cpu1.data 299 # number of demand (read+write) MSHR hits 2592system.cpu1.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits 2593system.cpu1.dcache.overall_mshr_hits::cpu1.data 299 # number of overall MSHR hits 2594system.cpu1.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits 2595system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154872 # number of ReadReq MSHR misses 2596system.cpu1.dcache.ReadReq_mshr_misses::total 154872 # number of ReadReq MSHR misses 2597system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103752 # number of WriteReq MSHR misses 2598system.cpu1.dcache.WriteReq_mshr_misses::total 103752 # number of WriteReq MSHR misses 2599system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33057 # number of SoftPFReq MSHR misses 2600system.cpu1.dcache.SoftPFReq_mshr_misses::total 33057 # number of SoftPFReq MSHR misses 2601system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5603 # number of LoadLockedReq MSHR misses 2602system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5603 # number of LoadLockedReq MSHR misses 2603system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23226 # number of StoreCondReq MSHR misses 2604system.cpu1.dcache.StoreCondReq_mshr_misses::total 23226 # number of StoreCondReq MSHR misses 2605system.cpu1.dcache.demand_mshr_misses::cpu1.data 258624 # number of demand (read+write) MSHR misses 2606system.cpu1.dcache.demand_mshr_misses::total 258624 # number of demand (read+write) MSHR misses 2607system.cpu1.dcache.overall_mshr_misses::cpu1.data 291681 # number of overall MSHR misses 2608system.cpu1.dcache.overall_mshr_misses::total 291681 # number of overall MSHR misses 2609system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901749734 # number of ReadReq MSHR miss cycles 2610system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901749734 # number of ReadReq MSHR miss cycles 2611system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2059007686 # number of WriteReq MSHR miss cycles 2612system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2059007686 # number of WriteReq MSHR miss cycles 2613system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496678249 # number of SoftPFReq MSHR miss cycles 2614system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496678249 # number of SoftPFReq MSHR miss cycles 2615system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84335500 # number of LoadLockedReq MSHR miss cycles 2616system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84335500 # number of LoadLockedReq MSHR miss cycles 2617system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490783295 # number of StoreCondReq MSHR miss cycles 2618system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490783295 # number of StoreCondReq MSHR miss cycles 2619system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1734500 # number of StoreCondFailReq MSHR miss cycles 2620system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1734500 # number of StoreCondFailReq MSHR miss cycles 2621system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3960757420 # number of demand (read+write) MSHR miss cycles 2622system.cpu1.dcache.demand_mshr_miss_latency::total 3960757420 # number of demand (read+write) MSHR miss cycles 2623system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4457435669 # number of overall MSHR miss cycles 2624system.cpu1.dcache.overall_mshr_miss_latency::total 4457435669 # number of overall MSHR miss cycles 2625system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961034499 # number of ReadReq MSHR uncacheable cycles 2626system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961034499 # number of ReadReq MSHR uncacheable cycles 2627system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382499 # number of WriteReq MSHR uncacheable cycles 2628system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382499 # number of WriteReq MSHR uncacheable cycles 2629system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794416998 # number of overall MSHR uncacheable cycles 2630system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794416998 # number of overall MSHR uncacheable cycles 2631system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033535 # mshr miss rate for ReadReq accesses 2632system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033535 # mshr miss rate for ReadReq accesses 2633system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025789 # mshr miss rate for WriteReq accesses 2634system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025789 # mshr miss rate for WriteReq accesses 2635system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335986 # mshr miss rate for SoftPFReq accesses 2636system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335986 # mshr miss rate for SoftPFReq accesses 2637system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053295 # mshr miss rate for LoadLockedReq accesses 2638system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053295 # mshr miss rate for LoadLockedReq accesses 2639system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225697 # mshr miss rate for StoreCondReq accesses 2640system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225697 # mshr miss rate for StoreCondReq accesses 2641system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029929 # mshr miss rate for demand accesses 2642system.cpu1.dcache.demand_mshr_miss_rate::total 0.029929 # mshr miss rate for demand accesses 2643system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033374 # mshr miss rate for overall accesses 2644system.cpu1.dcache.overall_mshr_miss_rate::total 0.033374 # mshr miss rate for overall accesses 2645system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608 # average ReadReq mshr miss latency 2646system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608 # average ReadReq mshr miss latency 2647system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651 # average WriteReq mshr miss latency 2648system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651 # average WriteReq mshr miss latency 2649system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924 # average SoftPFReq mshr miss latency 2650system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924 # average SoftPFReq mshr miss latency 2651system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225 # average LoadLockedReq mshr miss latency 2652system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225 # average LoadLockedReq mshr miss latency 2653system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334 # average StoreCondReq mshr miss latency 2654system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334 # average StoreCondReq mshr miss latency | 2593system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks 2594system.cpu1.dcache.writebacks::total 134894 # number of writebacks 2595system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits 2596system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits 2597system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits 2598system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits 2599system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits 2600system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits 2601system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits 2602system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits 2603system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses 2604system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses 2605system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses 2606system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses 2607system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses 2608system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses 2609system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses 2610system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses 2611system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses 2612system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses 2613system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses 2614system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses 2615system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses 2616system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses 2617system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles 2618system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles 2619system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles 2620system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles 2621system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles 2622system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles 2623system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles 2624system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles 2625system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles 2626system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles 2627system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles 2628system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles 2629system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles 2630system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles 2631system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles 2632system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles 2633system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles 2634system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles 2635system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles 2636system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles 2637system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles 2638system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles 2639system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses 2640system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses 2641system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses 2642system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses 2643system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses 2644system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses 2645system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses 2646system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses 2647system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses 2648system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses 2649system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses 2650system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses 2651system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses 2652system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses 2653system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency 2654system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency 2655system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency 2656system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency 2657system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency 2658system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency 2659system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency 2660system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency 2661system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency 2662system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency |
| 2655system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2656system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2663system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2664system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2657system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662 # average overall mshr miss latency 2658system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662 # average overall mshr miss latency 2659system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584 # average overall mshr miss latency 2660system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584 # average overall mshr miss latency | 2665system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency 2666system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency 2667system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency 2668system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency |
| 2661system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2662system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2663system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2664system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2665system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2666system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2667system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2669system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2670system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2671system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2672system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2673system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2674system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2675system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2668system.cpu1.toL2Bus.trans_dist::ReadReq 1206103 # Transaction distribution 2669system.cpu1.toL2Bus.trans_dist::ReadResp 816776 # Transaction distribution 2670system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution 2671system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution 2672system.cpu1.toL2Bus.trans_dist::Writeback 134926 # Transaction distribution 2673system.cpu1.toL2Bus.trans_dist::HardPFReq 169865 # Transaction distribution 2674system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 2675system.cpu1.toL2Bus.trans_dist::UpgradeReq 86284 # Transaction distribution 2676system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42512 # Transaction distribution 2677system.cpu1.toL2Bus.trans_dist::UpgradeResp 89712 # Transaction distribution 2678system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution 2679system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 2680system.cpu1.toL2Bus.trans_dist::ReadExReq 91056 # Transaction distribution 2681system.cpu1.toL2Bus.trans_dist::ReadExResp 78188 # Transaction distribution 2682system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131848 # Packet count per connected master and slave (bytes) 2683system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880488 # Packet count per connected master and slave (bytes) 2684system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) 2685system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9281 # Packet count per connected master and slave (bytes) 2686system.cpu1.toL2Bus.pkt_count::total 2026923 # Packet count per connected master and slave (bytes) 2687system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36208456 # Cumulative packet size per connected master and slave (bytes) 2688system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28775795 # Cumulative packet size per connected master and slave (bytes) 2689system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) 2690system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13440 # Cumulative packet size per connected master and slave (bytes) 2691system.cpu1.toL2Bus.pkt_size::total 65005615 # Cumulative packet size per connected master and slave (bytes) 2692system.cpu1.toL2Bus.snoops 818131 # Total snoops (count) 2693system.cpu1.toL2Bus.snoop_fanout::samples 1761210 # Request fanout histogram 2694system.cpu1.toL2Bus.snoop_fanout::mean 5.414931 # Request fanout histogram 2695system.cpu1.toL2Bus.snoop_fanout::stdev 0.492710 # Request fanout histogram | 2676system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution 2677system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution 2678system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution 2679system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution 2680system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution 2681system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution 2682system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution 2683system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution 2684system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution 2685system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution 2686system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 2687system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution 2688system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution 2689system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution 2690system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes) 2691system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes) 2692system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes) 2693system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes) 2694system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes) 2695system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes) 2696system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes) 2697system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes) 2698system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes) 2699system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes) 2700system.cpu1.toL2Bus.snoops 817024 # Total snoops (count) 2701system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram 2702system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram 2703system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram |
| 2696system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2697system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2698system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2699system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2700system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2701system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 2704system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2705system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2706system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2707system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2708system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2709system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 2702system.cpu1.toL2Bus.snoop_fanout::5 1030430 58.51% 58.51% # Request fanout histogram 2703system.cpu1.toL2Bus.snoop_fanout::6 730780 41.49% 100.00% # Request fanout histogram | 2710system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram 2711system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram |
| 2704system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2705system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2706system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 2712system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2713system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2714system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 2707system.cpu1.toL2Bus.snoop_fanout::total 1761210 # Request fanout histogram 2708system.cpu1.toL2Bus.reqLayer0.occupancy 658102724 # Layer occupancy (ticks) | 2715system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram 2716system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks) |
| 2709system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2717system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2710system.cpu1.toL2Bus.snoopLayer0.occupancy 89600499 # Layer occupancy (ticks) | 2718system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks) |
| 2711system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2719system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2712system.cpu1.toL2Bus.respLayer0.occupancy 848922781 # Layer occupancy (ticks) | 2720system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks) |
| 2713system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2721system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2714system.cpu1.toL2Bus.respLayer1.occupancy 438669538 # Layer occupancy (ticks) | 2722system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks) |
| 2715system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2716system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) 2717system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2723system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2724system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) 2725system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2718system.cpu1.toL2Bus.respLayer3.occupancy 5921500 # Layer occupancy (ticks) | 2726system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks) |
| 2719system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2727system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2720system.iocache.tags.replacements 36443 # number of replacements 2721system.iocache.tags.tagsinuse 14.446814 # Cycle average of tags in use 2722system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2723system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. 2724system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2725system.iocache.tags.warmup_cycle 277160524000 # Cycle when the warmup percentage was hit. 2726system.iocache.tags.occ_blocks::realview.ide 14.446814 # Average occupied blocks per requestor 2727system.iocache.tags.occ_percent::realview.ide 0.902926 # Average percentage of cache occupancy 2728system.iocache.tags.occ_percent::total 0.902926 # Average percentage of cache occupancy | 2728system.iocache.tags.replacements 36427 # number of replacements 2729system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use 2730system.iocache.tags.total_refs 16 # Total number of references to valid blocks. 2731system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks. 2732system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. 2733system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit. 2734system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor 2735system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy 2736system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy |
| 2729system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2730system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2731system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2737system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2738system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2739system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2732system.iocache.tags.tag_accesses 328549 # Number of tag accesses 2733system.iocache.tags.data_accesses 328549 # Number of data accesses | 2740system.iocache.tags.tag_accesses 328485 # Number of tag accesses 2741system.iocache.tags.data_accesses 328485 # Number of data accesses |
| 2734system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2735system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2736system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2737system.iocache.ReadReq_misses::total 253 # number of ReadReq misses | 2742system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2743system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2744system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2745system.iocache.ReadReq_misses::total 253 # number of ReadReq misses |
| 2738system.iocache.WriteInvalidateReq_misses::realview.ide 32 # number of WriteInvalidateReq misses 2739system.iocache.WriteInvalidateReq_misses::total 32 # number of WriteInvalidateReq misses | 2746system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses 2747system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses |
| 2740system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2741system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2742system.iocache.overall_misses::realview.ide 253 # number of overall misses 2743system.iocache.overall_misses::total 253 # number of overall misses | 2748system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2749system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2750system.iocache.overall_misses::realview.ide 253 # number of overall misses 2751system.iocache.overall_misses::total 253 # number of overall misses |
| 2744system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles 2745system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles 2746system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles 2747system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles 2748system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles 2749system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles | 2752system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles 2753system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles 2754system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles 2755system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles 2756system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles 2757system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles |
| 2750system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2751system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) | 2758system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2759system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) |
| 2752system.iocache.WriteInvalidateReq_accesses::realview.ide 36256 # number of WriteInvalidateReq accesses(hits+misses) 2753system.iocache.WriteInvalidateReq_accesses::total 36256 # number of WriteInvalidateReq accesses(hits+misses) | 2760system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses) 2761system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses) |
| 2754system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2755system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2756system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2757system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2758system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2759system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 2762system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2763system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2764system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2765system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2766system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2767system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 2760system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000883 # miss rate for WriteInvalidateReq accesses 2761system.iocache.WriteInvalidateReq_miss_rate::total 0.000883 # miss rate for WriteInvalidateReq accesses | 2768system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses 2769system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses |
| 2762system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2763system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2764system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2765system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2770system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2771system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2772system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2773system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2766system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency 2767system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency 2768system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2769system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency 2770system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2771system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency | 2774system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency 2775system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency 2776system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency 2777system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency 2778system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency 2779system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency |
| 2772system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2773system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2774system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2775system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2776system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2777system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2778system.iocache.fast_writes 36224 # number of fast writes performed 2779system.iocache.cache_copies 0 # number of cache copies performed 2780system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2781system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses 2782system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2783system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2784system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2785system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses | 2780system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2781system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2782system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2783system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2784system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2785system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2786system.iocache.fast_writes 36224 # number of fast writes performed 2787system.iocache.cache_copies 0 # number of cache copies performed 2788system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2789system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses 2790system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2791system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2792system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2793system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses |
| 2786system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles 2787system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles 2788system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2247085536 # number of WriteInvalidateReq MSHR miss cycles 2789system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2247085536 # number of WriteInvalidateReq MSHR miss cycles 2790system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles 2791system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles 2792system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles 2793system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles | 2794system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles 2795system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles 2796system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles 2797system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles 2798system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles 2799system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles 2800system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles 2801system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles |
| 2794system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2795system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2796system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2797system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2798system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2799system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2802system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2803system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2804system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2805system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2806system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2807system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2800system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency 2801system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency | 2808system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency 2809system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency |
| 2802system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2803system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency | 2810system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2811system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 2804system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2805system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency 2806system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2807system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency | 2812system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency 2813system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency 2814system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency 2815system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency |
| 2808system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2809 2810---------- End Simulation Statistics ---------- | 2816system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2817 2818---------- End Simulation Statistics ---------- |