| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.675181 # Number of seconds simulated 4sim_ticks 2675180779000 # Number of ticks simulated 5final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.866929 # Number of seconds simulated 4sim_ticks 2866929256000 # Number of ticks simulated 5final_tick 2866929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 349036 # Simulator instruction rate (inst/s) 8host_op_rate 416751 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14917331050 # Simulator tick rate (ticks/s) 10host_mem_usage 433588 # Number of bytes of host memory used 11host_seconds 179.33 # Real time elapsed on the host 12sim_insts 62593972 # Number of instructions simulated 13sim_ops 74737529 # Number of ops (including micro ops) simulated | 7host_inst_rate 703930 # Simulator instruction rate (inst/s) 8host_op_rate 851474 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15295798763 # Simulator tick rate (ticks/s) 10host_mem_usage 599572 # Number of bytes of host memory used 11host_seconds 187.43 # Real time elapsed on the host 12sim_insts 131939289 # Number of instructions simulated 13sim_ops 159593891 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 120908 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 513788 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 6659968 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 37828 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 531832 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 3262144 # Number of bytes read from this memory 26system.physmem.bytes_read::total 135383236 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 120908 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 37828 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 158736 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 4300032 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 33system.physmem.bytes_written::total 7329168 # Number of bytes written to this memory 34system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 8117 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 8087 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 104062 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.inst 682 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.data 8328 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.l2cache.prefetcher 50971 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 15712287 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 67188 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 824472 # Number of write requests responded to by this memory 49system.physmem.bw_read::realview.clcd 46447798 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.itb.walker 96 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.inst 45196 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.data 192057 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.l2cache.prefetcher 2489539 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.inst 14140 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.data 198802 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.l2cache.prefetcher 1219411 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 50607135 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 45196 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 14140 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 59337 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 1607380 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6355 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 1125956 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 2739691 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 1607380 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::realview.clcd 46447798 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.itb.walker 96 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.inst 45196 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.data 198412 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.l2cache.prefetcher 2489539 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.inst 14140 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.data 1324758 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.l2cache.prefetcher 1219411 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 53346826 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 15712287 # Number of read requests accepted 80system.physmem.writeReqs 824472 # Number of write requests accepted 81system.physmem.readBursts 15712287 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 824472 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 1005465984 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 120384 # Total number of bytes read from write queue 85system.physmem.bytesWritten 7344256 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 135383236 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 7329168 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 1881 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 709695 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 15472 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 981539 # Per bank write bursts 92system.physmem.perBankRdBursts::1 981448 # Per bank write bursts 93system.physmem.perBankRdBursts::2 981211 # Per bank write bursts 94system.physmem.perBankRdBursts::3 981521 # Per bank write bursts 95system.physmem.perBankRdBursts::4 988300 # Per bank write bursts 96system.physmem.perBankRdBursts::5 981533 # Per bank write bursts 97system.physmem.perBankRdBursts::6 981210 # Per bank write bursts 98system.physmem.perBankRdBursts::7 981071 # Per bank write bursts 99system.physmem.perBankRdBursts::8 981831 # Per bank write bursts 100system.physmem.perBankRdBursts::9 982015 # Per bank write bursts 101system.physmem.perBankRdBursts::10 981421 # Per bank write bursts 102system.physmem.perBankRdBursts::11 980878 # Per bank write bursts 103system.physmem.perBankRdBursts::12 981926 # Per bank write bursts 104system.physmem.perBankRdBursts::13 981948 # Per bank write bursts 105system.physmem.perBankRdBursts::14 981516 # Per bank write bursts 106system.physmem.perBankRdBursts::15 981038 # Per bank write bursts 107system.physmem.perBankWrBursts::0 7155 # Per bank write bursts 108system.physmem.perBankWrBursts::1 7293 # Per bank write bursts 109system.physmem.perBankWrBursts::2 6957 # Per bank write bursts 110system.physmem.perBankWrBursts::3 6994 # Per bank write bursts 111system.physmem.perBankWrBursts::4 7537 # Per bank write bursts 112system.physmem.perBankWrBursts::5 7187 # Per bank write bursts 113system.physmem.perBankWrBursts::6 7207 # Per bank write bursts 114system.physmem.perBankWrBursts::7 7058 # Per bank write bursts 115system.physmem.perBankWrBursts::8 7329 # Per bank write bursts 116system.physmem.perBankWrBursts::9 7596 # Per bank write bursts 117system.physmem.perBankWrBursts::10 7177 # Per bank write bursts 118system.physmem.perBankWrBursts::11 6681 # Per bank write bursts 119system.physmem.perBankWrBursts::12 7505 # Per bank write bursts 120system.physmem.perBankWrBursts::13 7329 # Per bank write bursts 121system.physmem.perBankWrBursts::14 7034 # Per bank write bursts 122system.physmem.perBankWrBursts::15 6715 # Per bank write bursts | 16system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 234148 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 830144 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu0.l2cache.prefetcher 9620672 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory 43system.physmem.bytes_read::cpu1.data 440928 # Number of bytes read from this memory 44system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365312 # Number of bytes read from this memory 45system.physmem.bytes_read::total 12542872 # Number of bytes read from this memory 46system.physmem.bytes_inst_read::cpu0.inst 234148 # Number of instructions bytes read from this memory 47system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory 48system.physmem.bytes_inst_read::total 284024 # Number of instructions bytes read from this memory 49system.physmem.bytes_written::writebacks 6392960 # Number of bytes written to this memory 50system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 51system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 52system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 53system.physmem.bytes_written::total 8729040 # Number of bytes written to this memory 54system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu0.inst 12112 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu0.data 13497 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu0.l2cache.prefetcher 150323 # Number of read requests responded to by this memory 60system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 61system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 62system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory 63system.physmem.num_reads::cpu1.data 6913 # Number of read requests responded to by this memory 64system.physmem.num_reads::cpu1.l2cache.prefetcher 21333 # Number of read requests responded to by this memory 65system.physmem.num_reads::total 205140 # Number of read requests responded to by this memory 66system.physmem.num_writes::writebacks 99890 # Number of write requests responded to by this memory 67system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 68system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 69system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 70system.physmem.num_writes::total 140550 # Number of write requests responded to by this memory 71system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::cpu0.inst 81672 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_read::cpu0.data 289559 # Total read bandwidth from this memory (bytes/s) 76system.physmem.bw_read::cpu0.l2cache.prefetcher 3355741 # Total read bandwidth from this memory (bytes/s) 77system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) 78system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) 79system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s) 80system.physmem.bw_read::cpu1.data 153798 # Total read bandwidth from this memory (bytes/s) 81system.physmem.bw_read::cpu1.l2cache.prefetcher 476228 # Total read bandwidth from this memory (bytes/s) 82system.physmem.bw_read::total 4375020 # Total read bandwidth from this memory (bytes/s) 83system.physmem.bw_inst_read::cpu0.inst 81672 # Instruction read bandwidth from this memory (bytes/s) 84system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s) 85system.physmem.bw_inst_read::total 99069 # Instruction read bandwidth from this memory (bytes/s) 86system.physmem.bw_write::writebacks 2229898 # Write bandwidth from this memory (bytes/s) 87system.physmem.bw_write::realview.ide 808648 # Write bandwidth from this memory (bytes/s) 88system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) 89system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 90system.physmem.bw_write::total 3044735 # Write bandwidth from this memory (bytes/s) 91system.physmem.bw_total::writebacks 2229898 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::realview.ide 808983 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 94system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 95system.physmem.bw_total::cpu0.inst 81672 # Total bandwidth to/from this memory (bytes/s) 96system.physmem.bw_total::cpu0.data 295734 # Total bandwidth to/from this memory (bytes/s) 97system.physmem.bw_total::cpu0.l2cache.prefetcher 3355741 # Total bandwidth to/from this memory (bytes/s) 98system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) 99system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) 100system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s) 101system.physmem.bw_total::cpu1.data 153812 # Total bandwidth to/from this memory (bytes/s) 102system.physmem.bw_total::cpu1.l2cache.prefetcher 476228 # Total bandwidth to/from this memory (bytes/s) 103system.physmem.bw_total::total 7419755 # Total bandwidth to/from this memory (bytes/s) 104system.physmem.readReqs 205141 # Number of read requests accepted 105system.physmem.writeReqs 140550 # Number of write requests accepted 106system.physmem.readBursts 205141 # Number of DRAM read bursts, including those serviced by the write queue 107system.physmem.writeBursts 140550 # Number of DRAM write bursts, including those merged in the write queue 108system.physmem.bytesReadDRAM 13114752 # Total number of bytes read from DRAM 109system.physmem.bytesReadWrQ 14272 # Total number of bytes read from write queue 110system.physmem.bytesWritten 8743552 # Total number of bytes written to DRAM 111system.physmem.bytesReadSys 12542936 # Total read bytes from the system interface side 112system.physmem.bytesWrittenSys 8729040 # Total written bytes from the system interface side 113system.physmem.servicedByWrQ 223 # Number of DRAM read bursts serviced by the write queue 114system.physmem.mergedWrBursts 3913 # Number of DRAM write bursts merged with an existing one 115system.physmem.neitherReadNorWriteReqs 15151 # Number of requests that are neither read nor write 116system.physmem.perBankRdBursts::0 12845 # Per bank write bursts 117system.physmem.perBankRdBursts::1 12298 # Per bank write bursts 118system.physmem.perBankRdBursts::2 13022 # Per bank write bursts 119system.physmem.perBankRdBursts::3 12754 # Per bank write bursts 120system.physmem.perBankRdBursts::4 21257 # Per bank write bursts 121system.physmem.perBankRdBursts::5 12515 # Per bank write bursts 122system.physmem.perBankRdBursts::6 12829 # Per bank write bursts 123system.physmem.perBankRdBursts::7 12945 # Per bank write bursts 124system.physmem.perBankRdBursts::8 12057 # Per bank write bursts 125system.physmem.perBankRdBursts::9 12100 # Per bank write bursts 126system.physmem.perBankRdBursts::10 12212 # Per bank write bursts 127system.physmem.perBankRdBursts::11 11004 # Per bank write bursts 128system.physmem.perBankRdBursts::12 11810 # Per bank write bursts 129system.physmem.perBankRdBursts::13 12145 # Per bank write bursts 130system.physmem.perBankRdBursts::14 11734 # Per bank write bursts 131system.physmem.perBankRdBursts::15 11391 # Per bank write bursts 132system.physmem.perBankWrBursts::0 8757 # Per bank write bursts 133system.physmem.perBankWrBursts::1 8655 # Per bank write bursts 134system.physmem.perBankWrBursts::2 9184 # Per bank write bursts 135system.physmem.perBankWrBursts::3 8823 # Per bank write bursts 136system.physmem.perBankWrBursts::4 8606 # Per bank write bursts 137system.physmem.perBankWrBursts::5 8736 # Per bank write bursts 138system.physmem.perBankWrBursts::6 8840 # Per bank write bursts 139system.physmem.perBankWrBursts::7 8881 # Per bank write bursts 140system.physmem.perBankWrBursts::8 8404 # Per bank write bursts 141system.physmem.perBankWrBursts::9 8549 # Per bank write bursts 142system.physmem.perBankWrBursts::10 8595 # Per bank write bursts 143system.physmem.perBankWrBursts::11 8133 # Per bank write bursts 144system.physmem.perBankWrBursts::12 8369 # Per bank write bursts 145system.physmem.perBankWrBursts::13 8306 # Per bank write bursts 146system.physmem.perBankWrBursts::14 8199 # Per bank write bursts 147system.physmem.perBankWrBursts::15 7581 # Per bank write bursts |
| 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 148system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 124system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 125system.physmem.totGap 2675178052500 # Total gap between requests | 149system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 150system.physmem.totGap 2866928814500 # Total gap between requests |
| 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) | 151system.physmem.readPktSize::0 0 # Read request sizes (log2) 152system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 128system.physmem.readPktSize::2 6799 # Read request sizes (log2) 129system.physmem.readPktSize::3 15532057 # Read request sizes (log2) | 153system.physmem.readPktSize::2 9742 # Read request sizes (log2) 154system.physmem.readPktSize::3 28 # Read request sizes (log2) |
| 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) | 155system.physmem.readPktSize::4 0 # Read request sizes (log2) 156system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 132system.physmem.readPktSize::6 173431 # Read request sizes (log2) | 157system.physmem.readPktSize::6 195371 # Read request sizes (log2) |
| 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) | 158system.physmem.writePktSize::0 0 # Write request sizes (log2) 159system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| 135system.physmem.writePktSize::2 757284 # Write request sizes (log2) | 160system.physmem.writePktSize::2 4436 # Write request sizes (log2) |
| 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) | 161system.physmem.writePktSize::3 0 # Write request sizes (log2) 162system.physmem.writePktSize::4 0 # Write request sizes (log2) 163system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 139system.physmem.writePktSize::6 67188 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 1100287 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 996591 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 996926 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 1111424 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 1006011 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 1072049 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 2766642 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 2669294 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3474563 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 133275 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 114946 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 106575 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 103058 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 20020 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 19187 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 18941 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 126 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 60 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 35 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 28 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 23 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see | 164system.physmem.writePktSize::6 136114 # Write request sizes (log2) 165system.physmem.rdQLenPdf::0 121124 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::1 21708 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::2 13339 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::3 11204 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::4 9572 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::5 8231 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::6 7040 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::7 6218 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::8 5357 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::9 501 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::11 142 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::13 64 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::15 26 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 190system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 191system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 192system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 193system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 194system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 195system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 196system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 197system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::15 4098 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 4127 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 4820 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 5767 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 6235 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6391 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 6628 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 6692 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 6804 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 6950 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 7066 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 7169 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 7372 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 7024 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 7083 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 52 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 1051606 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 963.108084 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 883.927529 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 220.726845 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 33004 3.14% 3.14% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 22001 2.09% 5.23% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 9307 0.89% 6.12% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 2514 0.24% 6.35% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 3272 0.31% 6.67% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 2167 0.21% 6.87% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 8722 0.83% 7.70% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 1051 0.10% 7.80% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 969568 92.20% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 1051606 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6601 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 2380.003939 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 98592.588392 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-262143 6595 99.91% 99.91% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::total 6601 # Reads before turning the bus around for writes 260system.physmem.wrPerTurnAround::samples 6601 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::mean 17.384336 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::gmean 17.341066 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::stdev 1.250693 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::16 2463 37.31% 37.31% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::17 32 0.48% 37.80% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::18 3686 55.84% 93.64% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::19 215 3.26% 96.89% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20 85 1.29% 98.18% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::21 50 0.76% 98.94% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::22 28 0.42% 99.36% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::24 14 0.21% 99.85% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::25 7 0.11% 99.95% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::total 6601 # Writes before turning the bus around for reads 276system.physmem.totQLat 408788863752 # Total ticks spent queuing 277system.physmem.totMemAccLat 703358976252 # Total ticks spent from burst creation until serviced by the DRAM 278system.physmem.totBusLat 78552030000 # Total ticks spent in databus transfers 279system.physmem.avgQLat 26020.26 # Average queueing delay per DRAM burst | 212system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::16 3287 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::17 4176 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::18 5630 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::19 6226 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::21 7608 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::22 8446 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::23 9168 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::24 10203 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::25 9843 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::26 9504 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::27 9253 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::28 9714 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::30 7664 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::31 7594 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::32 7157 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::33 408 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::34 309 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::39 181 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::41 152 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::43 141 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see 246system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::50 77 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see 249system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see 250system.physmem.wrQLenPdf::53 41 # What write queue length does an incoming req see 251system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see 252system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see 253system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see 254system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see 255system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see 256system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see 257system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see 258system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see 259system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see 260system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 261system.physmem.bytesPerActivate::samples 80974 # Bytes accessed per row activation 262system.physmem.bytesPerActivate::mean 269.941463 # Bytes accessed per row activation 263system.physmem.bytesPerActivate::gmean 151.852686 # Bytes accessed per row activation 264system.physmem.bytesPerActivate::stdev 318.869933 # Bytes accessed per row activation 265system.physmem.bytesPerActivate::0-127 39277 48.51% 48.51% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::128-255 16073 19.85% 68.36% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::256-383 6267 7.74% 76.09% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::384-511 3406 4.21% 80.30% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::512-639 3201 3.95% 84.25% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::640-767 1947 2.40% 86.66% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::768-895 1140 1.41% 88.07% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::896-1023 1004 1.24% 89.31% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::1024-1151 8659 10.69% 100.00% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::total 80974 # Bytes accessed per row activation 275system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes 276system.physmem.rdPerTurnAround::mean 30.475461 # Reads before turning the bus around for writes 277system.physmem.rdPerTurnAround::stdev 574.843547 # Reads before turning the bus around for writes 278system.physmem.rdPerTurnAround::0-2047 6723 99.99% 99.99% # Reads before turning the bus around for writes 279system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 280system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes 281system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::mean 20.317965 # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::gmean 18.827449 # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::stdev 11.656598 # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::16-19 5486 81.59% 81.59% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::20-23 426 6.34% 87.92% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::24-27 82 1.22% 89.14% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::28-31 201 2.99% 92.13% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::32-35 197 2.93% 95.06% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::36-39 21 0.31% 95.37% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::40-43 19 0.28% 95.66% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::44-47 16 0.24% 95.90% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::48-51 29 0.43% 96.33% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::52-55 5 0.07% 96.40% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::56-59 4 0.06% 96.46% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::60-63 3 0.04% 96.51% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::64-67 175 2.60% 99.11% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::68-71 8 0.12% 99.23% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::72-75 7 0.10% 99.33% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::76-79 4 0.06% 99.39% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::80-83 7 0.10% 99.49% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::88-91 2 0.03% 99.55% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::96-99 6 0.09% 99.64% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::104-107 1 0.01% 99.69% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::108-111 2 0.03% 99.72% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::112-115 4 0.06% 99.78% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::116-119 3 0.04% 99.82% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads 314system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads 315system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads 316system.physmem.totQLat 5972474500 # Total ticks spent queuing 317system.physmem.totMemAccLat 9814687000 # Total ticks spent from burst creation until serviced by the DRAM 318system.physmem.totBusLat 1024590000 # Total ticks spent in databus transfers 319system.physmem.avgQLat 29145.68 # Average queueing delay per DRAM burst |
| 280system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 320system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 281system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst 282system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s 283system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s 284system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s 285system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s | 321system.physmem.avgMemAccLat 47895.68 # Average memory access latency per DRAM burst 322system.physmem.avgRdBW 4.57 # Average DRAM read bandwidth in MiByte/s 323system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 324system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s 325system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s |
| 286system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 326system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 287system.physmem.busUtil 2.96 # Data bus utilization in percentage 288system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads | 327system.physmem.busUtil 0.06 # Data bus utilization in percentage 328system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads |
| 289system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 329system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 290system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing 291system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing 292system.physmem.readRowHits 14689438 # Number of row buffer hits during reads 293system.physmem.writeRowHits 84116 # Number of row buffer hits during writes 294system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 295system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes 296system.physmem.avgGap 161771.61 # Average gap between requests 297system.physmem.pageHitRate 93.35 # Row buffer hit rate, read and write combined 298system.physmem.memoryStateTime::IDLE 2326940534750 # Time in different power states 299system.physmem.memoryStateTime::REF 89330020000 # Time in different power states | 330system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing 331system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing 332system.physmem.readRowHits 175001 # Number of row buffer hits during reads 333system.physmem.writeRowHits 85560 # Number of row buffer hits during writes 334system.physmem.readRowHitRate 85.40 # Row buffer hit rate for reads 335system.physmem.writeRowHitRate 62.62 # Row buffer hit rate for writes 336system.physmem.avgGap 8293327.90 # Average gap between requests 337system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined 338system.physmem.memoryStateTime::IDLE 2731384342500 # Time in different power states 339system.physmem.memoryStateTime::REF 95733040000 # Time in different power states |
| 300system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 340system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 301system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states | 341system.physmem.memoryStateTime::ACT 39811853000 # Time in different power states |
| 302system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 342system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.physmem.actEnergy::0 3975289920 # Energy for activate commands per rank (pJ) 304system.physmem.actEnergy::1 3974851440 # Energy for activate commands per rank (pJ) 305system.physmem.preEnergy::0 2169057000 # Energy for precharge commands per rank (pJ) 306system.physmem.preEnergy::1 2168817750 # Energy for precharge commands per rank (pJ) 307system.physmem.readEnergy::0 61291097400 # Energy for read commands per rank (pJ) 308system.physmem.readEnergy::1 61250069400 # Energy for read commands per rank (pJ) 309system.physmem.writeEnergy::0 371874240 # Energy for write commands per rank (pJ) 310system.physmem.writeEnergy::1 371731680 # Energy for write commands per rank (pJ) 311system.physmem.refreshEnergy::0 174729519120 # Energy for refresh commands per rank (pJ) 312system.physmem.refreshEnergy::1 174729519120 # Energy for refresh commands per rank (pJ) 313system.physmem.actBackEnergy::0 149034867885 # Energy for active background per rank (pJ) 314system.physmem.actBackEnergy::1 147923300340 # Energy for active background per rank (pJ) 315system.physmem.preBackEnergy::0 1474373657250 # Energy for precharge background per rank (pJ) 316system.physmem.preBackEnergy::1 1475348716500 # Energy for precharge background per rank (pJ) 317system.physmem.totalEnergy::0 1865945362815 # Total energy per rank (pJ) 318system.physmem.totalEnergy::1 1865767006230 # Total energy per rank (pJ) 319system.physmem.averagePower::0 697.503604 # Core power per rank (mW) 320system.physmem.averagePower::1 697.436933 # Core power per rank (mW) 321system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 324system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 325system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 326system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 327system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 328system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 329system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 330system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 337system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) 338system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 339system.membus.trans_dist::ReadReq 16891737 # Transaction distribution 340system.membus.trans_dist::ReadResp 16891737 # Transaction distribution 341system.membus.trans_dist::WriteReq 769090 # Transaction distribution 342system.membus.trans_dist::WriteResp 769090 # Transaction distribution 343system.membus.trans_dist::Writeback 67188 # Transaction distribution 344system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution 345system.membus.trans_dist::SCUpgradeReq 22757 # Transaction distribution 346system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution 347system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 348system.membus.trans_dist::ReadExReq 15580 # Transaction distribution 349system.membus.trans_dist::ReadExResp 8709 # Transaction distribution 350system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384390 # Packet count per connected master and slave (bytes) 351system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 352system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13404 # Packet count per connected master and slave (bytes) 353system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 354system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes) 355system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes) 356system.membus.pkt_count_system.l2c.mem_side::total 4443432 # Packet count per connected master and slave (bytes) 357system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) 358system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) 359system.membus.pkt_count::total 35507496 # Packet count per connected master and slave (bytes) 360system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392696 # Cumulative packet size per connected master and slave (bytes) 361system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 362system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26808 # Cumulative packet size per connected master and slave (bytes) 363system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 364system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4196 # Cumulative packet size per connected master and slave (bytes) 365system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18456148 # Cumulative packet size per connected master and slave (bytes) 366system.membus.pkt_size_system.l2c.mem_side::total 20879924 # Cumulative packet size per connected master and slave (bytes) 367system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) 368system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) 369system.membus.pkt_size::total 145136180 # Cumulative packet size per connected master and slave (bytes) 370system.membus.snoops 70292 # Total snoops (count) 371system.membus.snoop_fanout::samples 326383 # Request fanout histogram | 343system.physmem.actEnergy::0 323167320 # Energy for activate commands per rank (pJ) 344system.physmem.actEnergy::1 288996120 # Energy for activate commands per rank (pJ) 345system.physmem.preEnergy::0 176331375 # Energy for precharge commands per rank (pJ) 346system.physmem.preEnergy::1 157686375 # Energy for precharge commands per rank (pJ) 347system.physmem.readEnergy::0 861627000 # Energy for read commands per rank (pJ) 348system.physmem.readEnergy::1 736725600 # Energy for read commands per rank (pJ) 349system.physmem.writeEnergy::0 456723360 # Energy for write commands per rank (pJ) 350system.physmem.writeEnergy::1 428561280 # Energy for write commands per rank (pJ) 351system.physmem.refreshEnergy::0 187253826240 # Energy for refresh commands per rank (pJ) 352system.physmem.refreshEnergy::1 187253826240 # Energy for refresh commands per rank (pJ) 353system.physmem.actBackEnergy::0 82374692850 # Energy for active background per rank (pJ) 354system.physmem.actBackEnergy::1 81185757210 # Energy for active background per rank (pJ) 355system.physmem.preBackEnergy::0 1647898682250 # Energy for precharge background per rank (pJ) 356system.physmem.preBackEnergy::1 1648941608250 # Energy for precharge background per rank (pJ) 357system.physmem.totalEnergy::0 1919345050395 # Total energy per rank (pJ) 358system.physmem.totalEnergy::1 1918993161075 # Total energy per rank (pJ) 359system.physmem.averagePower::0 669.477790 # Core power per rank (mW) 360system.physmem.averagePower::1 669.355049 # Core power per rank (mW) 361system.membus.trans_dist::ReadReq 228441 # Transaction distribution 362system.membus.trans_dist::ReadResp 228440 # Transaction distribution 363system.membus.trans_dist::WriteReq 31177 # Transaction distribution 364system.membus.trans_dist::WriteResp 31177 # Transaction distribution 365system.membus.trans_dist::Writeback 99890 # Transaction distribution 366system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 367system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 368system.membus.trans_dist::UpgradeReq 85859 # Transaction distribution 369system.membus.trans_dist::SCUpgradeReq 41212 # Transaction distribution 370system.membus.trans_dist::UpgradeResp 15151 # Transaction distribution 371system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 372system.membus.trans_dist::ReadExReq 28398 # Transaction distribution 373system.membus.trans_dist::ReadExResp 11478 # Transaction distribution 374system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes) 375system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) 376system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14560 # Packet count per connected master and slave (bytes) 377system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678158 # Packet count per connected master and slave (bytes) 378system.membus.pkt_count_system.l2c.mem_side::total 800720 # Packet count per connected master and slave (bytes) 379system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes) 380system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes) 381system.membus.pkt_count::total 873436 # Packet count per connected master and slave (bytes) 382system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes) 383system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) 384system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29120 # Cumulative packet size per connected master and slave (bytes) 385system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18952616 # Cumulative packet size per connected master and slave (bytes) 386system.membus.pkt_size_system.l2c.mem_side::total 19144659 # Cumulative packet size per connected master and slave (bytes) 387system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 388system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 389system.membus.pkt_size::total 21463955 # Cumulative packet size per connected master and slave (bytes) 390system.membus.snoops 129081 # Total snoops (count) 391system.membus.snoop_fanout::samples 475718 # Request fanout histogram |
| 372system.membus.snoop_fanout::mean 1 # Request fanout histogram 373system.membus.snoop_fanout::stdev 0 # Request fanout histogram 374system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 375system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 392system.membus.snoop_fanout::mean 1 # Request fanout histogram 393system.membus.snoop_fanout::stdev 0 # Request fanout histogram 394system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 395system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 376system.membus.snoop_fanout::1 326383 100.00% 100.00% # Request fanout histogram | 396system.membus.snoop_fanout::1 475718 100.00% 100.00% # Request fanout histogram |
| 377system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 378system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 379system.membus.snoop_fanout::min_value 1 # Request fanout histogram 380system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 397system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 398system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 399system.membus.snoop_fanout::min_value 1 # Request fanout histogram 400system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 381system.membus.snoop_fanout::total 326383 # Request fanout histogram 382system.membus.reqLayer0.occupancy 1567209495 # Layer occupancy (ticks) 383system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 384system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) | 401system.membus.snoop_fanout::total 475718 # Request fanout histogram 402system.membus.reqLayer0.occupancy 88161999 # Layer occupancy (ticks) 403system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 404system.membus.reqLayer1.occupancy 20500 # Layer occupancy (ticks) |
| 385system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 405system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 386system.membus.reqLayer2.occupancy 11789999 # Layer occupancy (ticks) | 406system.membus.reqLayer2.occupancy 12079498 # Layer occupancy (ticks) |
| 387system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 407system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 388system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 389system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 390system.membus.reqLayer5.occupancy 2092500 # Layer occupancy (ticks) 391system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 392system.membus.reqLayer6.occupancy 18080219999 # Layer occupancy (ticks) 393system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 394system.membus.respLayer1.occupancy 4994463970 # Layer occupancy (ticks) 395system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 396system.membus.respLayer2.occupancy 38410223885 # Layer occupancy (ticks) 397system.membus.respLayer2.utilization 1.4 # Layer utilization (%) | 408system.membus.reqLayer5.occupancy 1514580499 # Layer occupancy (ticks) 409system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 410system.membus.respLayer2.occupancy 1969894164 # Layer occupancy (ticks) 411system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 412system.membus.respLayer3.occupancy 38592409 # Layer occupancy (ticks) 413system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 398system.cpu_clk_domain.clock 500 # Clock period in ticks | 414system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 399system.l2c.tags.replacements 91391 # number of replacements 400system.l2c.tags.tagsinuse 54779.294121 # Cycle average of tags in use 401system.l2c.tags.total_refs 364235 # Total number of references to valid blocks. 402system.l2c.tags.sampled_refs 156090 # Sample count of references to valid blocks. 403system.l2c.tags.avg_refs 2.333493 # Average number of references to valid blocks. | 415system.l2c.tags.replacements 132728 # number of replacements 416system.l2c.tags.tagsinuse 64199.829322 # Cycle average of tags in use 417system.l2c.tags.total_refs 489645 # Total number of references to valid blocks. 418system.l2c.tags.sampled_refs 197292 # Sample count of references to valid blocks. 419system.l2c.tags.avg_refs 2.481829 # Average number of references to valid blocks. |
| 404system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 420system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 405system.l2c.tags.occ_blocks::writebacks 8096.170170 # Average occupied blocks per requestor 406system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.060665 # Average occupied blocks per requestor 407system.l2c.tags.occ_blocks::cpu0.itb.walker 1.035962 # Average occupied blocks per requestor 408system.l2c.tags.occ_blocks::cpu0.inst 869.411373 # Average occupied blocks per requestor 409system.l2c.tags.occ_blocks::cpu0.data 1869.125081 # Average occupied blocks per requestor 410system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218 # Average occupied blocks per requestor 411system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.888363 # Average occupied blocks per requestor 412system.l2c.tags.occ_blocks::cpu1.inst 410.348906 # Average occupied blocks per requestor 413system.l2c.tags.occ_blocks::cpu1.data 3214.362362 # Average occupied blocks per requestor 414system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021 # Average occupied blocks per requestor 415system.l2c.tags.occ_percent::writebacks 0.123538 # Average percentage of cache occupancy 416system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy 417system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 418system.l2c.tags.occ_percent::cpu0.inst 0.013266 # Average percentage of cache occupancy 419system.l2c.tags.occ_percent::cpu0.data 0.028521 # Average percentage of cache occupancy 420system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.446737 # Average percentage of cache occupancy 421system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy 422system.l2c.tags.occ_percent::cpu1.inst 0.006261 # Average percentage of cache occupancy 423system.l2c.tags.occ_percent::cpu1.data 0.049047 # Average percentage of cache occupancy 424system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.168450 # Average percentage of cache occupancy 425system.l2c.tags.occ_percent::total 0.835866 # Average percentage of cache occupancy 426system.l2c.tags.occ_task_id_blocks::1022 51568 # Occupied blocks per task id 427system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 428system.l2c.tags.occ_task_id_blocks::1024 13123 # Occupied blocks per task id 429system.l2c.tags.age_task_id_blocks_1022::2 28 # Occupied blocks per task id 430system.l2c.tags.age_task_id_blocks_1022::3 4964 # Occupied blocks per task id 431system.l2c.tags.age_task_id_blocks_1022::4 46576 # Occupied blocks per task id 432system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 433system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 434system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 435system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 436system.l2c.tags.age_task_id_blocks_1024::2 213 # Occupied blocks per task id 437system.l2c.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id 438system.l2c.tags.age_task_id_blocks_1024::4 11561 # Occupied blocks per task id 439system.l2c.tags.occ_task_id_percent::1022 0.786865 # Percentage of cache occupancy per task id 440system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 441system.l2c.tags.occ_task_id_percent::1024 0.200241 # Percentage of cache occupancy per task id 442system.l2c.tags.tag_accesses 4855174 # Number of tag accesses 443system.l2c.tags.data_accesses 4855174 # Number of data accesses 444system.l2c.ReadReq_hits::cpu0.dtb.walker 111 # number of ReadReq hits 445system.l2c.ReadReq_hits::cpu0.itb.walker 56 # number of ReadReq hits 446system.l2c.ReadReq_hits::cpu0.inst 5971 # number of ReadReq hits 447system.l2c.ReadReq_hits::cpu0.data 15212 # number of ReadReq hits 448system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88244 # number of ReadReq hits 449system.l2c.ReadReq_hits::cpu1.dtb.walker 87 # number of ReadReq hits 450system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits 451system.l2c.ReadReq_hits::cpu1.inst 4855 # number of ReadReq hits 452system.l2c.ReadReq_hits::cpu1.data 12536 # number of ReadReq hits 453system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47744 # number of ReadReq hits 454system.l2c.ReadReq_hits::total 174841 # number of ReadReq hits 455system.l2c.Writeback_hits::writebacks 208041 # number of Writeback hits 456system.l2c.Writeback_hits::total 208041 # number of Writeback hits 457system.l2c.UpgradeReq_hits::cpu0.data 3552 # number of UpgradeReq hits 458system.l2c.UpgradeReq_hits::cpu1.data 1697 # number of UpgradeReq hits 459system.l2c.UpgradeReq_hits::total 5249 # number of UpgradeReq hits 460system.l2c.SCUpgradeReq_hits::cpu0.data 114 # number of SCUpgradeReq hits 461system.l2c.SCUpgradeReq_hits::cpu1.data 201 # number of SCUpgradeReq hits 462system.l2c.SCUpgradeReq_hits::total 315 # number of SCUpgradeReq hits 463system.l2c.ReadExReq_hits::cpu0.data 2350 # number of ReadExReq hits 464system.l2c.ReadExReq_hits::cpu1.data 2153 # number of ReadExReq hits 465system.l2c.ReadExReq_hits::total 4503 # number of ReadExReq hits 466system.l2c.demand_hits::cpu0.dtb.walker 111 # number of demand (read+write) hits 467system.l2c.demand_hits::cpu0.itb.walker 56 # number of demand (read+write) hits 468system.l2c.demand_hits::cpu0.inst 5971 # number of demand (read+write) hits 469system.l2c.demand_hits::cpu0.data 17562 # number of demand (read+write) hits 470system.l2c.demand_hits::cpu0.l2cache.prefetcher 88244 # number of demand (read+write) hits 471system.l2c.demand_hits::cpu1.dtb.walker 87 # number of demand (read+write) hits 472system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits 473system.l2c.demand_hits::cpu1.inst 4855 # number of demand (read+write) hits 474system.l2c.demand_hits::cpu1.data 14689 # number of demand (read+write) hits 475system.l2c.demand_hits::cpu1.l2cache.prefetcher 47744 # number of demand (read+write) hits 476system.l2c.demand_hits::total 179344 # number of demand (read+write) hits 477system.l2c.overall_hits::cpu0.dtb.walker 111 # number of overall hits 478system.l2c.overall_hits::cpu0.itb.walker 56 # number of overall hits 479system.l2c.overall_hits::cpu0.inst 5971 # number of overall hits 480system.l2c.overall_hits::cpu0.data 17562 # number of overall hits 481system.l2c.overall_hits::cpu0.l2cache.prefetcher 88244 # number of overall hits 482system.l2c.overall_hits::cpu1.dtb.walker 87 # number of overall hits 483system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits 484system.l2c.overall_hits::cpu1.inst 4855 # number of overall hits 485system.l2c.overall_hits::cpu1.data 14689 # number of overall hits 486system.l2c.overall_hits::cpu1.l2cache.prefetcher 47744 # number of overall hits 487system.l2c.overall_hits::total 179344 # number of overall hits 488system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses 489system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 490system.l2c.ReadReq_misses::cpu0.inst 1474 # number of ReadReq misses 491system.l2c.ReadReq_misses::cpu0.data 3581 # number of ReadReq misses 492system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 104062 # number of ReadReq misses 493system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses 494system.l2c.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses 495system.l2c.ReadReq_misses::cpu1.data 4041 # number of ReadReq misses 496system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 50971 # number of ReadReq misses 497system.l2c.ReadReq_misses::total 164723 # number of ReadReq misses 498system.l2c.UpgradeReq_misses::cpu0.data 7774 # number of UpgradeReq misses 499system.l2c.UpgradeReq_misses::cpu1.data 5401 # number of UpgradeReq misses 500system.l2c.UpgradeReq_misses::total 13175 # number of UpgradeReq misses 501system.l2c.SCUpgradeReq_misses::cpu0.data 1167 # number of SCUpgradeReq misses 502system.l2c.SCUpgradeReq_misses::cpu1.data 1038 # number of SCUpgradeReq misses 503system.l2c.SCUpgradeReq_misses::total 2205 # number of SCUpgradeReq misses 504system.l2c.ReadExReq_misses::cpu0.data 4506 # number of ReadExReq misses 505system.l2c.ReadExReq_misses::cpu1.data 4295 # number of ReadExReq misses 506system.l2c.ReadExReq_misses::total 8801 # number of ReadExReq misses 507system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses 508system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 509system.l2c.demand_misses::cpu0.inst 1474 # number of demand (read+write) misses 510system.l2c.demand_misses::cpu0.data 8087 # number of demand (read+write) misses 511system.l2c.demand_misses::cpu0.l2cache.prefetcher 104062 # number of demand (read+write) misses 512system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses 513system.l2c.demand_misses::cpu1.inst 586 # number of demand (read+write) misses 514system.l2c.demand_misses::cpu1.data 8336 # number of demand (read+write) misses 515system.l2c.demand_misses::cpu1.l2cache.prefetcher 50971 # number of demand (read+write) misses 516system.l2c.demand_misses::total 173524 # number of demand (read+write) misses 517system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses 518system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 519system.l2c.overall_misses::cpu0.inst 1474 # number of overall misses 520system.l2c.overall_misses::cpu0.data 8087 # number of overall misses 521system.l2c.overall_misses::cpu0.l2cache.prefetcher 104062 # number of overall misses 522system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses 523system.l2c.overall_misses::cpu1.inst 586 # number of overall misses 524system.l2c.overall_misses::cpu1.data 8336 # number of overall misses 525system.l2c.overall_misses::cpu1.l2cache.prefetcher 50971 # number of overall misses 526system.l2c.overall_misses::total 173524 # number of overall misses 527system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 107000 # number of ReadReq miss cycles 528system.l2c.ReadReq_miss_latency::cpu0.itb.walker 298500 # number of ReadReq miss cycles 529system.l2c.ReadReq_miss_latency::cpu0.inst 119004500 # number of ReadReq miss cycles 530system.l2c.ReadReq_miss_latency::cpu0.data 272579750 # number of ReadReq miss cycles 531system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of ReadReq miss cycles 532system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 164250 # number of ReadReq miss cycles 533system.l2c.ReadReq_miss_latency::cpu1.inst 50120250 # number of ReadReq miss cycles 534system.l2c.ReadReq_miss_latency::cpu1.data 314939500 # number of ReadReq miss cycles 535system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of ReadReq miss cycles 536system.l2c.ReadReq_miss_latency::total 15882327372 # number of ReadReq miss cycles 537system.l2c.UpgradeReq_miss_latency::cpu0.data 13917901 # number of UpgradeReq miss cycles 538system.l2c.UpgradeReq_miss_latency::cpu1.data 3379857 # number of UpgradeReq miss cycles 539system.l2c.UpgradeReq_miss_latency::total 17297758 # number of UpgradeReq miss cycles 540system.l2c.SCUpgradeReq_miss_latency::cpu0.data 704472 # number of SCUpgradeReq miss cycles 541system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4360812 # number of SCUpgradeReq miss cycles 542system.l2c.SCUpgradeReq_miss_latency::total 5065284 # number of SCUpgradeReq miss cycles 543system.l2c.ReadExReq_miss_latency::cpu0.data 330076436 # number of ReadExReq miss cycles 544system.l2c.ReadExReq_miss_latency::cpu1.data 308773222 # number of ReadExReq miss cycles 545system.l2c.ReadExReq_miss_latency::total 638849658 # number of ReadExReq miss cycles 546system.l2c.demand_miss_latency::cpu0.dtb.walker 107000 # number of demand (read+write) miss cycles 547system.l2c.demand_miss_latency::cpu0.itb.walker 298500 # number of demand (read+write) miss cycles 548system.l2c.demand_miss_latency::cpu0.inst 119004500 # number of demand (read+write) miss cycles 549system.l2c.demand_miss_latency::cpu0.data 602656186 # number of demand (read+write) miss cycles 550system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of demand (read+write) miss cycles 551system.l2c.demand_miss_latency::cpu1.dtb.walker 164250 # number of demand (read+write) miss cycles 552system.l2c.demand_miss_latency::cpu1.inst 50120250 # number of demand (read+write) miss cycles 553system.l2c.demand_miss_latency::cpu1.data 623712722 # number of demand (read+write) miss cycles 554system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of demand (read+write) miss cycles 555system.l2c.demand_miss_latency::total 16521177030 # number of demand (read+write) miss cycles 556system.l2c.overall_miss_latency::cpu0.dtb.walker 107000 # number of overall miss cycles 557system.l2c.overall_miss_latency::cpu0.itb.walker 298500 # number of overall miss cycles 558system.l2c.overall_miss_latency::cpu0.inst 119004500 # number of overall miss cycles 559system.l2c.overall_miss_latency::cpu0.data 602656186 # number of overall miss cycles 560system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of overall miss cycles 561system.l2c.overall_miss_latency::cpu1.dtb.walker 164250 # number of overall miss cycles 562system.l2c.overall_miss_latency::cpu1.inst 50120250 # number of overall miss cycles 563system.l2c.overall_miss_latency::cpu1.data 623712722 # number of overall miss cycles 564system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of overall miss cycles 565system.l2c.overall_miss_latency::total 16521177030 # number of overall miss cycles 566system.l2c.ReadReq_accesses::cpu0.dtb.walker 113 # number of ReadReq accesses(hits+misses) 567system.l2c.ReadReq_accesses::cpu0.itb.walker 60 # number of ReadReq accesses(hits+misses) 568system.l2c.ReadReq_accesses::cpu0.inst 7445 # number of ReadReq accesses(hits+misses) 569system.l2c.ReadReq_accesses::cpu0.data 18793 # number of ReadReq accesses(hits+misses) 570system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 192306 # number of ReadReq accesses(hits+misses) 571system.l2c.ReadReq_accesses::cpu1.dtb.walker 89 # number of ReadReq accesses(hits+misses) 572system.l2c.ReadReq_accesses::cpu1.itb.walker 25 # number of ReadReq accesses(hits+misses) 573system.l2c.ReadReq_accesses::cpu1.inst 5441 # number of ReadReq accesses(hits+misses) 574system.l2c.ReadReq_accesses::cpu1.data 16577 # number of ReadReq accesses(hits+misses) 575system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 98715 # number of ReadReq accesses(hits+misses) 576system.l2c.ReadReq_accesses::total 339564 # number of ReadReq accesses(hits+misses) 577system.l2c.Writeback_accesses::writebacks 208041 # number of Writeback accesses(hits+misses) 578system.l2c.Writeback_accesses::total 208041 # number of Writeback accesses(hits+misses) 579system.l2c.UpgradeReq_accesses::cpu0.data 11326 # number of UpgradeReq accesses(hits+misses) 580system.l2c.UpgradeReq_accesses::cpu1.data 7098 # number of UpgradeReq accesses(hits+misses) 581system.l2c.UpgradeReq_accesses::total 18424 # number of UpgradeReq accesses(hits+misses) 582system.l2c.SCUpgradeReq_accesses::cpu0.data 1281 # number of SCUpgradeReq accesses(hits+misses) 583system.l2c.SCUpgradeReq_accesses::cpu1.data 1239 # number of SCUpgradeReq accesses(hits+misses) 584system.l2c.SCUpgradeReq_accesses::total 2520 # number of SCUpgradeReq accesses(hits+misses) 585system.l2c.ReadExReq_accesses::cpu0.data 6856 # number of ReadExReq accesses(hits+misses) 586system.l2c.ReadExReq_accesses::cpu1.data 6448 # number of ReadExReq accesses(hits+misses) 587system.l2c.ReadExReq_accesses::total 13304 # number of ReadExReq accesses(hits+misses) 588system.l2c.demand_accesses::cpu0.dtb.walker 113 # number of demand (read+write) accesses 589system.l2c.demand_accesses::cpu0.itb.walker 60 # number of demand (read+write) accesses 590system.l2c.demand_accesses::cpu0.inst 7445 # number of demand (read+write) accesses 591system.l2c.demand_accesses::cpu0.data 25649 # number of demand (read+write) accesses 592system.l2c.demand_accesses::cpu0.l2cache.prefetcher 192306 # number of demand (read+write) accesses 593system.l2c.demand_accesses::cpu1.dtb.walker 89 # number of demand (read+write) accesses 594system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses 595system.l2c.demand_accesses::cpu1.inst 5441 # number of demand (read+write) accesses 596system.l2c.demand_accesses::cpu1.data 23025 # number of demand (read+write) accesses 597system.l2c.demand_accesses::cpu1.l2cache.prefetcher 98715 # number of demand (read+write) accesses 598system.l2c.demand_accesses::total 352868 # number of demand (read+write) accesses 599system.l2c.overall_accesses::cpu0.dtb.walker 113 # number of overall (read+write) accesses 600system.l2c.overall_accesses::cpu0.itb.walker 60 # number of overall (read+write) accesses 601system.l2c.overall_accesses::cpu0.inst 7445 # number of overall (read+write) accesses 602system.l2c.overall_accesses::cpu0.data 25649 # number of overall (read+write) accesses 603system.l2c.overall_accesses::cpu0.l2cache.prefetcher 192306 # number of overall (read+write) accesses 604system.l2c.overall_accesses::cpu1.dtb.walker 89 # number of overall (read+write) accesses 605system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses 606system.l2c.overall_accesses::cpu1.inst 5441 # number of overall (read+write) accesses 607system.l2c.overall_accesses::cpu1.data 23025 # number of overall (read+write) accesses 608system.l2c.overall_accesses::cpu1.l2cache.prefetcher 98715 # number of overall (read+write) accesses 609system.l2c.overall_accesses::total 352868 # number of overall (read+write) accesses 610system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for ReadReq accesses 611system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.066667 # miss rate for ReadReq accesses 612system.l2c.ReadReq_miss_rate::cpu0.inst 0.197985 # miss rate for ReadReq accesses 613system.l2c.ReadReq_miss_rate::cpu0.data 0.190550 # miss rate for ReadReq accesses 614system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for ReadReq accesses 615system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for ReadReq accesses 616system.l2c.ReadReq_miss_rate::cpu1.inst 0.107701 # miss rate for ReadReq accesses 617system.l2c.ReadReq_miss_rate::cpu1.data 0.243771 # miss rate for ReadReq accesses 618system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for ReadReq accesses 619system.l2c.ReadReq_miss_rate::total 0.485101 # miss rate for ReadReq accesses 620system.l2c.UpgradeReq_miss_rate::cpu0.data 0.686385 # miss rate for UpgradeReq accesses 621system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760919 # miss rate for UpgradeReq accesses 622system.l2c.UpgradeReq_miss_rate::total 0.715100 # miss rate for UpgradeReq accesses 623system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.911007 # miss rate for SCUpgradeReq accesses 624system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.837772 # miss rate for SCUpgradeReq accesses 625system.l2c.SCUpgradeReq_miss_rate::total 0.875000 # miss rate for SCUpgradeReq accesses 626system.l2c.ReadExReq_miss_rate::cpu0.data 0.657235 # miss rate for ReadExReq accesses 627system.l2c.ReadExReq_miss_rate::cpu1.data 0.666098 # miss rate for ReadExReq accesses 628system.l2c.ReadExReq_miss_rate::total 0.661530 # miss rate for ReadExReq accesses 629system.l2c.demand_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for demand accesses 630system.l2c.demand_miss_rate::cpu0.itb.walker 0.066667 # miss rate for demand accesses 631system.l2c.demand_miss_rate::cpu0.inst 0.197985 # miss rate for demand accesses 632system.l2c.demand_miss_rate::cpu0.data 0.315295 # miss rate for demand accesses 633system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for demand accesses 634system.l2c.demand_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for demand accesses 635system.l2c.demand_miss_rate::cpu1.inst 0.107701 # miss rate for demand accesses 636system.l2c.demand_miss_rate::cpu1.data 0.362041 # miss rate for demand accesses 637system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for demand accesses 638system.l2c.demand_miss_rate::total 0.491753 # miss rate for demand accesses 639system.l2c.overall_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for overall accesses 640system.l2c.overall_miss_rate::cpu0.itb.walker 0.066667 # miss rate for overall accesses 641system.l2c.overall_miss_rate::cpu0.inst 0.197985 # miss rate for overall accesses 642system.l2c.overall_miss_rate::cpu0.data 0.315295 # miss rate for overall accesses 643system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for overall accesses 644system.l2c.overall_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for overall accesses 645system.l2c.overall_miss_rate::cpu1.inst 0.107701 # miss rate for overall accesses 646system.l2c.overall_miss_rate::cpu1.data 0.362041 # miss rate for overall accesses 647system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for overall accesses 648system.l2c.overall_miss_rate::total 0.491753 # miss rate for overall accesses 649system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 53500 # average ReadReq miss latency 650system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74625 # average ReadReq miss latency 651system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80735.753053 # average ReadReq miss latency 652system.l2c.ReadReq_avg_miss_latency::cpu0.data 76118.332868 # average ReadReq miss latency 653system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average ReadReq miss latency 654system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82125 # average ReadReq miss latency 655system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85529.436860 # average ReadReq miss latency 656system.l2c.ReadReq_avg_miss_latency::cpu1.data 77936.030685 # average ReadReq miss latency 657system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average ReadReq miss latency 658system.l2c.ReadReq_avg_miss_latency::total 96418.395561 # average ReadReq miss latency 659system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1790.313995 # average UpgradeReq miss latency 660system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 625.783559 # average UpgradeReq miss latency 661system.l2c.UpgradeReq_avg_miss_latency::total 1312.922808 # average UpgradeReq miss latency 662system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 603.660668 # average SCUpgradeReq miss latency 663system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4201.167630 # average SCUpgradeReq miss latency 664system.l2c.SCUpgradeReq_avg_miss_latency::total 2297.180952 # average SCUpgradeReq miss latency 665system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73252.648913 # average ReadExReq miss latency 666system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71891.320605 # average ReadExReq miss latency 667system.l2c.ReadExReq_avg_miss_latency::total 72588.303375 # average ReadExReq miss latency 668system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 53500 # average overall miss latency 669system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74625 # average overall miss latency 670system.l2c.demand_avg_miss_latency::cpu0.inst 80735.753053 # average overall miss latency 671system.l2c.demand_avg_miss_latency::cpu0.data 74521.600841 # average overall miss latency 672system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average overall miss latency 673system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82125 # average overall miss latency 674system.l2c.demand_avg_miss_latency::cpu1.inst 85529.436860 # average overall miss latency 675system.l2c.demand_avg_miss_latency::cpu1.data 74821.583733 # average overall miss latency 676system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average overall miss latency 677system.l2c.demand_avg_miss_latency::total 95209.752138 # average overall miss latency 678system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 53500 # average overall miss latency 679system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74625 # average overall miss latency 680system.l2c.overall_avg_miss_latency::cpu0.inst 80735.753053 # average overall miss latency 681system.l2c.overall_avg_miss_latency::cpu0.data 74521.600841 # average overall miss latency 682system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average overall miss latency 683system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82125 # average overall miss latency 684system.l2c.overall_avg_miss_latency::cpu1.inst 85529.436860 # average overall miss latency 685system.l2c.overall_avg_miss_latency::cpu1.data 74821.583733 # average overall miss latency 686system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average overall miss latency 687system.l2c.overall_avg_miss_latency::total 95209.752138 # average overall miss latency | 421system.l2c.tags.occ_blocks::writebacks 12574.713731 # Average occupied blocks per requestor 422system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.829645 # Average occupied blocks per requestor 423system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043526 # Average occupied blocks per requestor 424system.l2c.tags.occ_blocks::cpu0.inst 1158.059566 # Average occupied blocks per requestor 425system.l2c.tags.occ_blocks::cpu0.data 1408.624866 # Average occupied blocks per requestor 426system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390 # Average occupied blocks per requestor 427system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.540569 # Average occupied blocks per requestor 428system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007801 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu1.inst 536.338892 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu1.data 908.008157 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8820.200180 # Average occupied blocks per requestor 432system.l2c.tags.occ_percent::writebacks 0.191875 # Average percentage of cache occupancy 433system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy 434system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 435system.l2c.tags.occ_percent::cpu0.inst 0.017671 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu0.data 0.021494 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.591834 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000039 # Average percentage of cache occupancy 439system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 440system.l2c.tags.occ_percent::cpu1.inst 0.008184 # Average percentage of cache occupancy 441system.l2c.tags.occ_percent::cpu1.data 0.013855 # Average percentage of cache occupancy 442system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134586 # Average percentage of cache occupancy 443system.l2c.tags.occ_percent::total 0.979612 # Average percentage of cache occupancy 444system.l2c.tags.occ_task_id_blocks::1022 44718 # Occupied blocks per task id 445system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 446system.l2c.tags.occ_task_id_blocks::1024 19841 # Occupied blocks per task id 447system.l2c.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id 448system.l2c.tags.age_task_id_blocks_1022::3 5098 # Occupied blocks per task id 449system.l2c.tags.age_task_id_blocks_1022::4 39452 # Occupied blocks per task id 450system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 451system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 452system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 453system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id 454system.l2c.tags.age_task_id_blocks_1024::3 1574 # Occupied blocks per task id 455system.l2c.tags.age_task_id_blocks_1024::4 18054 # Occupied blocks per task id 456system.l2c.tags.occ_task_id_percent::1022 0.682343 # Percentage of cache occupancy per task id 457system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 458system.l2c.tags.occ_task_id_percent::1024 0.302750 # Percentage of cache occupancy per task id 459system.l2c.tags.tag_accesses 6148253 # Number of tag accesses 460system.l2c.tags.data_accesses 6148253 # Number of data accesses 461system.l2c.ReadReq_hits::cpu0.dtb.walker 127 # number of ReadReq hits 462system.l2c.ReadReq_hits::cpu0.itb.walker 159 # number of ReadReq hits 463system.l2c.ReadReq_hits::cpu0.inst 10419 # number of ReadReq hits 464system.l2c.ReadReq_hits::cpu0.data 29225 # number of ReadReq hits 465system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168428 # number of ReadReq hits 466system.l2c.ReadReq_hits::cpu1.dtb.walker 62 # number of ReadReq hits 467system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits 468system.l2c.ReadReq_hits::cpu1.inst 4147 # number of ReadReq hits 469system.l2c.ReadReq_hits::cpu1.data 10318 # number of ReadReq hits 470system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47800 # number of ReadReq hits 471system.l2c.ReadReq_hits::total 270735 # number of ReadReq hits 472system.l2c.Writeback_hits::writebacks 240561 # number of Writeback hits 473system.l2c.Writeback_hits::total 240561 # number of Writeback hits 474system.l2c.UpgradeReq_hits::cpu0.data 9666 # number of UpgradeReq hits 475system.l2c.UpgradeReq_hits::cpu1.data 1017 # number of UpgradeReq hits 476system.l2c.UpgradeReq_hits::total 10683 # number of UpgradeReq hits 477system.l2c.SCUpgradeReq_hits::cpu0.data 240 # number of SCUpgradeReq hits 478system.l2c.SCUpgradeReq_hits::cpu1.data 136 # number of SCUpgradeReq hits 479system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits 480system.l2c.ReadExReq_hits::cpu0.data 4189 # number of ReadExReq hits 481system.l2c.ReadExReq_hits::cpu1.data 2493 # number of ReadExReq hits 482system.l2c.ReadExReq_hits::total 6682 # number of ReadExReq hits 483system.l2c.demand_hits::cpu0.dtb.walker 127 # number of demand (read+write) hits 484system.l2c.demand_hits::cpu0.itb.walker 159 # number of demand (read+write) hits 485system.l2c.demand_hits::cpu0.inst 10419 # number of demand (read+write) hits 486system.l2c.demand_hits::cpu0.data 33414 # number of demand (read+write) hits 487system.l2c.demand_hits::cpu0.l2cache.prefetcher 168428 # number of demand (read+write) hits 488system.l2c.demand_hits::cpu1.dtb.walker 62 # number of demand (read+write) hits 489system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits 490system.l2c.demand_hits::cpu1.inst 4147 # number of demand (read+write) hits 491system.l2c.demand_hits::cpu1.data 12811 # number of demand (read+write) hits 492system.l2c.demand_hits::cpu1.l2cache.prefetcher 47800 # number of demand (read+write) hits 493system.l2c.demand_hits::total 277417 # number of demand (read+write) hits 494system.l2c.overall_hits::cpu0.dtb.walker 127 # number of overall hits 495system.l2c.overall_hits::cpu0.itb.walker 159 # number of overall hits 496system.l2c.overall_hits::cpu0.inst 10419 # number of overall hits 497system.l2c.overall_hits::cpu0.data 33414 # number of overall hits 498system.l2c.overall_hits::cpu0.l2cache.prefetcher 168428 # number of overall hits 499system.l2c.overall_hits::cpu1.dtb.walker 62 # number of overall hits 500system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits 501system.l2c.overall_hits::cpu1.inst 4147 # number of overall hits 502system.l2c.overall_hits::cpu1.data 12811 # number of overall hits 503system.l2c.overall_hits::cpu1.l2cache.prefetcher 47800 # number of overall hits 504system.l2c.overall_hits::total 277417 # number of overall hits 505system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 506system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses 507system.l2c.ReadReq_misses::cpu0.inst 3095 # number of ReadReq misses 508system.l2c.ReadReq_misses::cpu0.data 6926 # number of ReadReq misses 509system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq misses 510system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 511system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 512system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses 513system.l2c.ReadReq_misses::cpu1.data 1418 # number of ReadReq misses 514system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq misses 515system.l2c.ReadReq_misses::total 183878 # number of ReadReq misses 516system.l2c.UpgradeReq_misses::cpu0.data 8558 # number of UpgradeReq misses 517system.l2c.UpgradeReq_misses::cpu1.data 4221 # number of UpgradeReq misses 518system.l2c.UpgradeReq_misses::total 12779 # number of UpgradeReq misses 519system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses 520system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses 521system.l2c.SCUpgradeReq_misses::total 2199 # number of SCUpgradeReq misses 522system.l2c.ReadExReq_misses::cpu0.data 6118 # number of ReadExReq misses 523system.l2c.ReadExReq_misses::cpu1.data 5533 # number of ReadExReq misses 524system.l2c.ReadExReq_misses::total 11651 # number of ReadExReq misses 525system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 526system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses 527system.l2c.demand_misses::cpu0.inst 3095 # number of demand (read+write) misses 528system.l2c.demand_misses::cpu0.data 13044 # number of demand (read+write) misses 529system.l2c.demand_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) misses 530system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 531system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 532system.l2c.demand_misses::cpu1.inst 769 # number of demand (read+write) misses 533system.l2c.demand_misses::cpu1.data 6951 # number of demand (read+write) misses 534system.l2c.demand_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) misses 535system.l2c.demand_misses::total 195529 # number of demand (read+write) misses 536system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 537system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses 538system.l2c.overall_misses::cpu0.inst 3095 # number of overall misses 539system.l2c.overall_misses::cpu0.data 13044 # number of overall misses 540system.l2c.overall_misses::cpu0.l2cache.prefetcher 150324 # number of overall misses 541system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 542system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 543system.l2c.overall_misses::cpu1.inst 769 # number of overall misses 544system.l2c.overall_misses::cpu1.data 6951 # number of overall misses 545system.l2c.overall_misses::cpu1.l2cache.prefetcher 21333 # number of overall misses 546system.l2c.overall_misses::total 195529 # number of overall misses 547system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 510000 # number of ReadReq miss cycles 548system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles 549system.l2c.ReadReq_miss_latency::cpu0.inst 268587999 # number of ReadReq miss cycles 550system.l2c.ReadReq_miss_latency::cpu0.data 563686749 # number of ReadReq miss cycles 551system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of ReadReq miss cycles 552system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 328000 # number of ReadReq miss cycles 553system.l2c.ReadReq_miss_latency::cpu1.itb.walker 94250 # number of ReadReq miss cycles 554system.l2c.ReadReq_miss_latency::cpu1.inst 70493000 # number of ReadReq miss cycles 555system.l2c.ReadReq_miss_latency::cpu1.data 122227750 # number of ReadReq miss cycles 556system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of ReadReq miss cycles 557system.l2c.ReadReq_miss_latency::total 18379241574 # number of ReadReq miss cycles 558system.l2c.UpgradeReq_miss_latency::cpu0.data 8946128 # number of UpgradeReq miss cycles 559system.l2c.UpgradeReq_miss_latency::cpu1.data 10070574 # number of UpgradeReq miss cycles 560system.l2c.UpgradeReq_miss_latency::total 19016702 # number of UpgradeReq miss cycles 561system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1175950 # number of SCUpgradeReq miss cycles 562system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2179907 # number of SCUpgradeReq miss cycles 563system.l2c.SCUpgradeReq_miss_latency::total 3355857 # number of SCUpgradeReq miss cycles 564system.l2c.ReadExReq_miss_latency::cpu0.data 485246640 # number of ReadExReq miss cycles 565system.l2c.ReadExReq_miss_latency::cpu1.data 404862686 # number of ReadExReq miss cycles 566system.l2c.ReadExReq_miss_latency::total 890109326 # number of ReadExReq miss cycles 567system.l2c.demand_miss_latency::cpu0.dtb.walker 510000 # number of demand (read+write) miss cycles 568system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles 569system.l2c.demand_miss_latency::cpu0.inst 268587999 # number of demand (read+write) miss cycles 570system.l2c.demand_miss_latency::cpu0.data 1048933389 # number of demand (read+write) miss cycles 571system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of demand (read+write) miss cycles 572system.l2c.demand_miss_latency::cpu1.dtb.walker 328000 # number of demand (read+write) miss cycles 573system.l2c.demand_miss_latency::cpu1.itb.walker 94250 # number of demand (read+write) miss cycles 574system.l2c.demand_miss_latency::cpu1.inst 70493000 # number of demand (read+write) miss cycles 575system.l2c.demand_miss_latency::cpu1.data 527090436 # number of demand (read+write) miss cycles 576system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of demand (read+write) miss cycles 577system.l2c.demand_miss_latency::total 19269350900 # number of demand (read+write) miss cycles 578system.l2c.overall_miss_latency::cpu0.dtb.walker 510000 # number of overall miss cycles 579system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles 580system.l2c.overall_miss_latency::cpu0.inst 268587999 # number of overall miss cycles 581system.l2c.overall_miss_latency::cpu0.data 1048933389 # number of overall miss cycles 582system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of overall miss cycles 583system.l2c.overall_miss_latency::cpu1.dtb.walker 328000 # number of overall miss cycles 584system.l2c.overall_miss_latency::cpu1.itb.walker 94250 # number of overall miss cycles 585system.l2c.overall_miss_latency::cpu1.inst 70493000 # number of overall miss cycles 586system.l2c.overall_miss_latency::cpu1.data 527090436 # number of overall miss cycles 587system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of overall miss cycles 588system.l2c.overall_miss_latency::total 19269350900 # number of overall miss cycles 589system.l2c.ReadReq_accesses::cpu0.dtb.walker 134 # number of ReadReq accesses(hits+misses) 590system.l2c.ReadReq_accesses::cpu0.itb.walker 160 # number of ReadReq accesses(hits+misses) 591system.l2c.ReadReq_accesses::cpu0.inst 13514 # number of ReadReq accesses(hits+misses) 592system.l2c.ReadReq_accesses::cpu0.data 36151 # number of ReadReq accesses(hits+misses) 593system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318752 # number of ReadReq accesses(hits+misses) 594system.l2c.ReadReq_accesses::cpu1.dtb.walker 66 # number of ReadReq accesses(hits+misses) 595system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) 596system.l2c.ReadReq_accesses::cpu1.inst 4916 # number of ReadReq accesses(hits+misses) 597system.l2c.ReadReq_accesses::cpu1.data 11736 # number of ReadReq accesses(hits+misses) 598system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69133 # number of ReadReq accesses(hits+misses) 599system.l2c.ReadReq_accesses::total 454613 # number of ReadReq accesses(hits+misses) 600system.l2c.Writeback_accesses::writebacks 240561 # number of Writeback accesses(hits+misses) 601system.l2c.Writeback_accesses::total 240561 # number of Writeback accesses(hits+misses) 602system.l2c.UpgradeReq_accesses::cpu0.data 18224 # number of UpgradeReq accesses(hits+misses) 603system.l2c.UpgradeReq_accesses::cpu1.data 5238 # number of UpgradeReq accesses(hits+misses) 604system.l2c.UpgradeReq_accesses::total 23462 # number of UpgradeReq accesses(hits+misses) 605system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses) 606system.l2c.SCUpgradeReq_accesses::cpu1.data 1446 # number of SCUpgradeReq accesses(hits+misses) 607system.l2c.SCUpgradeReq_accesses::total 2575 # number of SCUpgradeReq accesses(hits+misses) 608system.l2c.ReadExReq_accesses::cpu0.data 10307 # number of ReadExReq accesses(hits+misses) 609system.l2c.ReadExReq_accesses::cpu1.data 8026 # number of ReadExReq accesses(hits+misses) 610system.l2c.ReadExReq_accesses::total 18333 # number of ReadExReq accesses(hits+misses) 611system.l2c.demand_accesses::cpu0.dtb.walker 134 # number of demand (read+write) accesses 612system.l2c.demand_accesses::cpu0.itb.walker 160 # number of demand (read+write) accesses 613system.l2c.demand_accesses::cpu0.inst 13514 # number of demand (read+write) accesses 614system.l2c.demand_accesses::cpu0.data 46458 # number of demand (read+write) accesses 615system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318752 # number of demand (read+write) accesses 616system.l2c.demand_accesses::cpu1.dtb.walker 66 # number of demand (read+write) accesses 617system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses 618system.l2c.demand_accesses::cpu1.inst 4916 # number of demand (read+write) accesses 619system.l2c.demand_accesses::cpu1.data 19762 # number of demand (read+write) accesses 620system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69133 # number of demand (read+write) accesses 621system.l2c.demand_accesses::total 472946 # number of demand (read+write) accesses 622system.l2c.overall_accesses::cpu0.dtb.walker 134 # number of overall (read+write) accesses 623system.l2c.overall_accesses::cpu0.itb.walker 160 # number of overall (read+write) accesses 624system.l2c.overall_accesses::cpu0.inst 13514 # number of overall (read+write) accesses 625system.l2c.overall_accesses::cpu0.data 46458 # number of overall (read+write) accesses 626system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318752 # number of overall (read+write) accesses 627system.l2c.overall_accesses::cpu1.dtb.walker 66 # number of overall (read+write) accesses 628system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses 629system.l2c.overall_accesses::cpu1.inst 4916 # number of overall (read+write) accesses 630system.l2c.overall_accesses::cpu1.data 19762 # number of overall (read+write) accesses 631system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69133 # number of overall (read+write) accesses 632system.l2c.overall_accesses::total 472946 # number of overall (read+write) accesses 633system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for ReadReq accesses 634system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006250 # miss rate for ReadReq accesses 635system.l2c.ReadReq_miss_rate::cpu0.inst 0.229022 # miss rate for ReadReq accesses 636system.l2c.ReadReq_miss_rate::cpu0.data 0.191585 # miss rate for ReadReq accesses 637system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for ReadReq accesses 638system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for ReadReq accesses 639system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses 640system.l2c.ReadReq_miss_rate::cpu1.inst 0.156428 # miss rate for ReadReq accesses 641system.l2c.ReadReq_miss_rate::cpu1.data 0.120825 # miss rate for ReadReq accesses 642system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for ReadReq accesses 643system.l2c.ReadReq_miss_rate::total 0.404471 # miss rate for ReadReq accesses 644system.l2c.UpgradeReq_miss_rate::cpu0.data 0.469601 # miss rate for UpgradeReq accesses 645system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805842 # miss rate for UpgradeReq accesses 646system.l2c.UpgradeReq_miss_rate::total 0.544668 # miss rate for UpgradeReq accesses 647system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787422 # miss rate for SCUpgradeReq accesses 648system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.905947 # miss rate for SCUpgradeReq accesses 649system.l2c.SCUpgradeReq_miss_rate::total 0.853981 # miss rate for SCUpgradeReq accesses 650system.l2c.ReadExReq_miss_rate::cpu0.data 0.593577 # miss rate for ReadExReq accesses 651system.l2c.ReadExReq_miss_rate::cpu1.data 0.689385 # miss rate for ReadExReq accesses 652system.l2c.ReadExReq_miss_rate::total 0.635521 # miss rate for ReadExReq accesses 653system.l2c.demand_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for demand accesses 654system.l2c.demand_miss_rate::cpu0.itb.walker 0.006250 # miss rate for demand accesses 655system.l2c.demand_miss_rate::cpu0.inst 0.229022 # miss rate for demand accesses 656system.l2c.demand_miss_rate::cpu0.data 0.280770 # miss rate for demand accesses 657system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for demand accesses 658system.l2c.demand_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for demand accesses 659system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses 660system.l2c.demand_miss_rate::cpu1.inst 0.156428 # miss rate for demand accesses 661system.l2c.demand_miss_rate::cpu1.data 0.351736 # miss rate for demand accesses 662system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for demand accesses 663system.l2c.demand_miss_rate::total 0.413428 # miss rate for demand accesses 664system.l2c.overall_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for overall accesses 665system.l2c.overall_miss_rate::cpu0.itb.walker 0.006250 # miss rate for overall accesses 666system.l2c.overall_miss_rate::cpu0.inst 0.229022 # miss rate for overall accesses 667system.l2c.overall_miss_rate::cpu0.data 0.280770 # miss rate for overall accesses 668system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for overall accesses 669system.l2c.overall_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for overall accesses 670system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses 671system.l2c.overall_miss_rate::cpu1.inst 0.156428 # miss rate for overall accesses 672system.l2c.overall_miss_rate::cpu1.data 0.351736 # miss rate for overall accesses 673system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for overall accesses 674system.l2c.overall_miss_rate::total 0.413428 # miss rate for overall accesses 675system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average ReadReq miss latency 676system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency 677system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86781.259774 # average ReadReq miss latency 678system.l2c.ReadReq_avg_miss_latency::cpu0.data 81387.055876 # average ReadReq miss latency 679system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average ReadReq miss latency 680system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82000 # average ReadReq miss latency 681system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 94250 # average ReadReq miss latency 682system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91668.400520 # average ReadReq miss latency 683system.l2c.ReadReq_avg_miss_latency::cpu1.data 86197.284908 # average ReadReq miss latency 684system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average ReadReq miss latency 685system.l2c.ReadReq_avg_miss_latency::total 99953.455954 # average ReadReq miss latency 686system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1045.352652 # average UpgradeReq miss latency 687system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2385.826581 # average UpgradeReq miss latency 688system.l2c.UpgradeReq_avg_miss_latency::total 1488.121293 # average UpgradeReq miss latency 689system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1322.778403 # average SCUpgradeReq miss latency 690system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1664.051145 # average SCUpgradeReq miss latency 691system.l2c.SCUpgradeReq_avg_miss_latency::total 1526.083220 # average SCUpgradeReq miss latency 692system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79314.586466 # average ReadExReq miss latency 693system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73172.363275 # average ReadExReq miss latency 694system.l2c.ReadExReq_avg_miss_latency::total 76397.676251 # average ReadExReq miss latency 695system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency 696system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 697system.l2c.demand_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency 698system.l2c.demand_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency 699system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency 700system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency 701system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency 702system.l2c.demand_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency 703system.l2c.demand_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency 704system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency 705system.l2c.demand_avg_miss_latency::total 98549.836086 # average overall miss latency 706system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency 707system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency 708system.l2c.overall_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency 709system.l2c.overall_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency 710system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency 711system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency 712system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency 713system.l2c.overall_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency 714system.l2c.overall_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency 715system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency 716system.l2c.overall_avg_miss_latency::total 98549.836086 # average overall miss latency |
| 688system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 689system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 690system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 691system.l2c.blocked::no_targets 0 # number of cycles access was blocked 692system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 693system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 694system.l2c.fast_writes 0 # number of fast writes performed 695system.l2c.cache_copies 0 # number of cache copies performed | 717system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 720system.l2c.blocked::no_targets 0 # number of cycles access was blocked 721system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.l2c.fast_writes 0 # number of fast writes performed 724system.l2c.cache_copies 0 # number of cache copies performed |
| 696system.l2c.writebacks::writebacks 67188 # number of writebacks 697system.l2c.writebacks::total 67188 # number of writebacks 698system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 699system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 700system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 701system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 702system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 703system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 704system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2 # number of ReadReq MSHR misses 705system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses 706system.l2c.ReadReq_mshr_misses::cpu0.inst 1474 # number of ReadReq MSHR misses 707system.l2c.ReadReq_mshr_misses::cpu0.data 3581 # number of ReadReq MSHR misses 708system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 104062 # number of ReadReq MSHR misses 709system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2 # number of ReadReq MSHR misses 710system.l2c.ReadReq_mshr_misses::cpu1.inst 585 # number of ReadReq MSHR misses 711system.l2c.ReadReq_mshr_misses::cpu1.data 4041 # number of ReadReq MSHR misses 712system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 50971 # number of ReadReq MSHR misses 713system.l2c.ReadReq_mshr_misses::total 164722 # number of ReadReq MSHR misses 714system.l2c.UpgradeReq_mshr_misses::cpu0.data 7774 # number of UpgradeReq MSHR misses 715system.l2c.UpgradeReq_mshr_misses::cpu1.data 5401 # number of UpgradeReq MSHR misses 716system.l2c.UpgradeReq_mshr_misses::total 13175 # number of UpgradeReq MSHR misses 717system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1167 # number of SCUpgradeReq MSHR misses 718system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1038 # number of SCUpgradeReq MSHR misses 719system.l2c.SCUpgradeReq_mshr_misses::total 2205 # number of SCUpgradeReq MSHR misses 720system.l2c.ReadExReq_mshr_misses::cpu0.data 4506 # number of ReadExReq MSHR misses 721system.l2c.ReadExReq_mshr_misses::cpu1.data 4295 # number of ReadExReq MSHR misses 722system.l2c.ReadExReq_mshr_misses::total 8801 # number of ReadExReq MSHR misses 723system.l2c.demand_mshr_misses::cpu0.dtb.walker 2 # number of demand (read+write) MSHR misses 724system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses 725system.l2c.demand_mshr_misses::cpu0.inst 1474 # number of demand (read+write) MSHR misses 726system.l2c.demand_mshr_misses::cpu0.data 8087 # number of demand (read+write) MSHR misses 727system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 104062 # number of demand (read+write) MSHR misses 728system.l2c.demand_mshr_misses::cpu1.dtb.walker 2 # number of demand (read+write) MSHR misses 729system.l2c.demand_mshr_misses::cpu1.inst 585 # number of demand (read+write) MSHR misses 730system.l2c.demand_mshr_misses::cpu1.data 8336 # number of demand (read+write) MSHR misses 731system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 50971 # number of demand (read+write) MSHR misses 732system.l2c.demand_mshr_misses::total 173523 # number of demand (read+write) MSHR misses 733system.l2c.overall_mshr_misses::cpu0.dtb.walker 2 # number of overall MSHR misses 734system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses 735system.l2c.overall_mshr_misses::cpu0.inst 1474 # number of overall MSHR misses 736system.l2c.overall_mshr_misses::cpu0.data 8087 # number of overall MSHR misses 737system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 104062 # number of overall MSHR misses 738system.l2c.overall_mshr_misses::cpu1.dtb.walker 2 # number of overall MSHR misses 739system.l2c.overall_mshr_misses::cpu1.inst 585 # number of overall MSHR misses 740system.l2c.overall_mshr_misses::cpu1.data 8336 # number of overall MSHR misses 741system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 50971 # number of overall MSHR misses 742system.l2c.overall_mshr_misses::total 173523 # number of overall MSHR misses 743system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 82500 # number of ReadReq MSHR miss cycles 744system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 250000 # number of ReadReq MSHR miss cycles 745system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 100663500 # number of ReadReq MSHR miss cycles 746system.l2c.ReadReq_mshr_miss_latency::cpu0.data 227794750 # number of ReadReq MSHR miss cycles 747system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 7718948941 # number of ReadReq MSHR miss cycles 748system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 138750 # number of ReadReq MSHR miss cycles 749system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 42844000 # number of ReadReq MSHR miss cycles 750system.l2c.ReadReq_mshr_miss_latency::cpu1.data 264712000 # number of ReadReq MSHR miss cycles 751system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 5479054183 # number of ReadReq MSHR miss cycles 752system.l2c.ReadReq_mshr_miss_latency::total 13834488624 # number of ReadReq MSHR miss cycles 753system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 78078748 # number of UpgradeReq MSHR miss cycles 754system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 54145386 # number of UpgradeReq MSHR miss cycles 755system.l2c.UpgradeReq_mshr_miss_latency::total 132224134 # number of UpgradeReq MSHR miss cycles 756system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 11801161 # number of SCUpgradeReq MSHR miss cycles 757system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10401535 # number of SCUpgradeReq MSHR miss cycles 758system.l2c.SCUpgradeReq_mshr_miss_latency::total 22202696 # number of SCUpgradeReq MSHR miss cycles 759system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 273742064 # number of ReadExReq MSHR miss cycles 760system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 254569278 # number of ReadExReq MSHR miss cycles 761system.l2c.ReadExReq_mshr_miss_latency::total 528311342 # number of ReadExReq MSHR miss cycles 762system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 82500 # number of demand (read+write) MSHR miss cycles 763system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 250000 # number of demand (read+write) MSHR miss cycles 764system.l2c.demand_mshr_miss_latency::cpu0.inst 100663500 # number of demand (read+write) MSHR miss cycles 765system.l2c.demand_mshr_miss_latency::cpu0.data 501536814 # number of demand (read+write) MSHR miss cycles 766system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 7718948941 # number of demand (read+write) MSHR miss cycles 767system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles 768system.l2c.demand_mshr_miss_latency::cpu1.inst 42844000 # number of demand (read+write) MSHR miss cycles 769system.l2c.demand_mshr_miss_latency::cpu1.data 519281278 # number of demand (read+write) MSHR miss cycles 770system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 5479054183 # number of demand (read+write) MSHR miss cycles 771system.l2c.demand_mshr_miss_latency::total 14362799966 # number of demand (read+write) MSHR miss cycles 772system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 82500 # number of overall MSHR miss cycles 773system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 250000 # number of overall MSHR miss cycles 774system.l2c.overall_mshr_miss_latency::cpu0.inst 100663500 # number of overall MSHR miss cycles 775system.l2c.overall_mshr_miss_latency::cpu0.data 501536814 # number of overall MSHR miss cycles 776system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 7718948941 # number of overall MSHR miss cycles 777system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 138750 # number of overall MSHR miss cycles 778system.l2c.overall_mshr_miss_latency::cpu1.inst 42844000 # number of overall MSHR miss cycles 779system.l2c.overall_mshr_miss_latency::cpu1.data 519281278 # number of overall MSHR miss cycles 780system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 5479054183 # number of overall MSHR miss cycles 781system.l2c.overall_mshr_miss_latency::total 14362799966 # number of overall MSHR miss cycles 782system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 352521750 # number of ReadReq MSHR uncacheable cycles 783system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 156454617998 # number of ReadReq MSHR uncacheable cycles 784system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles 785system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 10840620247 # number of ReadReq MSHR uncacheable cycles 786system.l2c.ReadReq_mshr_uncacheable_latency::total 167653362745 # number of ReadReq MSHR uncacheable cycles 787system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1361015000 # number of WriteReq MSHR uncacheable cycles 788system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15491155851 # number of WriteReq MSHR uncacheable cycles 789system.l2c.WriteReq_mshr_uncacheable_latency::total 16852170851 # number of WriteReq MSHR uncacheable cycles 790system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 352521750 # number of overall MSHR uncacheable cycles 791system.l2c.overall_mshr_uncacheable_latency::cpu0.data 157815632998 # number of overall MSHR uncacheable cycles 792system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles 793system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26331776098 # number of overall MSHR uncacheable cycles 794system.l2c.overall_mshr_uncacheable_latency::total 184505533596 # number of overall MSHR uncacheable cycles 795system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for ReadReq accesses 796system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for ReadReq accesses 797system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for ReadReq accesses 798system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.190550 # mshr miss rate for ReadReq accesses 799system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for ReadReq accesses 800system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for ReadReq accesses 801system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for ReadReq accesses 802system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.243771 # mshr miss rate for ReadReq accesses 803system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for ReadReq accesses 804system.l2c.ReadReq_mshr_miss_rate::total 0.485099 # mshr miss rate for ReadReq accesses 805system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.686385 # mshr miss rate for UpgradeReq accesses 806system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760919 # mshr miss rate for UpgradeReq accesses 807system.l2c.UpgradeReq_mshr_miss_rate::total 0.715100 # mshr miss rate for UpgradeReq accesses 808system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911007 # mshr miss rate for SCUpgradeReq accesses 809system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837772 # mshr miss rate for SCUpgradeReq accesses 810system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.875000 # mshr miss rate for SCUpgradeReq accesses 811system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.657235 # mshr miss rate for ReadExReq accesses 812system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.666098 # mshr miss rate for ReadExReq accesses 813system.l2c.ReadExReq_mshr_miss_rate::total 0.661530 # mshr miss rate for ReadExReq accesses 814system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for demand accesses 815system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for demand accesses 816system.l2c.demand_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for demand accesses 817system.l2c.demand_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for demand accesses 818system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for demand accesses 819system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for demand accesses 820system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for demand accesses 821system.l2c.demand_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for demand accesses 822system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for demand accesses 823system.l2c.demand_mshr_miss_rate::total 0.491750 # mshr miss rate for demand accesses 824system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for overall accesses 825system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for overall accesses 826system.l2c.overall_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for overall accesses 827system.l2c.overall_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for overall accesses 828system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for overall accesses 829system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for overall accesses 830system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for overall accesses 831system.l2c.overall_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for overall accesses 832system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for overall accesses 833system.l2c.overall_mshr_miss_rate::total 0.491750 # mshr miss rate for overall accesses 834system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average ReadReq mshr miss latency | 725system.l2c.writebacks::writebacks 99890 # number of writebacks 726system.l2c.writebacks::total 99890 # number of writebacks 727system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses 728system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses 729system.l2c.ReadReq_mshr_misses::cpu0.inst 3095 # number of ReadReq MSHR misses 730system.l2c.ReadReq_mshr_misses::cpu0.data 6926 # number of ReadReq MSHR misses 731system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq MSHR misses 732system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses 733system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 734system.l2c.ReadReq_mshr_misses::cpu1.inst 769 # number of ReadReq MSHR misses 735system.l2c.ReadReq_mshr_misses::cpu1.data 1418 # number of ReadReq MSHR misses 736system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq MSHR misses 737system.l2c.ReadReq_mshr_misses::total 183878 # number of ReadReq MSHR misses 738system.l2c.UpgradeReq_mshr_misses::cpu0.data 8558 # number of UpgradeReq MSHR misses 739system.l2c.UpgradeReq_mshr_misses::cpu1.data 4221 # number of UpgradeReq MSHR misses 740system.l2c.UpgradeReq_mshr_misses::total 12779 # number of UpgradeReq MSHR misses 741system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses 742system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1310 # number of SCUpgradeReq MSHR misses 743system.l2c.SCUpgradeReq_mshr_misses::total 2199 # number of SCUpgradeReq MSHR misses 744system.l2c.ReadExReq_mshr_misses::cpu0.data 6118 # number of ReadExReq MSHR misses 745system.l2c.ReadExReq_mshr_misses::cpu1.data 5533 # number of ReadExReq MSHR misses 746system.l2c.ReadExReq_mshr_misses::total 11651 # number of ReadExReq MSHR misses 747system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 748system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses 749system.l2c.demand_mshr_misses::cpu0.inst 3095 # number of demand (read+write) MSHR misses 750system.l2c.demand_mshr_misses::cpu0.data 13044 # number of demand (read+write) MSHR misses 751system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) MSHR misses 752system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses 753system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 754system.l2c.demand_mshr_misses::cpu1.inst 769 # number of demand (read+write) MSHR misses 755system.l2c.demand_mshr_misses::cpu1.data 6951 # number of demand (read+write) MSHR misses 756system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) MSHR misses 757system.l2c.demand_mshr_misses::total 195529 # number of demand (read+write) MSHR misses 758system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 759system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses 760system.l2c.overall_mshr_misses::cpu0.inst 3095 # number of overall MSHR misses 761system.l2c.overall_mshr_misses::cpu0.data 13044 # number of overall MSHR misses 762system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of overall MSHR misses 763system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses 764system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 765system.l2c.overall_mshr_misses::cpu1.inst 769 # number of overall MSHR misses 766system.l2c.overall_mshr_misses::cpu1.data 6951 # number of overall MSHR misses 767system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of overall MSHR misses 768system.l2c.overall_mshr_misses::total 195529 # number of overall MSHR misses 769system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 423500 # number of ReadReq MSHR miss cycles 770system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles 771system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230146499 # number of ReadReq MSHR miss cycles 772system.l2c.ReadReq_mshr_miss_latency::cpu0.data 477536249 # number of ReadReq MSHR miss cycles 773system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of ReadReq MSHR miss cycles 774system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 278000 # number of ReadReq MSHR miss cycles 775system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 81250 # number of ReadReq MSHR miss cycles 776system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60929000 # number of ReadReq MSHR miss cycles 777system.l2c.ReadReq_mshr_miss_latency::cpu1.data 104521250 # number of ReadReq MSHR miss cycles 778system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of ReadReq MSHR miss cycles 779system.l2c.ReadReq_mshr_miss_latency::total 16097880074 # number of ReadReq MSHR miss cycles 780system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86272013 # number of UpgradeReq MSHR miss cycles 781system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42559203 # number of UpgradeReq MSHR miss cycles 782system.l2c.UpgradeReq_mshr_miss_latency::total 128831216 # number of UpgradeReq MSHR miss cycles 783system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8927886 # number of SCUpgradeReq MSHR miss cycles 784system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13175305 # number of SCUpgradeReq MSHR miss cycles 785system.l2c.SCUpgradeReq_mshr_miss_latency::total 22103191 # number of SCUpgradeReq MSHR miss cycles 786system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 408771858 # number of ReadExReq MSHR miss cycles 787system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 334873814 # number of ReadExReq MSHR miss cycles 788system.l2c.ReadExReq_mshr_miss_latency::total 743645672 # number of ReadExReq MSHR miss cycles 789system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 423500 # number of demand (read+write) MSHR miss cycles 790system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 791system.l2c.demand_mshr_miss_latency::cpu0.inst 230146499 # number of demand (read+write) MSHR miss cycles 792system.l2c.demand_mshr_miss_latency::cpu0.data 886308107 # number of demand (read+write) MSHR miss cycles 793system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of demand (read+write) MSHR miss cycles 794system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 278000 # number of demand (read+write) MSHR miss cycles 795system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 81250 # number of demand (read+write) MSHR miss cycles 796system.l2c.demand_mshr_miss_latency::cpu1.inst 60929000 # number of demand (read+write) MSHR miss cycles 797system.l2c.demand_mshr_miss_latency::cpu1.data 439395064 # number of demand (read+write) MSHR miss cycles 798system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of demand (read+write) MSHR miss cycles 799system.l2c.demand_mshr_miss_latency::total 16841525746 # number of demand (read+write) MSHR miss cycles 800system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 423500 # number of overall MSHR miss cycles 801system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles 802system.l2c.overall_mshr_miss_latency::cpu0.inst 230146499 # number of overall MSHR miss cycles 803system.l2c.overall_mshr_miss_latency::cpu0.data 886308107 # number of overall MSHR miss cycles 804system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of overall MSHR miss cycles 805system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 278000 # number of overall MSHR miss cycles 806system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 81250 # number of overall MSHR miss cycles 807system.l2c.overall_mshr_miss_latency::cpu1.inst 60929000 # number of overall MSHR miss cycles 808system.l2c.overall_mshr_miss_latency::cpu1.data 439395064 # number of overall MSHR miss cycles 809system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of overall MSHR miss cycles 810system.l2c.overall_mshr_miss_latency::total 16841525746 # number of overall MSHR miss cycles 811system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476853500 # number of ReadReq MSHR uncacheable cycles 812system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4797337250 # number of ReadReq MSHR uncacheable cycles 813system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9261250 # number of ReadReq MSHR uncacheable cycles 814system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814340500 # number of ReadReq MSHR uncacheable cycles 815system.l2c.ReadReq_mshr_uncacheable_latency::total 6097792500 # number of ReadReq MSHR uncacheable cycles 816system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540127500 # number of WriteReq MSHR uncacheable cycles 817system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712608500 # number of WriteReq MSHR uncacheable cycles 818system.l2c.WriteReq_mshr_uncacheable_latency::total 4252736000 # number of WriteReq MSHR uncacheable cycles 819system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476853500 # number of overall MSHR uncacheable cycles 820system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337464750 # number of overall MSHR uncacheable cycles 821system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9261250 # number of overall MSHR uncacheable cycles 822system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526949000 # number of overall MSHR uncacheable cycles 823system.l2c.overall_mshr_uncacheable_latency::total 10350528500 # number of overall MSHR uncacheable cycles 824system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for ReadReq accesses 825system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for ReadReq accesses 826system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for ReadReq accesses 827system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191585 # mshr miss rate for ReadReq accesses 828system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for ReadReq accesses 829system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for ReadReq accesses 830system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses 831system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for ReadReq accesses 832system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120825 # mshr miss rate for ReadReq accesses 833system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for ReadReq accesses 834system.l2c.ReadReq_mshr_miss_rate::total 0.404471 # mshr miss rate for ReadReq accesses 835system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.469601 # mshr miss rate for UpgradeReq accesses 836system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805842 # mshr miss rate for UpgradeReq accesses 837system.l2c.UpgradeReq_mshr_miss_rate::total 0.544668 # mshr miss rate for UpgradeReq accesses 838system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787422 # mshr miss rate for SCUpgradeReq accesses 839system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.905947 # mshr miss rate for SCUpgradeReq accesses 840system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.853981 # mshr miss rate for SCUpgradeReq accesses 841system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593577 # mshr miss rate for ReadExReq accesses 842system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.689385 # mshr miss rate for ReadExReq accesses 843system.l2c.ReadExReq_mshr_miss_rate::total 0.635521 # mshr miss rate for ReadExReq accesses 844system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for demand accesses 845system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for demand accesses 846system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for demand accesses 847system.l2c.demand_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for demand accesses 848system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for demand accesses 849system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for demand accesses 850system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses 851system.l2c.demand_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for demand accesses 852system.l2c.demand_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for demand accesses 853system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for demand accesses 854system.l2c.demand_mshr_miss_rate::total 0.413428 # mshr miss rate for demand accesses 855system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for overall accesses 856system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for overall accesses 857system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for overall accesses 858system.l2c.overall_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for overall accesses 859system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for overall accesses 860system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for overall accesses 861system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses 862system.l2c.overall_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for overall accesses 863system.l2c.overall_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for overall accesses 864system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for overall accesses 865system.l2c.overall_mshr_miss_rate::total 0.413428 # mshr miss rate for overall accesses 866system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average ReadReq mshr miss latency |
| 835system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 867system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 836system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average ReadReq mshr miss latency 837system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707 # average ReadReq mshr miss latency 838system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average ReadReq mshr miss latency 839system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average ReadReq mshr miss latency 840system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average ReadReq mshr miss latency 841system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783 # average ReadReq mshr miss latency 842system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average ReadReq mshr miss latency 843system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786 # average ReadReq mshr miss latency 844system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479 # average UpgradeReq mshr miss latency 845system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839 # average UpgradeReq mshr miss latency 846system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400 # average UpgradeReq mshr miss latency 847system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602 # average SCUpgradeReq mshr miss latency 848system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628 # average SCUpgradeReq mshr miss latency 849system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887 # average SCUpgradeReq mshr miss latency 850system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019 # average ReadExReq mshr miss latency 851system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532 # average ReadExReq mshr miss latency 852system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346 # average ReadExReq mshr miss latency 853system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency | 868system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average ReadReq mshr miss latency 869system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665 # average ReadReq mshr miss latency 870system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average ReadReq mshr miss latency 871system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average ReadReq mshr miss latency 872system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average ReadReq mshr miss latency 873system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average ReadReq mshr miss latency 874system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453 # average ReadReq mshr miss latency 875system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average ReadReq mshr miss latency 876system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816 # average ReadReq mshr miss latency 877system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533 # average UpgradeReq mshr miss latency 878system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922 # average UpgradeReq mshr miss latency 879system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676 # average UpgradeReq mshr miss latency 880system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423 # average SCUpgradeReq mshr miss latency 881system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733 # average SCUpgradeReq mshr miss latency 882system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852 # average SCUpgradeReq mshr miss latency 883system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099 # average ReadExReq mshr miss latency 884system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940 # average ReadExReq mshr miss latency 885system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831 # average ReadExReq mshr miss latency 886system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency |
| 854system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 887system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 855system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency 856system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency 857system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency 858system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency 859system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency 860system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency 861system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency 862system.l2c.demand_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency 863system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency | 888system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency 889system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency 890system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency 891system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency 892system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency 893system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency 894system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency 895system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency 896system.l2c.demand_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency 897system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency |
| 864system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 898system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 865system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency 866system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency 867system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency 868system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency 869system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency 870system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency 871system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency 872system.l2c.overall_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency | 899system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency 900system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency 901system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency 902system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency 903system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency 904system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency 905system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency 906system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency 907system.l2c.overall_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency |
| 873system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 874system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 875system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 876system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 877system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 878system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 879system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 880system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 881system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 882system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 883system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 884system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 885system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 886system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 908system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 910system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 911system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 912system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 913system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 914system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 915system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 916system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 917system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 918system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 919system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 920system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 921system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 922system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 923system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 924system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 925system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 926system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 927system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 928system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 929system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 930system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 931system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 932system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 933system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 934system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 935system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 936system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 937system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 938system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 939system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 940system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 941system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 942system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 943system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 944system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 945system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 946system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 947system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 948system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 949system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 950system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 951system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 952system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 887system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). | 953system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| 888system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 889system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 890system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 891system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 892system.cf0.dma_write_txs 0 # Number of DMA write transactions. 893system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution 894system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution 895system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution 896system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution 897system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution 898system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution 899system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution 900system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution 901system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution 902system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution 903system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution 904system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution 905system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes) 906system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes) 907system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes) 908system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes) 909system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes) 910system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes) 911system.toL2Bus.snoops 171942 # Total snoops (count) 912system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram 913system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 914system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 954system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 955system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 956system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 957system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 958system.cf0.dma_write_txs 631 # Number of DMA write transactions. 959system.toL2Bus.trans_dist::ReadReq 633918 # Transaction distribution 960system.toL2Bus.trans_dist::ReadResp 633902 # Transaction distribution 961system.toL2Bus.trans_dist::WriteReq 31177 # Transaction distribution 962system.toL2Bus.trans_dist::WriteResp 31177 # Transaction distribution 963system.toL2Bus.trans_dist::Writeback 240561 # Transaction distribution 964system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 965system.toL2Bus.trans_dist::UpgradeReq 96369 # Transaction distribution 966system.toL2Bus.trans_dist::SCUpgradeReq 41588 # Transaction distribution 967system.toL2Bus.trans_dist::UpgradeResp 137957 # Transaction distribution 968system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 969system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 970system.toL2Bus.trans_dist::ReadExReq 39943 # Transaction distribution 971system.toL2Bus.trans_dist::ReadExResp 39943 # Transaction distribution 972system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1258028 # Packet count per connected master and slave (bytes) 973system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 400059 # Packet count per connected master and slave (bytes) 974system.toL2Bus.pkt_count::total 1658087 # Packet count per connected master and slave (bytes) 975system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37640280 # Cumulative packet size per connected master and slave (bytes) 976system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8288315 # Cumulative packet size per connected master and slave (bytes) 977system.toL2Bus.pkt_size::total 45928595 # Cumulative packet size per connected master and slave (bytes) 978system.toL2Bus.snoops 305065 # Total snoops (count) 979system.toL2Bus.snoop_fanout::samples 1044371 # Request fanout histogram 980system.toL2Bus.snoop_fanout::mean 1.034928 # Request fanout histogram 981system.toL2Bus.snoop_fanout::stdev 0.183598 # Request fanout histogram |
| 915system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 916system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 982system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 983system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 917system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram 918system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram | 984system.toL2Bus.snoop_fanout::1 1007893 96.51% 96.51% # Request fanout histogram 985system.toL2Bus.snoop_fanout::2 36478 3.49% 100.00% # Request fanout histogram |
| 919system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 920system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 986system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 987system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram |
| 921system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 922system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram 923system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks) | 988system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 989system.toL2Bus.snoop_fanout::total 1044371 # Request fanout histogram 990system.toL2Bus.reqLayer0.occupancy 1521180751 # Layer occupancy (ticks) |
| 924system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 991system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 925system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks) | 992system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) 993system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 994system.toL2Bus.respLayer0.occupancy 2136308825 # Layer occupancy (ticks) |
| 926system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 995system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 927system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks) | 996system.toL2Bus.respLayer1.occupancy 850635338 # Layer occupancy (ticks) |
| 928system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 997system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 929system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution 930system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution 931system.iobus.trans_dist::WriteReq 8087 # Transaction distribution 932system.iobus.trans_dist::WriteResp 8087 # Transaction distribution 933system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes) 934system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes) | 998system.iobus.trans_dist::ReadReq 31019 # Transaction distribution 999system.iobus.trans_dist::ReadResp 31019 # Transaction distribution 1000system.iobus.trans_dist::WriteReq 59408 # Transaction distribution 1001system.iobus.trans_dist::WriteResp 59440 # Transaction distribution 1002system.iobus.trans_dist::WriteInvalidateReq 32 # Transaction distribution 1003system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) |
| 935system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 1005system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 936system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) 937system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) | 1006system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) |
| 938system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 1007system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 939system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 940system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 941system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) | 1008system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) 1009system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) |
| 942system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 943system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 944system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) | 1010system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1011system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1012system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 945system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 946system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) | 1013system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) |
| 947system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 1014system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 948system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 949system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 950system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 951system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 952system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) | |
| 953system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) | 1015system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 1016system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1017system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) |
|
| 954system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) | 1018system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 955system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 956system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes) 957system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) 958system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) 959system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes) | 1019system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1020system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1021system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1022system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1023system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1024system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes) 1025system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) 1026system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) 1027system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes) 1028system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) 1029system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) |
| 962system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) | 1030system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) |
| 963system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) 964system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) | 1031system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) |
| 965system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 1032system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 966system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 968system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1033system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) 1034system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) |
| 969system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 970system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 971system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1035system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1036system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1037system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 972system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 973system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) | 1038system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) |
| 974system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1039system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 975system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 976system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 977system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 978system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 979system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | |
| 980system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1040system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 1041system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1042system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) |
|
| 981system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 1043system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 982system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 983system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes) 984system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) 985system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) 986system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes) 987system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks) | 1044system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) 1052system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) |
| 988system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1054system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 989system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks) | 1055system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) |
| 990system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1056system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 991system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) | 1057system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) |
| 992system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1058system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 993system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) | 1059system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) |
| 994system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1060system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 995system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 996system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 997system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 998system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 999system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) | 1061system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) |
| 1000system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) | 1062system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
| 1001system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) | 1063system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) |
| 1002system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1064system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1003system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1004system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1005system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) | 1065system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) |
| 1006system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 1066system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 1007system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 1008system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1009system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 1010system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) | |
| 1011system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1012system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 1067system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1068system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 1013system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) | 1069system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) |
| 1014system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1015system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1016system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 1070system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1071system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1072system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 1017system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) | 1073system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) |
| 1018system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1019system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1020system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1021system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1022system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1074system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1075system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1076system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1077system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1078system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1023system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) | 1079system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) |
| 1024system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1025system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1026system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1027system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1028system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1080system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1081system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1082system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1083system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1084system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1029system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1030system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1031system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) | 1085system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) |
| 1032system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1086system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1033system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) 1034system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 1035system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks) 1036system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 1037system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks) 1038system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) | 1087system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1088system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1090system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1092system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1093system.iobus.reqLayer27.occupancy 326676322 # Layer occupancy (ticks) 1094system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1096system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1097system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks) 1098system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1099system.iobus.respLayer3.occupancy 36842591 # Layer occupancy (ticks) 1100system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1039system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1040system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1041system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1042system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1043system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1044system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1045system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1046system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1054system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1055system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1056system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1057system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1058system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1059system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1060system.cpu0.dtb.inst_hits 0 # ITB inst hits 1061system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1101system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1102system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1103system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1104system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1105system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1106system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1107system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1108system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1116system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1117system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1118system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1119system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1120system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1121system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1122system.cpu0.dtb.inst_hits 0 # ITB inst hits 1123system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1062system.cpu0.dtb.read_hits 7131006 # DTB read hits 1063system.cpu0.dtb.read_misses 3644 # DTB read misses 1064system.cpu0.dtb.write_hits 6127729 # DTB write hits 1065system.cpu0.dtb.write_misses 663 # DTB write misses 1066system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1067system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1068system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1069system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1070system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB | 1124system.cpu0.dtb.read_hits 24353899 # DTB read hits 1125system.cpu0.dtb.read_misses 6408 # DTB read misses 1126system.cpu0.dtb.write_hits 18126722 # DTB write hits 1127system.cpu0.dtb.write_misses 1115 # DTB write misses 1128system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1129system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1130system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1131system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1132system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB |
| 1071system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1133system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1072system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch | 1134system.cpu0.dtb.prefetch_faults 1442 # Number of TLB faults due to prefetch |
| 1073system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1135system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1074system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1075system.cpu0.dtb.read_accesses 7134650 # DTB read accesses 1076system.cpu0.dtb.write_accesses 6128392 # DTB write accesses | 1136system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 1137system.cpu0.dtb.read_accesses 24360307 # DTB read accesses 1138system.cpu0.dtb.write_accesses 18127837 # DTB write accesses |
| 1077system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1139system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1078system.cpu0.dtb.hits 13258735 # DTB hits 1079system.cpu0.dtb.misses 4307 # DTB misses 1080system.cpu0.dtb.accesses 13263042 # DTB accesses | 1140system.cpu0.dtb.hits 42480621 # DTB hits 1141system.cpu0.dtb.misses 7523 # DTB misses 1142system.cpu0.dtb.accesses 42488144 # DTB accesses |
| 1081system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1082system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1083system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1084system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1085system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1086system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1087system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1088system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1094system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1095system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1096system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1097system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1098system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1099system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1100system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1101system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1143system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1144system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1145system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1146system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1147system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1148system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1149system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1150system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1156system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1157system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1158system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1159system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1160system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1161system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1162system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1163system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1102system.cpu0.itb.inst_hits 31182741 # ITB inst hits 1103system.cpu0.itb.inst_misses 2176 # ITB inst misses | 1164system.cpu0.itb.inst_hits 115074724 # ITB inst hits 1165system.cpu0.itb.inst_misses 3350 # ITB inst misses |
| 1104system.cpu0.itb.read_hits 0 # DTB read hits 1105system.cpu0.itb.read_misses 0 # DTB read misses 1106system.cpu0.itb.write_hits 0 # DTB write hits 1107system.cpu0.itb.write_misses 0 # DTB write misses | 1166system.cpu0.itb.read_hits 0 # DTB read hits 1167system.cpu0.itb.read_misses 0 # DTB read misses 1168system.cpu0.itb.write_hits 0 # DTB write hits 1169system.cpu0.itb.write_misses 0 # DTB write misses |
| 1108system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1109system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1110system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1111system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1112system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB | 1170system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 1171system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1172system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1173system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1174system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB |
| 1113system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1114system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1115system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1116system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1117system.cpu0.itb.read_accesses 0 # DTB read accesses 1118system.cpu0.itb.write_accesses 0 # DTB write accesses | 1175system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1176system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1177system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1178system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1179system.cpu0.itb.read_accesses 0 # DTB read accesses 1180system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1119system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses 1120system.cpu0.itb.hits 31182741 # DTB hits 1121system.cpu0.itb.misses 2176 # DTB misses 1122system.cpu0.itb.accesses 31184917 # DTB accesses 1123system.cpu0.numCycles 5349463018 # number of cpu cycles simulated | 1181system.cpu0.itb.inst_accesses 115078074 # ITB inst accesses 1182system.cpu0.itb.hits 115074724 # DTB hits 1183system.cpu0.itb.misses 3350 # DTB misses 1184system.cpu0.itb.accesses 115078074 # DTB accesses 1185system.cpu0.numCycles 5733858512 # number of cpu cycles simulated |
| 1124system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1125system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1186system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1187system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1126system.cpu0.committedInsts 30507218 # Number of instructions committed 1127system.cpu0.committedOps 36803230 # Number of ops (including micro ops) committed 1128system.cpu0.num_int_alu_accesses 32859018 # Number of integer alu accesses 1129system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 1130system.cpu0.num_func_calls 1290775 # number of times a function call or return occured 1131system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls 1132system.cpu0.num_int_insts 32859018 # number of integer instructions 1133system.cpu0.num_fp_insts 5449 # number of float instructions 1134system.cpu0.num_int_register_reads 60131579 # number of times the integer registers were read 1135system.cpu0.num_int_register_writes 21902535 # number of times the integer registers were written 1136system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 1137system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 1138system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read 1139system.cpu0.num_cc_register_writes 14490121 # number of times the CC registers were written 1140system.cpu0.num_mem_refs 13795466 # number of memory refs 1141system.cpu0.num_load_insts 7343231 # Number of load instructions 1142system.cpu0.num_store_insts 6452235 # Number of store instructions 1143system.cpu0.num_idle_cycles 4898257252.279955 # Number of idle cycles 1144system.cpu0.num_busy_cycles 451205765.720045 # Number of busy cycles 1145system.cpu0.not_idle_fraction 0.084346 # Percentage of non-idle cycles 1146system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles 1147system.cpu0.Branches 5660514 # Number of branches fetched 1148system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction 1149system.cpu0.op_class::IntAlu 23591543 62.99% 63.03% # Class of executed instruction 1150system.cpu0.op_class::IntMult 47189 0.13% 63.16% # Class of executed instruction 1151system.cpu0.op_class::IntDiv 0 0.00% 63.16% # Class of executed instruction 1152system.cpu0.op_class::FloatAdd 0 0.00% 63.16% # Class of executed instruction 1153system.cpu0.op_class::FloatCmp 0 0.00% 63.16% # Class of executed instruction 1154system.cpu0.op_class::FloatCvt 0 0.00% 63.16% # Class of executed instruction 1155system.cpu0.op_class::FloatMult 0 0.00% 63.16% # Class of executed instruction 1156system.cpu0.op_class::FloatDiv 0 0.00% 63.16% # Class of executed instruction 1157system.cpu0.op_class::FloatSqrt 0 0.00% 63.16% # Class of executed instruction 1158system.cpu0.op_class::SimdAdd 0 0.00% 63.16% # Class of executed instruction 1159system.cpu0.op_class::SimdAddAcc 0 0.00% 63.16% # Class of executed instruction 1160system.cpu0.op_class::SimdAlu 0 0.00% 63.16% # Class of executed instruction 1161system.cpu0.op_class::SimdCmp 0 0.00% 63.16% # Class of executed instruction 1162system.cpu0.op_class::SimdCvt 0 0.00% 63.16% # Class of executed instruction 1163system.cpu0.op_class::SimdMisc 0 0.00% 63.16% # Class of executed instruction 1164system.cpu0.op_class::SimdMult 0 0.00% 63.16% # Class of executed instruction 1165system.cpu0.op_class::SimdMultAcc 0 0.00% 63.16% # Class of executed instruction 1166system.cpu0.op_class::SimdShift 0 0.00% 63.16% # Class of executed instruction 1167system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.16% # Class of executed instruction 1168system.cpu0.op_class::SimdSqrt 0 0.00% 63.16% # Class of executed instruction 1169system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.16% # Class of executed instruction 1170system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.16% # Class of executed instruction 1171system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.16% # Class of executed instruction 1172system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.16% # Class of executed instruction 1173system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.16% # Class of executed instruction 1174system.cpu0.op_class::SimdFloatMisc 1591 0.00% 63.17% # Class of executed instruction 1175system.cpu0.op_class::SimdFloatMult 0 0.00% 63.17% # Class of executed instruction 1176system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.17% # Class of executed instruction 1177system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.17% # Class of executed instruction 1178system.cpu0.op_class::MemRead 7343231 19.61% 82.77% # Class of executed instruction 1179system.cpu0.op_class::MemWrite 6452235 17.23% 100.00% # Class of executed instruction | 1188system.cpu0.committedInsts 111430460 # Number of instructions committed 1189system.cpu0.committedOps 134719109 # Number of ops (including micro ops) committed 1190system.cpu0.num_int_alu_accesses 119427816 # Number of integer alu accesses 1191system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 1192system.cpu0.num_func_calls 12527987 # number of times a function call or return occured 1193system.cpu0.num_conditional_control_insts 14980229 # number of instructions that are conditional controls 1194system.cpu0.num_int_insts 119427816 # number of integer instructions 1195system.cpu0.num_fp_insts 9755 # number of float instructions 1196system.cpu0.num_int_register_reads 220379706 # number of times the integer registers were read 1197system.cpu0.num_int_register_writes 83050844 # number of times the integer registers were written 1198system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 1199system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 1200system.cpu0.num_cc_register_reads 488414813 # number of times the CC registers were read 1201system.cpu0.num_cc_register_writes 49991768 # number of times the CC registers were written 1202system.cpu0.num_mem_refs 43590115 # number of memory refs 1203system.cpu0.num_load_insts 24600281 # Number of load instructions 1204system.cpu0.num_store_insts 18989834 # Number of store instructions 1205system.cpu0.num_idle_cycles 5477713409.888090 # Number of idle cycles 1206system.cpu0.num_busy_cycles 256145102.111911 # Number of busy cycles 1207system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles 1208system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles 1209system.cpu0.Branches 28216928 # Number of branches fetched 1210system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction 1211system.cpu0.op_class::IntAlu 94734127 68.43% 68.43% # Class of executed instruction 1212system.cpu0.op_class::IntMult 104105 0.08% 68.51% # Class of executed instruction 1213system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction 1214system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction 1215system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction 1216system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction 1217system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction 1218system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction 1219system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction 1220system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction 1221system.cpu0.op_class::SimdAddAcc 0 0.00% 68.51% # Class of executed instruction 1222system.cpu0.op_class::SimdAlu 0 0.00% 68.51% # Class of executed instruction 1223system.cpu0.op_class::SimdCmp 0 0.00% 68.51% # Class of executed instruction 1224system.cpu0.op_class::SimdCvt 0 0.00% 68.51% # Class of executed instruction 1225system.cpu0.op_class::SimdMisc 0 0.00% 68.51% # Class of executed instruction 1226system.cpu0.op_class::SimdMult 0 0.00% 68.51% # Class of executed instruction 1227system.cpu0.op_class::SimdMultAcc 0 0.00% 68.51% # Class of executed instruction 1228system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction 1229system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction 1230system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction 1231system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction 1232system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction 1233system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction 1234system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction 1235system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction 1236system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction 1237system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction 1238system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction 1239system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction 1240system.cpu0.op_class::MemRead 24600281 17.77% 86.28% # Class of executed instruction 1241system.cpu0.op_class::MemWrite 18989834 13.72% 100.00% # Class of executed instruction |
| 1180system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1181system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1242system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1243system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1182system.cpu0.op_class::total 37452110 # Class of executed instruction | 1244system.cpu0.op_class::total 138438000 # Class of executed instruction |
| 1183system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1245system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1184system.cpu0.kern.inst.quiesce 51950 # number of quiesce instructions executed 1185system.cpu0.icache.tags.replacements 369506 # number of replacements 1186system.cpu0.icache.tags.tagsinuse 511.465010 # Cycle average of tags in use 1187system.cpu0.icache.tags.total_refs 30812705 # Total number of references to valid blocks. 1188system.cpu0.icache.tags.sampled_refs 370018 # Sample count of references to valid blocks. 1189system.cpu0.icache.tags.avg_refs 83.273530 # Average number of references to valid blocks. 1190system.cpu0.icache.tags.warmup_cycle 10201796750 # Cycle when the warmup percentage was hit. 1191system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.465010 # Average occupied blocks per requestor 1192system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998955 # Average percentage of cache occupancy 1193system.cpu0.icache.tags.occ_percent::total 0.998955 # Average percentage of cache occupancy | 1246system.cpu0.kern.inst.quiesce 2074 # number of quiesce instructions executed 1247system.cpu0.icache.tags.replacements 1061133 # number of replacements 1248system.cpu0.icache.tags.tagsinuse 511.483144 # Cycle average of tags in use 1249system.cpu0.icache.tags.total_refs 114013070 # Total number of references to valid blocks. 1250system.cpu0.icache.tags.sampled_refs 1061645 # Sample count of references to valid blocks. 1251system.cpu0.icache.tags.avg_refs 107.392838 # Average number of references to valid blocks. 1252system.cpu0.icache.tags.warmup_cycle 12807152500 # Cycle when the warmup percentage was hit. 1253system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483144 # Average occupied blocks per requestor 1254system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy 1255system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy |
| 1194system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1256system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1195system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id 1196system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id | 1257system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 1258system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id 1259system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id |
| 1197system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1260system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1198system.cpu0.icache.tags.tag_accesses 62735467 # Number of tag accesses 1199system.cpu0.icache.tags.data_accesses 62735467 # Number of data accesses 1200system.cpu0.icache.ReadReq_hits::cpu0.inst 30812705 # number of ReadReq hits 1201system.cpu0.icache.ReadReq_hits::total 30812705 # number of ReadReq hits 1202system.cpu0.icache.demand_hits::cpu0.inst 30812705 # number of demand (read+write) hits 1203system.cpu0.icache.demand_hits::total 30812705 # number of demand (read+write) hits 1204system.cpu0.icache.overall_hits::cpu0.inst 30812705 # number of overall hits 1205system.cpu0.icache.overall_hits::total 30812705 # number of overall hits 1206system.cpu0.icache.ReadReq_misses::cpu0.inst 370019 # number of ReadReq misses 1207system.cpu0.icache.ReadReq_misses::total 370019 # number of ReadReq misses 1208system.cpu0.icache.demand_misses::cpu0.inst 370019 # number of demand (read+write) misses 1209system.cpu0.icache.demand_misses::total 370019 # number of demand (read+write) misses 1210system.cpu0.icache.overall_misses::cpu0.inst 370019 # number of overall misses 1211system.cpu0.icache.overall_misses::total 370019 # number of overall misses 1212system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3209345752 # number of ReadReq miss cycles 1213system.cpu0.icache.ReadReq_miss_latency::total 3209345752 # number of ReadReq miss cycles 1214system.cpu0.icache.demand_miss_latency::cpu0.inst 3209345752 # number of demand (read+write) miss cycles 1215system.cpu0.icache.demand_miss_latency::total 3209345752 # number of demand (read+write) miss cycles 1216system.cpu0.icache.overall_miss_latency::cpu0.inst 3209345752 # number of overall miss cycles 1217system.cpu0.icache.overall_miss_latency::total 3209345752 # number of overall miss cycles 1218system.cpu0.icache.ReadReq_accesses::cpu0.inst 31182724 # number of ReadReq accesses(hits+misses) 1219system.cpu0.icache.ReadReq_accesses::total 31182724 # number of ReadReq accesses(hits+misses) 1220system.cpu0.icache.demand_accesses::cpu0.inst 31182724 # number of demand (read+write) accesses 1221system.cpu0.icache.demand_accesses::total 31182724 # number of demand (read+write) accesses 1222system.cpu0.icache.overall_accesses::cpu0.inst 31182724 # number of overall (read+write) accesses 1223system.cpu0.icache.overall_accesses::total 31182724 # number of overall (read+write) accesses 1224system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011866 # miss rate for ReadReq accesses 1225system.cpu0.icache.ReadReq_miss_rate::total 0.011866 # miss rate for ReadReq accesses 1226system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011866 # miss rate for demand accesses 1227system.cpu0.icache.demand_miss_rate::total 0.011866 # miss rate for demand accesses 1228system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011866 # miss rate for overall accesses 1229system.cpu0.icache.overall_miss_rate::total 0.011866 # miss rate for overall accesses 1230system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8673.462044 # average ReadReq miss latency 1231system.cpu0.icache.ReadReq_avg_miss_latency::total 8673.462044 # average ReadReq miss latency 1232system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency 1233system.cpu0.icache.demand_avg_miss_latency::total 8673.462044 # average overall miss latency 1234system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency 1235system.cpu0.icache.overall_avg_miss_latency::total 8673.462044 # average overall miss latency | 1261system.cpu0.icache.tags.tag_accesses 231211102 # Number of tag accesses 1262system.cpu0.icache.tags.data_accesses 231211102 # Number of data accesses 1263system.cpu0.icache.ReadReq_hits::cpu0.inst 114013070 # number of ReadReq hits 1264system.cpu0.icache.ReadReq_hits::total 114013070 # number of ReadReq hits 1265system.cpu0.icache.demand_hits::cpu0.inst 114013070 # number of demand (read+write) hits 1266system.cpu0.icache.demand_hits::total 114013070 # number of demand (read+write) hits 1267system.cpu0.icache.overall_hits::cpu0.inst 114013070 # number of overall hits 1268system.cpu0.icache.overall_hits::total 114013070 # number of overall hits 1269system.cpu0.icache.ReadReq_misses::cpu0.inst 1061654 # number of ReadReq misses 1270system.cpu0.icache.ReadReq_misses::total 1061654 # number of ReadReq misses 1271system.cpu0.icache.demand_misses::cpu0.inst 1061654 # number of demand (read+write) misses 1272system.cpu0.icache.demand_misses::total 1061654 # number of demand (read+write) misses 1273system.cpu0.icache.overall_misses::cpu0.inst 1061654 # number of overall misses 1274system.cpu0.icache.overall_misses::total 1061654 # number of overall misses 1275system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000777256 # number of ReadReq miss cycles 1276system.cpu0.icache.ReadReq_miss_latency::total 9000777256 # number of ReadReq miss cycles 1277system.cpu0.icache.demand_miss_latency::cpu0.inst 9000777256 # number of demand (read+write) miss cycles 1278system.cpu0.icache.demand_miss_latency::total 9000777256 # number of demand (read+write) miss cycles 1279system.cpu0.icache.overall_miss_latency::cpu0.inst 9000777256 # number of overall miss cycles 1280system.cpu0.icache.overall_miss_latency::total 9000777256 # number of overall miss cycles 1281system.cpu0.icache.ReadReq_accesses::cpu0.inst 115074724 # number of ReadReq accesses(hits+misses) 1282system.cpu0.icache.ReadReq_accesses::total 115074724 # number of ReadReq accesses(hits+misses) 1283system.cpu0.icache.demand_accesses::cpu0.inst 115074724 # number of demand (read+write) accesses 1284system.cpu0.icache.demand_accesses::total 115074724 # number of demand (read+write) accesses 1285system.cpu0.icache.overall_accesses::cpu0.inst 115074724 # number of overall (read+write) accesses 1286system.cpu0.icache.overall_accesses::total 115074724 # number of overall (read+write) accesses 1287system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses 1288system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses 1289system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses 1290system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses 1291system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses 1292system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses 1293system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.070309 # average ReadReq miss latency 1294system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.070309 # average ReadReq miss latency 1295system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency 1296system.cpu0.icache.demand_avg_miss_latency::total 8478.070309 # average overall miss latency 1297system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency 1298system.cpu0.icache.overall_avg_miss_latency::total 8478.070309 # average overall miss latency |
| 1236system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1237system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1238system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1239system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1240system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1241system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1242system.cpu0.icache.fast_writes 0 # number of fast writes performed 1243system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1299system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1300system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1301system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1302system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1303system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1304system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1305system.cpu0.icache.fast_writes 0 # number of fast writes performed 1306system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1244system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 370019 # number of ReadReq MSHR misses 1245system.cpu0.icache.ReadReq_mshr_misses::total 370019 # number of ReadReq MSHR misses 1246system.cpu0.icache.demand_mshr_misses::cpu0.inst 370019 # number of demand (read+write) MSHR misses 1247system.cpu0.icache.demand_mshr_misses::total 370019 # number of demand (read+write) MSHR misses 1248system.cpu0.icache.overall_mshr_misses::cpu0.inst 370019 # number of overall MSHR misses 1249system.cpu0.icache.overall_mshr_misses::total 370019 # number of overall MSHR misses 1250system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2653955748 # number of ReadReq MSHR miss cycles 1251system.cpu0.icache.ReadReq_mshr_miss_latency::total 2653955748 # number of ReadReq MSHR miss cycles 1252system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2653955748 # number of demand (read+write) MSHR miss cycles 1253system.cpu0.icache.demand_mshr_miss_latency::total 2653955748 # number of demand (read+write) MSHR miss cycles 1254system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2653955748 # number of overall MSHR miss cycles 1255system.cpu0.icache.overall_mshr_miss_latency::total 2653955748 # number of overall MSHR miss cycles 1256system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 531257750 # number of ReadReq MSHR uncacheable cycles 1257system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 531257750 # number of ReadReq MSHR uncacheable cycles 1258system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 531257750 # number of overall MSHR uncacheable cycles 1259system.cpu0.icache.overall_mshr_uncacheable_latency::total 531257750 # number of overall MSHR uncacheable cycles 1260system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for ReadReq accesses 1261system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011866 # mshr miss rate for ReadReq accesses 1262system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for demand accesses 1263system.cpu0.icache.demand_mshr_miss_rate::total 0.011866 # mshr miss rate for demand accesses 1264system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for overall accesses 1265system.cpu0.icache.overall_mshr_miss_rate::total 0.011866 # mshr miss rate for overall accesses 1266system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average ReadReq mshr miss latency 1267system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7172.485056 # average ReadReq mshr miss latency 1268system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency 1269system.cpu0.icache.demand_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency 1270system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency 1271system.cpu0.icache.overall_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency | 1307system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061654 # number of ReadReq MSHR misses 1308system.cpu0.icache.ReadReq_mshr_misses::total 1061654 # number of ReadReq MSHR misses 1309system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061654 # number of demand (read+write) MSHR misses 1310system.cpu0.icache.demand_mshr_misses::total 1061654 # number of demand (read+write) MSHR misses 1311system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061654 # number of overall MSHR misses 1312system.cpu0.icache.overall_mshr_misses::total 1061654 # number of overall MSHR misses 1313system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407609744 # number of ReadReq MSHR miss cycles 1314system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407609744 # number of ReadReq MSHR miss cycles 1315system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407609744 # number of demand (read+write) MSHR miss cycles 1316system.cpu0.icache.demand_mshr_miss_latency::total 7407609744 # number of demand (read+write) MSHR miss cycles 1317system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407609744 # number of overall MSHR miss cycles 1318system.cpu0.icache.overall_mshr_miss_latency::total 7407609744 # number of overall MSHR miss cycles 1319system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719278000 # number of ReadReq MSHR uncacheable cycles 1320system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719278000 # number of ReadReq MSHR uncacheable cycles 1321system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719278000 # number of overall MSHR uncacheable cycles 1322system.cpu0.icache.overall_mshr_uncacheable_latency::total 719278000 # number of overall MSHR uncacheable cycles 1323system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses 1324system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses 1325system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses 1326system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses 1327system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses 1328system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses 1329system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average ReadReq mshr miss latency 1330system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.423665 # average ReadReq mshr miss latency 1331system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency 1332system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency 1333system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency 1334system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency |
| 1272system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1273system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1274system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1275system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1276system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1335system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1336system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1337system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1338system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1339system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1277system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 4129417 # number of hwpf identified 1278system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 113341 # number of hwpf that were already in mshr 1279system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3763718 # number of hwpf that were already in the cache 1280system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 300 # number of hwpf that were already in the prefetch queue | 1340system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923568 # number of hwpf identified 1341system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 227909 # number of hwpf that were already in mshr 1342system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9246862 # number of hwpf that were already in the cache 1343system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 529 # number of hwpf that were already in the prefetch queue |
| 1281system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 1344system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 1282system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 22 # number of hwpf removed because MSHR allocated 1283system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 252036 # number of hwpf issued 1284system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 312183 # number of hwpf spanning a virtual page | 1345system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 49 # number of hwpf removed because MSHR allocated 1346system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 448219 # number of hwpf issued 1347system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778472 # number of hwpf spanning a virtual page |
| 1285system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1348system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1286system.cpu0.l2cache.tags.replacements 213190 # number of replacements 1287system.cpu0.l2cache.tags.tagsinuse 16168.240053 # Cycle average of tags in use 1288system.cpu0.l2cache.tags.total_refs 848978 # Total number of references to valid blocks. 1289system.cpu0.l2cache.tags.sampled_refs 228702 # Sample count of references to valid blocks. 1290system.cpu0.l2cache.tags.avg_refs 3.712158 # Average number of references to valid blocks. 1291system.cpu0.l2cache.tags.warmup_cycle 7921739000 # Cycle when the warmup percentage was hit. 1292system.cpu0.l2cache.tags.occ_blocks::writebacks 4749.054127 # Average occupied blocks per requestor 1293system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.517230 # Average occupied blocks per requestor 1294system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.260718 # Average occupied blocks per requestor 1295system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 821.211493 # Average occupied blocks per requestor 1296system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1542.145038 # Average occupied blocks per requestor 1297system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9052.051448 # Average occupied blocks per requestor 1298system.cpu0.l2cache.tags.occ_percent::writebacks 0.289859 # Average percentage of cache occupancy 1299system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy 1300system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 1301system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050123 # Average percentage of cache occupancy 1302system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.094125 # Average percentage of cache occupancy 1303system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.552493 # Average percentage of cache occupancy 1304system.cpu0.l2cache.tags.occ_percent::total 0.986831 # Average percentage of cache occupancy 1305system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8284 # Occupied blocks per task id 1306system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1307system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7219 # Occupied blocks per task id 1308system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1260 # Occupied blocks per task id 1309system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1944 # Occupied blocks per task id 1310system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 5080 # Occupied blocks per task id 1311system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1312system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1313system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1775 # Occupied blocks per task id 1314system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id 1315system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3501 # Occupied blocks per task id 1316system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.505615 # Percentage of cache occupancy per task id 1317system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 1318system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.440613 # Percentage of cache occupancy per task id 1319system.cpu0.l2cache.tags.tag_accesses 17864213 # Number of tag accesses 1320system.cpu0.l2cache.tags.data_accesses 17864213 # Number of data accesses 1321system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4737 # number of ReadReq hits 1322system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2374 # number of ReadReq hits 1323system.cpu0.l2cache.ReadReq_hits::cpu0.inst 361048 # number of ReadReq hits 1324system.cpu0.l2cache.ReadReq_hits::cpu0.data 184302 # number of ReadReq hits 1325system.cpu0.l2cache.ReadReq_hits::total 552461 # number of ReadReq hits 1326system.cpu0.l2cache.Writeback_hits::writebacks 286361 # number of Writeback hits 1327system.cpu0.l2cache.Writeback_hits::total 286361 # number of Writeback hits 1328system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 5612 # number of UpgradeReq hits 1329system.cpu0.l2cache.UpgradeReq_hits::total 5612 # number of UpgradeReq hits 1330system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 831 # number of SCUpgradeReq hits 1331system.cpu0.l2cache.SCUpgradeReq_hits::total 831 # number of SCUpgradeReq hits 1332system.cpu0.l2cache.ReadExReq_hits::cpu0.data 133749 # number of ReadExReq hits 1333system.cpu0.l2cache.ReadExReq_hits::total 133749 # number of ReadExReq hits 1334system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4737 # number of demand (read+write) hits 1335system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2374 # number of demand (read+write) hits 1336system.cpu0.l2cache.demand_hits::cpu0.inst 361048 # number of demand (read+write) hits 1337system.cpu0.l2cache.demand_hits::cpu0.data 318051 # number of demand (read+write) hits 1338system.cpu0.l2cache.demand_hits::total 686210 # number of demand (read+write) hits 1339system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4737 # number of overall hits 1340system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2374 # number of overall hits 1341system.cpu0.l2cache.overall_hits::cpu0.inst 361048 # number of overall hits 1342system.cpu0.l2cache.overall_hits::cpu0.data 318051 # number of overall hits 1343system.cpu0.l2cache.overall_hits::total 686210 # number of overall hits 1344system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses 1345system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses 1346system.cpu0.l2cache.ReadReq_misses::cpu0.inst 8693 # number of ReadReq misses 1347system.cpu0.l2cache.ReadReq_misses::cpu0.data 48360 # number of ReadReq misses 1348system.cpu0.l2cache.ReadReq_misses::total 57424 # number of ReadReq misses 1349system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 1350system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses 1351system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 18405 # number of UpgradeReq misses 1352system.cpu0.l2cache.UpgradeReq_misses::total 18405 # number of UpgradeReq misses 1353system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10323 # number of SCUpgradeReq misses 1354system.cpu0.l2cache.SCUpgradeReq_misses::total 10323 # number of SCUpgradeReq misses 1355system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1356system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1357system.cpu0.l2cache.ReadExReq_misses::cpu0.data 24100 # number of ReadExReq misses 1358system.cpu0.l2cache.ReadExReq_misses::total 24100 # number of ReadExReq misses 1359system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses 1360system.cpu0.l2cache.demand_misses::cpu0.itb.walker 146 # number of demand (read+write) misses 1361system.cpu0.l2cache.demand_misses::cpu0.inst 8693 # number of demand (read+write) misses 1362system.cpu0.l2cache.demand_misses::cpu0.data 72460 # number of demand (read+write) misses 1363system.cpu0.l2cache.demand_misses::total 81524 # number of demand (read+write) misses 1364system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses 1365system.cpu0.l2cache.overall_misses::cpu0.itb.walker 146 # number of overall misses 1366system.cpu0.l2cache.overall_misses::cpu0.inst 8693 # number of overall misses 1367system.cpu0.l2cache.overall_misses::cpu0.data 72460 # number of overall misses 1368system.cpu0.l2cache.overall_misses::total 81524 # number of overall misses 1369system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4897000 # number of ReadReq miss cycles 1370system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3307000 # number of ReadReq miss cycles 1371system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 300815745 # number of ReadReq miss cycles 1372system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1253383203 # number of ReadReq miss cycles 1373system.cpu0.l2cache.ReadReq_miss_latency::total 1562402948 # number of ReadReq miss cycles 1374system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 288253128 # number of UpgradeReq miss cycles 1375system.cpu0.l2cache.UpgradeReq_miss_latency::total 288253128 # number of UpgradeReq miss cycles 1376system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 204026156 # number of SCUpgradeReq miss cycles 1377system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 204026156 # number of SCUpgradeReq miss cycles 1378system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1056000 # number of SCUpgradeFailReq miss cycles 1379system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1056000 # number of SCUpgradeFailReq miss cycles 1380system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 855610215 # number of ReadExReq miss cycles 1381system.cpu0.l2cache.ReadExReq_miss_latency::total 855610215 # number of ReadExReq miss cycles 1382system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4897000 # number of demand (read+write) miss cycles 1383system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3307000 # number of demand (read+write) miss cycles 1384system.cpu0.l2cache.demand_miss_latency::cpu0.inst 300815745 # number of demand (read+write) miss cycles 1385system.cpu0.l2cache.demand_miss_latency::cpu0.data 2108993418 # number of demand (read+write) miss cycles 1386system.cpu0.l2cache.demand_miss_latency::total 2418013163 # number of demand (read+write) miss cycles 1387system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4897000 # number of overall miss cycles 1388system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3307000 # number of overall miss cycles 1389system.cpu0.l2cache.overall_miss_latency::cpu0.inst 300815745 # number of overall miss cycles 1390system.cpu0.l2cache.overall_miss_latency::cpu0.data 2108993418 # number of overall miss cycles 1391system.cpu0.l2cache.overall_miss_latency::total 2418013163 # number of overall miss cycles 1392system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4962 # number of ReadReq accesses(hits+misses) 1393system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2520 # number of ReadReq accesses(hits+misses) 1394system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 369741 # number of ReadReq accesses(hits+misses) 1395system.cpu0.l2cache.ReadReq_accesses::cpu0.data 232662 # number of ReadReq accesses(hits+misses) 1396system.cpu0.l2cache.ReadReq_accesses::total 609885 # number of ReadReq accesses(hits+misses) 1397system.cpu0.l2cache.Writeback_accesses::writebacks 286363 # number of Writeback accesses(hits+misses) 1398system.cpu0.l2cache.Writeback_accesses::total 286363 # number of Writeback accesses(hits+misses) 1399system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 24017 # number of UpgradeReq accesses(hits+misses) 1400system.cpu0.l2cache.UpgradeReq_accesses::total 24017 # number of UpgradeReq accesses(hits+misses) 1401system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11154 # number of SCUpgradeReq accesses(hits+misses) 1402system.cpu0.l2cache.SCUpgradeReq_accesses::total 11154 # number of SCUpgradeReq accesses(hits+misses) 1403system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1404system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1405system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 157849 # number of ReadExReq accesses(hits+misses) 1406system.cpu0.l2cache.ReadExReq_accesses::total 157849 # number of ReadExReq accesses(hits+misses) 1407system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4962 # number of demand (read+write) accesses 1408system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2520 # number of demand (read+write) accesses 1409system.cpu0.l2cache.demand_accesses::cpu0.inst 369741 # number of demand (read+write) accesses 1410system.cpu0.l2cache.demand_accesses::cpu0.data 390511 # number of demand (read+write) accesses 1411system.cpu0.l2cache.demand_accesses::total 767734 # number of demand (read+write) accesses 1412system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4962 # number of overall (read+write) accesses 1413system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2520 # number of overall (read+write) accesses 1414system.cpu0.l2cache.overall_accesses::cpu0.inst 369741 # number of overall (read+write) accesses 1415system.cpu0.l2cache.overall_accesses::cpu0.data 390511 # number of overall (read+write) accesses 1416system.cpu0.l2cache.overall_accesses::total 767734 # number of overall (read+write) accesses 1417system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for ReadReq accesses 1418system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057937 # miss rate for ReadReq accesses 1419system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.023511 # miss rate for ReadReq accesses 1420system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.207855 # miss rate for ReadReq accesses 1421system.cpu0.l2cache.ReadReq_miss_rate::total 0.094155 # miss rate for ReadReq accesses 1422system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses 1423system.cpu0.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses 1424system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.766332 # miss rate for UpgradeReq accesses 1425system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.766332 # miss rate for UpgradeReq accesses 1426system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.925498 # miss rate for SCUpgradeReq accesses 1427system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.925498 # miss rate for SCUpgradeReq accesses | 1349system.cpu0.l2cache.tags.replacements 358131 # number of replacements 1350system.cpu0.l2cache.tags.tagsinuse 16113.840521 # Cycle average of tags in use 1351system.cpu0.l2cache.tags.total_refs 1936015 # Total number of references to valid blocks. 1352system.cpu0.l2cache.tags.sampled_refs 374364 # Sample count of references to valid blocks. 1353system.cpu0.l2cache.tags.avg_refs 5.171477 # Average number of references to valid blocks. 1354system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1355system.cpu0.l2cache.tags.occ_blocks::writebacks 6748.405331 # Average occupied blocks per requestor 1356system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.298352 # Average occupied blocks per requestor 1357system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.117074 # Average occupied blocks per requestor 1358system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 799.968206 # Average occupied blocks per requestor 1359system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1087.232896 # Average occupied blocks per requestor 1360system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7475.818663 # Average occupied blocks per requestor 1361system.cpu0.l2cache.tags.occ_percent::writebacks 0.411890 # Average percentage of cache occupancy 1362system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000140 # Average percentage of cache occupancy 1363system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy 1364system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048826 # Average percentage of cache occupancy 1365system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.066359 # Average percentage of cache occupancy 1366system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.456288 # Average percentage of cache occupancy 1367system.cpu0.l2cache.tags.occ_percent::total 0.983511 # Average percentage of cache occupancy 1368system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7939 # Occupied blocks per task id 1369system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 1370system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8291 # Occupied blocks per task id 1371system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id 1372system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 127 # Occupied blocks per task id 1373system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1966 # Occupied blocks per task id 1374system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4890 # Occupied blocks per task id 1375system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 915 # Occupied blocks per task id 1376system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 1377system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1378system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 1379system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id 1380system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2895 # Occupied blocks per task id 1381system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4675 # Occupied blocks per task id 1382system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id 1383system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.484558 # Percentage of cache occupancy per task id 1384system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 1385system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.506042 # Percentage of cache occupancy per task id 1386system.cpu0.l2cache.tags.tag_accesses 38026831 # Number of tag accesses 1387system.cpu0.l2cache.tags.data_accesses 38026831 # Number of data accesses 1388system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 6990 # number of ReadReq hits 1389system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3189 # number of ReadReq hits 1390system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045942 # number of ReadReq hits 1391system.cpu0.l2cache.ReadReq_hits::cpu0.data 372788 # number of ReadReq hits 1392system.cpu0.l2cache.ReadReq_hits::total 1428909 # number of ReadReq hits 1393system.cpu0.l2cache.Writeback_hits::writebacks 483936 # number of Writeback hits 1394system.cpu0.l2cache.Writeback_hits::total 483936 # number of Writeback hits 1395system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10087 # number of UpgradeReq hits 1396system.cpu0.l2cache.UpgradeReq_hits::total 10087 # number of UpgradeReq hits 1397system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2033 # number of SCUpgradeReq hits 1398system.cpu0.l2cache.SCUpgradeReq_hits::total 2033 # number of SCUpgradeReq hits 1399system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212805 # number of ReadExReq hits 1400system.cpu0.l2cache.ReadExReq_hits::total 212805 # number of ReadExReq hits 1401system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 6990 # number of demand (read+write) hits 1402system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3189 # number of demand (read+write) hits 1403system.cpu0.l2cache.demand_hits::cpu0.inst 1045942 # number of demand (read+write) hits 1404system.cpu0.l2cache.demand_hits::cpu0.data 585593 # number of demand (read+write) hits 1405system.cpu0.l2cache.demand_hits::total 1641714 # number of demand (read+write) hits 1406system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 6990 # number of overall hits 1407system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3189 # number of overall hits 1408system.cpu0.l2cache.overall_hits::cpu0.inst 1045942 # number of overall hits 1409system.cpu0.l2cache.overall_hits::cpu0.data 585593 # number of overall hits 1410system.cpu0.l2cache.overall_hits::total 1641714 # number of overall hits 1411system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 263 # number of ReadReq misses 1412system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 219 # number of ReadReq misses 1413system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15712 # number of ReadReq misses 1414system.cpu0.l2cache.ReadReq_misses::cpu0.data 83577 # number of ReadReq misses 1415system.cpu0.l2cache.ReadReq_misses::total 99771 # number of ReadReq misses 1416system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29878 # number of UpgradeReq misses 1417system.cpu0.l2cache.UpgradeReq_misses::total 29878 # number of UpgradeReq misses 1418system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19321 # number of SCUpgradeReq misses 1419system.cpu0.l2cache.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses 1420system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 1421system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1422system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44921 # number of ReadExReq misses 1423system.cpu0.l2cache.ReadExReq_misses::total 44921 # number of ReadExReq misses 1424system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 263 # number of demand (read+write) misses 1425system.cpu0.l2cache.demand_misses::cpu0.itb.walker 219 # number of demand (read+write) misses 1426system.cpu0.l2cache.demand_misses::cpu0.inst 15712 # number of demand (read+write) misses 1427system.cpu0.l2cache.demand_misses::cpu0.data 128498 # number of demand (read+write) misses 1428system.cpu0.l2cache.demand_misses::total 144692 # number of demand (read+write) misses 1429system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 263 # number of overall misses 1430system.cpu0.l2cache.overall_misses::cpu0.itb.walker 219 # number of overall misses 1431system.cpu0.l2cache.overall_misses::cpu0.inst 15712 # number of overall misses 1432system.cpu0.l2cache.overall_misses::cpu0.data 128498 # number of overall misses 1433system.cpu0.l2cache.overall_misses::total 144692 # number of overall misses 1434system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6061000 # number of ReadReq miss cycles 1435system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4899500 # number of ReadReq miss cycles 1436system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598206723 # number of ReadReq miss cycles 1437system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2260687668 # number of ReadReq miss cycles 1438system.cpu0.l2cache.ReadReq_miss_latency::total 2869854891 # number of ReadReq miss cycles 1439system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 524614292 # number of UpgradeReq miss cycles 1440system.cpu0.l2cache.UpgradeReq_miss_latency::total 524614292 # number of UpgradeReq miss cycles 1441system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377658880 # number of SCUpgradeReq miss cycles 1442system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377658880 # number of SCUpgradeReq miss cycles 1443system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1333497 # number of SCUpgradeFailReq miss cycles 1444system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1333497 # number of SCUpgradeFailReq miss cycles 1445system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1506710587 # number of ReadExReq miss cycles 1446system.cpu0.l2cache.ReadExReq_miss_latency::total 1506710587 # number of ReadExReq miss cycles 1447system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6061000 # number of demand (read+write) miss cycles 1448system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4899500 # number of demand (read+write) miss cycles 1449system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598206723 # number of demand (read+write) miss cycles 1450system.cpu0.l2cache.demand_miss_latency::cpu0.data 3767398255 # number of demand (read+write) miss cycles 1451system.cpu0.l2cache.demand_miss_latency::total 4376565478 # number of demand (read+write) miss cycles 1452system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6061000 # number of overall miss cycles 1453system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4899500 # number of overall miss cycles 1454system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598206723 # number of overall miss cycles 1455system.cpu0.l2cache.overall_miss_latency::cpu0.data 3767398255 # number of overall miss cycles 1456system.cpu0.l2cache.overall_miss_latency::total 4376565478 # number of overall miss cycles 1457system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7253 # number of ReadReq accesses(hits+misses) 1458system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3408 # number of ReadReq accesses(hits+misses) 1459system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061654 # number of ReadReq accesses(hits+misses) 1460system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456365 # number of ReadReq accesses(hits+misses) 1461system.cpu0.l2cache.ReadReq_accesses::total 1528680 # number of ReadReq accesses(hits+misses) 1462system.cpu0.l2cache.Writeback_accesses::writebacks 483936 # number of Writeback accesses(hits+misses) 1463system.cpu0.l2cache.Writeback_accesses::total 483936 # number of Writeback accesses(hits+misses) 1464system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39965 # number of UpgradeReq accesses(hits+misses) 1465system.cpu0.l2cache.UpgradeReq_accesses::total 39965 # number of UpgradeReq accesses(hits+misses) 1466system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21354 # number of SCUpgradeReq accesses(hits+misses) 1467system.cpu0.l2cache.SCUpgradeReq_accesses::total 21354 # number of SCUpgradeReq accesses(hits+misses) 1468system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1469system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1470system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257726 # number of ReadExReq accesses(hits+misses) 1471system.cpu0.l2cache.ReadExReq_accesses::total 257726 # number of ReadExReq accesses(hits+misses) 1472system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7253 # number of demand (read+write) accesses 1473system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3408 # number of demand (read+write) accesses 1474system.cpu0.l2cache.demand_accesses::cpu0.inst 1061654 # number of demand (read+write) accesses 1475system.cpu0.l2cache.demand_accesses::cpu0.data 714091 # number of demand (read+write) accesses 1476system.cpu0.l2cache.demand_accesses::total 1786406 # number of demand (read+write) accesses 1477system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7253 # number of overall (read+write) accesses 1478system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3408 # number of overall (read+write) accesses 1479system.cpu0.l2cache.overall_accesses::cpu0.inst 1061654 # number of overall (read+write) accesses 1480system.cpu0.l2cache.overall_accesses::cpu0.data 714091 # number of overall (read+write) accesses 1481system.cpu0.l2cache.overall_accesses::total 1786406 # number of overall (read+write) accesses 1482system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for ReadReq accesses 1483system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064261 # miss rate for ReadReq accesses 1484system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014800 # miss rate for ReadReq accesses 1485system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183136 # miss rate for ReadReq accesses 1486system.cpu0.l2cache.ReadReq_miss_rate::total 0.065266 # miss rate for ReadReq accesses 1487system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.747604 # miss rate for UpgradeReq accesses 1488system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.747604 # miss rate for UpgradeReq accesses 1489system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.904795 # miss rate for SCUpgradeReq accesses 1490system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.904795 # miss rate for SCUpgradeReq accesses |
| 1428system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1429system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1491system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1492system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1430system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.152678 # miss rate for ReadExReq accesses 1431system.cpu0.l2cache.ReadExReq_miss_rate::total 0.152678 # miss rate for ReadExReq accesses 1432system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for demand accesses 1433system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057937 # miss rate for demand accesses 1434system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.023511 # miss rate for demand accesses 1435system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185552 # miss rate for demand accesses 1436system.cpu0.l2cache.demand_miss_rate::total 0.106188 # miss rate for demand accesses 1437system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for overall accesses 1438system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057937 # miss rate for overall accesses 1439system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.023511 # miss rate for overall accesses 1440system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185552 # miss rate for overall accesses 1441system.cpu0.l2cache.overall_miss_rate::total 0.106188 # miss rate for overall accesses 1442system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average ReadReq miss latency 1443system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22650.684932 # average ReadReq miss latency 1444system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 34604.365006 # average ReadReq miss latency 1445system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25917.766811 # average ReadReq miss latency 1446system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27208.187308 # average ReadReq miss latency 1447system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15661.674980 # average UpgradeReq miss latency 1448system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15661.674980 # average UpgradeReq miss latency 1449system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19764.230941 # average SCUpgradeReq miss latency 1450system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19764.230941 # average SCUpgradeReq miss latency 1451system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528000 # average SCUpgradeFailReq miss latency 1452system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528000 # average SCUpgradeFailReq miss latency 1453system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 35502.498548 # average ReadExReq miss latency 1454system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35502.498548 # average ReadExReq miss latency 1455system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average overall miss latency 1456system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22650.684932 # average overall miss latency 1457system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34604.365006 # average overall miss latency 1458system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29105.622661 # average overall miss latency 1459system.cpu0.l2cache.demand_avg_miss_latency::total 29660.138892 # average overall miss latency 1460system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average overall miss latency 1461system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22650.684932 # average overall miss latency 1462system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34604.365006 # average overall miss latency 1463system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29105.622661 # average overall miss latency 1464system.cpu0.l2cache.overall_avg_miss_latency::total 29660.138892 # average overall miss latency 1465system.cpu0.l2cache.blocked_cycles::no_mshrs 1020 # number of cycles access was blocked | 1493system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174298 # miss rate for ReadExReq accesses 1494system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174298 # miss rate for ReadExReq accesses 1495system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for demand accesses 1496system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064261 # miss rate for demand accesses 1497system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014800 # miss rate for demand accesses 1498system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179946 # miss rate for demand accesses 1499system.cpu0.l2cache.demand_miss_rate::total 0.080996 # miss rate for demand accesses 1500system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for overall accesses 1501system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064261 # miss rate for overall accesses 1502system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014800 # miss rate for overall accesses 1503system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179946 # miss rate for overall accesses 1504system.cpu0.l2cache.overall_miss_rate::total 0.080996 # miss rate for overall accesses 1505system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average ReadReq miss latency 1506system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22372.146119 # average ReadReq miss latency 1507system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38073.238480 # average ReadReq miss latency 1508system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27049.160271 # average ReadReq miss latency 1509system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28764.419430 # average ReadReq miss latency 1510system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17558.547828 # average UpgradeReq miss latency 1511system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828 # average UpgradeReq miss latency 1512system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350 # average SCUpgradeReq miss latency 1513system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.549350 # average SCUpgradeReq miss latency 1514system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190499.571429 # average SCUpgradeFailReq miss latency 1515system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190499.571429 # average SCUpgradeFailReq miss latency 1516system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177 # average ReadExReq miss latency 1517system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33541.341177 # average ReadExReq miss latency 1518system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency 1519system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency 1520system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency 1521system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency 1522system.cpu0.l2cache.demand_avg_miss_latency::total 30247.459970 # average overall miss latency 1523system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency 1524system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency 1525system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency 1526system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency 1527system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970 # average overall miss latency 1528system.cpu0.l2cache.blocked_cycles::no_mshrs 5815 # number of cycles access was blocked |
| 1466system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1529system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1467system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked | 1530system.cpu0.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked |
| 1468system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1531system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1469system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.903226 # average number of cycles each access was blocked | 1532system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 76.513158 # average number of cycles each access was blocked |
| 1470system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1471system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1472system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1533system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1534system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1535system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1473system.cpu0.l2cache.writebacks::writebacks 141584 # number of writebacks 1474system.cpu0.l2cache.writebacks::total 141584 # number of writebacks 1475system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1192 # number of ReadReq MSHR hits 1476system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 751 # number of ReadReq MSHR hits 1477system.cpu0.l2cache.ReadReq_mshr_hits::total 1943 # number of ReadReq MSHR hits 1478system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 493 # number of ReadExReq MSHR hits 1479system.cpu0.l2cache.ReadExReq_mshr_hits::total 493 # number of ReadExReq MSHR hits 1480system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1192 # number of demand (read+write) MSHR hits 1481system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits 1482system.cpu0.l2cache.demand_mshr_hits::total 2436 # number of demand (read+write) MSHR hits 1483system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1192 # number of overall MSHR hits 1484system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits 1485system.cpu0.l2cache.overall_mshr_hits::total 2436 # number of overall MSHR hits 1486system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 225 # number of ReadReq MSHR misses 1487system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 146 # number of ReadReq MSHR misses 1488system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 7501 # number of ReadReq MSHR misses 1489system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 47609 # number of ReadReq MSHR misses 1490system.cpu0.l2cache.ReadReq_mshr_misses::total 55481 # number of ReadReq MSHR misses 1491system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses 1492system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses 1493system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 252027 # number of HardPFReq MSHR misses 1494system.cpu0.l2cache.HardPFReq_mshr_misses::total 252027 # number of HardPFReq MSHR misses 1495system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 18405 # number of UpgradeReq MSHR misses 1496system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18405 # number of UpgradeReq MSHR misses 1497system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10323 # number of SCUpgradeReq MSHR misses 1498system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10323 # number of SCUpgradeReq MSHR misses 1499system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1500system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1501system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 23607 # number of ReadExReq MSHR misses 1502system.cpu0.l2cache.ReadExReq_mshr_misses::total 23607 # number of ReadExReq MSHR misses 1503system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 225 # number of demand (read+write) MSHR misses 1504system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 146 # number of demand (read+write) MSHR misses 1505system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 7501 # number of demand (read+write) MSHR misses 1506system.cpu0.l2cache.demand_mshr_misses::cpu0.data 71216 # number of demand (read+write) MSHR misses 1507system.cpu0.l2cache.demand_mshr_misses::total 79088 # number of demand (read+write) MSHR misses 1508system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 225 # number of overall MSHR misses 1509system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 146 # number of overall MSHR misses 1510system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 7501 # number of overall MSHR misses 1511system.cpu0.l2cache.overall_mshr_misses::cpu0.data 71216 # number of overall MSHR misses 1512system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 252027 # number of overall MSHR misses 1513system.cpu0.l2cache.overall_mshr_misses::total 331115 # number of overall MSHR misses 1514system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of ReadReq MSHR miss cycles 1515system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2285000 # number of ReadReq MSHR miss cycles 1516system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 227161754 # number of ReadReq MSHR miss cycles 1517system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 910924475 # number of ReadReq MSHR miss cycles 1518system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1143693229 # number of ReadReq MSHR miss cycles 1519system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of HardPFReq MSHR miss cycles 1520system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 10450561115 # number of HardPFReq MSHR miss cycles 1521system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 330354697 # number of UpgradeReq MSHR miss cycles 1522system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 330354697 # number of UpgradeReq MSHR miss cycles 1523system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 150011322 # number of SCUpgradeReq MSHR miss cycles 1524system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 150011322 # number of SCUpgradeReq MSHR miss cycles 1525system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 888000 # number of SCUpgradeFailReq MSHR miss cycles 1526system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 888000 # number of SCUpgradeFailReq MSHR miss cycles 1527system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 642746273 # number of ReadExReq MSHR miss cycles 1528system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 642746273 # number of ReadExReq MSHR miss cycles 1529system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of demand (read+write) MSHR miss cycles 1530system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2285000 # number of demand (read+write) MSHR miss cycles 1531system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 227161754 # number of demand (read+write) MSHR miss cycles 1532system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1553670748 # number of demand (read+write) MSHR miss cycles 1533system.cpu0.l2cache.demand_mshr_miss_latency::total 1786439502 # number of demand (read+write) MSHR miss cycles 1534system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of overall MSHR miss cycles 1535system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2285000 # number of overall MSHR miss cycles 1536system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 227161754 # number of overall MSHR miss cycles 1537system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1553670748 # number of overall MSHR miss cycles 1538system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of overall MSHR miss cycles 1539system.cpu0.l2cache.overall_mshr_miss_latency::total 12237000617 # number of overall MSHR miss cycles 1540system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 478295250 # number of ReadReq MSHR uncacheable cycles 1541system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 176453658508 # number of ReadReq MSHR uncacheable cycles 1542system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 176931953758 # number of ReadReq MSHR uncacheable cycles 1543system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1575154999 # number of WriteReq MSHR uncacheable cycles 1544system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1575154999 # number of WriteReq MSHR uncacheable cycles 1545system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 478295250 # number of overall MSHR uncacheable cycles 1546system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 178028813507 # number of overall MSHR uncacheable cycles 1547system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 178507108757 # number of overall MSHR uncacheable cycles 1548system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for ReadReq accesses 1549system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for ReadReq accesses 1550system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for ReadReq accesses 1551system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.204627 # mshr miss rate for ReadReq accesses 1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.090970 # mshr miss rate for ReadReq accesses 1553system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses 1554system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses | 1536system.cpu0.l2cache.writebacks::writebacks 205462 # number of writebacks 1537system.cpu0.l2cache.writebacks::total 205462 # number of writebacks 1538system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2206 # number of ReadReq MSHR hits 1539system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2737 # number of ReadReq MSHR hits 1540system.cpu0.l2cache.ReadReq_mshr_hits::total 4943 # number of ReadReq MSHR hits 1541system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1219 # number of ReadExReq MSHR hits 1542system.cpu0.l2cache.ReadExReq_mshr_hits::total 1219 # number of ReadExReq MSHR hits 1543system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2206 # number of demand (read+write) MSHR hits 1544system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3956 # number of demand (read+write) MSHR hits 1545system.cpu0.l2cache.demand_mshr_hits::total 6162 # number of demand (read+write) MSHR hits 1546system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2206 # number of overall MSHR hits 1547system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3956 # number of overall MSHR hits 1548system.cpu0.l2cache.overall_mshr_hits::total 6162 # number of overall MSHR hits 1549system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 263 # number of ReadReq MSHR misses 1550system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 219 # number of ReadReq MSHR misses 1551system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13506 # number of ReadReq MSHR misses 1552system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80840 # number of ReadReq MSHR misses 1553system.cpu0.l2cache.ReadReq_mshr_misses::total 94828 # number of ReadReq MSHR misses 1554system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of HardPFReq MSHR misses 1555system.cpu0.l2cache.HardPFReq_mshr_misses::total 448214 # number of HardPFReq MSHR misses 1556system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29878 # number of UpgradeReq MSHR misses 1557system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29878 # number of UpgradeReq MSHR misses 1558system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19321 # number of SCUpgradeReq MSHR misses 1559system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19321 # number of SCUpgradeReq MSHR misses 1560system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1561system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1562system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43702 # number of ReadExReq MSHR misses 1563system.cpu0.l2cache.ReadExReq_mshr_misses::total 43702 # number of ReadExReq MSHR misses 1564system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 263 # number of demand (read+write) MSHR misses 1565system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 219 # number of demand (read+write) MSHR misses 1566system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13506 # number of demand (read+write) MSHR misses 1567system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124542 # number of demand (read+write) MSHR misses 1568system.cpu0.l2cache.demand_mshr_misses::total 138530 # number of demand (read+write) MSHR misses 1569system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 263 # number of overall MSHR misses 1570system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 219 # number of overall MSHR misses 1571system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13506 # number of overall MSHR misses 1572system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124542 # number of overall MSHR misses 1573system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of overall MSHR misses 1574system.cpu0.l2cache.overall_mshr_misses::total 586744 # number of overall MSHR misses 1575system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of ReadReq MSHR miss cycles 1576system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3366500 # number of ReadReq MSHR miss cycles 1577system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457538021 # number of ReadReq MSHR miss cycles 1578system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1656533968 # number of ReadReq MSHR miss cycles 1579system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2121657489 # number of ReadReq MSHR miss cycles 1580system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of HardPFReq MSHR miss cycles 1581system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17785493022 # number of HardPFReq MSHR miss cycles 1582system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 490939499 # number of UpgradeReq MSHR miss cycles 1583system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 490939499 # number of UpgradeReq MSHR miss cycles 1584system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261550596 # number of SCUpgradeReq MSHR miss cycles 1585system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261550596 # number of SCUpgradeReq MSHR miss cycles 1586system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1060497 # number of SCUpgradeFailReq MSHR miss cycles 1587system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1060497 # number of SCUpgradeFailReq MSHR miss cycles 1588system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1074359119 # number of ReadExReq MSHR miss cycles 1589system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1074359119 # number of ReadExReq MSHR miss cycles 1590system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of demand (read+write) MSHR miss cycles 1591system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3366500 # number of demand (read+write) MSHR miss cycles 1592system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457538021 # number of demand (read+write) MSHR miss cycles 1593system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2730893087 # number of demand (read+write) MSHR miss cycles 1594system.cpu0.l2cache.demand_mshr_miss_latency::total 3196016608 # number of demand (read+write) MSHR miss cycles 1595system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of overall MSHR miss cycles 1596system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3366500 # number of overall MSHR miss cycles 1597system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457538021 # number of overall MSHR miss cycles 1598system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2730893087 # number of overall MSHR miss cycles 1599system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of overall MSHR miss cycles 1600system.cpu0.l2cache.overall_mshr_miss_latency::total 20981509630 # number of overall MSHR miss cycles 1601system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647388500 # number of ReadReq MSHR uncacheable cycles 1602system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328873750 # number of ReadReq MSHR uncacheable cycles 1603system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5976262250 # number of ReadReq MSHR uncacheable cycles 1604system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987021005 # number of WriteReq MSHR uncacheable cycles 1605system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987021005 # number of WriteReq MSHR uncacheable cycles 1606system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647388500 # number of overall MSHR uncacheable cycles 1607system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315894755 # number of overall MSHR uncacheable cycles 1608system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9963283255 # number of overall MSHR uncacheable cycles 1609system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for ReadReq accesses 1610system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for ReadReq accesses 1611system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for ReadReq accesses 1612system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177139 # mshr miss rate for ReadReq accesses 1613system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062033 # mshr miss rate for ReadReq accesses |
| 1555system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1556system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1614system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1615system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1557system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.766332 # mshr miss rate for UpgradeReq accesses 1558system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.766332 # mshr miss rate for UpgradeReq accesses 1559system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.925498 # mshr miss rate for SCUpgradeReq accesses 1560system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.925498 # mshr miss rate for SCUpgradeReq accesses | 1616system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.747604 # mshr miss rate for UpgradeReq accesses 1617system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.747604 # mshr miss rate for UpgradeReq accesses 1618system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.904795 # mshr miss rate for SCUpgradeReq accesses 1619system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.904795 # mshr miss rate for SCUpgradeReq accesses |
| 1561system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1562system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1620system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1621system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1563system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149554 # mshr miss rate for ReadExReq accesses 1564system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149554 # mshr miss rate for ReadExReq accesses 1565system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for demand accesses 1566system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for demand accesses 1567system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for demand accesses 1568system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for demand accesses 1569system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103015 # mshr miss rate for demand accesses 1570system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for overall accesses 1571system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for overall accesses 1572system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for overall accesses 1573system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for overall accesses | 1622system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169568 # mshr miss rate for ReadExReq accesses 1623system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169568 # mshr miss rate for ReadExReq accesses 1624system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for demand accesses 1625system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for demand accesses 1626system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for demand accesses 1627system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for demand accesses 1628system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077547 # mshr miss rate for demand accesses 1629system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for overall accesses 1630system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for overall accesses 1631system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for overall accesses 1632system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for overall accesses |
| 1574system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1633system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1575system.cpu0.l2cache.overall_mshr_miss_rate::total 0.431289 # mshr miss rate for overall accesses 1576system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average ReadReq mshr miss latency 1577system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average ReadReq mshr miss latency 1578system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average ReadReq mshr miss latency 1579system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133 # average ReadReq mshr miss latency 1580system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20614.142301 # average ReadReq mshr miss latency 1581system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average HardPFReq mshr miss latency 1582system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825 # average HardPFReq mshr miss latency 1583system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17949.182124 # average UpgradeReq mshr miss latency 1584system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124 # average UpgradeReq mshr miss latency 1585system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466 # average SCUpgradeReq mshr miss latency 1586system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466 # average SCUpgradeReq mshr miss latency 1587system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 444000 # average SCUpgradeFailReq mshr miss latency 1588system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 444000 # average SCUpgradeFailReq mshr miss latency 1589system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 27226.935782 # average ReadExReq mshr miss latency 1590system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27226.935782 # average ReadExReq mshr miss latency 1591system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average overall mshr miss latency 1592system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency 1593system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency 1594system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency 1595system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22587.996940 # average overall mshr miss latency 1596system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average overall mshr miss latency 1597system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency 1598system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency 1599system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency 1600system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average overall mshr miss latency 1601system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356 # average overall mshr miss latency | 1634system.cpu0.l2cache.overall_mshr_miss_rate::total 0.328449 # mshr miss rate for overall accesses 1635system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average ReadReq mshr miss latency 1636system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average ReadReq mshr miss latency 1637system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average ReadReq mshr miss latency 1638system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706 # average ReadReq mshr miss latency 1639system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980 # average ReadReq mshr miss latency 1640system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average HardPFReq mshr miss latency 1641system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539 # average HardPFReq mshr miss latency 1642system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283 # average UpgradeReq mshr miss latency 1643system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283 # average UpgradeReq mshr miss latency 1644system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849 # average SCUpgradeReq mshr miss latency 1645system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849 # average SCUpgradeReq mshr miss latency 1646system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429 # average SCUpgradeFailReq mshr miss latency 1647system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429 # average SCUpgradeFailReq mshr miss latency 1648system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750 # average ReadExReq mshr miss latency 1649system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750 # average ReadExReq mshr miss latency 1650system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency 1651system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency 1652system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency 1653system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency 1654system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873 # average overall mshr miss latency 1655system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency 1656system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency 1657system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency 1658system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency 1659system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average overall mshr miss latency 1660system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154 # average overall mshr miss latency |
| 1602system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1603system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1604system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1605system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1606system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1607system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1608system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1609system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1610system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1661system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1662system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1663system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1664system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1665system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1666system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1667system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1668system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1669system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1611system.cpu0.dcache.tags.replacements 355829 # number of replacements 1612system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use 1613system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks. 1614system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks. 1615system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks. 1616system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit. 1617system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.967445 # Average occupied blocks per requestor 1618system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970640 # Average percentage of cache occupancy 1619system.cpu0.dcache.tags.occ_percent::total 0.970640 # Average percentage of cache occupancy 1620system.cpu0.dcache.tags.occ_task_id_blocks::1024 330 # Occupied blocks per task id 1621system.cpu0.dcache.tags.age_task_id_blocks_1024::2 330 # Occupied blocks per task id 1622system.cpu0.dcache.tags.occ_task_id_percent::1024 0.644531 # Percentage of cache occupancy per task id 1623system.cpu0.dcache.tags.tag_accesses 24668842 # Number of tag accesses 1624system.cpu0.dcache.tags.data_accesses 24668842 # Number of data accesses 1625system.cpu0.dcache.ReadReq_hits::cpu0.data 5548461 # number of ReadReq hits 1626system.cpu0.dcache.ReadReq_hits::total 5548461 # number of ReadReq hits 1627system.cpu0.dcache.WriteReq_hits::cpu0.data 5771889 # number of WriteReq hits 1628system.cpu0.dcache.WriteReq_hits::total 5771889 # number of WriteReq hits 1629system.cpu0.dcache.SoftPFReq_hits::cpu0.data 62661 # number of SoftPFReq hits 1630system.cpu0.dcache.SoftPFReq_hits::total 62661 # number of SoftPFReq hits 1631system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 153118 # number of LoadLockedReq hits 1632system.cpu0.dcache.LoadLockedReq_hits::total 153118 # number of LoadLockedReq hits 1633system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152372 # number of StoreCondReq hits 1634system.cpu0.dcache.StoreCondReq_hits::total 152372 # number of StoreCondReq hits 1635system.cpu0.dcache.demand_hits::cpu0.data 11320350 # number of demand (read+write) hits 1636system.cpu0.dcache.demand_hits::total 11320350 # number of demand (read+write) hits 1637system.cpu0.dcache.overall_hits::cpu0.data 11383011 # number of overall hits 1638system.cpu0.dcache.overall_hits::total 11383011 # number of overall hits 1639system.cpu0.dcache.ReadReq_misses::cpu0.data 178532 # number of ReadReq misses 1640system.cpu0.dcache.ReadReq_misses::total 178532 # number of ReadReq misses 1641system.cpu0.dcache.WriteReq_misses::cpu0.data 183693 # number of WriteReq misses 1642system.cpu0.dcache.WriteReq_misses::total 183693 # number of WriteReq misses 1643system.cpu0.dcache.SoftPFReq_misses::cpu0.data 66756 # number of SoftPFReq misses 1644system.cpu0.dcache.SoftPFReq_misses::total 66756 # number of SoftPFReq misses 1645system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10498 # number of LoadLockedReq misses 1646system.cpu0.dcache.LoadLockedReq_misses::total 10498 # number of LoadLockedReq misses 1647system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11173 # number of StoreCondReq misses 1648system.cpu0.dcache.StoreCondReq_misses::total 11173 # number of StoreCondReq misses 1649system.cpu0.dcache.demand_misses::cpu0.data 362225 # number of demand (read+write) misses 1650system.cpu0.dcache.demand_misses::total 362225 # number of demand (read+write) misses 1651system.cpu0.dcache.overall_misses::cpu0.data 428981 # number of overall misses 1652system.cpu0.dcache.overall_misses::total 428981 # number of overall misses 1653system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2139066005 # number of ReadReq miss cycles 1654system.cpu0.dcache.ReadReq_miss_latency::total 2139066005 # number of ReadReq miss cycles 1655system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 2832298001 # number of WriteReq miss cycles 1656system.cpu0.dcache.WriteReq_miss_latency::total 2832298001 # number of WriteReq miss cycles 1657system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 176126000 # number of LoadLockedReq miss cycles 1658system.cpu0.dcache.LoadLockedReq_miss_latency::total 176126000 # number of LoadLockedReq miss cycles 1659system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 261398841 # number of StoreCondReq miss cycles 1660system.cpu0.dcache.StoreCondReq_miss_latency::total 261398841 # number of StoreCondReq miss cycles 1661system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1128000 # number of StoreCondFailReq miss cycles 1662system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1128000 # number of StoreCondFailReq miss cycles 1663system.cpu0.dcache.demand_miss_latency::cpu0.data 4971364006 # number of demand (read+write) miss cycles 1664system.cpu0.dcache.demand_miss_latency::total 4971364006 # number of demand (read+write) miss cycles 1665system.cpu0.dcache.overall_miss_latency::cpu0.data 4971364006 # number of overall miss cycles 1666system.cpu0.dcache.overall_miss_latency::total 4971364006 # number of overall miss cycles 1667system.cpu0.dcache.ReadReq_accesses::cpu0.data 5726993 # number of ReadReq accesses(hits+misses) 1668system.cpu0.dcache.ReadReq_accesses::total 5726993 # number of ReadReq accesses(hits+misses) 1669system.cpu0.dcache.WriteReq_accesses::cpu0.data 5955582 # number of WriteReq accesses(hits+misses) 1670system.cpu0.dcache.WriteReq_accesses::total 5955582 # number of WriteReq accesses(hits+misses) 1671system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129417 # number of SoftPFReq accesses(hits+misses) 1672system.cpu0.dcache.SoftPFReq_accesses::total 129417 # number of SoftPFReq accesses(hits+misses) 1673system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163616 # number of LoadLockedReq accesses(hits+misses) 1674system.cpu0.dcache.LoadLockedReq_accesses::total 163616 # number of LoadLockedReq accesses(hits+misses) 1675system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 163545 # number of StoreCondReq accesses(hits+misses) 1676system.cpu0.dcache.StoreCondReq_accesses::total 163545 # number of StoreCondReq accesses(hits+misses) 1677system.cpu0.dcache.demand_accesses::cpu0.data 11682575 # number of demand (read+write) accesses 1678system.cpu0.dcache.demand_accesses::total 11682575 # number of demand (read+write) accesses 1679system.cpu0.dcache.overall_accesses::cpu0.data 11811992 # number of overall (read+write) accesses 1680system.cpu0.dcache.overall_accesses::total 11811992 # number of overall (read+write) accesses 1681system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031174 # miss rate for ReadReq accesses 1682system.cpu0.dcache.ReadReq_miss_rate::total 0.031174 # miss rate for ReadReq accesses 1683system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030844 # miss rate for WriteReq accesses 1684system.cpu0.dcache.WriteReq_miss_rate::total 0.030844 # miss rate for WriteReq accesses 1685system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.515821 # miss rate for SoftPFReq accesses 1686system.cpu0.dcache.SoftPFReq_miss_rate::total 0.515821 # miss rate for SoftPFReq accesses 1687system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064162 # miss rate for LoadLockedReq accesses 1688system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064162 # miss rate for LoadLockedReq accesses 1689system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068318 # miss rate for StoreCondReq accesses 1690system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068318 # miss rate for StoreCondReq accesses 1691system.cpu0.dcache.demand_miss_rate::cpu0.data 0.031006 # miss rate for demand accesses 1692system.cpu0.dcache.demand_miss_rate::total 0.031006 # miss rate for demand accesses 1693system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036317 # miss rate for overall accesses 1694system.cpu0.dcache.overall_miss_rate::total 0.036317 # miss rate for overall accesses 1695system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11981.415124 # average ReadReq miss latency 1696system.cpu0.dcache.ReadReq_avg_miss_latency::total 11981.415124 # average ReadReq miss latency 1697system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15418.649600 # average WriteReq miss latency 1698system.cpu0.dcache.WriteReq_avg_miss_latency::total 15418.649600 # average WriteReq miss latency 1699system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16777.100400 # average LoadLockedReq miss latency 1700system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16777.100400 # average LoadLockedReq miss latency 1701system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23395.582297 # average StoreCondReq miss latency 1702system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297 # average StoreCondReq miss latency | 1670system.cpu0.dcache.tags.replacements 658799 # number of replacements 1671system.cpu0.dcache.tags.tagsinuse 485.164758 # Cycle average of tags in use 1672system.cpu0.dcache.tags.total_refs 41683742 # Total number of references to valid blocks. 1673system.cpu0.dcache.tags.sampled_refs 659311 # Sample count of references to valid blocks. 1674system.cpu0.dcache.tags.avg_refs 63.223186 # Average number of references to valid blocks. 1675system.cpu0.dcache.tags.warmup_cycle 1016179000 # Cycle when the warmup percentage was hit. 1676system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.164758 # Average occupied blocks per requestor 1677system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947587 # Average percentage of cache occupancy 1678system.cpu0.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy 1679system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1680system.cpu0.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 1681system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 1682system.cpu0.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id 1683system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1684system.cpu0.dcache.tags.tag_accesses 85573160 # Number of tag accesses 1685system.cpu0.dcache.tags.data_accesses 85573160 # Number of data accesses 1686system.cpu0.dcache.ReadReq_hits::cpu0.data 23155425 # number of ReadReq hits 1687system.cpu0.dcache.ReadReq_hits::total 23155425 # number of ReadReq hits 1688system.cpu0.dcache.WriteReq_hits::cpu0.data 17431620 # number of WriteReq hits 1689system.cpu0.dcache.WriteReq_hits::total 17431620 # number of WriteReq hits 1690system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323179 # number of SoftPFReq hits 1691system.cpu0.dcache.SoftPFReq_hits::total 323179 # number of SoftPFReq hits 1692system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358328 # number of LoadLockedReq hits 1693system.cpu0.dcache.LoadLockedReq_hits::total 358328 # number of LoadLockedReq hits 1694system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353864 # number of StoreCondReq hits 1695system.cpu0.dcache.StoreCondReq_hits::total 353864 # number of StoreCondReq hits 1696system.cpu0.dcache.demand_hits::cpu0.data 40587045 # number of demand (read+write) hits 1697system.cpu0.dcache.demand_hits::total 40587045 # number of demand (read+write) hits 1698system.cpu0.dcache.overall_hits::cpu0.data 40910224 # number of overall hits 1699system.cpu0.dcache.overall_hits::total 40910224 # number of overall hits 1700system.cpu0.dcache.ReadReq_misses::cpu0.data 360428 # number of ReadReq misses 1701system.cpu0.dcache.ReadReq_misses::total 360428 # number of ReadReq misses 1702system.cpu0.dcache.WriteReq_misses::cpu0.data 297691 # number of WriteReq misses 1703system.cpu0.dcache.WriteReq_misses::total 297691 # number of WriteReq misses 1704system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106192 # number of SoftPFReq misses 1705system.cpu0.dcache.SoftPFReq_misses::total 106192 # number of SoftPFReq misses 1706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21416 # number of LoadLockedReq misses 1707system.cpu0.dcache.LoadLockedReq_misses::total 21416 # number of LoadLockedReq misses 1708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses 1709system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses 1710system.cpu0.dcache.demand_misses::cpu0.data 658119 # number of demand (read+write) misses 1711system.cpu0.dcache.demand_misses::total 658119 # number of demand (read+write) misses 1712system.cpu0.dcache.overall_misses::cpu0.data 764311 # number of overall misses 1713system.cpu0.dcache.overall_misses::total 764311 # number of overall misses 1714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4473033768 # number of ReadReq miss cycles 1715system.cpu0.dcache.ReadReq_miss_latency::total 4473033768 # number of ReadReq miss cycles 1716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4445222415 # number of WriteReq miss cycles 1717system.cpu0.dcache.WriteReq_miss_latency::total 4445222415 # number of WriteReq miss cycles 1718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335592501 # number of LoadLockedReq miss cycles 1719system.cpu0.dcache.LoadLockedReq_miss_latency::total 335592501 # number of LoadLockedReq miss cycles 1720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473344116 # number of StoreCondReq miss cycles 1721system.cpu0.dcache.StoreCondReq_miss_latency::total 473344116 # number of StoreCondReq miss cycles 1722system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1450500 # number of StoreCondFailReq miss cycles 1723system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1450500 # number of StoreCondFailReq miss cycles 1724system.cpu0.dcache.demand_miss_latency::cpu0.data 8918256183 # number of demand (read+write) miss cycles 1725system.cpu0.dcache.demand_miss_latency::total 8918256183 # number of demand (read+write) miss cycles 1726system.cpu0.dcache.overall_miss_latency::cpu0.data 8918256183 # number of overall miss cycles 1727system.cpu0.dcache.overall_miss_latency::total 8918256183 # number of overall miss cycles 1728system.cpu0.dcache.ReadReq_accesses::cpu0.data 23515853 # number of ReadReq accesses(hits+misses) 1729system.cpu0.dcache.ReadReq_accesses::total 23515853 # number of ReadReq accesses(hits+misses) 1730system.cpu0.dcache.WriteReq_accesses::cpu0.data 17729311 # number of WriteReq accesses(hits+misses) 1731system.cpu0.dcache.WriteReq_accesses::total 17729311 # number of WriteReq accesses(hits+misses) 1732system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429371 # number of SoftPFReq accesses(hits+misses) 1733system.cpu0.dcache.SoftPFReq_accesses::total 429371 # number of SoftPFReq accesses(hits+misses) 1734system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379744 # number of LoadLockedReq accesses(hits+misses) 1735system.cpu0.dcache.LoadLockedReq_accesses::total 379744 # number of LoadLockedReq accesses(hits+misses) 1736system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375234 # number of StoreCondReq accesses(hits+misses) 1737system.cpu0.dcache.StoreCondReq_accesses::total 375234 # number of StoreCondReq accesses(hits+misses) 1738system.cpu0.dcache.demand_accesses::cpu0.data 41245164 # number of demand (read+write) accesses 1739system.cpu0.dcache.demand_accesses::total 41245164 # number of demand (read+write) accesses 1740system.cpu0.dcache.overall_accesses::cpu0.data 41674535 # number of overall (read+write) accesses 1741system.cpu0.dcache.overall_accesses::total 41674535 # number of overall (read+write) accesses 1742system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015327 # miss rate for ReadReq accesses 1743system.cpu0.dcache.ReadReq_miss_rate::total 0.015327 # miss rate for ReadReq accesses 1744system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016791 # miss rate for WriteReq accesses 1745system.cpu0.dcache.WriteReq_miss_rate::total 0.016791 # miss rate for WriteReq accesses 1746system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247320 # miss rate for SoftPFReq accesses 1747system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247320 # miss rate for SoftPFReq accesses 1748system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056396 # miss rate for LoadLockedReq accesses 1749system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056396 # miss rate for LoadLockedReq accesses 1750system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses 1751system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses 1752system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015956 # miss rate for demand accesses 1753system.cpu0.dcache.demand_miss_rate::total 0.015956 # miss rate for demand accesses 1754system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018340 # miss rate for overall accesses 1755system.cpu0.dcache.overall_miss_rate::total 0.018340 # miss rate for overall accesses 1756system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286 # average ReadReq miss latency 1757system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286 # average ReadReq miss latency 1758system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273 # average WriteReq miss latency 1759system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273 # average WriteReq miss latency 1760system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550 # average LoadLockedReq miss latency 1761system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550 # average LoadLockedReq miss latency 1762system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236 # average StoreCondReq miss latency 1763system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236 # average StoreCondReq miss latency |
| 1703system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1704system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1764system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1765system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1705system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13724.519307 # average overall miss latency 1706system.cpu0.dcache.demand_avg_miss_latency::total 13724.519307 # average overall miss latency 1707system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11588.774342 # average overall miss latency 1708system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342 # average overall miss latency | 1766system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089 # average overall miss latency 1767system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089 # average overall miss latency 1768system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370 # average overall miss latency 1769system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370 # average overall miss latency |
| 1709system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1710system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1711system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1712system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1713system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1714system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1715system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1716system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1770system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1771system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1772system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1773system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1774system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1775system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1776system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1777system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1717system.cpu0.dcache.writebacks::writebacks 286365 # number of writebacks 1718system.cpu0.dcache.writebacks::total 286365 # number of writebacks 1719system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3418 # number of ReadReq MSHR hits 1720system.cpu0.dcache.ReadReq_mshr_hits::total 3418 # number of ReadReq MSHR hits 1721system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2438 # number of WriteReq MSHR hits 1722system.cpu0.dcache.WriteReq_mshr_hits::total 2438 # number of WriteReq MSHR hits 1723system.cpu0.dcache.demand_mshr_hits::cpu0.data 5856 # number of demand (read+write) MSHR hits 1724system.cpu0.dcache.demand_mshr_hits::total 5856 # number of demand (read+write) MSHR hits 1725system.cpu0.dcache.overall_mshr_hits::cpu0.data 5856 # number of overall MSHR hits 1726system.cpu0.dcache.overall_mshr_hits::total 5856 # number of overall MSHR hits 1727system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 175114 # number of ReadReq MSHR misses 1728system.cpu0.dcache.ReadReq_mshr_misses::total 175114 # number of ReadReq MSHR misses 1729system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 181255 # number of WriteReq MSHR misses 1730system.cpu0.dcache.WriteReq_mshr_misses::total 181255 # number of WriteReq MSHR misses 1731system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 47050 # number of SoftPFReq MSHR misses 1732system.cpu0.dcache.SoftPFReq_mshr_misses::total 47050 # number of SoftPFReq MSHR misses 1733system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 10498 # number of LoadLockedReq MSHR misses 1734system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10498 # number of LoadLockedReq MSHR misses 1735system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11156 # number of StoreCondReq MSHR misses 1736system.cpu0.dcache.StoreCondReq_mshr_misses::total 11156 # number of StoreCondReq MSHR misses 1737system.cpu0.dcache.demand_mshr_misses::cpu0.data 356369 # number of demand (read+write) MSHR misses 1738system.cpu0.dcache.demand_mshr_misses::total 356369 # number of demand (read+write) MSHR misses 1739system.cpu0.dcache.overall_mshr_misses::cpu0.data 403419 # number of overall MSHR misses 1740system.cpu0.dcache.overall_mshr_misses::total 403419 # number of overall MSHR misses 1741system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1737360745 # number of ReadReq MSHR miss cycles 1742system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1737360745 # number of ReadReq MSHR miss cycles 1743system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2335118999 # number of WriteReq MSHR miss cycles 1744system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2335118999 # number of WriteReq MSHR miss cycles 1745system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 699675494 # number of SoftPFReq MSHR miss cycles 1746system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 699675494 # number of SoftPFReq MSHR miss cycles 1747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 155125000 # number of LoadLockedReq MSHR miss cycles 1748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 155125000 # number of LoadLockedReq MSHR miss cycles 1749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 237977159 # number of StoreCondReq MSHR miss cycles 1750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 237977159 # number of StoreCondReq MSHR miss cycles 1751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1080000 # number of StoreCondFailReq MSHR miss cycles 1752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1080000 # number of StoreCondFailReq MSHR miss cycles 1753system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 4072479744 # number of demand (read+write) MSHR miss cycles 1754system.cpu0.dcache.demand_mshr_miss_latency::total 4072479744 # number of demand (read+write) MSHR miss cycles 1755system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4772155238 # number of overall MSHR miss cycles 1756system.cpu0.dcache.overall_mshr_miss_latency::total 4772155238 # number of overall MSHR miss cycles 1757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990 # number of ReadReq MSHR uncacheable cycles 1758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990 # number of ReadReq MSHR uncacheable cycles 1759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1669232496 # number of WriteReq MSHR uncacheable cycles 1760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1669232496 # number of WriteReq MSHR uncacheable cycles 1761system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486 # number of overall MSHR uncacheable cycles 1762system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486 # number of overall MSHR uncacheable cycles 1763system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030577 # mshr miss rate for ReadReq accesses 1764system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030577 # mshr miss rate for ReadReq accesses 1765system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030434 # mshr miss rate for WriteReq accesses 1766system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030434 # mshr miss rate for WriteReq accesses 1767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.363553 # mshr miss rate for SoftPFReq accesses 1768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.363553 # mshr miss rate for SoftPFReq accesses 1769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064162 # mshr miss rate for LoadLockedReq accesses 1770system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses 1771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.068214 # mshr miss rate for StoreCondReq accesses 1772system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.068214 # mshr miss rate for StoreCondReq accesses 1773system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030504 # mshr miss rate for demand accesses 1774system.cpu0.dcache.demand_mshr_miss_rate::total 0.030504 # mshr miss rate for demand accesses 1775system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034153 # mshr miss rate for overall accesses 1776system.cpu0.dcache.overall_mshr_miss_rate::total 0.034153 # mshr miss rate for overall accesses 1777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 9921.312659 # average ReadReq mshr miss latency 1778system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9921.312659 # average ReadReq mshr miss latency 1779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772 # average WriteReq mshr miss latency 1780system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772 # average WriteReq mshr miss latency 1781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540 # average SoftPFReq mshr miss latency 1782system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency 1783system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119 # average LoadLockedReq mshr miss latency 1784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency 1785system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984 # average StoreCondReq mshr miss latency 1786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency | 1778system.cpu0.dcache.writebacks::writebacks 483937 # number of writebacks 1779system.cpu0.dcache.writebacks::total 483937 # number of writebacks 1780system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7364 # number of ReadReq MSHR hits 1781system.cpu0.dcache.ReadReq_mshr_hits::total 7364 # number of ReadReq MSHR hits 1782system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15075 # number of LoadLockedReq MSHR hits 1783system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15075 # number of LoadLockedReq MSHR hits 1784system.cpu0.dcache.demand_mshr_hits::cpu0.data 7364 # number of demand (read+write) MSHR hits 1785system.cpu0.dcache.demand_mshr_hits::total 7364 # number of demand (read+write) MSHR hits 1786system.cpu0.dcache.overall_mshr_hits::cpu0.data 7364 # number of overall MSHR hits 1787system.cpu0.dcache.overall_mshr_hits::total 7364 # number of overall MSHR hits 1788system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353064 # number of ReadReq MSHR misses 1789system.cpu0.dcache.ReadReq_mshr_misses::total 353064 # number of ReadReq MSHR misses 1790system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297691 # number of WriteReq MSHR misses 1791system.cpu0.dcache.WriteReq_mshr_misses::total 297691 # number of WriteReq MSHR misses 1792system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96960 # number of SoftPFReq MSHR misses 1793system.cpu0.dcache.SoftPFReq_mshr_misses::total 96960 # number of SoftPFReq MSHR misses 1794system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6341 # number of LoadLockedReq MSHR misses 1795system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6341 # number of LoadLockedReq MSHR misses 1796system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21361 # number of StoreCondReq MSHR misses 1797system.cpu0.dcache.StoreCondReq_mshr_misses::total 21361 # number of StoreCondReq MSHR misses 1798system.cpu0.dcache.demand_mshr_misses::cpu0.data 650755 # number of demand (read+write) MSHR misses 1799system.cpu0.dcache.demand_mshr_misses::total 650755 # number of demand (read+write) MSHR misses 1800system.cpu0.dcache.overall_mshr_misses::cpu0.data 747715 # number of overall MSHR misses 1801system.cpu0.dcache.overall_mshr_misses::total 747715 # number of overall MSHR misses 1802system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3674066732 # number of ReadReq MSHR miss cycles 1803system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3674066732 # number of ReadReq MSHR miss cycles 1804system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3839615585 # number of WriteReq MSHR miss cycles 1805system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3839615585 # number of WriteReq MSHR miss cycles 1806system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1190903244 # number of SoftPFReq MSHR miss cycles 1807system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1190903244 # number of SoftPFReq MSHR miss cycles 1808system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89864249 # number of LoadLockedReq MSHR miss cycles 1809system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89864249 # number of LoadLockedReq MSHR miss cycles 1810system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429815884 # number of StoreCondReq MSHR miss cycles 1811system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429815884 # number of StoreCondReq MSHR miss cycles 1812system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1372500 # number of StoreCondFailReq MSHR miss cycles 1813system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1372500 # number of StoreCondFailReq MSHR miss cycles 1814system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7513682317 # number of demand (read+write) MSHR miss cycles 1815system.cpu0.dcache.demand_mshr_miss_latency::total 7513682317 # number of demand (read+write) MSHR miss cycles 1816system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8704585561 # number of overall MSHR miss cycles 1817system.cpu0.dcache.overall_mshr_miss_latency::total 8704585561 # number of overall MSHR miss cycles 1818system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564939750 # number of ReadReq MSHR uncacheable cycles 1819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564939750 # number of ReadReq MSHR uncacheable cycles 1820system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183945995 # number of WriteReq MSHR uncacheable cycles 1821system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183945995 # number of WriteReq MSHR uncacheable cycles 1822system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748885745 # number of overall MSHR uncacheable cycles 1823system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748885745 # number of overall MSHR uncacheable cycles 1824system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015014 # mshr miss rate for ReadReq accesses 1825system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015014 # mshr miss rate for ReadReq accesses 1826system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016791 # mshr miss rate for WriteReq accesses 1827system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016791 # mshr miss rate for WriteReq accesses 1828system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225819 # mshr miss rate for SoftPFReq accesses 1829system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225819 # mshr miss rate for SoftPFReq accesses 1830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016698 # mshr miss rate for LoadLockedReq accesses 1831system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016698 # mshr miss rate for LoadLockedReq accesses 1832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056927 # mshr miss rate for StoreCondReq accesses 1833system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056927 # mshr miss rate for StoreCondReq accesses 1834system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015778 # mshr miss rate for demand accesses 1835system.cpu0.dcache.demand_mshr_miss_rate::total 0.015778 # mshr miss rate for demand accesses 1836system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017942 # mshr miss rate for overall accesses 1837system.cpu0.dcache.overall_mshr_miss_rate::total 0.017942 # mshr miss rate for overall accesses 1838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371 # average ReadReq mshr miss latency 1839system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371 # average ReadReq mshr miss latency 1840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148 # average WriteReq mshr miss latency 1841system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148 # average WriteReq mshr miss latency 1842system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946 # average SoftPFReq mshr miss latency 1843system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946 # average SoftPFReq mshr miss latency 1844system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445 # average LoadLockedReq mshr miss latency 1845system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445 # average LoadLockedReq mshr miss latency 1846system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460 # average StoreCondReq mshr miss latency 1847system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460 # average StoreCondReq mshr miss latency |
| 1787system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1848system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1849system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1789system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency 1790system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency 1791system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency 1792system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency | 1850system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018 # average overall mshr miss latency 1851system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018 # average overall mshr miss latency 1852system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101 # average overall mshr miss latency 1853system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101 # average overall mshr miss latency |
| 1793system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1795system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1797system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1799system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1854system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1855system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1856system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1857system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1858system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1859system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1860system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1800system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution 1801system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution 1802system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution 1803system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution 1804system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution 1805system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution 1806system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution 1807system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution 1808system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution 1809system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution 1810system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution 1811system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution 1812system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution 1813system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes) 1814system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes) 1815system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes) 1816system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes) 1817system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes) 1818system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes) 1819system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes) 1820system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes) 1821system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes) 1822system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes) 1823system.cpu0.toL2Bus.snoops 631972 # Total snoops (count) 1824system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram 1825system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram 1826system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram | 1861system.cpu0.toL2Bus.trans_dist::ReadReq 1734717 # Transaction distribution 1862system.cpu0.toL2Bus.trans_dist::ReadResp 1628862 # Transaction distribution 1863system.cpu0.toL2Bus.trans_dist::WriteReq 26256 # Transaction distribution 1864system.cpu0.toL2Bus.trans_dist::WriteResp 26256 # Transaction distribution 1865system.cpu0.toL2Bus.trans_dist::Writeback 483936 # Transaction distribution 1866system.cpu0.toL2Bus.trans_dist::HardPFReq 598763 # Transaction distribution 1867system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1868system.cpu0.toL2Bus.trans_dist::UpgradeReq 81012 # Transaction distribution 1869system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43653 # Transaction distribution 1870system.cpu0.toL2Bus.trans_dist::UpgradeResp 101651 # Transaction distribution 1871system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 1872system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 1873system.cpu0.toL2Bus.trans_dist::ReadExReq 279403 # Transaction distribution 1874system.cpu0.toL2Bus.trans_dist::ReadExResp 269117 # Transaction distribution 1875system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141354 # Packet count per connected master and slave (bytes) 1876system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2250253 # Packet count per connected master and slave (bytes) 1877system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9809 # Packet count per connected master and slave (bytes) 1878system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 20976 # Packet count per connected master and slave (bytes) 1879system.cpu0.toL2Bus.pkt_count::total 4422392 # Packet count per connected master and slave (bytes) 1880system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981948 # Cumulative packet size per connected master and slave (bytes) 1881system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80932636 # Cumulative packet size per connected master and slave (bytes) 1882system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13632 # Cumulative packet size per connected master and slave (bytes) 1883system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29012 # Cumulative packet size per connected master and slave (bytes) 1884system.cpu0.toL2Bus.pkt_size::total 148957228 # Cumulative packet size per connected master and slave (bytes) 1885system.cpu0.toL2Bus.snoops 991588 # Total snoops (count) 1886system.cpu0.toL2Bus.snoop_fanout::samples 3219253 # Request fanout histogram 1887system.cpu0.toL2Bus.snoop_fanout::mean 5.272771 # Request fanout histogram 1888system.cpu0.toL2Bus.snoop_fanout::stdev 0.445384 # Request fanout histogram |
| 1827system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1828system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1829system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1830system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1831system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1832system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1889system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1890system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1891system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1892system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1893system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1894system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1833system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram 1834system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram | 1895system.cpu0.toL2Bus.snoop_fanout::5 2341135 72.72% 72.72% # Request fanout histogram 1896system.cpu0.toL2Bus.snoop_fanout::6 878118 27.28% 100.00% # Request fanout histogram |
| 1835system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1836system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1837system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1897system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1898system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1899system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1838system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram 1839system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks) | 1900system.cpu0.toL2Bus.snoop_fanout::total 3219253 # Request fanout histogram 1901system.cpu0.toL2Bus.reqLayer0.occupancy 1700320883 # Layer occupancy (ticks) |
| 1840system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1902system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1841system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks) | 1903system.cpu0.toL2Bus.snoopLayer0.occupancy 115643997 # Layer occupancy (ticks) |
| 1842system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1904system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1843system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks) 1844system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1845system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks) 1846system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1847system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks) | 1905system.cpu0.toL2Bus.respLayer0.occupancy 1603955756 # Layer occupancy (ticks) 1906system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1907system.cpu0.toL2Bus.respLayer1.occupancy 1150860061 # Layer occupancy (ticks) 1908system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1909system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks) |
| 1848system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1910system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1849system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks) | 1911system.cpu0.toL2Bus.respLayer3.occupancy 13723500 # Layer occupancy (ticks) |
| 1850system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1851system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1852system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1853system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1854system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1855system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1856system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1857system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1866system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1867system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1868system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1869system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1870system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1871system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1872system.cpu1.dtb.inst_hits 0 # ITB inst hits 1873system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1912system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1913system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1914system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1915system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1916system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1917system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1918system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1919system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 1928system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1929system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1930system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1931system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1932system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1933system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1934system.cpu1.dtb.inst_hits 0 # ITB inst hits 1935system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1874system.cpu1.dtb.read_hits 6599972 # DTB read hits 1875system.cpu1.dtb.read_misses 3720 # DTB read misses 1876system.cpu1.dtb.write_hits 5539858 # DTB write hits 1877system.cpu1.dtb.write_misses 1581 # DTB write misses 1878system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1879system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1880system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1881system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1882system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB | 1936system.cpu1.dtb.read_hits 4827395 # DTB read hits 1937system.cpu1.dtb.read_misses 2744 # DTB read misses 1938system.cpu1.dtb.write_hits 4131070 # DTB write hits 1939system.cpu1.dtb.write_misses 524 # DTB write misses 1940system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1941system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1942system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1943system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1944system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB |
| 1883system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1945system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1884system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch | 1946system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch |
| 1885system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1947system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1886system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1887system.cpu1.dtb.read_accesses 6603692 # DTB read accesses 1888system.cpu1.dtb.write_accesses 5541439 # DTB write accesses | 1948system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1949system.cpu1.dtb.read_accesses 4830139 # DTB read accesses 1950system.cpu1.dtb.write_accesses 4131594 # DTB write accesses |
| 1889system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1951system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1890system.cpu1.dtb.hits 12139830 # DTB hits 1891system.cpu1.dtb.misses 5301 # DTB misses 1892system.cpu1.dtb.accesses 12145131 # DTB accesses | 1952system.cpu1.dtb.hits 8958465 # DTB hits 1953system.cpu1.dtb.misses 3268 # DTB misses 1954system.cpu1.dtb.accesses 8961733 # DTB accesses |
| 1893system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1894system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1895system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1896system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1897system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1898system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1899system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1900system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1906system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1907system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1908system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1909system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1910system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1911system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1912system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1913system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1955system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1956system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1957system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1958system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1959system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1960system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1961system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1962system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1968system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1969system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1970system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1971system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1972system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1973system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1974system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1975system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1914system.cpu1.itb.inst_hits 32728613 # ITB inst hits 1915system.cpu1.itb.inst_misses 2200 # ITB inst misses | 1976system.cpu1.itb.inst_hits 20889672 # ITB inst hits 1977system.cpu1.itb.inst_misses 1747 # ITB inst misses |
| 1916system.cpu1.itb.read_hits 0 # DTB read hits 1917system.cpu1.itb.read_misses 0 # DTB read misses 1918system.cpu1.itb.write_hits 0 # DTB write hits 1919system.cpu1.itb.write_misses 0 # DTB write misses | 1978system.cpu1.itb.read_hits 0 # DTB read hits 1979system.cpu1.itb.read_misses 0 # DTB read misses 1980system.cpu1.itb.write_hits 0 # DTB write hits 1981system.cpu1.itb.write_misses 0 # DTB write misses |
| 1920system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1921system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1922system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1923system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1924system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB | 1982system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1983system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1984system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1985system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1986system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB |
| 1925system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1926system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1927system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1928system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1929system.cpu1.itb.read_accesses 0 # DTB read accesses 1930system.cpu1.itb.write_accesses 0 # DTB write accesses | 1987system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1988system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1989system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1990system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1991system.cpu1.itb.read_accesses 0 # DTB read accesses 1992system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1931system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses 1932system.cpu1.itb.hits 32728613 # DTB hits 1933system.cpu1.itb.misses 2200 # DTB misses 1934system.cpu1.itb.accesses 32730813 # DTB accesses 1935system.cpu1.numCycles 5350361558 # number of cpu cycles simulated | 1993system.cpu1.itb.inst_accesses 20891419 # ITB inst accesses 1994system.cpu1.itb.hits 20889672 # DTB hits 1995system.cpu1.itb.misses 1747 # DTB misses 1996system.cpu1.itb.accesses 20891419 # DTB accesses 1997system.cpu1.numCycles 5732950771 # number of cpu cycles simulated |
| 1936system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1937system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1998system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1999system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1938system.cpu1.committedInsts 32086754 # Number of instructions committed 1939system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed 1940system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses 1941system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 1942system.cpu1.num_func_calls 973285 # number of times a function call or return occured 1943system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls 1944system.cpu1.num_int_insts 33961237 # number of integer instructions 1945system.cpu1.num_fp_insts 4436 # number of float instructions 1946system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read 1947system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written 1948system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 1949system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 1950system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read 1951system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written 1952system.cpu1.num_mem_refs 12531559 # number of memory refs 1953system.cpu1.num_load_insts 6744563 # Number of load instructions 1954system.cpu1.num_store_insts 5786996 # Number of store instructions 1955system.cpu1.num_idle_cycles 5182201093.372063 # Number of idle cycles 1956system.cpu1.num_busy_cycles 168160464.627937 # Number of busy cycles 1957system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles 1958system.cpu1.idle_fraction 0.968570 # Percentage of idle cycles 1959system.cpu1.Branches 5094014 # Number of branches fetched 1960system.cpu1.op_class::No_OpClass 12501 0.03% 0.03% # Class of executed instruction 1961system.cpu1.op_class::IntAlu 25826807 67.22% 67.25% # Class of executed instruction 1962system.cpu1.op_class::IntMult 50699 0.13% 67.38% # Class of executed instruction 1963system.cpu1.op_class::IntDiv 0 0.00% 67.38% # Class of executed instruction 1964system.cpu1.op_class::FloatAdd 0 0.00% 67.38% # Class of executed instruction 1965system.cpu1.op_class::FloatCmp 0 0.00% 67.38% # Class of executed instruction 1966system.cpu1.op_class::FloatCvt 0 0.00% 67.38% # Class of executed instruction 1967system.cpu1.op_class::FloatMult 0 0.00% 67.38% # Class of executed instruction 1968system.cpu1.op_class::FloatDiv 0 0.00% 67.38% # Class of executed instruction 1969system.cpu1.op_class::FloatSqrt 0 0.00% 67.38% # Class of executed instruction 1970system.cpu1.op_class::SimdAdd 0 0.00% 67.38% # Class of executed instruction 1971system.cpu1.op_class::SimdAddAcc 0 0.00% 67.38% # Class of executed instruction 1972system.cpu1.op_class::SimdAlu 0 0.00% 67.38% # Class of executed instruction 1973system.cpu1.op_class::SimdCmp 0 0.00% 67.38% # Class of executed instruction 1974system.cpu1.op_class::SimdCvt 0 0.00% 67.38% # Class of executed instruction 1975system.cpu1.op_class::SimdMisc 0 0.00% 67.38% # Class of executed instruction 1976system.cpu1.op_class::SimdMult 0 0.00% 67.38% # Class of executed instruction 1977system.cpu1.op_class::SimdMultAcc 0 0.00% 67.38% # Class of executed instruction 1978system.cpu1.op_class::SimdShift 0 0.00% 67.38% # Class of executed instruction 1979system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.38% # Class of executed instruction 1980system.cpu1.op_class::SimdSqrt 0 0.00% 67.38% # Class of executed instruction 1981system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.38% # Class of executed instruction 1982system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.38% # Class of executed instruction 1983system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.38% # Class of executed instruction 1984system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.38% # Class of executed instruction 1985system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.38% # Class of executed instruction 1986system.cpu1.op_class::SimdFloatMisc 745 0.00% 67.38% # Class of executed instruction 1987system.cpu1.op_class::SimdFloatMult 0 0.00% 67.38% # Class of executed instruction 1988system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.38% # Class of executed instruction 1989system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.38% # Class of executed instruction 1990system.cpu1.op_class::MemRead 6744563 17.55% 84.94% # Class of executed instruction 1991system.cpu1.op_class::MemWrite 5786996 15.06% 100.00% # Class of executed instruction | 2000system.cpu1.committedInsts 20508829 # Number of instructions committed 2001system.cpu1.committedOps 24874782 # Number of ops (including micro ops) committed 2002system.cpu1.num_int_alu_accesses 22190598 # Number of integer alu accesses 2003system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 2004system.cpu1.num_func_calls 1209607 # number of times a function call or return occured 2005system.cpu1.num_conditional_control_insts 2572400 # number of instructions that are conditional controls 2006system.cpu1.num_int_insts 22190598 # number of integer instructions 2007system.cpu1.num_fp_insts 1792 # number of float instructions 2008system.cpu1.num_int_register_reads 39855869 # number of times the integer registers were read 2009system.cpu1.num_int_register_writes 15449003 # number of times the integer registers were written 2010system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 2011system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 2012system.cpu1.num_cc_register_reads 90462747 # number of times the CC registers were read 2013system.cpu1.num_cc_register_writes 8862782 # number of times the CC registers were written 2014system.cpu1.num_mem_refs 9247846 # number of memory refs 2015system.cpu1.num_load_insts 4946569 # Number of load instructions 2016system.cpu1.num_store_insts 4301277 # Number of store instructions 2017system.cpu1.num_idle_cycles 5671538888.273010 # Number of idle cycles 2018system.cpu1.num_busy_cycles 61411882.726990 # Number of busy cycles 2019system.cpu1.not_idle_fraction 0.010712 # Percentage of non-idle cycles 2020system.cpu1.idle_fraction 0.989288 # Percentage of idle cycles 2021system.cpu1.Branches 3892747 # Number of branches fetched 2022system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction 2023system.cpu1.op_class::IntAlu 16017837 63.30% 63.30% # Class of executed instruction 2024system.cpu1.op_class::IntMult 33571 0.13% 63.44% # Class of executed instruction 2025system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction 2026system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction 2027system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction 2028system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction 2029system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction 2030system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction 2031system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction 2032system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction 2033system.cpu1.op_class::SimdAddAcc 0 0.00% 63.44% # Class of executed instruction 2034system.cpu1.op_class::SimdAlu 0 0.00% 63.44% # Class of executed instruction 2035system.cpu1.op_class::SimdCmp 0 0.00% 63.44% # Class of executed instruction 2036system.cpu1.op_class::SimdCvt 0 0.00% 63.44% # Class of executed instruction 2037system.cpu1.op_class::SimdMisc 0 0.00% 63.44% # Class of executed instruction 2038system.cpu1.op_class::SimdMult 0 0.00% 63.44% # Class of executed instruction 2039system.cpu1.op_class::SimdMultAcc 0 0.00% 63.44% # Class of executed instruction 2040system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction 2041system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction 2042system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction 2043system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction 2044system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction 2045system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction 2046system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction 2047system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction 2048system.cpu1.op_class::SimdFloatMisc 4039 0.02% 63.45% # Class of executed instruction 2049system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction 2050system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction 2051system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction 2052system.cpu1.op_class::MemRead 4946569 19.55% 83.00% # Class of executed instruction 2053system.cpu1.op_class::MemWrite 4301277 17.00% 100.00% # Class of executed instruction |
| 1992system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1993system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 2054system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2055system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1994system.cpu1.op_class::total 38422311 # Class of executed instruction | 2056system.cpu1.op_class::total 25303360 # Class of executed instruction |
| 1995system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 2057system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1996system.cpu1.kern.inst.quiesce 40934 # number of quiesce instructions executed 1997system.cpu1.icache.tags.replacements 375227 # number of replacements 1998system.cpu1.icache.tags.tagsinuse 498.528279 # Cycle average of tags in use 1999system.cpu1.icache.tags.total_refs 32352870 # Total number of references to valid blocks. 2000system.cpu1.icache.tags.sampled_refs 375739 # Sample count of references to valid blocks. 2001system.cpu1.icache.tags.avg_refs 86.104636 # Average number of references to valid blocks. 2002system.cpu1.icache.tags.warmup_cycle 79843888000 # Cycle when the warmup percentage was hit. 2003system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.528279 # Average occupied blocks per requestor 2004system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973688 # Average percentage of cache occupancy 2005system.cpu1.icache.tags.occ_percent::total 0.973688 # Average percentage of cache occupancy | 2058system.cpu1.kern.inst.quiesce 2751 # number of quiesce instructions executed 2059system.cpu1.icache.tags.replacements 565233 # number of replacements 2060system.cpu1.icache.tags.tagsinuse 498.685358 # Cycle average of tags in use 2061system.cpu1.icache.tags.total_refs 20323921 # Total number of references to valid blocks. 2062system.cpu1.icache.tags.sampled_refs 565745 # Sample count of references to valid blocks. 2063system.cpu1.icache.tags.avg_refs 35.924173 # Average number of references to valid blocks. 2064system.cpu1.icache.tags.warmup_cycle 115078716000 # Cycle when the warmup percentage was hit. 2065system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.685358 # Average occupied blocks per requestor 2066system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973995 # Average percentage of cache occupancy 2067system.cpu1.icache.tags.occ_percent::total 0.973995 # Average percentage of cache occupancy |
| 2006system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2068system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2007system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 2008system.cpu1.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 2009system.cpu1.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 2010system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id | 2069system.cpu1.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id 2070system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id 2071system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id |
| 2011system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2072system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2012system.cpu1.icache.tags.tag_accesses 65832957 # Number of tag accesses 2013system.cpu1.icache.tags.data_accesses 65832957 # Number of data accesses 2014system.cpu1.icache.ReadReq_hits::cpu1.inst 32352870 # number of ReadReq hits 2015system.cpu1.icache.ReadReq_hits::total 32352870 # number of ReadReq hits 2016system.cpu1.icache.demand_hits::cpu1.inst 32352870 # number of demand (read+write) hits 2017system.cpu1.icache.demand_hits::total 32352870 # number of demand (read+write) hits 2018system.cpu1.icache.overall_hits::cpu1.inst 32352870 # number of overall hits 2019system.cpu1.icache.overall_hits::total 32352870 # number of overall hits 2020system.cpu1.icache.ReadReq_misses::cpu1.inst 375739 # number of ReadReq misses 2021system.cpu1.icache.ReadReq_misses::total 375739 # number of ReadReq misses 2022system.cpu1.icache.demand_misses::cpu1.inst 375739 # number of demand (read+write) misses 2023system.cpu1.icache.demand_misses::total 375739 # number of demand (read+write) misses 2024system.cpu1.icache.overall_misses::cpu1.inst 375739 # number of overall misses 2025system.cpu1.icache.overall_misses::total 375739 # number of overall misses 2026system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3159151510 # number of ReadReq miss cycles 2027system.cpu1.icache.ReadReq_miss_latency::total 3159151510 # number of ReadReq miss cycles 2028system.cpu1.icache.demand_miss_latency::cpu1.inst 3159151510 # number of demand (read+write) miss cycles 2029system.cpu1.icache.demand_miss_latency::total 3159151510 # number of demand (read+write) miss cycles 2030system.cpu1.icache.overall_miss_latency::cpu1.inst 3159151510 # number of overall miss cycles 2031system.cpu1.icache.overall_miss_latency::total 3159151510 # number of overall miss cycles 2032system.cpu1.icache.ReadReq_accesses::cpu1.inst 32728609 # number of ReadReq accesses(hits+misses) 2033system.cpu1.icache.ReadReq_accesses::total 32728609 # number of ReadReq accesses(hits+misses) 2034system.cpu1.icache.demand_accesses::cpu1.inst 32728609 # number of demand (read+write) accesses 2035system.cpu1.icache.demand_accesses::total 32728609 # number of demand (read+write) accesses 2036system.cpu1.icache.overall_accesses::cpu1.inst 32728609 # number of overall (read+write) accesses 2037system.cpu1.icache.overall_accesses::total 32728609 # number of overall (read+write) accesses 2038system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011480 # miss rate for ReadReq accesses 2039system.cpu1.icache.ReadReq_miss_rate::total 0.011480 # miss rate for ReadReq accesses 2040system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011480 # miss rate for demand accesses 2041system.cpu1.icache.demand_miss_rate::total 0.011480 # miss rate for demand accesses 2042system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011480 # miss rate for overall accesses 2043system.cpu1.icache.overall_miss_rate::total 0.011480 # miss rate for overall accesses 2044system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8407.834987 # average ReadReq miss latency 2045system.cpu1.icache.ReadReq_avg_miss_latency::total 8407.834987 # average ReadReq miss latency 2046system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency 2047system.cpu1.icache.demand_avg_miss_latency::total 8407.834987 # average overall miss latency 2048system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency 2049system.cpu1.icache.overall_avg_miss_latency::total 8407.834987 # average overall miss latency | 2073system.cpu1.icache.tags.tag_accesses 42345080 # Number of tag accesses 2074system.cpu1.icache.tags.data_accesses 42345080 # Number of data accesses 2075system.cpu1.icache.ReadReq_hits::cpu1.inst 20323921 # number of ReadReq hits 2076system.cpu1.icache.ReadReq_hits::total 20323921 # number of ReadReq hits 2077system.cpu1.icache.demand_hits::cpu1.inst 20323921 # number of demand (read+write) hits 2078system.cpu1.icache.demand_hits::total 20323921 # number of demand (read+write) hits 2079system.cpu1.icache.overall_hits::cpu1.inst 20323921 # number of overall hits 2080system.cpu1.icache.overall_hits::total 20323921 # number of overall hits 2081system.cpu1.icache.ReadReq_misses::cpu1.inst 565746 # number of ReadReq misses 2082system.cpu1.icache.ReadReq_misses::total 565746 # number of ReadReq misses 2083system.cpu1.icache.demand_misses::cpu1.inst 565746 # number of demand (read+write) misses 2084system.cpu1.icache.demand_misses::total 565746 # number of demand (read+write) misses 2085system.cpu1.icache.overall_misses::cpu1.inst 565746 # number of overall misses 2086system.cpu1.icache.overall_misses::total 565746 # number of overall misses 2087system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4684636281 # number of ReadReq miss cycles 2088system.cpu1.icache.ReadReq_miss_latency::total 4684636281 # number of ReadReq miss cycles 2089system.cpu1.icache.demand_miss_latency::cpu1.inst 4684636281 # number of demand (read+write) miss cycles 2090system.cpu1.icache.demand_miss_latency::total 4684636281 # number of demand (read+write) miss cycles 2091system.cpu1.icache.overall_miss_latency::cpu1.inst 4684636281 # number of overall miss cycles 2092system.cpu1.icache.overall_miss_latency::total 4684636281 # number of overall miss cycles 2093system.cpu1.icache.ReadReq_accesses::cpu1.inst 20889667 # number of ReadReq accesses(hits+misses) 2094system.cpu1.icache.ReadReq_accesses::total 20889667 # number of ReadReq accesses(hits+misses) 2095system.cpu1.icache.demand_accesses::cpu1.inst 20889667 # number of demand (read+write) accesses 2096system.cpu1.icache.demand_accesses::total 20889667 # number of demand (read+write) accesses 2097system.cpu1.icache.overall_accesses::cpu1.inst 20889667 # number of overall (read+write) accesses 2098system.cpu1.icache.overall_accesses::total 20889667 # number of overall (read+write) accesses 2099system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027083 # miss rate for ReadReq accesses 2100system.cpu1.icache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses 2101system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027083 # miss rate for demand accesses 2102system.cpu1.icache.demand_miss_rate::total 0.027083 # miss rate for demand accesses 2103system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027083 # miss rate for overall accesses 2104system.cpu1.icache.overall_miss_rate::total 0.027083 # miss rate for overall accesses 2105system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8280.458511 # average ReadReq miss latency 2106system.cpu1.icache.ReadReq_avg_miss_latency::total 8280.458511 # average ReadReq miss latency 2107system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency 2108system.cpu1.icache.demand_avg_miss_latency::total 8280.458511 # average overall miss latency 2109system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency 2110system.cpu1.icache.overall_avg_miss_latency::total 8280.458511 # average overall miss latency |
| 2050system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2051system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2052system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2053system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2054system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2055system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2056system.cpu1.icache.fast_writes 0 # number of fast writes performed 2057system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2111system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2112system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2113system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2114system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2115system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2116system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2117system.cpu1.icache.fast_writes 0 # number of fast writes performed 2118system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2058system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 375739 # number of ReadReq MSHR misses 2059system.cpu1.icache.ReadReq_mshr_misses::total 375739 # number of ReadReq MSHR misses 2060system.cpu1.icache.demand_mshr_misses::cpu1.inst 375739 # number of demand (read+write) MSHR misses 2061system.cpu1.icache.demand_mshr_misses::total 375739 # number of demand (read+write) MSHR misses 2062system.cpu1.icache.overall_mshr_misses::cpu1.inst 375739 # number of overall MSHR misses 2063system.cpu1.icache.overall_mshr_misses::total 375739 # number of overall MSHR misses 2064system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2595414990 # number of ReadReq MSHR miss cycles 2065system.cpu1.icache.ReadReq_mshr_miss_latency::total 2595414990 # number of ReadReq MSHR miss cycles 2066system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2595414990 # number of demand (read+write) MSHR miss cycles 2067system.cpu1.icache.demand_mshr_miss_latency::total 2595414990 # number of demand (read+write) MSHR miss cycles 2068system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2595414990 # number of overall MSHR miss cycles 2069system.cpu1.icache.overall_mshr_miss_latency::total 2595414990 # number of overall MSHR miss cycles 2070system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8511750 # number of ReadReq MSHR uncacheable cycles 2071system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8511750 # number of ReadReq MSHR uncacheable cycles 2072system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8511750 # number of overall MSHR uncacheable cycles 2073system.cpu1.icache.overall_mshr_uncacheable_latency::total 8511750 # number of overall MSHR uncacheable cycles 2074system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for ReadReq accesses 2075system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011480 # mshr miss rate for ReadReq accesses 2076system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for demand accesses 2077system.cpu1.icache.demand_mshr_miss_rate::total 0.011480 # mshr miss rate for demand accesses 2078system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for overall accesses 2079system.cpu1.icache.overall_mshr_miss_rate::total 0.011480 # mshr miss rate for overall accesses 2080system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average ReadReq mshr miss latency 2081system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6907.494271 # average ReadReq mshr miss latency 2082system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency 2083system.cpu1.icache.demand_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency 2084system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency 2085system.cpu1.icache.overall_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency | 2119system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565746 # number of ReadReq MSHR misses 2120system.cpu1.icache.ReadReq_mshr_misses::total 565746 # number of ReadReq MSHR misses 2121system.cpu1.icache.demand_mshr_misses::cpu1.inst 565746 # number of demand (read+write) MSHR misses 2122system.cpu1.icache.demand_mshr_misses::total 565746 # number of demand (read+write) MSHR misses 2123system.cpu1.icache.overall_mshr_misses::cpu1.inst 565746 # number of overall MSHR misses 2124system.cpu1.icache.overall_mshr_misses::total 565746 # number of overall MSHR misses 2125system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835844219 # number of ReadReq MSHR miss cycles 2126system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835844219 # number of ReadReq MSHR miss cycles 2127system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835844219 # number of demand (read+write) MSHR miss cycles 2128system.cpu1.icache.demand_mshr_miss_latency::total 3835844219 # number of demand (read+write) MSHR miss cycles 2129system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835844219 # number of overall MSHR miss cycles 2130system.cpu1.icache.overall_mshr_miss_latency::total 3835844219 # number of overall MSHR miss cycles 2131system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14025750 # number of ReadReq MSHR uncacheable cycles 2132system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14025750 # number of ReadReq MSHR uncacheable cycles 2133system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14025750 # number of overall MSHR uncacheable cycles 2134system.cpu1.icache.overall_mshr_uncacheable_latency::total 14025750 # number of overall MSHR uncacheable cycles 2135system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for ReadReq accesses 2136system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027083 # mshr miss rate for ReadReq accesses 2137system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for demand accesses 2138system.cpu1.icache.demand_mshr_miss_rate::total 0.027083 # mshr miss rate for demand accesses 2139system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for overall accesses 2140system.cpu1.icache.overall_mshr_miss_rate::total 0.027083 # mshr miss rate for overall accesses 2141system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average ReadReq mshr miss latency 2142system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6780.152611 # average ReadReq mshr miss latency 2143system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency 2144system.cpu1.icache.demand_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency 2145system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency 2146system.cpu1.icache.overall_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency |
| 2086system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2087system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2088system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2089system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2090system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2147system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2148system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2149system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2150system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2151system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2091system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 3539349 # number of hwpf identified 2092system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 109722 # number of hwpf that were already in mshr 2093system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3291325 # number of hwpf that were already in the cache 2094system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 217 # number of hwpf that were already in the prefetch queue | 2152system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4613211 # number of hwpf identified 2153system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23452 # number of hwpf that were already in mshr 2154system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471751 # number of hwpf that were already in the cache 2155system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 253 # number of hwpf that were already in the prefetch queue |
| 2095system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left | 2156system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| 2096system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 15 # number of hwpf removed because MSHR allocated 2097system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 138070 # number of hwpf issued 2098system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 329563 # number of hwpf spanning a virtual page | 2157system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 21 # number of hwpf removed because MSHR allocated 2158system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 117734 # number of hwpf issued 2159system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522133 # number of hwpf spanning a virtual page |
| 2099system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 2160system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 2100system.cpu1.l2cache.tags.replacements 122650 # number of replacements 2101system.cpu1.l2cache.tags.tagsinuse 15477.303394 # Cycle average of tags in use 2102system.cpu1.l2cache.tags.total_refs 769651 # Total number of references to valid blocks. 2103system.cpu1.l2cache.tags.sampled_refs 138796 # Sample count of references to valid blocks. 2104system.cpu1.l2cache.tags.avg_refs 5.545196 # Average number of references to valid blocks. 2105system.cpu1.l2cache.tags.warmup_cycle 2606454315500 # Cycle when the warmup percentage was hit. 2106system.cpu1.l2cache.tags.occ_blocks::writebacks 5482.269126 # Average occupied blocks per requestor 2107system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.040765 # Average occupied blocks per requestor 2108system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.187836 # Average occupied blocks per requestor 2109system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 603.787912 # Average occupied blocks per requestor 2110system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2723.851785 # Average occupied blocks per requestor 2111system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6655.165971 # Average occupied blocks per requestor 2112system.cpu1.l2cache.tags.occ_percent::writebacks 0.334611 # Average percentage of cache occupancy 2113system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000735 # Average percentage of cache occupancy 2114system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000011 # Average percentage of cache occupancy 2115system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036852 # Average percentage of cache occupancy 2116system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.166251 # Average percentage of cache occupancy 2117system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.406199 # Average percentage of cache occupancy 2118system.cpu1.l2cache.tags.occ_percent::total 0.944660 # Average percentage of cache occupancy 2119system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7087 # Occupied blocks per task id | 2161system.cpu1.l2cache.tags.replacements 85099 # number of replacements 2162system.cpu1.l2cache.tags.tagsinuse 15602.150946 # Cycle average of tags in use 2163system.cpu1.l2cache.tags.total_refs 830949 # Total number of references to valid blocks. 2164system.cpu1.l2cache.tags.sampled_refs 100297 # Sample count of references to valid blocks. 2165system.cpu1.l2cache.tags.avg_refs 8.284884 # Average number of references to valid blocks. 2166system.cpu1.l2cache.tags.warmup_cycle 2855978416500 # Cycle when the warmup percentage was hit. 2167system.cpu1.l2cache.tags.occ_blocks::writebacks 4730.109881 # Average occupied blocks per requestor 2168system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.755019 # Average occupied blocks per requestor 2169system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.314200 # Average occupied blocks per requestor 2170system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 871.040386 # Average occupied blocks per requestor 2171system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1529.848587 # Average occupied blocks per requestor 2172system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8465.082873 # Average occupied blocks per requestor 2173system.cpu1.l2cache.tags.occ_percent::writebacks 0.288703 # Average percentage of cache occupancy 2174system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000351 # Average percentage of cache occupancy 2175system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000019 # Average percentage of cache occupancy 2176system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053164 # Average percentage of cache occupancy 2177system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.093375 # Average percentage of cache occupancy 2178system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.516668 # Average percentage of cache occupancy 2179system.cpu1.l2cache.tags.occ_percent::total 0.952280 # Average percentage of cache occupancy 2180system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9308 # Occupied blocks per task id |
| 2120system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id | 2181system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id |
| 2121system.cpu1.l2cache.tags.occ_task_id_blocks::1024 9051 # Occupied blocks per task id 2122system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id 2123system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id 2124system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 481 # Occupied blocks per task id 2125system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4215 # Occupied blocks per task id 2126system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2330 # Occupied blocks per task id 2127system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 2128system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 2129system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 2130system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 2131system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 2132system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1744 # Occupied blocks per task id 2133system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5747 # Occupied blocks per task id 2134system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id 2135system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.432556 # Percentage of cache occupancy per task id | 2182system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5882 # Occupied blocks per task id 2183system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id 2184system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1130 # Occupied blocks per task id 2185system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8114 # Occupied blocks per task id 2186system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 2187system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 2188system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id 2189system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1134 # Occupied blocks per task id 2190system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4474 # Occupied blocks per task id 2191system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.568115 # Percentage of cache occupancy per task id |
| 2136system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id | 2192system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id |
| 2137system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.552429 # Percentage of cache occupancy per task id 2138system.cpu1.l2cache.tags.tag_accesses 16022455 # Number of tag accesses 2139system.cpu1.l2cache.tags.data_accesses 16022455 # Number of data accesses 2140system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 6174 # number of ReadReq hits 2141system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2268 # number of ReadReq hits 2142system.cpu1.l2cache.ReadReq_hits::cpu1.inst 369218 # number of ReadReq hits 2143system.cpu1.l2cache.ReadReq_hits::cpu1.data 169436 # number of ReadReq hits 2144system.cpu1.l2cache.ReadReq_hits::total 547096 # number of ReadReq hits 2145system.cpu1.l2cache.Writeback_hits::writebacks 225255 # number of Writeback hits 2146system.cpu1.l2cache.Writeback_hits::total 225255 # number of Writeback hits 2147system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1340 # number of UpgradeReq hits 2148system.cpu1.l2cache.UpgradeReq_hits::total 1340 # number of UpgradeReq hits 2149system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits 2150system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits 2151system.cpu1.l2cache.ReadExReq_hits::cpu1.data 86607 # number of ReadExReq hits 2152system.cpu1.l2cache.ReadExReq_hits::total 86607 # number of ReadExReq hits 2153system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 6174 # number of demand (read+write) hits 2154system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2268 # number of demand (read+write) hits 2155system.cpu1.l2cache.demand_hits::cpu1.inst 369218 # number of demand (read+write) hits 2156system.cpu1.l2cache.demand_hits::cpu1.data 256043 # number of demand (read+write) hits 2157system.cpu1.l2cache.demand_hits::total 633703 # number of demand (read+write) hits 2158system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 6174 # number of overall hits 2159system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2268 # number of overall hits 2160system.cpu1.l2cache.overall_hits::cpu1.inst 369218 # number of overall hits 2161system.cpu1.l2cache.overall_hits::cpu1.data 256043 # number of overall hits 2162system.cpu1.l2cache.overall_hits::total 633703 # number of overall hits 2163system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 268 # number of ReadReq misses 2164system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 169 # number of ReadReq misses 2165system.cpu1.l2cache.ReadReq_misses::cpu1.inst 6377 # number of ReadReq misses 2166system.cpu1.l2cache.ReadReq_misses::cpu1.data 56923 # number of ReadReq misses 2167system.cpu1.l2cache.ReadReq_misses::total 63737 # number of ReadReq misses 2168system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20417 # number of UpgradeReq misses 2169system.cpu1.l2cache.UpgradeReq_misses::total 20417 # number of UpgradeReq misses 2170system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 12784 # number of SCUpgradeReq misses 2171system.cpu1.l2cache.SCUpgradeReq_misses::total 12784 # number of SCUpgradeReq misses 2172system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2173system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 2174system.cpu1.l2cache.ReadExReq_misses::cpu1.data 23524 # number of ReadExReq misses 2175system.cpu1.l2cache.ReadExReq_misses::total 23524 # number of ReadExReq misses 2176system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 268 # number of demand (read+write) misses 2177system.cpu1.l2cache.demand_misses::cpu1.itb.walker 169 # number of demand (read+write) misses 2178system.cpu1.l2cache.demand_misses::cpu1.inst 6377 # number of demand (read+write) misses 2179system.cpu1.l2cache.demand_misses::cpu1.data 80447 # number of demand (read+write) misses 2180system.cpu1.l2cache.demand_misses::total 87261 # number of demand (read+write) misses 2181system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 268 # number of overall misses 2182system.cpu1.l2cache.overall_misses::cpu1.itb.walker 169 # number of overall misses 2183system.cpu1.l2cache.overall_misses::cpu1.inst 6377 # number of overall misses 2184system.cpu1.l2cache.overall_misses::cpu1.data 80447 # number of overall misses 2185system.cpu1.l2cache.overall_misses::total 87261 # number of overall misses 2186system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5694000 # number of ReadReq miss cycles 2187system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3369000 # number of ReadReq miss cycles 2188system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191106990 # number of ReadReq miss cycles 2189system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1462989443 # number of ReadReq miss cycles 2190system.cpu1.l2cache.ReadReq_miss_latency::total 1663159433 # number of ReadReq miss cycles 2191system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 341145571 # number of UpgradeReq miss cycles 2192system.cpu1.l2cache.UpgradeReq_miss_latency::total 341145571 # number of UpgradeReq miss cycles 2193system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 259918262 # number of SCUpgradeReq miss cycles 2194system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 259918262 # number of SCUpgradeReq miss cycles 2195system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 478999 # number of SCUpgradeFailReq miss cycles 2196system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 478999 # number of SCUpgradeFailReq miss cycles 2197system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 892976093 # number of ReadExReq miss cycles 2198system.cpu1.l2cache.ReadExReq_miss_latency::total 892976093 # number of ReadExReq miss cycles 2199system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5694000 # number of demand (read+write) miss cycles 2200system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3369000 # number of demand (read+write) miss cycles 2201system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191106990 # number of demand (read+write) miss cycles 2202system.cpu1.l2cache.demand_miss_latency::cpu1.data 2355965536 # number of demand (read+write) miss cycles 2203system.cpu1.l2cache.demand_miss_latency::total 2556135526 # number of demand (read+write) miss cycles 2204system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5694000 # number of overall miss cycles 2205system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3369000 # number of overall miss cycles 2206system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191106990 # number of overall miss cycles 2207system.cpu1.l2cache.overall_miss_latency::cpu1.data 2355965536 # number of overall miss cycles 2208system.cpu1.l2cache.overall_miss_latency::total 2556135526 # number of overall miss cycles 2209system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6442 # number of ReadReq accesses(hits+misses) 2210system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2437 # number of ReadReq accesses(hits+misses) 2211system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 375595 # number of ReadReq accesses(hits+misses) 2212system.cpu1.l2cache.ReadReq_accesses::cpu1.data 226359 # number of ReadReq accesses(hits+misses) 2213system.cpu1.l2cache.ReadReq_accesses::total 610833 # number of ReadReq accesses(hits+misses) 2214system.cpu1.l2cache.Writeback_accesses::writebacks 225255 # number of Writeback accesses(hits+misses) 2215system.cpu1.l2cache.Writeback_accesses::total 225255 # number of Writeback accesses(hits+misses) 2216system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 21757 # number of UpgradeReq accesses(hits+misses) 2217system.cpu1.l2cache.UpgradeReq_accesses::total 21757 # number of UpgradeReq accesses(hits+misses) 2218system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 13669 # number of SCUpgradeReq accesses(hits+misses) 2219system.cpu1.l2cache.SCUpgradeReq_accesses::total 13669 # number of SCUpgradeReq accesses(hits+misses) 2220system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2221system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 2222system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 110131 # number of ReadExReq accesses(hits+misses) 2223system.cpu1.l2cache.ReadExReq_accesses::total 110131 # number of ReadExReq accesses(hits+misses) 2224system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6442 # number of demand (read+write) accesses 2225system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2437 # number of demand (read+write) accesses 2226system.cpu1.l2cache.demand_accesses::cpu1.inst 375595 # number of demand (read+write) accesses 2227system.cpu1.l2cache.demand_accesses::cpu1.data 336490 # number of demand (read+write) accesses 2228system.cpu1.l2cache.demand_accesses::total 720964 # number of demand (read+write) accesses 2229system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6442 # number of overall (read+write) accesses 2230system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2437 # number of overall (read+write) accesses 2231system.cpu1.l2cache.overall_accesses::cpu1.inst 375595 # number of overall (read+write) accesses 2232system.cpu1.l2cache.overall_accesses::cpu1.data 336490 # number of overall (read+write) accesses 2233system.cpu1.l2cache.overall_accesses::total 720964 # number of overall (read+write) accesses 2234system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for ReadReq accesses 2235system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.069348 # miss rate for ReadReq accesses 2236system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.016978 # miss rate for ReadReq accesses 2237system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.251472 # miss rate for ReadReq accesses 2238system.cpu1.l2cache.ReadReq_miss_rate::total 0.104344 # miss rate for ReadReq accesses 2239system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938411 # miss rate for UpgradeReq accesses 2240system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938411 # miss rate for UpgradeReq accesses 2241system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.935255 # miss rate for SCUpgradeReq accesses 2242system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.935255 # miss rate for SCUpgradeReq accesses | 2193system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359009 # Percentage of cache occupancy per task id 2194system.cpu1.l2cache.tags.tag_accesses 16690228 # Number of tag accesses 2195system.cpu1.l2cache.tags.data_accesses 16690228 # Number of data accesses 2196system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3013 # number of ReadReq hits 2197system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1699 # number of ReadReq hits 2198system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560147 # number of ReadReq hits 2199system.cpu1.l2cache.ReadReq_hits::cpu1.data 123235 # number of ReadReq hits 2200system.cpu1.l2cache.ReadReq_hits::total 688094 # number of ReadReq hits 2201system.cpu1.l2cache.Writeback_hits::writebacks 134926 # number of Writeback hits 2202system.cpu1.l2cache.Writeback_hits::total 134926 # number of Writeback hits 2203system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1530 # number of UpgradeReq hits 2204system.cpu1.l2cache.UpgradeReq_hits::total 1530 # number of UpgradeReq hits 2205system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 889 # number of SCUpgradeReq hits 2206system.cpu1.l2cache.SCUpgradeReq_hits::total 889 # number of SCUpgradeReq hits 2207system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39290 # number of ReadExReq hits 2208system.cpu1.l2cache.ReadExReq_hits::total 39290 # number of ReadExReq hits 2209system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3013 # number of demand (read+write) hits 2210system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1699 # number of demand (read+write) hits 2211system.cpu1.l2cache.demand_hits::cpu1.inst 560147 # number of demand (read+write) hits 2212system.cpu1.l2cache.demand_hits::cpu1.data 162525 # number of demand (read+write) hits 2213system.cpu1.l2cache.demand_hits::total 727384 # number of demand (read+write) hits 2214system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3013 # number of overall hits 2215system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1699 # number of overall hits 2216system.cpu1.l2cache.overall_hits::cpu1.inst 560147 # number of overall hits 2217system.cpu1.l2cache.overall_hits::cpu1.data 162525 # number of overall hits 2218system.cpu1.l2cache.overall_hits::total 727384 # number of overall hits 2219system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 347 # number of ReadReq misses 2220system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses 2221system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5599 # number of ReadReq misses 2222system.cpu1.l2cache.ReadReq_misses::cpu1.data 70297 # number of ReadReq misses 2223system.cpu1.l2cache.ReadReq_misses::total 76525 # number of ReadReq misses 2224system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29432 # number of UpgradeReq misses 2225system.cpu1.l2cache.UpgradeReq_misses::total 29432 # number of UpgradeReq misses 2226system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22334 # number of SCUpgradeReq misses 2227system.cpu1.l2cache.SCUpgradeReq_misses::total 22334 # number of SCUpgradeReq misses 2228system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2229system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2230system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33500 # number of ReadExReq misses 2231system.cpu1.l2cache.ReadExReq_misses::total 33500 # number of ReadExReq misses 2232system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 347 # number of demand (read+write) misses 2233system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses 2234system.cpu1.l2cache.demand_misses::cpu1.inst 5599 # number of demand (read+write) misses 2235system.cpu1.l2cache.demand_misses::cpu1.data 103797 # number of demand (read+write) misses 2236system.cpu1.l2cache.demand_misses::total 110025 # number of demand (read+write) misses 2237system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 347 # number of overall misses 2238system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses 2239system.cpu1.l2cache.overall_misses::cpu1.inst 5599 # number of overall misses 2240system.cpu1.l2cache.overall_misses::cpu1.data 103797 # number of overall misses 2241system.cpu1.l2cache.overall_misses::total 110025 # number of overall misses 2242system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7263500 # number of ReadReq miss cycles 2243system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5687750 # number of ReadReq miss cycles 2244system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191326469 # number of ReadReq miss cycles 2245system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1549353898 # number of ReadReq miss cycles 2246system.cpu1.l2cache.ReadReq_miss_latency::total 1753631617 # number of ReadReq miss cycles 2247system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537113129 # number of UpgradeReq miss cycles 2248system.cpu1.l2cache.UpgradeReq_miss_latency::total 537113129 # number of UpgradeReq miss cycles 2249system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436542574 # number of SCUpgradeReq miss cycles 2250system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436542574 # number of SCUpgradeReq miss cycles 2251system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1696500 # number of SCUpgradeFailReq miss cycles 2252system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1696500 # number of SCUpgradeFailReq miss cycles 2253system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1074535378 # number of ReadExReq miss cycles 2254system.cpu1.l2cache.ReadExReq_miss_latency::total 1074535378 # number of ReadExReq miss cycles 2255system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7263500 # number of demand (read+write) miss cycles 2256system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5687750 # number of demand (read+write) miss cycles 2257system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191326469 # number of demand (read+write) miss cycles 2258system.cpu1.l2cache.demand_miss_latency::cpu1.data 2623889276 # number of demand (read+write) miss cycles 2259system.cpu1.l2cache.demand_miss_latency::total 2828166995 # number of demand (read+write) miss cycles 2260system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7263500 # number of overall miss cycles 2261system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5687750 # number of overall miss cycles 2262system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191326469 # number of overall miss cycles 2263system.cpu1.l2cache.overall_miss_latency::cpu1.data 2623889276 # number of overall miss cycles 2264system.cpu1.l2cache.overall_miss_latency::total 2828166995 # number of overall miss cycles 2265system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3360 # number of ReadReq accesses(hits+misses) 2266system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses) 2267system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565746 # number of ReadReq accesses(hits+misses) 2268system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193532 # number of ReadReq accesses(hits+misses) 2269system.cpu1.l2cache.ReadReq_accesses::total 764619 # number of ReadReq accesses(hits+misses) 2270system.cpu1.l2cache.Writeback_accesses::writebacks 134926 # number of Writeback accesses(hits+misses) 2271system.cpu1.l2cache.Writeback_accesses::total 134926 # number of Writeback accesses(hits+misses) 2272system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30962 # number of UpgradeReq accesses(hits+misses) 2273system.cpu1.l2cache.UpgradeReq_accesses::total 30962 # number of UpgradeReq accesses(hits+misses) 2274system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23223 # number of SCUpgradeReq accesses(hits+misses) 2275system.cpu1.l2cache.SCUpgradeReq_accesses::total 23223 # number of SCUpgradeReq accesses(hits+misses) 2276system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2277system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2278system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72790 # number of ReadExReq accesses(hits+misses) 2279system.cpu1.l2cache.ReadExReq_accesses::total 72790 # number of ReadExReq accesses(hits+misses) 2280system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3360 # number of demand (read+write) accesses 2281system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses 2282system.cpu1.l2cache.demand_accesses::cpu1.inst 565746 # number of demand (read+write) accesses 2283system.cpu1.l2cache.demand_accesses::cpu1.data 266322 # number of demand (read+write) accesses 2284system.cpu1.l2cache.demand_accesses::total 837409 # number of demand (read+write) accesses 2285system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3360 # number of overall (read+write) accesses 2286system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses 2287system.cpu1.l2cache.overall_accesses::cpu1.inst 565746 # number of overall (read+write) accesses 2288system.cpu1.l2cache.overall_accesses::cpu1.data 266322 # number of overall (read+write) accesses 2289system.cpu1.l2cache.overall_accesses::total 837409 # number of overall (read+write) accesses 2290system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for ReadReq accesses 2291system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.142352 # miss rate for ReadReq accesses 2292system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009897 # miss rate for ReadReq accesses 2293system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363232 # miss rate for ReadReq accesses 2294system.cpu1.l2cache.ReadReq_miss_rate::total 0.100083 # miss rate for ReadReq accesses 2295system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950585 # miss rate for UpgradeReq accesses 2296system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950585 # miss rate for UpgradeReq accesses 2297system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961719 # miss rate for SCUpgradeReq accesses 2298system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961719 # miss rate for SCUpgradeReq accesses |
| 2243system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2244system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2299system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2300system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2245system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.213600 # miss rate for ReadExReq accesses 2246system.cpu1.l2cache.ReadExReq_miss_rate::total 0.213600 # miss rate for ReadExReq accesses 2247system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for demand accesses 2248system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.069348 # miss rate for demand accesses 2249system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.016978 # miss rate for demand accesses 2250system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.239077 # miss rate for demand accesses 2251system.cpu1.l2cache.demand_miss_rate::total 0.121034 # miss rate for demand accesses 2252system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for overall accesses 2253system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.069348 # miss rate for overall accesses 2254system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.016978 # miss rate for overall accesses 2255system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.239077 # miss rate for overall accesses 2256system.cpu1.l2cache.overall_miss_rate::total 0.121034 # miss rate for overall accesses 2257system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21246.268657 # average ReadReq miss latency 2258system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19934.911243 # average ReadReq miss latency 2259system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29968.165281 # average ReadReq miss latency 2260system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 25701.200622 # average ReadReq miss latency 2261system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26094.096569 # average ReadReq miss latency 2262system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16708.898026 # average UpgradeReq miss latency 2263system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16708.898026 # average UpgradeReq miss latency 2264system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20331.528630 # average SCUpgradeReq miss latency 2265system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20331.528630 # average SCUpgradeReq miss latency 2266system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 239499.500000 # average SCUpgradeFailReq miss latency 2267system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 239499.500000 # average SCUpgradeFailReq miss latency 2268system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37960.214802 # average ReadExReq miss latency 2269system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37960.214802 # average ReadExReq miss latency 2270system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21246.268657 # average overall miss latency 2271system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19934.911243 # average overall miss latency 2272system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29968.165281 # average overall miss latency 2273system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29285.934044 # average overall miss latency 2274system.cpu1.l2cache.demand_avg_miss_latency::total 29292.989148 # average overall miss latency 2275system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21246.268657 # average overall miss latency 2276system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19934.911243 # average overall miss latency 2277system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29968.165281 # average overall miss latency 2278system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29285.934044 # average overall miss latency 2279system.cpu1.l2cache.overall_avg_miss_latency::total 29292.989148 # average overall miss latency 2280system.cpu1.l2cache.blocked_cycles::no_mshrs 579 # number of cycles access was blocked | 2301system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.460228 # miss rate for ReadExReq accesses 2302system.cpu1.l2cache.ReadExReq_miss_rate::total 0.460228 # miss rate for ReadExReq accesses 2303system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for demand accesses 2304system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.142352 # miss rate for demand accesses 2305system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009897 # miss rate for demand accesses 2306system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389742 # miss rate for demand accesses 2307system.cpu1.l2cache.demand_miss_rate::total 0.131387 # miss rate for demand accesses 2308system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for overall accesses 2309system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.142352 # miss rate for overall accesses 2310system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009897 # miss rate for overall accesses 2311system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389742 # miss rate for overall accesses 2312system.cpu1.l2cache.overall_miss_rate::total 0.131387 # miss rate for overall accesses 2313system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average ReadReq miss latency 2314system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241 # average ReadReq miss latency 2315system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954 # average ReadReq miss latency 2316system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059 # average ReadReq miss latency 2317system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287 # average ReadReq miss latency 2318system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874 # average UpgradeReq miss latency 2319system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874 # average UpgradeReq miss latency 2320system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952 # average SCUpgradeReq miss latency 2321system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952 # average SCUpgradeReq miss latency 2322system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 565500 # average SCUpgradeFailReq miss latency 2323system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 565500 # average SCUpgradeFailReq miss latency 2324system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925 # average ReadExReq miss latency 2325system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925 # average ReadExReq miss latency 2326system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency 2327system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency 2328system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency 2329system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency 2330system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053 # average overall miss latency 2331system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency 2332system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency 2333system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency 2334system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency 2335system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053 # average overall miss latency 2336system.cpu1.l2cache.blocked_cycles::no_mshrs 1025 # number of cycles access was blocked |
| 2281system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2337system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2282system.cpu1.l2cache.blocked::no_mshrs 19 # number of cycles access was blocked | 2338system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked |
| 2283system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2339system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2284system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.473684 # average number of cycles each access was blocked | 2340system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.285714 # average number of cycles each access was blocked |
| 2285system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2286system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2287system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2341system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2342system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2343system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2288system.cpu1.l2cache.writebacks::writebacks 66455 # number of writebacks 2289system.cpu1.l2cache.writebacks::total 66455 # number of writebacks 2290system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 767 # number of ReadReq MSHR hits 2291system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 80 # number of ReadReq MSHR hits 2292system.cpu1.l2cache.ReadReq_mshr_hits::total 847 # number of ReadReq MSHR hits 2293system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1344 # number of ReadExReq MSHR hits 2294system.cpu1.l2cache.ReadExReq_mshr_hits::total 1344 # number of ReadExReq MSHR hits 2295system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 767 # number of demand (read+write) MSHR hits 2296system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1424 # number of demand (read+write) MSHR hits 2297system.cpu1.l2cache.demand_mshr_hits::total 2191 # number of demand (read+write) MSHR hits 2298system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 767 # number of overall MSHR hits 2299system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1424 # number of overall MSHR hits 2300system.cpu1.l2cache.overall_mshr_hits::total 2191 # number of overall MSHR hits 2301system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 268 # number of ReadReq MSHR misses 2302system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 169 # number of ReadReq MSHR misses 2303system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 5610 # number of ReadReq MSHR misses 2304system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 56843 # number of ReadReq MSHR misses 2305system.cpu1.l2cache.ReadReq_mshr_misses::total 62890 # number of ReadReq MSHR misses 2306system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 138069 # number of HardPFReq MSHR misses 2307system.cpu1.l2cache.HardPFReq_mshr_misses::total 138069 # number of HardPFReq MSHR misses 2308system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20417 # number of UpgradeReq MSHR misses 2309system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20417 # number of UpgradeReq MSHR misses 2310system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 12784 # number of SCUpgradeReq MSHR misses 2311system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12784 # number of SCUpgradeReq MSHR misses 2312system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2313system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2314system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 22180 # number of ReadExReq MSHR misses 2315system.cpu1.l2cache.ReadExReq_mshr_misses::total 22180 # number of ReadExReq MSHR misses 2316system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 268 # number of demand (read+write) MSHR misses 2317system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 169 # number of demand (read+write) MSHR misses 2318system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 5610 # number of demand (read+write) MSHR misses 2319system.cpu1.l2cache.demand_mshr_misses::cpu1.data 79023 # number of demand (read+write) MSHR misses 2320system.cpu1.l2cache.demand_mshr_misses::total 85070 # number of demand (read+write) MSHR misses 2321system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 268 # number of overall MSHR misses 2322system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 169 # number of overall MSHR misses 2323system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 5610 # number of overall MSHR misses 2324system.cpu1.l2cache.overall_mshr_misses::cpu1.data 79023 # number of overall MSHR misses 2325system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 138069 # number of overall MSHR misses 2326system.cpu1.l2cache.overall_mshr_misses::total 223139 # number of overall MSHR misses 2327system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of ReadReq MSHR miss cycles 2328system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2186000 # number of ReadReq MSHR miss cycles 2329system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 137414260 # number of ReadReq MSHR miss cycles 2330system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1062900207 # number of ReadReq MSHR miss cycles 2331system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206317967 # number of ReadReq MSHR miss cycles 2332system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7048181570 # number of HardPFReq MSHR miss cycles 2333system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 7048181570 # number of HardPFReq MSHR miss cycles 2334system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 332046976 # number of UpgradeReq MSHR miss cycles 2335system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 332046976 # number of UpgradeReq MSHR miss cycles 2336system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 180785968 # number of SCUpgradeReq MSHR miss cycles 2337system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 180785968 # number of SCUpgradeReq MSHR miss cycles 2338system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 373999 # number of SCUpgradeFailReq MSHR miss cycles 2339system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 373999 # number of SCUpgradeFailReq MSHR miss cycles 2340system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 591403879 # number of ReadExReq MSHR miss cycles 2341system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 591403879 # number of ReadExReq MSHR miss cycles 2342system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of demand (read+write) MSHR miss cycles 2343system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2186000 # number of demand (read+write) MSHR miss cycles 2344system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 137414260 # number of demand (read+write) MSHR miss cycles 2345system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1654304086 # number of demand (read+write) MSHR miss cycles 2346system.cpu1.l2cache.demand_mshr_miss_latency::total 1797721846 # number of demand (read+write) MSHR miss cycles 2347system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of overall MSHR miss cycles 2348system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2186000 # number of overall MSHR miss cycles 2349system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 137414260 # number of overall MSHR miss cycles 2350system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1654304086 # number of overall MSHR miss cycles 2351system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7048181570 # number of overall MSHR miss cycles 2352system.cpu1.l2cache.overall_mshr_miss_latency::total 8845903416 # number of overall MSHR miss cycles 2353system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7648750 # number of ReadReq MSHR uncacheable cycles 2354system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 12231230753 # number of ReadReq MSHR uncacheable cycles 2355system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 12238879503 # number of ReadReq MSHR uncacheable cycles 2356system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 28539732155 # number of WriteReq MSHR uncacheable cycles 2357system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28539732155 # number of WriteReq MSHR uncacheable cycles 2358system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7648750 # number of overall MSHR uncacheable cycles 2359system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 40770962908 # number of overall MSHR uncacheable cycles 2360system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 40778611658 # number of overall MSHR uncacheable cycles 2361system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for ReadReq accesses 2362system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for ReadReq accesses 2363system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for ReadReq accesses 2364system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.251119 # mshr miss rate for ReadReq accesses 2365system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.102958 # mshr miss rate for ReadReq accesses | 2344system.cpu1.l2cache.writebacks::writebacks 35099 # number of writebacks 2345system.cpu1.l2cache.writebacks::total 35099 # number of writebacks 2346system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 685 # number of ReadReq MSHR hits 2347system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 96 # number of ReadReq MSHR hits 2348system.cpu1.l2cache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits 2349system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 214 # number of ReadExReq MSHR hits 2350system.cpu1.l2cache.ReadExReq_mshr_hits::total 214 # number of ReadExReq MSHR hits 2351system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 685 # number of demand (read+write) MSHR hits 2352system.cpu1.l2cache.demand_mshr_hits::cpu1.data 310 # number of demand (read+write) MSHR hits 2353system.cpu1.l2cache.demand_mshr_hits::total 995 # number of demand (read+write) MSHR hits 2354system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 685 # number of overall MSHR hits 2355system.cpu1.l2cache.overall_mshr_hits::cpu1.data 310 # number of overall MSHR hits 2356system.cpu1.l2cache.overall_mshr_hits::total 995 # number of overall MSHR hits 2357system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 347 # number of ReadReq MSHR misses 2358system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses 2359system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4914 # number of ReadReq MSHR misses 2360system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70201 # number of ReadReq MSHR misses 2361system.cpu1.l2cache.ReadReq_mshr_misses::total 75744 # number of ReadReq MSHR misses 2362system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of HardPFReq MSHR misses 2363system.cpu1.l2cache.HardPFReq_mshr_misses::total 117733 # number of HardPFReq MSHR misses 2364system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29432 # number of UpgradeReq MSHR misses 2365system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29432 # number of UpgradeReq MSHR misses 2366system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22334 # number of SCUpgradeReq MSHR misses 2367system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22334 # number of SCUpgradeReq MSHR misses 2368system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2369system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2370system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33286 # number of ReadExReq MSHR misses 2371system.cpu1.l2cache.ReadExReq_mshr_misses::total 33286 # number of ReadExReq MSHR misses 2372system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 347 # number of demand (read+write) MSHR misses 2373system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses 2374system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4914 # number of demand (read+write) MSHR misses 2375system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103487 # number of demand (read+write) MSHR misses 2376system.cpu1.l2cache.demand_mshr_misses::total 109030 # number of demand (read+write) MSHR misses 2377system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 347 # number of overall MSHR misses 2378system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses 2379system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4914 # number of overall MSHR misses 2380system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103487 # number of overall MSHR misses 2381system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of overall MSHR misses 2382system.cpu1.l2cache.overall_mshr_misses::total 226763 # number of overall MSHR misses 2383system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of ReadReq MSHR miss cycles 2384system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3713250 # number of ReadReq MSHR miss cycles 2385system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143751774 # number of ReadReq MSHR miss cycles 2386system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1055636432 # number of ReadReq MSHR miss cycles 2387system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1207934956 # number of ReadReq MSHR miss cycles 2388system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of HardPFReq MSHR miss cycles 2389system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3298666709 # number of HardPFReq MSHR miss cycles 2390system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 431077198 # number of UpgradeReq MSHR miss cycles 2391system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 431077198 # number of UpgradeReq MSHR miss cycles 2392system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306544179 # number of SCUpgradeReq MSHR miss cycles 2393system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306544179 # number of SCUpgradeReq MSHR miss cycles 2394system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1430500 # number of SCUpgradeFailReq MSHR miss cycles 2395system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1430500 # number of SCUpgradeFailReq MSHR miss cycles 2396system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820609092 # number of ReadExReq MSHR miss cycles 2397system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820609092 # number of ReadExReq MSHR miss cycles 2398system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of demand (read+write) MSHR miss cycles 2399system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3713250 # number of demand (read+write) MSHR miss cycles 2400system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143751774 # number of demand (read+write) MSHR miss cycles 2401system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1876245524 # number of demand (read+write) MSHR miss cycles 2402system.cpu1.l2cache.demand_mshr_miss_latency::total 2028544048 # number of demand (read+write) MSHR miss cycles 2403system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of overall MSHR miss cycles 2404system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3713250 # number of overall MSHR miss cycles 2405system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143751774 # number of overall MSHR miss cycles 2406system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1876245524 # number of overall MSHR miss cycles 2407system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of overall MSHR miss cycles 2408system.cpu1.l2cache.overall_mshr_miss_latency::total 5327210757 # number of overall MSHR miss cycles 2409system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12612250 # number of ReadReq MSHR uncacheable cycles 2410system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916010500 # number of ReadReq MSHR uncacheable cycles 2411system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928622750 # number of ReadReq MSHR uncacheable cycles 2412system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796474001 # number of WriteReq MSHR uncacheable cycles 2413system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796474001 # number of WriteReq MSHR uncacheable cycles 2414system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12612250 # number of overall MSHR uncacheable cycles 2415system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712484501 # number of overall MSHR uncacheable cycles 2416system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725096751 # number of overall MSHR uncacheable cycles 2417system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for ReadReq accesses 2418system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for ReadReq accesses 2419system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for ReadReq accesses 2420system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362736 # mshr miss rate for ReadReq accesses 2421system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099061 # mshr miss rate for ReadReq accesses |
| 2366system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2367system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2422system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2423system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2368system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938411 # mshr miss rate for UpgradeReq accesses 2369system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses 2370system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935255 # mshr miss rate for SCUpgradeReq accesses 2371system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.935255 # mshr miss rate for SCUpgradeReq accesses | 2424system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950585 # mshr miss rate for UpgradeReq accesses 2425system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950585 # mshr miss rate for UpgradeReq accesses 2426system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961719 # mshr miss rate for SCUpgradeReq accesses 2427system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961719 # mshr miss rate for SCUpgradeReq accesses |
| 2372system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2373system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2428system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2429system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2374system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.201397 # mshr miss rate for ReadExReq accesses 2375system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.201397 # mshr miss rate for ReadExReq accesses 2376system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for demand accesses 2377system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for demand accesses 2378system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for demand accesses 2379system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for demand accesses 2380system.cpu1.l2cache.demand_mshr_miss_rate::total 0.117995 # mshr miss rate for demand accesses 2381system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for overall accesses 2382system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for overall accesses 2383system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for overall accesses 2384system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for overall accesses | 2430system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457288 # mshr miss rate for ReadExReq accesses 2431system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457288 # mshr miss rate for ReadExReq accesses 2432system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for demand accesses 2433system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for demand accesses 2434system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for demand accesses 2435system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for demand accesses 2436system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130199 # mshr miss rate for demand accesses 2437system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for overall accesses 2438system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for overall accesses 2439system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for overall accesses 2440system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for overall accesses |
| 2385system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2441system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2386system.cpu1.l2cache.overall_mshr_miss_rate::total 0.309501 # mshr miss rate for overall accesses 2387system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average ReadReq mshr miss latency 2388system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average ReadReq mshr miss latency 2389system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average ReadReq mshr miss latency 2390system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 18698.875974 # average ReadReq mshr miss latency 2391system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 19181.395564 # average ReadReq mshr miss latency 2392system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average HardPFReq mshr miss latency 2393system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365 # average HardPFReq mshr miss latency 2394system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832 # average UpgradeReq mshr miss latency 2395system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency 2396system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726 # average SCUpgradeReq mshr miss latency 2397system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726 # average SCUpgradeReq mshr miss latency 2398system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000 # average SCUpgradeFailReq mshr miss latency 2399system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000 # average SCUpgradeFailReq mshr miss latency 2400system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843 # average ReadExReq mshr miss latency 2401system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # average ReadExReq mshr miss latency 2402system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency 2403system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency 2404system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency 2405system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency 2406system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21132.265734 # average overall mshr miss latency 2407system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency 2408system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency 2409system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency 2410system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency 2411system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average overall mshr miss latency 2412system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101 # average overall mshr miss latency | 2442system.cpu1.l2cache.overall_mshr_miss_rate::total 0.270791 # mshr miss rate for overall accesses 2443system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average ReadReq mshr miss latency 2444system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average ReadReq mshr miss latency 2445system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average ReadReq mshr miss latency 2446system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804 # average ReadReq mshr miss latency 2447system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229 # average ReadReq mshr miss latency 2448system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average HardPFReq mshr miss latency 2449system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732 # average HardPFReq mshr miss latency 2450system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907 # average UpgradeReq mshr miss latency 2451system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907 # average UpgradeReq mshr miss latency 2452system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046 # average SCUpgradeReq mshr miss latency 2453system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046 # average SCUpgradeReq mshr miss latency 2454system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333 # average SCUpgradeFailReq mshr miss latency 2455system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333 # average SCUpgradeFailReq mshr miss latency 2456system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418 # average ReadExReq mshr miss latency 2457system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418 # average ReadExReq mshr miss latency 2458system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency 2459system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency 2460system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency 2461system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency 2462system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108 # average overall mshr miss latency 2463system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency 2464system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency 2465system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency 2466system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency 2467system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average overall mshr miss latency 2468system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122 # average overall mshr miss latency |
| 2413system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2414system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2415system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2416system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2417system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2418system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2419system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2420system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2421system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2469system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2470system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2471system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2472system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2473system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2474system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2475system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2476system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2477system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2422system.cpu1.dcache.tags.replacements 313601 # number of replacements 2423system.cpu1.dcache.tags.tagsinuse 474.302028 # Cycle average of tags in use 2424system.cpu1.dcache.tags.total_refs 10949850 # Total number of references to valid blocks. 2425system.cpu1.dcache.tags.sampled_refs 314113 # Sample count of references to valid blocks. 2426system.cpu1.dcache.tags.avg_refs 34.859589 # Average number of references to valid blocks. 2427system.cpu1.dcache.tags.warmup_cycle 76456711000 # Cycle when the warmup percentage was hit. 2428system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.302028 # Average occupied blocks per requestor 2429system.cpu1.dcache.tags.occ_percent::cpu1.data 0.926371 # Average percentage of cache occupancy 2430system.cpu1.dcache.tags.occ_percent::total 0.926371 # Average percentage of cache occupancy 2431system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2432system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 2433system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id 2434system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id 2435system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2436system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses 2437system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses 2438system.cpu1.dcache.ReadReq_hits::cpu1.data 6183420 # number of ReadReq hits 2439system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits 2440system.cpu1.dcache.WriteReq_hits::cpu1.data 4558750 # number of WriteReq hits 2441system.cpu1.dcache.WriteReq_hits::total 4558750 # number of WriteReq hits 2442system.cpu1.dcache.SoftPFReq_hits::cpu1.data 19290 # number of SoftPFReq hits 2443system.cpu1.dcache.SoftPFReq_hits::total 19290 # number of SoftPFReq hits 2444system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77402 # number of LoadLockedReq hits 2445system.cpu1.dcache.LoadLockedReq_hits::total 77402 # number of LoadLockedReq hits 2446system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75753 # number of StoreCondReq hits 2447system.cpu1.dcache.StoreCondReq_hits::total 75753 # number of StoreCondReq hits 2448system.cpu1.dcache.demand_hits::cpu1.data 10742170 # number of demand (read+write) hits 2449system.cpu1.dcache.demand_hits::total 10742170 # number of demand (read+write) hits 2450system.cpu1.dcache.overall_hits::cpu1.data 10761460 # number of overall hits 2451system.cpu1.dcache.overall_hits::total 10761460 # number of overall hits 2452system.cpu1.dcache.ReadReq_misses::cpu1.data 187243 # number of ReadReq misses 2453system.cpu1.dcache.ReadReq_misses::total 187243 # number of ReadReq misses 2454system.cpu1.dcache.WriteReq_misses::cpu1.data 134937 # number of WriteReq misses 2455system.cpu1.dcache.WriteReq_misses::total 134937 # number of WriteReq misses 2456system.cpu1.dcache.SoftPFReq_misses::cpu1.data 43327 # number of SoftPFReq misses 2457system.cpu1.dcache.SoftPFReq_misses::total 43327 # number of SoftPFReq misses 2458system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12089 # number of LoadLockedReq misses 2459system.cpu1.dcache.LoadLockedReq_misses::total 12089 # number of LoadLockedReq misses 2460system.cpu1.dcache.StoreCondReq_misses::cpu1.data 13673 # number of StoreCondReq misses 2461system.cpu1.dcache.StoreCondReq_misses::total 13673 # number of StoreCondReq misses 2462system.cpu1.dcache.demand_misses::cpu1.data 322180 # number of demand (read+write) misses 2463system.cpu1.dcache.demand_misses::total 322180 # number of demand (read+write) misses 2464system.cpu1.dcache.overall_misses::cpu1.data 365507 # number of overall misses 2465system.cpu1.dcache.overall_misses::total 365507 # number of overall misses 2466system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2299329756 # number of ReadReq miss cycles 2467system.cpu1.dcache.ReadReq_miss_latency::total 2299329756 # number of ReadReq miss cycles 2468system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2509975628 # number of WriteReq miss cycles 2469system.cpu1.dcache.WriteReq_miss_latency::total 2509975628 # number of WriteReq miss cycles 2470system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 218034000 # number of LoadLockedReq miss cycles 2471system.cpu1.dcache.LoadLockedReq_miss_latency::total 218034000 # number of LoadLockedReq miss cycles 2472system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 317344970 # number of StoreCondReq miss cycles 2473system.cpu1.dcache.StoreCondReq_miss_latency::total 317344970 # number of StoreCondReq miss cycles 2474system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 524000 # number of StoreCondFailReq miss cycles 2475system.cpu1.dcache.StoreCondFailReq_miss_latency::total 524000 # number of StoreCondFailReq miss cycles 2476system.cpu1.dcache.demand_miss_latency::cpu1.data 4809305384 # number of demand (read+write) miss cycles 2477system.cpu1.dcache.demand_miss_latency::total 4809305384 # number of demand (read+write) miss cycles 2478system.cpu1.dcache.overall_miss_latency::cpu1.data 4809305384 # number of overall miss cycles 2479system.cpu1.dcache.overall_miss_latency::total 4809305384 # number of overall miss cycles 2480system.cpu1.dcache.ReadReq_accesses::cpu1.data 6370663 # number of ReadReq accesses(hits+misses) 2481system.cpu1.dcache.ReadReq_accesses::total 6370663 # number of ReadReq accesses(hits+misses) 2482system.cpu1.dcache.WriteReq_accesses::cpu1.data 4693687 # number of WriteReq accesses(hits+misses) 2483system.cpu1.dcache.WriteReq_accesses::total 4693687 # number of WriteReq accesses(hits+misses) 2484system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 62617 # number of SoftPFReq accesses(hits+misses) 2485system.cpu1.dcache.SoftPFReq_accesses::total 62617 # number of SoftPFReq accesses(hits+misses) 2486system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89491 # number of LoadLockedReq accesses(hits+misses) 2487system.cpu1.dcache.LoadLockedReq_accesses::total 89491 # number of LoadLockedReq accesses(hits+misses) 2488system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89426 # number of StoreCondReq accesses(hits+misses) 2489system.cpu1.dcache.StoreCondReq_accesses::total 89426 # number of StoreCondReq accesses(hits+misses) 2490system.cpu1.dcache.demand_accesses::cpu1.data 11064350 # number of demand (read+write) accesses 2491system.cpu1.dcache.demand_accesses::total 11064350 # number of demand (read+write) accesses 2492system.cpu1.dcache.overall_accesses::cpu1.data 11126967 # number of overall (read+write) accesses 2493system.cpu1.dcache.overall_accesses::total 11126967 # number of overall (read+write) accesses 2494system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029391 # miss rate for ReadReq accesses 2495system.cpu1.dcache.ReadReq_miss_rate::total 0.029391 # miss rate for ReadReq accesses 2496system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028749 # miss rate for WriteReq accesses 2497system.cpu1.dcache.WriteReq_miss_rate::total 0.028749 # miss rate for WriteReq accesses 2498system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.691937 # miss rate for SoftPFReq accesses 2499system.cpu1.dcache.SoftPFReq_miss_rate::total 0.691937 # miss rate for SoftPFReq accesses 2500system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135086 # miss rate for LoadLockedReq accesses 2501system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135086 # miss rate for LoadLockedReq accesses 2502system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.152897 # miss rate for StoreCondReq accesses 2503system.cpu1.dcache.StoreCondReq_miss_rate::total 0.152897 # miss rate for StoreCondReq accesses 2504system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029119 # miss rate for demand accesses 2505system.cpu1.dcache.demand_miss_rate::total 0.029119 # miss rate for demand accesses 2506system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032849 # miss rate for overall accesses 2507system.cpu1.dcache.overall_miss_rate::total 0.032849 # miss rate for overall accesses 2508system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency 2509system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency 2510system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency 2511system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency 2512system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966 # average LoadLockedReq miss latency 2513system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency 2514system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987 # average StoreCondReq miss latency 2515system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency | 2478system.cpu1.dcache.tags.replacements 218932 # number of replacements 2479system.cpu1.dcache.tags.tagsinuse 479.958616 # Cycle average of tags in use 2480system.cpu1.dcache.tags.total_refs 8645395 # Total number of references to valid blocks. 2481system.cpu1.dcache.tags.sampled_refs 219287 # Sample count of references to valid blocks. 2482system.cpu1.dcache.tags.avg_refs 39.425023 # Average number of references to valid blocks. 2483system.cpu1.dcache.tags.warmup_cycle 104115576500 # Cycle when the warmup percentage was hit. 2484system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.958616 # Average occupied blocks per requestor 2485system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937419 # Average percentage of cache occupancy 2486system.cpu1.dcache.tags.occ_percent::total 0.937419 # Average percentage of cache occupancy 2487system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 2488system.cpu1.dcache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id 2489system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id 2490system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id 2491system.cpu1.dcache.tags.tag_accesses 18161929 # Number of tag accesses 2492system.cpu1.dcache.tags.data_accesses 18161929 # Number of data accesses 2493system.cpu1.dcache.ReadReq_hits::cpu1.data 4463105 # number of ReadReq hits 2494system.cpu1.dcache.ReadReq_hits::total 4463105 # number of ReadReq hits 2495system.cpu1.dcache.WriteReq_hits::cpu1.data 3919326 # number of WriteReq hits 2496system.cpu1.dcache.WriteReq_hits::total 3919326 # number of WriteReq hits 2497system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64192 # number of SoftPFReq hits 2498system.cpu1.dcache.SoftPFReq_hits::total 64192 # number of SoftPFReq hits 2499system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87200 # number of LoadLockedReq hits 2500system.cpu1.dcache.LoadLockedReq_hits::total 87200 # number of LoadLockedReq hits 2501system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79632 # number of StoreCondReq hits 2502system.cpu1.dcache.StoreCondReq_hits::total 79632 # number of StoreCondReq hits 2503system.cpu1.dcache.demand_hits::cpu1.data 8382431 # number of demand (read+write) hits 2504system.cpu1.dcache.demand_hits::total 8382431 # number of demand (read+write) hits 2505system.cpu1.dcache.overall_hits::cpu1.data 8446623 # number of overall hits 2506system.cpu1.dcache.overall_hits::total 8446623 # number of overall hits 2507system.cpu1.dcache.ReadReq_misses::cpu1.data 155171 # number of ReadReq misses 2508system.cpu1.dcache.ReadReq_misses::total 155171 # number of ReadReq misses 2509system.cpu1.dcache.WriteReq_misses::cpu1.data 103752 # number of WriteReq misses 2510system.cpu1.dcache.WriteReq_misses::total 103752 # number of WriteReq misses 2511system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34196 # number of SoftPFReq misses 2512system.cpu1.dcache.SoftPFReq_misses::total 34196 # number of SoftPFReq misses 2513system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17931 # number of LoadLockedReq misses 2514system.cpu1.dcache.LoadLockedReq_misses::total 17931 # number of LoadLockedReq misses 2515system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23276 # number of StoreCondReq misses 2516system.cpu1.dcache.StoreCondReq_misses::total 23276 # number of StoreCondReq misses 2517system.cpu1.dcache.demand_misses::cpu1.data 258923 # number of demand (read+write) misses 2518system.cpu1.dcache.demand_misses::total 258923 # number of demand (read+write) misses 2519system.cpu1.dcache.overall_misses::cpu1.data 293119 # number of overall misses 2520system.cpu1.dcache.overall_misses::total 293119 # number of overall misses 2521system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220270266 # number of ReadReq miss cycles 2522system.cpu1.dcache.ReadReq_miss_latency::total 2220270266 # number of ReadReq miss cycles 2523system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2272762314 # number of WriteReq miss cycles 2524system.cpu1.dcache.WriteReq_miss_latency::total 2272762314 # number of WriteReq miss cycles 2525system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325809000 # number of LoadLockedReq miss cycles 2526system.cpu1.dcache.LoadLockedReq_miss_latency::total 325809000 # number of LoadLockedReq miss cycles 2527system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538454705 # number of StoreCondReq miss cycles 2528system.cpu1.dcache.StoreCondReq_miss_latency::total 538454705 # number of StoreCondReq miss cycles 2529system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1810500 # number of StoreCondFailReq miss cycles 2530system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1810500 # number of StoreCondFailReq miss cycles 2531system.cpu1.dcache.demand_miss_latency::cpu1.data 4493032580 # number of demand (read+write) miss cycles 2532system.cpu1.dcache.demand_miss_latency::total 4493032580 # number of demand (read+write) miss cycles 2533system.cpu1.dcache.overall_miss_latency::cpu1.data 4493032580 # number of overall miss cycles 2534system.cpu1.dcache.overall_miss_latency::total 4493032580 # number of overall miss cycles 2535system.cpu1.dcache.ReadReq_accesses::cpu1.data 4618276 # number of ReadReq accesses(hits+misses) 2536system.cpu1.dcache.ReadReq_accesses::total 4618276 # number of ReadReq accesses(hits+misses) 2537system.cpu1.dcache.WriteReq_accesses::cpu1.data 4023078 # number of WriteReq accesses(hits+misses) 2538system.cpu1.dcache.WriteReq_accesses::total 4023078 # number of WriteReq accesses(hits+misses) 2539system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98388 # number of SoftPFReq accesses(hits+misses) 2540system.cpu1.dcache.SoftPFReq_accesses::total 98388 # number of SoftPFReq accesses(hits+misses) 2541system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105131 # number of LoadLockedReq accesses(hits+misses) 2542system.cpu1.dcache.LoadLockedReq_accesses::total 105131 # number of LoadLockedReq accesses(hits+misses) 2543system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102908 # number of StoreCondReq accesses(hits+misses) 2544system.cpu1.dcache.StoreCondReq_accesses::total 102908 # number of StoreCondReq accesses(hits+misses) 2545system.cpu1.dcache.demand_accesses::cpu1.data 8641354 # number of demand (read+write) accesses 2546system.cpu1.dcache.demand_accesses::total 8641354 # number of demand (read+write) accesses 2547system.cpu1.dcache.overall_accesses::cpu1.data 8739742 # number of overall (read+write) accesses 2548system.cpu1.dcache.overall_accesses::total 8739742 # number of overall (read+write) accesses 2549system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033599 # miss rate for ReadReq accesses 2550system.cpu1.dcache.ReadReq_miss_rate::total 0.033599 # miss rate for ReadReq accesses 2551system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025789 # miss rate for WriteReq accesses 2552system.cpu1.dcache.WriteReq_miss_rate::total 0.025789 # miss rate for WriteReq accesses 2553system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347563 # miss rate for SoftPFReq accesses 2554system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347563 # miss rate for SoftPFReq accesses 2555system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170559 # miss rate for LoadLockedReq accesses 2556system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170559 # miss rate for LoadLockedReq accesses 2557system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226183 # miss rate for StoreCondReq accesses 2558system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226183 # miss rate for StoreCondReq accesses 2559system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029963 # miss rate for demand accesses 2560system.cpu1.dcache.demand_miss_rate::total 0.029963 # miss rate for demand accesses 2561system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033539 # miss rate for overall accesses 2562system.cpu1.dcache.overall_miss_rate::total 0.033539 # miss rate for overall accesses 2563system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748 # average ReadReq miss latency 2564system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748 # average ReadReq miss latency 2565system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507 # average WriteReq miss latency 2566system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507 # average WriteReq miss latency 2567system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250 # average LoadLockedReq miss latency 2568system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250 # average LoadLockedReq miss latency 2569system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461 # average StoreCondReq miss latency 2570system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461 # average StoreCondReq miss latency |
| 2516system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2517system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2571system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2572system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2518system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency 2519system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency 2520system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency 2521system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency | 2573system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072 # average overall miss latency 2574system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072 # average overall miss latency 2575system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674 # average overall miss latency 2576system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674 # average overall miss latency |
| 2522system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2523system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2524system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2525system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2526system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2527system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2528system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2529system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2577system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2578system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2579system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2580system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 2581system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2582system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2583system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2584system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2530system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks 2531system.cpu1.dcache.writebacks::total 225255 # number of writebacks 2532system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits 2533system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits 2534system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits 2535system.cpu1.dcache.WriteReq_mshr_hits::total 3242 # number of WriteReq MSHR hits 2536system.cpu1.dcache.demand_mshr_hits::cpu1.data 4036 # number of demand (read+write) MSHR hits 2537system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits 2538system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits 2539system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits 2540system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 186449 # number of ReadReq MSHR misses 2541system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses 2542system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 131695 # number of WriteReq MSHR misses 2543system.cpu1.dcache.WriteReq_mshr_misses::total 131695 # number of WriteReq MSHR misses 2544system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 27821 # number of SoftPFReq MSHR misses 2545system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses 2546system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses 2547system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12089 # number of LoadLockedReq MSHR misses 2548system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses 2549system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses 2550system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses 2551system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses 2552system.cpu1.dcache.overall_mshr_misses::cpu1.data 345965 # number of overall MSHR misses 2553system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses 2554system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles 2555system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1916001744 # number of ReadReq MSHR miss cycles 2556system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles 2557system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2027549872 # number of WriteReq MSHR miss cycles 2558system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 596503999 # number of SoftPFReq MSHR miss cycles 2559system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 596503999 # number of SoftPFReq MSHR miss cycles 2560system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles 2561system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles 2562system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 289002030 # number of StoreCondReq MSHR miss cycles 2563system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 289002030 # number of StoreCondReq MSHR miss cycles 2564system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 494000 # number of StoreCondFailReq MSHR miss cycles 2565system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 494000 # number of StoreCondFailReq MSHR miss cycles 2566system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles 2567system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles 2568system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles 2569system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles 2570system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles 2571system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles 2572system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles 2573system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles 2574system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 47062844087 # number of overall MSHR uncacheable cycles 2575system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles 2576system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses 2577system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses 2578system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses 2579system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028058 # mshr miss rate for WriteReq accesses 2580system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses 2581system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses 2582system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses 2583system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses 2584system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.152875 # mshr miss rate for StoreCondReq accesses 2585system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses 2586system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028754 # mshr miss rate for demand accesses 2587system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses 2588system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses 2589system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses 2590system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency 2591system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency 2592system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency 2593system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency 2594system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency 2595system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency 2596system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency 2597system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency 2598system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency 2599system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency | 2585system.cpu1.dcache.writebacks::writebacks 134926 # number of writebacks 2586system.cpu1.dcache.writebacks::total 134926 # number of writebacks 2587system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits 2588system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits 2589system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12328 # number of LoadLockedReq MSHR hits 2590system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12328 # number of LoadLockedReq MSHR hits 2591system.cpu1.dcache.demand_mshr_hits::cpu1.data 299 # number of demand (read+write) MSHR hits 2592system.cpu1.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits 2593system.cpu1.dcache.overall_mshr_hits::cpu1.data 299 # number of overall MSHR hits 2594system.cpu1.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits 2595system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154872 # number of ReadReq MSHR misses 2596system.cpu1.dcache.ReadReq_mshr_misses::total 154872 # number of ReadReq MSHR misses 2597system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103752 # number of WriteReq MSHR misses 2598system.cpu1.dcache.WriteReq_mshr_misses::total 103752 # number of WriteReq MSHR misses 2599system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33057 # number of SoftPFReq MSHR misses 2600system.cpu1.dcache.SoftPFReq_mshr_misses::total 33057 # number of SoftPFReq MSHR misses 2601system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5603 # number of LoadLockedReq MSHR misses 2602system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5603 # number of LoadLockedReq MSHR misses 2603system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23226 # number of StoreCondReq MSHR misses 2604system.cpu1.dcache.StoreCondReq_mshr_misses::total 23226 # number of StoreCondReq MSHR misses 2605system.cpu1.dcache.demand_mshr_misses::cpu1.data 258624 # number of demand (read+write) MSHR misses 2606system.cpu1.dcache.demand_mshr_misses::total 258624 # number of demand (read+write) MSHR misses 2607system.cpu1.dcache.overall_mshr_misses::cpu1.data 291681 # number of overall MSHR misses 2608system.cpu1.dcache.overall_mshr_misses::total 291681 # number of overall MSHR misses 2609system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901749734 # number of ReadReq MSHR miss cycles 2610system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901749734 # number of ReadReq MSHR miss cycles 2611system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2059007686 # number of WriteReq MSHR miss cycles 2612system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2059007686 # number of WriteReq MSHR miss cycles 2613system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496678249 # number of SoftPFReq MSHR miss cycles 2614system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496678249 # number of SoftPFReq MSHR miss cycles 2615system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84335500 # number of LoadLockedReq MSHR miss cycles 2616system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84335500 # number of LoadLockedReq MSHR miss cycles 2617system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490783295 # number of StoreCondReq MSHR miss cycles 2618system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490783295 # number of StoreCondReq MSHR miss cycles 2619system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1734500 # number of StoreCondFailReq MSHR miss cycles 2620system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1734500 # number of StoreCondFailReq MSHR miss cycles 2621system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3960757420 # number of demand (read+write) MSHR miss cycles 2622system.cpu1.dcache.demand_mshr_miss_latency::total 3960757420 # number of demand (read+write) MSHR miss cycles 2623system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4457435669 # number of overall MSHR miss cycles 2624system.cpu1.dcache.overall_mshr_miss_latency::total 4457435669 # number of overall MSHR miss cycles 2625system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961034499 # number of ReadReq MSHR uncacheable cycles 2626system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961034499 # number of ReadReq MSHR uncacheable cycles 2627system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382499 # number of WriteReq MSHR uncacheable cycles 2628system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382499 # number of WriteReq MSHR uncacheable cycles 2629system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794416998 # number of overall MSHR uncacheable cycles 2630system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794416998 # number of overall MSHR uncacheable cycles 2631system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033535 # mshr miss rate for ReadReq accesses 2632system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033535 # mshr miss rate for ReadReq accesses 2633system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025789 # mshr miss rate for WriteReq accesses 2634system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025789 # mshr miss rate for WriteReq accesses 2635system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335986 # mshr miss rate for SoftPFReq accesses 2636system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335986 # mshr miss rate for SoftPFReq accesses 2637system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053295 # mshr miss rate for LoadLockedReq accesses 2638system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053295 # mshr miss rate for LoadLockedReq accesses 2639system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225697 # mshr miss rate for StoreCondReq accesses 2640system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225697 # mshr miss rate for StoreCondReq accesses 2641system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029929 # mshr miss rate for demand accesses 2642system.cpu1.dcache.demand_mshr_miss_rate::total 0.029929 # mshr miss rate for demand accesses 2643system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033374 # mshr miss rate for overall accesses 2644system.cpu1.dcache.overall_mshr_miss_rate::total 0.033374 # mshr miss rate for overall accesses 2645system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608 # average ReadReq mshr miss latency 2646system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608 # average ReadReq mshr miss latency 2647system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651 # average WriteReq mshr miss latency 2648system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651 # average WriteReq mshr miss latency 2649system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924 # average SoftPFReq mshr miss latency 2650system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924 # average SoftPFReq mshr miss latency 2651system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225 # average LoadLockedReq mshr miss latency 2652system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225 # average LoadLockedReq mshr miss latency 2653system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334 # average StoreCondReq mshr miss latency 2654system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334 # average StoreCondReq mshr miss latency |
| 2600system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2601system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2655system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2656system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2602system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency 2603system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency 2604system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency 2605system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency | 2657system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662 # average overall mshr miss latency 2658system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662 # average overall mshr miss latency 2659system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584 # average overall mshr miss latency 2660system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584 # average overall mshr miss latency |
| 2606system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2607system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2608system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2609system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2610system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2611system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2612system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2661system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2662system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2663system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2664system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2665system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2666system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2667system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2613system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution 2614system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution 2615system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution 2616system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution 2617system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution 2618system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution 2619system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution 2620system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution 2621system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution 2622system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution 2623system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution 2624system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution 2625system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution 2626system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes) 2627system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes) 2628system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes) 2629system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes) 2630system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes) 2631system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes) 2632system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes) 2633system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes) 2634system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes) 2635system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes) 2636system.cpu1.toL2Bus.snoops 549743 # Total snoops (count) 2637system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram 2638system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram 2639system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram | 2668system.cpu1.toL2Bus.trans_dist::ReadReq 1206103 # Transaction distribution 2669system.cpu1.toL2Bus.trans_dist::ReadResp 816776 # Transaction distribution 2670system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution 2671system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution 2672system.cpu1.toL2Bus.trans_dist::Writeback 134926 # Transaction distribution 2673system.cpu1.toL2Bus.trans_dist::HardPFReq 169865 # Transaction distribution 2674system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 2675system.cpu1.toL2Bus.trans_dist::UpgradeReq 86284 # Transaction distribution 2676system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42512 # Transaction distribution 2677system.cpu1.toL2Bus.trans_dist::UpgradeResp 89712 # Transaction distribution 2678system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution 2679system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution 2680system.cpu1.toL2Bus.trans_dist::ReadExReq 91056 # Transaction distribution 2681system.cpu1.toL2Bus.trans_dist::ReadExResp 78188 # Transaction distribution 2682system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131848 # Packet count per connected master and slave (bytes) 2683system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880488 # Packet count per connected master and slave (bytes) 2684system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes) 2685system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9281 # Packet count per connected master and slave (bytes) 2686system.cpu1.toL2Bus.pkt_count::total 2026923 # Packet count per connected master and slave (bytes) 2687system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36208456 # Cumulative packet size per connected master and slave (bytes) 2688system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28775795 # Cumulative packet size per connected master and slave (bytes) 2689system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes) 2690system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13440 # Cumulative packet size per connected master and slave (bytes) 2691system.cpu1.toL2Bus.pkt_size::total 65005615 # Cumulative packet size per connected master and slave (bytes) 2692system.cpu1.toL2Bus.snoops 818131 # Total snoops (count) 2693system.cpu1.toL2Bus.snoop_fanout::samples 1761210 # Request fanout histogram 2694system.cpu1.toL2Bus.snoop_fanout::mean 5.414931 # Request fanout histogram 2695system.cpu1.toL2Bus.snoop_fanout::stdev 0.492710 # Request fanout histogram |
| 2640system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2641system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2642system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2643system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2644system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2645system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 2696system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2697system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2698system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2699system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2700system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2701system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 2646system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram 2647system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram | 2702system.cpu1.toL2Bus.snoop_fanout::5 1030430 58.51% 58.51% # Request fanout histogram 2703system.cpu1.toL2Bus.snoop_fanout::6 730780 41.49% 100.00% # Request fanout histogram |
| 2648system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2649system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2650system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 2704system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2705system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2706system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 2651system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram 2652system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks) 2653system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2654system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks) | 2707system.cpu1.toL2Bus.snoop_fanout::total 1761210 # Request fanout histogram 2708system.cpu1.toL2Bus.reqLayer0.occupancy 658102724 # Layer occupancy (ticks) 2709system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2710system.cpu1.toL2Bus.snoopLayer0.occupancy 89600499 # Layer occupancy (ticks) |
| 2655system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2711system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2656system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks) | 2712system.cpu1.toL2Bus.respLayer0.occupancy 848922781 # Layer occupancy (ticks) |
| 2657system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2713system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2658system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks) | 2714system.cpu1.toL2Bus.respLayer1.occupancy 438669538 # Layer occupancy (ticks) |
| 2659system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2715system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2660system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks) | 2716system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks) |
| 2661system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2717system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2662system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks) | 2718system.cpu1.toL2Bus.respLayer3.occupancy 5921500 # Layer occupancy (ticks) |
| 2663system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2719system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2664system.iocache.tags.replacements 0 # number of replacements 2665system.iocache.tags.tagsinuse 0 # Cycle average of tags in use | 2720system.iocache.tags.replacements 36443 # number of replacements 2721system.iocache.tags.tagsinuse 14.446814 # Cycle average of tags in use |
| 2666system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 2722system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 2667system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2668system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2669system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2670system.iocache.tags.tag_accesses 0 # Number of tag accesses 2671system.iocache.tags.data_accesses 0 # Number of data accesses | 2723system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks. 2724system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2725system.iocache.tags.warmup_cycle 277160524000 # Cycle when the warmup percentage was hit. 2726system.iocache.tags.occ_blocks::realview.ide 14.446814 # Average occupied blocks per requestor 2727system.iocache.tags.occ_percent::realview.ide 0.902926 # Average percentage of cache occupancy 2728system.iocache.tags.occ_percent::total 0.902926 # Average percentage of cache occupancy 2729system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2730system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2731system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2732system.iocache.tags.tag_accesses 328549 # Number of tag accesses 2733system.iocache.tags.data_accesses 328549 # Number of data accesses 2734system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 2735system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 2736system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses 2737system.iocache.ReadReq_misses::total 253 # number of ReadReq misses 2738system.iocache.WriteInvalidateReq_misses::realview.ide 32 # number of WriteInvalidateReq misses 2739system.iocache.WriteInvalidateReq_misses::total 32 # number of WriteInvalidateReq misses 2740system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses 2741system.iocache.demand_misses::total 253 # number of demand (read+write) misses 2742system.iocache.overall_misses::realview.ide 253 # number of overall misses 2743system.iocache.overall_misses::total 253 # number of overall misses 2744system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles 2745system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles 2746system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles 2747system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles 2748system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles 2749system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles 2750system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) 2751system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) 2752system.iocache.WriteInvalidateReq_accesses::realview.ide 36256 # number of WriteInvalidateReq accesses(hits+misses) 2753system.iocache.WriteInvalidateReq_accesses::total 36256 # number of WriteInvalidateReq accesses(hits+misses) 2754system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses 2755system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses 2756system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses 2757system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses 2758system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2759system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2760system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000883 # miss rate for WriteInvalidateReq accesses 2761system.iocache.WriteInvalidateReq_miss_rate::total 0.000883 # miss rate for WriteInvalidateReq accesses 2762system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2763system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2764system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2765system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2766system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency 2767system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency 2768system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2769system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency 2770system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency 2771system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency |
| 2672system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2673system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2674system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2675system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2676system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2677system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2772system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2773system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2774system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2775system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2776system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2777system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2678system.iocache.fast_writes 0 # number of fast writes performed | 2778system.iocache.fast_writes 36224 # number of fast writes performed |
| 2679system.iocache.cache_copies 0 # number of cache copies performed | 2779system.iocache.cache_copies 0 # number of cache copies performed |
| 2680system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles 2681system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles 2682system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles 2683system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles 2684system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2685system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2686system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2687system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2780system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses 2781system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses 2782system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses 2783system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses 2784system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses 2785system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses 2786system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles 2787system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles 2788system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2247085536 # number of WriteInvalidateReq MSHR miss cycles 2789system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2247085536 # number of WriteInvalidateReq MSHR miss cycles 2790system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles 2791system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles 2792system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles 2793system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles 2794system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2795system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2796system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2797system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2798system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2799system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2800system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency 2801system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency 2802system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 2803system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 2804system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2805system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency 2806system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency 2807system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency |
| 2688system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2689 2690---------- End Simulation Statistics ---------- | 2808system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2809 2810---------- End Simulation Statistics ---------- |