| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.194312 # Number of seconds simulated 4sim_ticks 1194312178000 # Number of ticks simulated 5final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.675181 # Number of seconds simulated 4sim_ticks 2675180779000 # Number of ticks simulated 5final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 475403 # Simulator instruction rate (inst/s) 8host_op_rate 567868 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9241250441 # Simulator tick rate (ticks/s) 10host_mem_usage 438040 # Number of bytes of host memory used 11host_seconds 129.24 # Real time elapsed on the host 12sim_insts 61439698 # Number of instructions simulated 13sim_ops 73389630 # Number of ops (including micro ops) simulated | 7host_inst_rate 485184 # Simulator instruction rate (inst/s) 8host_op_rate 579312 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20736099933 # Simulator tick rate (ticks/s) 10host_mem_usage 486856 # Number of bytes of host memory used 11host_seconds 129.01 # Real time elapsed on the host 12sim_insts 62593972 # Number of instructions simulated 13sim_ops 74737529 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory 25system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory | 16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 120908 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 513788 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu0.l2cache.prefetcher 6659968 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.inst 37828 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.data 531832 # Number of bytes read from this memory 43system.physmem.bytes_read::cpu1.l2cache.prefetcher 3262144 # Number of bytes read from this memory 44system.physmem.bytes_read::total 135383236 # Number of bytes read from this memory 45system.physmem.bytes_inst_read::cpu0.inst 120908 # Number of instructions bytes read from this memory 46system.physmem.bytes_inst_read::cpu1.inst 37828 # Number of instructions bytes read from this memory 47system.physmem.bytes_inst_read::total 158736 # Number of instructions bytes read from this memory 48system.physmem.bytes_written::writebacks 4300032 # Number of bytes written to this memory |
| 30system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory | 49system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 32system.physmem.bytes_written::total 7124560 # Number of bytes written to this memory 33system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 12383 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 73653 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 5145 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 74957 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 6654210 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 64019 # Number of write requests responded to by this memory | 50system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory 51system.physmem.bytes_written::total 7329168 # Number of bytes written to this memory 52system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.inst 8117 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu0.data 8087 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu0.l2cache.prefetcher 104062 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu1.inst 682 # Number of read requests responded to by this memory 60system.physmem.num_reads::cpu1.data 8328 # Number of read requests responded to by this memory 61system.physmem.num_reads::cpu1.l2cache.prefetcher 50971 # Number of read requests responded to by this memory 62system.physmem.num_reads::total 15712287 # Number of read requests responded to by this memory 63system.physmem.num_writes::writebacks 67188 # Number of write requests responded to by this memory |
| 44system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory | 64system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory |
| 45system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory 47system.physmem.bw_read::realview.clcd 43459753 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 329840 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.inst 270834 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.data 4015774 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 270834 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 3430607 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.clcd 43459753 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 329840 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 3957937 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 270834 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.data 6536341 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 6654210 # Number of read requests accepted 76system.physmem.writeReqs 820855 # Number of write requests accepted 77system.physmem.readBursts 6654210 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue 81system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 62128516 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 415236 # Per bank write bursts 88system.physmem.perBankRdBursts::1 415218 # Per bank write bursts 89system.physmem.perBankRdBursts::2 415240 # Per bank write bursts 90system.physmem.perBankRdBursts::3 415658 # Per bank write bursts 91system.physmem.perBankRdBursts::4 422402 # Per bank write bursts 92system.physmem.perBankRdBursts::5 415506 # Per bank write bursts 93system.physmem.perBankRdBursts::6 415779 # Per bank write bursts 94system.physmem.perBankRdBursts::7 415682 # Per bank write bursts 95system.physmem.perBankRdBursts::8 416047 # Per bank write bursts 96system.physmem.perBankRdBursts::9 415577 # Per bank write bursts 97system.physmem.perBankRdBursts::10 415398 # Per bank write bursts 98system.physmem.perBankRdBursts::11 414862 # Per bank write bursts 99system.physmem.perBankRdBursts::12 415007 # Per bank write bursts 100system.physmem.perBankRdBursts::13 415552 # Per bank write bursts 101system.physmem.perBankRdBursts::14 415496 # Per bank write bursts 102system.physmem.perBankRdBursts::15 415066 # Per bank write bursts 103system.physmem.perBankWrBursts::0 6763 # Per bank write bursts 104system.physmem.perBankWrBursts::1 6728 # Per bank write bursts 105system.physmem.perBankWrBursts::2 6819 # Per bank write bursts 106system.physmem.perBankWrBursts::3 7055 # Per bank write bursts 107system.physmem.perBankWrBursts::4 7301 # Per bank write bursts 108system.physmem.perBankWrBursts::5 7028 # Per bank write bursts 109system.physmem.perBankWrBursts::6 7316 # Per bank write bursts 110system.physmem.perBankWrBursts::7 7231 # Per bank write bursts 111system.physmem.perBankWrBursts::8 7485 # Per bank write bursts 112system.physmem.perBankWrBursts::9 7107 # Per bank write bursts 113system.physmem.perBankWrBursts::10 7000 # Per bank write bursts 114system.physmem.perBankWrBursts::11 6549 # Per bank write bursts 115system.physmem.perBankWrBursts::12 6696 # Per bank write bursts 116system.physmem.perBankWrBursts::13 6902 # Per bank write bursts 117system.physmem.perBankWrBursts::14 6960 # Per bank write bursts 118system.physmem.perBankWrBursts::15 6567 # Per bank write bursts | 65system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory 66system.physmem.num_writes::total 824472 # Number of write requests responded to by this memory 67system.physmem.bw_read::realview.clcd 46447798 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu0.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.itb.walker 96 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu0.inst 45196 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu0.data 192057 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu0.l2cache.prefetcher 2489539 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu1.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::cpu1.inst 14140 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_read::cpu1.data 198802 # Total read bandwidth from this memory (bytes/s) 76system.physmem.bw_read::cpu1.l2cache.prefetcher 1219411 # Total read bandwidth from this memory (bytes/s) 77system.physmem.bw_read::total 50607135 # Total read bandwidth from this memory (bytes/s) 78system.physmem.bw_inst_read::cpu0.inst 45196 # Instruction read bandwidth from this memory (bytes/s) 79system.physmem.bw_inst_read::cpu1.inst 14140 # Instruction read bandwidth from this memory (bytes/s) 80system.physmem.bw_inst_read::total 59337 # Instruction read bandwidth from this memory (bytes/s) 81system.physmem.bw_write::writebacks 1607380 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_write::cpu0.data 6355 # Write bandwidth from this memory (bytes/s) 83system.physmem.bw_write::cpu1.data 1125956 # Write bandwidth from this memory (bytes/s) 84system.physmem.bw_write::total 2739691 # Write bandwidth from this memory (bytes/s) 85system.physmem.bw_total::writebacks 1607380 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::realview.clcd 46447798 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu0.itb.walker 96 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu0.inst 45196 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu0.data 198412 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::cpu0.l2cache.prefetcher 2489539 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::cpu1.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.bw_total::cpu1.inst 14140 # Total bandwidth to/from this memory (bytes/s) 94system.physmem.bw_total::cpu1.data 1324758 # Total bandwidth to/from this memory (bytes/s) 95system.physmem.bw_total::cpu1.l2cache.prefetcher 1219411 # Total bandwidth to/from this memory (bytes/s) 96system.physmem.bw_total::total 53346826 # Total bandwidth to/from this memory (bytes/s) 97system.physmem.readReqs 15712287 # Number of read requests accepted 98system.physmem.writeReqs 824472 # Number of write requests accepted 99system.physmem.readBursts 15712287 # Number of DRAM read bursts, including those serviced by the write queue 100system.physmem.writeBursts 824472 # Number of DRAM write bursts, including those merged in the write queue 101system.physmem.bytesReadDRAM 1005465984 # Total number of bytes read from DRAM 102system.physmem.bytesReadWrQ 120384 # Total number of bytes read from write queue 103system.physmem.bytesWritten 7344256 # Total number of bytes written to DRAM 104system.physmem.bytesReadSys 135383236 # Total read bytes from the system interface side 105system.physmem.bytesWrittenSys 7329168 # Total written bytes from the system interface side 106system.physmem.servicedByWrQ 1881 # Number of DRAM read bursts serviced by the write queue 107system.physmem.mergedWrBursts 709695 # Number of DRAM write bursts merged with an existing one 108system.physmem.neitherReadNorWriteReqs 15472 # Number of requests that are neither read nor write 109system.physmem.perBankRdBursts::0 981539 # Per bank write bursts 110system.physmem.perBankRdBursts::1 981448 # Per bank write bursts 111system.physmem.perBankRdBursts::2 981211 # Per bank write bursts 112system.physmem.perBankRdBursts::3 981521 # Per bank write bursts 113system.physmem.perBankRdBursts::4 988300 # Per bank write bursts 114system.physmem.perBankRdBursts::5 981533 # Per bank write bursts 115system.physmem.perBankRdBursts::6 981210 # Per bank write bursts 116system.physmem.perBankRdBursts::7 981071 # Per bank write bursts 117system.physmem.perBankRdBursts::8 981831 # Per bank write bursts 118system.physmem.perBankRdBursts::9 982015 # Per bank write bursts 119system.physmem.perBankRdBursts::10 981421 # Per bank write bursts 120system.physmem.perBankRdBursts::11 980878 # Per bank write bursts 121system.physmem.perBankRdBursts::12 981926 # Per bank write bursts 122system.physmem.perBankRdBursts::13 981948 # Per bank write bursts 123system.physmem.perBankRdBursts::14 981516 # Per bank write bursts 124system.physmem.perBankRdBursts::15 981038 # Per bank write bursts 125system.physmem.perBankWrBursts::0 7155 # Per bank write bursts 126system.physmem.perBankWrBursts::1 7293 # Per bank write bursts 127system.physmem.perBankWrBursts::2 6957 # Per bank write bursts 128system.physmem.perBankWrBursts::3 6994 # Per bank write bursts 129system.physmem.perBankWrBursts::4 7537 # Per bank write bursts 130system.physmem.perBankWrBursts::5 7187 # Per bank write bursts 131system.physmem.perBankWrBursts::6 7207 # Per bank write bursts 132system.physmem.perBankWrBursts::7 7058 # Per bank write bursts 133system.physmem.perBankWrBursts::8 7329 # Per bank write bursts 134system.physmem.perBankWrBursts::9 7596 # Per bank write bursts 135system.physmem.perBankWrBursts::10 7177 # Per bank write bursts 136system.physmem.perBankWrBursts::11 6681 # Per bank write bursts 137system.physmem.perBankWrBursts::12 7505 # Per bank write bursts 138system.physmem.perBankWrBursts::13 7329 # Per bank write bursts 139system.physmem.perBankWrBursts::14 7034 # Per bank write bursts 140system.physmem.perBankWrBursts::15 6715 # Per bank write bursts |
| 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 120system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 141system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 142system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 121system.physmem.totGap 1194307723500 # Total gap between requests | 143system.physmem.totGap 2675178052500 # Total gap between requests |
| 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 6799 # Read request sizes (log2) | 144system.physmem.readPktSize::0 0 # Read request sizes (log2) 145system.physmem.readPktSize::1 0 # Read request sizes (log2) 146system.physmem.readPktSize::2 6799 # Read request sizes (log2) |
| 125system.physmem.readPktSize::3 6488089 # Read request sizes (log2) | 147system.physmem.readPktSize::3 15532057 # Read request sizes (log2) |
| 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) | 148system.physmem.readPktSize::4 0 # Read request sizes (log2) 149system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 128system.physmem.readPktSize::6 159322 # Read request sizes (log2) | 150system.physmem.readPktSize::6 173431 # Read request sizes (log2) |
| 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) | 151system.physmem.writePktSize::0 0 # Write request sizes (log2) 152system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| 131system.physmem.writePktSize::2 756836 # Write request sizes (log2) | 153system.physmem.writePktSize::2 757284 # Write request sizes (log2) |
| 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) | 154system.physmem.writePktSize::3 0 # Write request sizes (log2) 155system.physmem.writePktSize::4 0 # Write request sizes (log2) 156system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 135system.physmem.writePktSize::6 64019 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 572550 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 410650 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 412558 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 460055 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 417389 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 445707 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 1151151 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 1116358 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 1442650 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 62467 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 48974 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 44870 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 43130 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 8689 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 8270 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 8147 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see | 157system.physmem.writePktSize::6 67188 # Write request sizes (log2) 158system.physmem.rdQLenPdf::0 1100287 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::1 996591 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::2 996926 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::3 1111424 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::4 1006011 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::5 1072049 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::6 2766642 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::7 2669294 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::8 3474563 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::9 133275 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::10 114946 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::11 106575 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::12 103058 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::13 20020 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::14 19187 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::15 18941 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::17 126 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::18 60 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::21 35 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::22 28 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::23 23 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see |
| 165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 187system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 190system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::15 3883 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 3903 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 6480 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 6485 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 6491 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 6485 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 6483 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 6485 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 6483 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 6486 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 6495 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 6488 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 6484 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 6484 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 6481 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see | 205system.physmem.wrQLenPdf::15 4098 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::16 4127 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::17 4820 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::18 5767 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::19 6235 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::20 6391 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::22 6628 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::23 6692 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::24 6804 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::25 6950 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::26 7066 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::27 7169 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::28 7372 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::29 7024 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::30 7083 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::34 52 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see |
| 224system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 246system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 247system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 248system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 249system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 250system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 251system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 252system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 253system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 232system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 5869 1.24% 11.08% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 17.176618 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16 2581 39.82% 39.82% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads 267system.physmem.totQLat 170730095750 # Total ticks spent queuing 268system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 33268630000 # Total ticks spent in databus transfers 270system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst | 254system.physmem.bytesPerActivate::samples 1051606 # Bytes accessed per row activation 255system.physmem.bytesPerActivate::mean 963.108084 # Bytes accessed per row activation 256system.physmem.bytesPerActivate::gmean 883.927529 # Bytes accessed per row activation 257system.physmem.bytesPerActivate::stdev 220.726845 # Bytes accessed per row activation 258system.physmem.bytesPerActivate::0-127 33004 3.14% 3.14% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::128-255 22001 2.09% 5.23% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::256-383 9307 0.89% 6.12% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::384-511 2514 0.24% 6.35% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::512-639 3272 0.31% 6.67% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::640-767 2167 0.21% 6.87% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::768-895 8722 0.83% 7.70% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::896-1023 1051 0.10% 7.80% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::1024-1151 969568 92.20% 100.00% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::total 1051606 # Bytes accessed per row activation 268system.physmem.rdPerTurnAround::samples 6601 # Reads before turning the bus around for writes 269system.physmem.rdPerTurnAround::mean 2380.003939 # Reads before turning the bus around for writes 270system.physmem.rdPerTurnAround::stdev 98592.588392 # Reads before turning the bus around for writes 271system.physmem.rdPerTurnAround::0-262143 6595 99.91% 99.91% # Reads before turning the bus around for writes 272system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes 273system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 274system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes 275system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 276system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 277system.physmem.rdPerTurnAround::total 6601 # Reads before turning the bus around for writes 278system.physmem.wrPerTurnAround::samples 6601 # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::mean 17.384336 # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::gmean 17.341066 # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::stdev 1.250693 # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::16 2463 37.31% 37.31% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::17 32 0.48% 37.80% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::18 3686 55.84% 93.64% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::19 215 3.26% 96.89% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::20 85 1.29% 98.18% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::21 50 0.76% 98.94% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::22 28 0.42% 99.36% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::24 14 0.21% 99.85% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::25 7 0.11% 99.95% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::total 6601 # Writes before turning the bus around for reads 294system.physmem.totQLat 408788863752 # Total ticks spent queuing 295system.physmem.totMemAccLat 703358976252 # Total ticks spent from burst creation until serviced by the DRAM 296system.physmem.totBusLat 78552030000 # Total ticks spent in databus transfers 297system.physmem.avgQLat 26020.26 # Average queueing delay per DRAM burst |
| 271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 298system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 272system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst 273system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s 274system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s 275system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s 276system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s | 299system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst 300system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s 301system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s 302system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s 303system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s |
| 277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 304system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 278system.physmem.busUtil 2.83 # Data bus utilization in percentage 279system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads 280system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 281system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing 282system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing 283system.physmem.readRowHits 6199598 # Number of row buffer hits during reads 284system.physmem.writeRowHits 92343 # Number of row buffer hits during writes 285system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads 286system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes 287system.physmem.avgGap 159772.22 # Average gap between requests 288system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined 289system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states 290system.physmem.memoryStateTime::REF 39880620000 # Time in different power states | 305system.physmem.busUtil 2.96 # Data bus utilization in percentage 306system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads 307system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 308system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing 309system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing 310system.physmem.readRowHits 14689438 # Number of row buffer hits during reads 311system.physmem.writeRowHits 84116 # Number of row buffer hits during writes 312system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads 313system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes 314system.physmem.avgGap 161771.61 # Average gap between requests 315system.physmem.pageHitRate 93.35 # Row buffer hit rate, read and write combined 316system.physmem.memoryStateTime::IDLE 2326940534750 # Time in different power states 317system.physmem.memoryStateTime::REF 89330020000 # Time in different power states |
| 291system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 318system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 292system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states | 319system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states |
| 293system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 320system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 294system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 295system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 296system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 297system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 298system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 299system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 300system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 301system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 302system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 303system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 304system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 305system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 306system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 307system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 308system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 309system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 310system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 311system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 312system.membus.throughput 60005732 # Throughput (bytes/s) 313system.membus.trans_dist::ReadReq 7703348 # Transaction distribution 314system.membus.trans_dist::ReadResp 7703348 # Transaction distribution 315system.membus.trans_dist::WriteReq 767581 # Transaction distribution 316system.membus.trans_dist::WriteResp 767581 # Transaction distribution 317system.membus.trans_dist::Writeback 64019 # Transaction distribution 318system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution 319system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution 320system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution 321system.membus.trans_dist::ReadExReq 137481 # Transaction distribution 322system.membus.trans_dist::ReadExResp 137066 # Transaction distribution 323system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382642 # Packet count per connected master and slave (bytes) | 321system.membus.trans_dist::ReadReq 16891737 # Transaction distribution 322system.membus.trans_dist::ReadResp 16891737 # Transaction distribution 323system.membus.trans_dist::WriteReq 769090 # Transaction distribution 324system.membus.trans_dist::WriteResp 769090 # Transaction distribution 325system.membus.trans_dist::Writeback 67188 # Transaction distribution 326system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution 327system.membus.trans_dist::SCUpgradeReq 22757 # Transaction distribution 328system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution 329system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 330system.membus.trans_dist::ReadExReq 15580 # Transaction distribution 331system.membus.trans_dist::ReadExResp 8709 # Transaction distribution 332system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384390 # Packet count per connected master and slave (bytes) |
| 324system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 333system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 325system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10312 # Packet count per connected master and slave (bytes) | 334system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13404 # Packet count per connected master and slave (bytes) |
| 326system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) | 335system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) |
| 327system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971036 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes) 333system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes) 334system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 335system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20624 # Cumulative packet size per connected master and slave (bytes) 336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) 338system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes) 339system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes) 340system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 341system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes) 343system.membus.data_through_bus 71665577 # Total data (bytes) 344system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 345system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks) | 336system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.l2c.mem_side::total 4443432 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count::total 35507496 # Packet count per connected master and slave (bytes) 342system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392696 # Cumulative packet size per connected master and slave (bytes) 343system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 344system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26808 # Cumulative packet size per connected master and slave (bytes) 345system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4196 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18456148 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.l2c.mem_side::total 20879924 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) 350system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size::total 145136180 # Cumulative packet size per connected master and slave (bytes) 352system.membus.snoops 70292 # Total snoops (count) 353system.membus.snoop_fanout::samples 326383 # Request fanout histogram 354system.membus.snoop_fanout::mean 1 # Request fanout histogram 355system.membus.snoop_fanout::stdev 0 # Request fanout histogram 356system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 357system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 358system.membus.snoop_fanout::1 326383 100.00% 100.00% # Request fanout histogram 359system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 360system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 361system.membus.snoop_fanout::min_value 1 # Request fanout histogram 362system.membus.snoop_fanout::max_value 1 # Request fanout histogram 363system.membus.snoop_fanout::total 326383 # Request fanout histogram 364system.membus.reqLayer0.occupancy 1567209495 # Layer occupancy (ticks) |
| 346system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 347system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 348system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 365system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 366system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 367system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 349system.membus.reqLayer2.occupancy 9231500 # Layer occupancy (ticks) | 368system.membus.reqLayer2.occupancy 11789999 # Layer occupancy (ticks) |
| 350system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 351system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 352system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 369system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 370system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 371system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 353system.membus.reqLayer5.occupancy 778500 # Layer occupancy (ticks) | 372system.membus.reqLayer5.occupancy 2092500 # Layer occupancy (ticks) |
| 354system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 373system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 355system.membus.reqLayer6.occupancy 9212282000 # Layer occupancy (ticks) 356system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) 357system.membus.respLayer1.occupancy 5079172023 # Layer occupancy (ticks) 358system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 359system.membus.respLayer2.occupancy 16050388750 # Layer occupancy (ticks) 360system.membus.respLayer2.utilization 1.3 # Layer utilization (%) | 374system.membus.reqLayer6.occupancy 18080219999 # Layer occupancy (ticks) 375system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 376system.membus.respLayer1.occupancy 4994463970 # Layer occupancy (ticks) 377system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 378system.membus.respLayer2.occupancy 38410223885 # Layer occupancy (ticks) 379system.membus.respLayer2.utilization 1.4 # Layer utilization (%) |
| 361system.cpu_clk_domain.clock 500 # Clock period in ticks | 380system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 362system.l2c.tags.replacements 69203 # number of replacements 363system.l2c.tags.tagsinuse 52959.316379 # Cycle average of tags in use 364system.l2c.tags.total_refs 1672724 # Total number of references to valid blocks. 365system.l2c.tags.sampled_refs 134375 # Sample count of references to valid blocks. 366system.l2c.tags.avg_refs 12.448179 # Average number of references to valid blocks. | 381system.l2c.tags.replacements 91391 # number of replacements 382system.l2c.tags.tagsinuse 54779.294121 # Cycle average of tags in use 383system.l2c.tags.total_refs 364235 # Total number of references to valid blocks. 384system.l2c.tags.sampled_refs 156090 # Sample count of references to valid blocks. 385system.l2c.tags.avg_refs 2.333493 # Average number of references to valid blocks. |
| 367system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 386system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 368system.l2c.tags.occ_blocks::writebacks 40136.915421 # Average occupied blocks per requestor 369system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor 370system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor 371system.l2c.tags.occ_blocks::cpu0.inst 3716.167205 # Average occupied blocks per requestor 372system.l2c.tags.occ_blocks::cpu0.data 4233.542603 # Average occupied blocks per requestor 373system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.741623 # Average occupied blocks per requestor 374system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001622 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu1.inst 2809.362324 # Average occupied blocks per requestor 376system.l2c.tags.occ_blocks::cpu1.data 2060.583626 # Average occupied blocks per requestor 377system.l2c.tags.occ_percent::writebacks 0.612441 # Average percentage of cache occupancy 378system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 379system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 380system.l2c.tags.occ_percent::cpu0.inst 0.056704 # Average percentage of cache occupancy 381system.l2c.tags.occ_percent::cpu0.data 0.064599 # Average percentage of cache occupancy 382system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 383system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 384system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy 385system.l2c.tags.occ_percent::cpu1.data 0.031442 # Average percentage of cache occupancy 386system.l2c.tags.occ_percent::total 0.808095 # Average percentage of cache occupancy 387system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 388system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id | 387system.l2c.tags.occ_blocks::writebacks 8096.170170 # Average occupied blocks per requestor 388system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.060665 # Average occupied blocks per requestor 389system.l2c.tags.occ_blocks::cpu0.itb.walker 1.035962 # Average occupied blocks per requestor 390system.l2c.tags.occ_blocks::cpu0.inst 869.411373 # Average occupied blocks per requestor 391system.l2c.tags.occ_blocks::cpu0.data 1869.125081 # Average occupied blocks per requestor 392system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218 # Average occupied blocks per requestor 393system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.888363 # Average occupied blocks per requestor 394system.l2c.tags.occ_blocks::cpu1.inst 410.348906 # Average occupied blocks per requestor 395system.l2c.tags.occ_blocks::cpu1.data 3214.362362 # Average occupied blocks per requestor 396system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021 # Average occupied blocks per requestor 397system.l2c.tags.occ_percent::writebacks 0.123538 # Average percentage of cache occupancy 398system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy 399system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 400system.l2c.tags.occ_percent::cpu0.inst 0.013266 # Average percentage of cache occupancy 401system.l2c.tags.occ_percent::cpu0.data 0.028521 # Average percentage of cache occupancy 402system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.446737 # Average percentage of cache occupancy 403system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy 404system.l2c.tags.occ_percent::cpu1.inst 0.006261 # Average percentage of cache occupancy 405system.l2c.tags.occ_percent::cpu1.data 0.049047 # Average percentage of cache occupancy 406system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.168450 # Average percentage of cache occupancy 407system.l2c.tags.occ_percent::total 0.835866 # Average percentage of cache occupancy 408system.l2c.tags.occ_task_id_blocks::1022 51568 # Occupied blocks per task id 409system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 410system.l2c.tags.occ_task_id_blocks::1024 13123 # Occupied blocks per task id 411system.l2c.tags.age_task_id_blocks_1022::2 28 # Occupied blocks per task id 412system.l2c.tags.age_task_id_blocks_1022::3 4964 # Occupied blocks per task id 413system.l2c.tags.age_task_id_blocks_1022::4 46576 # Occupied blocks per task id |
| 389system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id | 414system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 390system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 391system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 392system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 393system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id 394system.l2c.tags.age_task_id_blocks_1024::3 8176 # Occupied blocks per task id 395system.l2c.tags.age_task_id_blocks_1024::4 55031 # Occupied blocks per task id 396system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 397system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id 398system.l2c.tags.tag_accesses 17204185 # Number of tag accesses 399system.l2c.tags.data_accesses 17204185 # Number of data accesses 400system.l2c.ReadReq_hits::cpu0.dtb.walker 3944 # number of ReadReq hits 401system.l2c.ReadReq_hits::cpu0.itb.walker 1786 # number of ReadReq hits 402system.l2c.ReadReq_hits::cpu0.inst 419390 # number of ReadReq hits 403system.l2c.ReadReq_hits::cpu0.data 205855 # number of ReadReq hits 404system.l2c.ReadReq_hits::cpu1.dtb.walker 5333 # number of ReadReq hits 405system.l2c.ReadReq_hits::cpu1.itb.walker 1846 # number of ReadReq hits 406system.l2c.ReadReq_hits::cpu1.inst 464270 # number of ReadReq hits 407system.l2c.ReadReq_hits::cpu1.data 143434 # number of ReadReq hits 408system.l2c.ReadReq_hits::total 1245858 # number of ReadReq hits 409system.l2c.Writeback_hits::writebacks 570720 # number of Writeback hits 410system.l2c.Writeback_hits::total 570720 # number of Writeback hits 411system.l2c.UpgradeReq_hits::cpu0.data 1291 # number of UpgradeReq hits 412system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits 413system.l2c.UpgradeReq_hits::total 1814 # number of UpgradeReq hits 414system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits 415system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits 416system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits 417system.l2c.ReadExReq_hits::cpu0.data 56339 # number of ReadExReq hits 418system.l2c.ReadExReq_hits::cpu1.data 52717 # number of ReadExReq hits 419system.l2c.ReadExReq_hits::total 109056 # number of ReadExReq hits 420system.l2c.demand_hits::cpu0.dtb.walker 3944 # number of demand (read+write) hits 421system.l2c.demand_hits::cpu0.itb.walker 1786 # number of demand (read+write) hits 422system.l2c.demand_hits::cpu0.inst 419390 # number of demand (read+write) hits 423system.l2c.demand_hits::cpu0.data 262194 # number of demand (read+write) hits 424system.l2c.demand_hits::cpu1.dtb.walker 5333 # number of demand (read+write) hits 425system.l2c.demand_hits::cpu1.itb.walker 1846 # number of demand (read+write) hits 426system.l2c.demand_hits::cpu1.inst 464270 # number of demand (read+write) hits 427system.l2c.demand_hits::cpu1.data 196151 # number of demand (read+write) hits 428system.l2c.demand_hits::total 1354914 # number of demand (read+write) hits 429system.l2c.overall_hits::cpu0.dtb.walker 3944 # number of overall hits 430system.l2c.overall_hits::cpu0.itb.walker 1786 # number of overall hits 431system.l2c.overall_hits::cpu0.inst 419390 # number of overall hits 432system.l2c.overall_hits::cpu0.data 262194 # number of overall hits 433system.l2c.overall_hits::cpu1.dtb.walker 5333 # number of overall hits 434system.l2c.overall_hits::cpu1.itb.walker 1846 # number of overall hits 435system.l2c.overall_hits::cpu1.inst 464270 # number of overall hits 436system.l2c.overall_hits::cpu1.data 196151 # number of overall hits 437system.l2c.overall_hits::total 1354914 # number of overall hits 438system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 439system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 440system.l2c.ReadReq_misses::cpu0.inst 5741 # number of ReadReq misses 441system.l2c.ReadReq_misses::cpu0.data 7844 # number of ReadReq misses 442system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 443system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 444system.l2c.ReadReq_misses::cpu1.inst 5048 # number of ReadReq misses 445system.l2c.ReadReq_misses::cpu1.data 3616 # number of ReadReq misses 446system.l2c.ReadReq_misses::total 22257 # number of ReadReq misses 447system.l2c.UpgradeReq_misses::cpu0.data 4858 # number of UpgradeReq misses 448system.l2c.UpgradeReq_misses::cpu1.data 3744 # number of UpgradeReq misses 449system.l2c.UpgradeReq_misses::total 8602 # number of UpgradeReq misses 450system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses 451system.l2c.SCUpgradeReq_misses::cpu1.data 472 # number of SCUpgradeReq misses 452system.l2c.SCUpgradeReq_misses::total 1039 # number of SCUpgradeReq misses 453system.l2c.ReadExReq_misses::cpu0.data 67076 # number of ReadExReq misses 454system.l2c.ReadExReq_misses::cpu1.data 72428 # number of ReadExReq misses 455system.l2c.ReadExReq_misses::total 139504 # number of ReadExReq misses 456system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 457system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 458system.l2c.demand_misses::cpu0.inst 5741 # number of demand (read+write) misses 459system.l2c.demand_misses::cpu0.data 74920 # number of demand (read+write) misses 460system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 461system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 462system.l2c.demand_misses::cpu1.inst 5048 # number of demand (read+write) misses 463system.l2c.demand_misses::cpu1.data 76044 # number of demand (read+write) misses 464system.l2c.demand_misses::total 161761 # number of demand (read+write) misses 465system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 466system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 467system.l2c.overall_misses::cpu0.inst 5741 # number of overall misses 468system.l2c.overall_misses::cpu0.data 74920 # number of overall misses 469system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 470system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 471system.l2c.overall_misses::cpu1.inst 5048 # number of overall misses 472system.l2c.overall_misses::cpu1.data 76044 # number of overall misses 473system.l2c.overall_misses::total 161761 # number of overall misses 474system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles 475system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 476system.l2c.ReadReq_miss_latency::cpu0.inst 405931250 # number of ReadReq miss cycles 477system.l2c.ReadReq_miss_latency::cpu0.data 580562999 # number of ReadReq miss cycles 478system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 320500 # number of ReadReq miss cycles 479system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles 480system.l2c.ReadReq_miss_latency::cpu1.inst 360408000 # number of ReadReq miss cycles 481system.l2c.ReadReq_miss_latency::cpu1.data 277006500 # number of ReadReq miss cycles 482system.l2c.ReadReq_miss_latency::total 1624485749 # number of ReadReq miss cycles 483system.l2c.UpgradeReq_miss_latency::cpu0.data 12826446 # number of UpgradeReq miss cycles 484system.l2c.UpgradeReq_miss_latency::cpu1.data 12064984 # number of UpgradeReq miss cycles 485system.l2c.UpgradeReq_miss_latency::total 24891430 # number of UpgradeReq miss cycles 486system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1764424 # number of SCUpgradeReq miss cycles 487system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2465394 # number of SCUpgradeReq miss cycles 488system.l2c.SCUpgradeReq_miss_latency::total 4229818 # number of SCUpgradeReq miss cycles 489system.l2c.ReadExReq_miss_latency::cpu0.data 4470263914 # number of ReadExReq miss cycles 490system.l2c.ReadExReq_miss_latency::cpu1.data 5223424391 # number of ReadExReq miss cycles 491system.l2c.ReadExReq_miss_latency::total 9693688305 # number of ReadExReq miss cycles 492system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles 493system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 494system.l2c.demand_miss_latency::cpu0.inst 405931250 # number of demand (read+write) miss cycles 495system.l2c.demand_miss_latency::cpu0.data 5050826913 # number of demand (read+write) miss cycles 496system.l2c.demand_miss_latency::cpu1.dtb.walker 320500 # number of demand (read+write) miss cycles 497system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles 498system.l2c.demand_miss_latency::cpu1.inst 360408000 # number of demand (read+write) miss cycles 499system.l2c.demand_miss_latency::cpu1.data 5500430891 # number of demand (read+write) miss cycles 500system.l2c.demand_miss_latency::total 11318174054 # number of demand (read+write) miss cycles 501system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles 502system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 503system.l2c.overall_miss_latency::cpu0.inst 405931250 # number of overall miss cycles 504system.l2c.overall_miss_latency::cpu0.data 5050826913 # number of overall miss cycles 505system.l2c.overall_miss_latency::cpu1.dtb.walker 320500 # number of overall miss cycles 506system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles 507system.l2c.overall_miss_latency::cpu1.inst 360408000 # number of overall miss cycles 508system.l2c.overall_miss_latency::cpu1.data 5500430891 # number of overall miss cycles 509system.l2c.overall_miss_latency::total 11318174054 # number of overall miss cycles 510system.l2c.ReadReq_accesses::cpu0.dtb.walker 3945 # number of ReadReq accesses(hits+misses) 511system.l2c.ReadReq_accesses::cpu0.itb.walker 1788 # number of ReadReq accesses(hits+misses) 512system.l2c.ReadReq_accesses::cpu0.inst 425131 # number of ReadReq accesses(hits+misses) 513system.l2c.ReadReq_accesses::cpu0.data 213699 # number of ReadReq accesses(hits+misses) 514system.l2c.ReadReq_accesses::cpu1.dtb.walker 5337 # number of ReadReq accesses(hits+misses) 515system.l2c.ReadReq_accesses::cpu1.itb.walker 1847 # number of ReadReq accesses(hits+misses) 516system.l2c.ReadReq_accesses::cpu1.inst 469318 # number of ReadReq accesses(hits+misses) 517system.l2c.ReadReq_accesses::cpu1.data 147050 # number of ReadReq accesses(hits+misses) 518system.l2c.ReadReq_accesses::total 1268115 # number of ReadReq accesses(hits+misses) 519system.l2c.Writeback_accesses::writebacks 570720 # number of Writeback accesses(hits+misses) 520system.l2c.Writeback_accesses::total 570720 # number of Writeback accesses(hits+misses) 521system.l2c.UpgradeReq_accesses::cpu0.data 6149 # number of UpgradeReq accesses(hits+misses) 522system.l2c.UpgradeReq_accesses::cpu1.data 4267 # number of UpgradeReq accesses(hits+misses) 523system.l2c.UpgradeReq_accesses::total 10416 # number of UpgradeReq accesses(hits+misses) 524system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) 525system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses) 526system.l2c.SCUpgradeReq_accesses::total 1350 # number of SCUpgradeReq accesses(hits+misses) 527system.l2c.ReadExReq_accesses::cpu0.data 123415 # number of ReadExReq accesses(hits+misses) 528system.l2c.ReadExReq_accesses::cpu1.data 125145 # number of ReadExReq accesses(hits+misses) 529system.l2c.ReadExReq_accesses::total 248560 # number of ReadExReq accesses(hits+misses) 530system.l2c.demand_accesses::cpu0.dtb.walker 3945 # number of demand (read+write) accesses 531system.l2c.demand_accesses::cpu0.itb.walker 1788 # number of demand (read+write) accesses 532system.l2c.demand_accesses::cpu0.inst 425131 # number of demand (read+write) accesses 533system.l2c.demand_accesses::cpu0.data 337114 # number of demand (read+write) accesses 534system.l2c.demand_accesses::cpu1.dtb.walker 5337 # number of demand (read+write) accesses 535system.l2c.demand_accesses::cpu1.itb.walker 1847 # number of demand (read+write) accesses 536system.l2c.demand_accesses::cpu1.inst 469318 # number of demand (read+write) accesses 537system.l2c.demand_accesses::cpu1.data 272195 # number of demand (read+write) accesses 538system.l2c.demand_accesses::total 1516675 # number of demand (read+write) accesses 539system.l2c.overall_accesses::cpu0.dtb.walker 3945 # number of overall (read+write) accesses 540system.l2c.overall_accesses::cpu0.itb.walker 1788 # number of overall (read+write) accesses 541system.l2c.overall_accesses::cpu0.inst 425131 # number of overall (read+write) accesses 542system.l2c.overall_accesses::cpu0.data 337114 # number of overall (read+write) accesses 543system.l2c.overall_accesses::cpu1.dtb.walker 5337 # number of overall (read+write) accesses 544system.l2c.overall_accesses::cpu1.itb.walker 1847 # number of overall (read+write) accesses 545system.l2c.overall_accesses::cpu1.inst 469318 # number of overall (read+write) accesses 546system.l2c.overall_accesses::cpu1.data 272195 # number of overall (read+write) accesses 547system.l2c.overall_accesses::total 1516675 # number of overall (read+write) accesses 548system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000253 # miss rate for ReadReq accesses 549system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001119 # miss rate for ReadReq accesses 550system.l2c.ReadReq_miss_rate::cpu0.inst 0.013504 # miss rate for ReadReq accesses 551system.l2c.ReadReq_miss_rate::cpu0.data 0.036706 # miss rate for ReadReq accesses 552system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000749 # miss rate for ReadReq accesses 553system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000541 # miss rate for ReadReq accesses 554system.l2c.ReadReq_miss_rate::cpu1.inst 0.010756 # miss rate for ReadReq accesses 555system.l2c.ReadReq_miss_rate::cpu1.data 0.024590 # miss rate for ReadReq accesses 556system.l2c.ReadReq_miss_rate::total 0.017551 # miss rate for ReadReq accesses 557system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790047 # miss rate for UpgradeReq accesses 558system.l2c.UpgradeReq_miss_rate::cpu1.data 0.877431 # miss rate for UpgradeReq accesses 559system.l2c.UpgradeReq_miss_rate::total 0.825845 # miss rate for UpgradeReq accesses 560system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725992 # miss rate for SCUpgradeReq accesses 561system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.829525 # miss rate for SCUpgradeReq accesses 562system.l2c.SCUpgradeReq_miss_rate::total 0.769630 # miss rate for SCUpgradeReq accesses 563system.l2c.ReadExReq_miss_rate::cpu0.data 0.543500 # miss rate for ReadExReq accesses 564system.l2c.ReadExReq_miss_rate::cpu1.data 0.578753 # miss rate for ReadExReq accesses 565system.l2c.ReadExReq_miss_rate::total 0.561249 # miss rate for ReadExReq accesses 566system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000253 # miss rate for demand accesses 567system.l2c.demand_miss_rate::cpu0.itb.walker 0.001119 # miss rate for demand accesses 568system.l2c.demand_miss_rate::cpu0.inst 0.013504 # miss rate for demand accesses 569system.l2c.demand_miss_rate::cpu0.data 0.222239 # miss rate for demand accesses 570system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000749 # miss rate for demand accesses 571system.l2c.demand_miss_rate::cpu1.itb.walker 0.000541 # miss rate for demand accesses 572system.l2c.demand_miss_rate::cpu1.inst 0.010756 # miss rate for demand accesses 573system.l2c.demand_miss_rate::cpu1.data 0.279373 # miss rate for demand accesses 574system.l2c.demand_miss_rate::total 0.106655 # miss rate for demand accesses 575system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000253 # miss rate for overall accesses 576system.l2c.overall_miss_rate::cpu0.itb.walker 0.001119 # miss rate for overall accesses 577system.l2c.overall_miss_rate::cpu0.inst 0.013504 # miss rate for overall accesses 578system.l2c.overall_miss_rate::cpu0.data 0.222239 # miss rate for overall accesses 579system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000749 # miss rate for overall accesses 580system.l2c.overall_miss_rate::cpu1.itb.walker 0.000541 # miss rate for overall accesses 581system.l2c.overall_miss_rate::cpu1.inst 0.010756 # miss rate for overall accesses 582system.l2c.overall_miss_rate::cpu1.data 0.279373 # miss rate for overall accesses 583system.l2c.overall_miss_rate::total 0.106655 # miss rate for overall accesses 584system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency 585system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 586system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70707.411601 # average ReadReq miss latency 587system.l2c.ReadReq_avg_miss_latency::cpu0.data 74013.640872 # average ReadReq miss latency 588system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80125 # average ReadReq miss latency 589system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency 590system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71396.196513 # average ReadReq miss latency 591system.l2c.ReadReq_avg_miss_latency::cpu1.data 76605.779867 # average ReadReq miss latency 592system.l2c.ReadReq_avg_miss_latency::total 72987.633059 # average ReadReq miss latency 593system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2640.272952 # average UpgradeReq miss latency 594system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3222.485043 # average UpgradeReq miss latency 595system.l2c.UpgradeReq_avg_miss_latency::total 2893.679377 # average UpgradeReq miss latency 596system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3111.858907 # average SCUpgradeReq miss latency 597system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5223.292373 # average SCUpgradeReq miss latency 598system.l2c.SCUpgradeReq_avg_miss_latency::total 4071.047161 # average SCUpgradeReq miss latency 599system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66644.759884 # average ReadExReq miss latency 600system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72118.854462 # average ReadExReq miss latency 601system.l2c.ReadExReq_avg_miss_latency::total 69486.812600 # average ReadExReq miss latency 602system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency 603system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 604system.l2c.demand_avg_miss_latency::cpu0.inst 70707.411601 # average overall miss latency 605system.l2c.demand_avg_miss_latency::cpu0.data 67416.269527 # average overall miss latency 606system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80125 # average overall miss latency 607system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 608system.l2c.demand_avg_miss_latency::cpu1.inst 71396.196513 # average overall miss latency 609system.l2c.demand_avg_miss_latency::cpu1.data 72332.214126 # average overall miss latency 610system.l2c.demand_avg_miss_latency::total 69968.497067 # average overall miss latency 611system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency 612system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 613system.l2c.overall_avg_miss_latency::cpu0.inst 70707.411601 # average overall miss latency 614system.l2c.overall_avg_miss_latency::cpu0.data 67416.269527 # average overall miss latency 615system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80125 # average overall miss latency 616system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency 617system.l2c.overall_avg_miss_latency::cpu1.inst 71396.196513 # average overall miss latency 618system.l2c.overall_avg_miss_latency::cpu1.data 72332.214126 # average overall miss latency 619system.l2c.overall_avg_miss_latency::total 69968.497067 # average overall miss latency | 415system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 416system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 417system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 418system.l2c.tags.age_task_id_blocks_1024::2 213 # Occupied blocks per task id 419system.l2c.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id 420system.l2c.tags.age_task_id_blocks_1024::4 11561 # Occupied blocks per task id 421system.l2c.tags.occ_task_id_percent::1022 0.786865 # Percentage of cache occupancy per task id 422system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id 423system.l2c.tags.occ_task_id_percent::1024 0.200241 # Percentage of cache occupancy per task id 424system.l2c.tags.tag_accesses 4855174 # Number of tag accesses 425system.l2c.tags.data_accesses 4855174 # Number of data accesses 426system.l2c.ReadReq_hits::cpu0.dtb.walker 111 # number of ReadReq hits 427system.l2c.ReadReq_hits::cpu0.itb.walker 56 # number of ReadReq hits 428system.l2c.ReadReq_hits::cpu0.inst 5971 # number of ReadReq hits 429system.l2c.ReadReq_hits::cpu0.data 15212 # number of ReadReq hits 430system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88244 # number of ReadReq hits 431system.l2c.ReadReq_hits::cpu1.dtb.walker 87 # number of ReadReq hits 432system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits 433system.l2c.ReadReq_hits::cpu1.inst 4855 # number of ReadReq hits 434system.l2c.ReadReq_hits::cpu1.data 12536 # number of ReadReq hits 435system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47744 # number of ReadReq hits 436system.l2c.ReadReq_hits::total 174841 # number of ReadReq hits 437system.l2c.Writeback_hits::writebacks 208041 # number of Writeback hits 438system.l2c.Writeback_hits::total 208041 # number of Writeback hits 439system.l2c.UpgradeReq_hits::cpu0.data 3552 # number of UpgradeReq hits 440system.l2c.UpgradeReq_hits::cpu1.data 1697 # number of UpgradeReq hits 441system.l2c.UpgradeReq_hits::total 5249 # number of UpgradeReq hits 442system.l2c.SCUpgradeReq_hits::cpu0.data 114 # number of SCUpgradeReq hits 443system.l2c.SCUpgradeReq_hits::cpu1.data 201 # number of SCUpgradeReq hits 444system.l2c.SCUpgradeReq_hits::total 315 # number of SCUpgradeReq hits 445system.l2c.ReadExReq_hits::cpu0.data 2350 # number of ReadExReq hits 446system.l2c.ReadExReq_hits::cpu1.data 2153 # number of ReadExReq hits 447system.l2c.ReadExReq_hits::total 4503 # number of ReadExReq hits 448system.l2c.demand_hits::cpu0.dtb.walker 111 # number of demand (read+write) hits 449system.l2c.demand_hits::cpu0.itb.walker 56 # number of demand (read+write) hits 450system.l2c.demand_hits::cpu0.inst 5971 # number of demand (read+write) hits 451system.l2c.demand_hits::cpu0.data 17562 # number of demand (read+write) hits 452system.l2c.demand_hits::cpu0.l2cache.prefetcher 88244 # number of demand (read+write) hits 453system.l2c.demand_hits::cpu1.dtb.walker 87 # number of demand (read+write) hits 454system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits 455system.l2c.demand_hits::cpu1.inst 4855 # number of demand (read+write) hits 456system.l2c.demand_hits::cpu1.data 14689 # number of demand (read+write) hits 457system.l2c.demand_hits::cpu1.l2cache.prefetcher 47744 # number of demand (read+write) hits 458system.l2c.demand_hits::total 179344 # number of demand (read+write) hits 459system.l2c.overall_hits::cpu0.dtb.walker 111 # number of overall hits 460system.l2c.overall_hits::cpu0.itb.walker 56 # number of overall hits 461system.l2c.overall_hits::cpu0.inst 5971 # number of overall hits 462system.l2c.overall_hits::cpu0.data 17562 # number of overall hits 463system.l2c.overall_hits::cpu0.l2cache.prefetcher 88244 # number of overall hits 464system.l2c.overall_hits::cpu1.dtb.walker 87 # number of overall hits 465system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits 466system.l2c.overall_hits::cpu1.inst 4855 # number of overall hits 467system.l2c.overall_hits::cpu1.data 14689 # number of overall hits 468system.l2c.overall_hits::cpu1.l2cache.prefetcher 47744 # number of overall hits 469system.l2c.overall_hits::total 179344 # number of overall hits 470system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses 471system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses 472system.l2c.ReadReq_misses::cpu0.inst 1474 # number of ReadReq misses 473system.l2c.ReadReq_misses::cpu0.data 3581 # number of ReadReq misses 474system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 104062 # number of ReadReq misses 475system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses 476system.l2c.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses 477system.l2c.ReadReq_misses::cpu1.data 4041 # number of ReadReq misses 478system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 50971 # number of ReadReq misses 479system.l2c.ReadReq_misses::total 164723 # number of ReadReq misses 480system.l2c.UpgradeReq_misses::cpu0.data 7774 # number of UpgradeReq misses 481system.l2c.UpgradeReq_misses::cpu1.data 5401 # number of UpgradeReq misses 482system.l2c.UpgradeReq_misses::total 13175 # number of UpgradeReq misses 483system.l2c.SCUpgradeReq_misses::cpu0.data 1167 # number of SCUpgradeReq misses 484system.l2c.SCUpgradeReq_misses::cpu1.data 1038 # number of SCUpgradeReq misses 485system.l2c.SCUpgradeReq_misses::total 2205 # number of SCUpgradeReq misses 486system.l2c.ReadExReq_misses::cpu0.data 4506 # number of ReadExReq misses 487system.l2c.ReadExReq_misses::cpu1.data 4295 # number of ReadExReq misses 488system.l2c.ReadExReq_misses::total 8801 # number of ReadExReq misses 489system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses 490system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses 491system.l2c.demand_misses::cpu0.inst 1474 # number of demand (read+write) misses 492system.l2c.demand_misses::cpu0.data 8087 # number of demand (read+write) misses 493system.l2c.demand_misses::cpu0.l2cache.prefetcher 104062 # number of demand (read+write) misses 494system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses 495system.l2c.demand_misses::cpu1.inst 586 # number of demand (read+write) misses 496system.l2c.demand_misses::cpu1.data 8336 # number of demand (read+write) misses 497system.l2c.demand_misses::cpu1.l2cache.prefetcher 50971 # number of demand (read+write) misses 498system.l2c.demand_misses::total 173524 # number of demand (read+write) misses 499system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses 500system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses 501system.l2c.overall_misses::cpu0.inst 1474 # number of overall misses 502system.l2c.overall_misses::cpu0.data 8087 # number of overall misses 503system.l2c.overall_misses::cpu0.l2cache.prefetcher 104062 # number of overall misses 504system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses 505system.l2c.overall_misses::cpu1.inst 586 # number of overall misses 506system.l2c.overall_misses::cpu1.data 8336 # number of overall misses 507system.l2c.overall_misses::cpu1.l2cache.prefetcher 50971 # number of overall misses 508system.l2c.overall_misses::total 173524 # number of overall misses 509system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 107000 # number of ReadReq miss cycles 510system.l2c.ReadReq_miss_latency::cpu0.itb.walker 298500 # number of ReadReq miss cycles 511system.l2c.ReadReq_miss_latency::cpu0.inst 119004500 # number of ReadReq miss cycles 512system.l2c.ReadReq_miss_latency::cpu0.data 272579750 # number of ReadReq miss cycles 513system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of ReadReq miss cycles 514system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 164250 # number of ReadReq miss cycles 515system.l2c.ReadReq_miss_latency::cpu1.inst 50120250 # number of ReadReq miss cycles 516system.l2c.ReadReq_miss_latency::cpu1.data 314939500 # number of ReadReq miss cycles 517system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of ReadReq miss cycles 518system.l2c.ReadReq_miss_latency::total 15882327372 # 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number of overall miss cycles 540system.l2c.overall_miss_latency::cpu0.inst 119004500 # number of overall miss cycles 541system.l2c.overall_miss_latency::cpu0.data 602656186 # number of overall miss cycles 542system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of overall miss cycles 543system.l2c.overall_miss_latency::cpu1.dtb.walker 164250 # number of overall miss cycles 544system.l2c.overall_miss_latency::cpu1.inst 50120250 # number of overall miss cycles 545system.l2c.overall_miss_latency::cpu1.data 623712722 # number of overall miss cycles 546system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of overall miss cycles 547system.l2c.overall_miss_latency::total 16521177030 # number of overall miss cycles 548system.l2c.ReadReq_accesses::cpu0.dtb.walker 113 # number of ReadReq accesses(hits+misses) 549system.l2c.ReadReq_accesses::cpu0.itb.walker 60 # number of ReadReq accesses(hits+misses) 550system.l2c.ReadReq_accesses::cpu0.inst 7445 # number of ReadReq accesses(hits+misses) 551system.l2c.ReadReq_accesses::cpu0.data 18793 # number of ReadReq accesses(hits+misses) 552system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 192306 # number of ReadReq accesses(hits+misses) 553system.l2c.ReadReq_accesses::cpu1.dtb.walker 89 # number of ReadReq accesses(hits+misses) 554system.l2c.ReadReq_accesses::cpu1.itb.walker 25 # number of ReadReq accesses(hits+misses) 555system.l2c.ReadReq_accesses::cpu1.inst 5441 # number of ReadReq accesses(hits+misses) 556system.l2c.ReadReq_accesses::cpu1.data 16577 # number of ReadReq accesses(hits+misses) 557system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 98715 # number of ReadReq accesses(hits+misses) 558system.l2c.ReadReq_accesses::total 339564 # number of ReadReq accesses(hits+misses) 559system.l2c.Writeback_accesses::writebacks 208041 # number of Writeback accesses(hits+misses) 560system.l2c.Writeback_accesses::total 208041 # number of Writeback accesses(hits+misses) 561system.l2c.UpgradeReq_accesses::cpu0.data 11326 # number of UpgradeReq accesses(hits+misses) 562system.l2c.UpgradeReq_accesses::cpu1.data 7098 # number of UpgradeReq accesses(hits+misses) 563system.l2c.UpgradeReq_accesses::total 18424 # number of UpgradeReq accesses(hits+misses) 564system.l2c.SCUpgradeReq_accesses::cpu0.data 1281 # number of SCUpgradeReq accesses(hits+misses) 565system.l2c.SCUpgradeReq_accesses::cpu1.data 1239 # number of SCUpgradeReq accesses(hits+misses) 566system.l2c.SCUpgradeReq_accesses::total 2520 # number of SCUpgradeReq accesses(hits+misses) 567system.l2c.ReadExReq_accesses::cpu0.data 6856 # number of ReadExReq accesses(hits+misses) 568system.l2c.ReadExReq_accesses::cpu1.data 6448 # number of ReadExReq accesses(hits+misses) 569system.l2c.ReadExReq_accesses::total 13304 # number of ReadExReq accesses(hits+misses) 570system.l2c.demand_accesses::cpu0.dtb.walker 113 # number of demand (read+write) accesses 571system.l2c.demand_accesses::cpu0.itb.walker 60 # number of demand (read+write) accesses 572system.l2c.demand_accesses::cpu0.inst 7445 # number of demand (read+write) accesses 573system.l2c.demand_accesses::cpu0.data 25649 # number of demand (read+write) accesses 574system.l2c.demand_accesses::cpu0.l2cache.prefetcher 192306 # number of demand (read+write) accesses 575system.l2c.demand_accesses::cpu1.dtb.walker 89 # number of demand (read+write) accesses 576system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses 577system.l2c.demand_accesses::cpu1.inst 5441 # number of demand (read+write) accesses 578system.l2c.demand_accesses::cpu1.data 23025 # number of demand (read+write) accesses 579system.l2c.demand_accesses::cpu1.l2cache.prefetcher 98715 # number of demand (read+write) accesses 580system.l2c.demand_accesses::total 352868 # number of demand (read+write) accesses 581system.l2c.overall_accesses::cpu0.dtb.walker 113 # number of overall (read+write) accesses 582system.l2c.overall_accesses::cpu0.itb.walker 60 # number of overall (read+write) accesses 583system.l2c.overall_accesses::cpu0.inst 7445 # number of overall (read+write) accesses 584system.l2c.overall_accesses::cpu0.data 25649 # number of overall (read+write) accesses 585system.l2c.overall_accesses::cpu0.l2cache.prefetcher 192306 # number of overall (read+write) accesses 586system.l2c.overall_accesses::cpu1.dtb.walker 89 # number of overall (read+write) accesses 587system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses 588system.l2c.overall_accesses::cpu1.inst 5441 # number of overall (read+write) accesses 589system.l2c.overall_accesses::cpu1.data 23025 # number of overall (read+write) accesses 590system.l2c.overall_accesses::cpu1.l2cache.prefetcher 98715 # number of overall (read+write) accesses 591system.l2c.overall_accesses::total 352868 # number of overall (read+write) accesses 592system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for ReadReq accesses 593system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.066667 # miss rate for ReadReq accesses 594system.l2c.ReadReq_miss_rate::cpu0.inst 0.197985 # miss rate for ReadReq accesses 595system.l2c.ReadReq_miss_rate::cpu0.data 0.190550 # miss rate for ReadReq accesses 596system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for ReadReq accesses 597system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for ReadReq accesses 598system.l2c.ReadReq_miss_rate::cpu1.inst 0.107701 # miss rate for ReadReq accesses 599system.l2c.ReadReq_miss_rate::cpu1.data 0.243771 # miss rate for ReadReq accesses 600system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for ReadReq accesses 601system.l2c.ReadReq_miss_rate::total 0.485101 # miss rate for ReadReq accesses 602system.l2c.UpgradeReq_miss_rate::cpu0.data 0.686385 # miss rate for UpgradeReq accesses 603system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760919 # miss rate for UpgradeReq accesses 604system.l2c.UpgradeReq_miss_rate::total 0.715100 # miss rate for UpgradeReq accesses 605system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.911007 # miss rate for SCUpgradeReq accesses 606system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.837772 # miss rate for SCUpgradeReq accesses 607system.l2c.SCUpgradeReq_miss_rate::total 0.875000 # miss rate for SCUpgradeReq accesses 608system.l2c.ReadExReq_miss_rate::cpu0.data 0.657235 # miss rate for ReadExReq accesses 609system.l2c.ReadExReq_miss_rate::cpu1.data 0.666098 # miss rate for ReadExReq accesses 610system.l2c.ReadExReq_miss_rate::total 0.661530 # miss rate for ReadExReq accesses 611system.l2c.demand_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for demand accesses 612system.l2c.demand_miss_rate::cpu0.itb.walker 0.066667 # miss rate for demand accesses 613system.l2c.demand_miss_rate::cpu0.inst 0.197985 # miss rate for demand accesses 614system.l2c.demand_miss_rate::cpu0.data 0.315295 # miss rate for demand accesses 615system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for demand accesses 616system.l2c.demand_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for demand accesses 617system.l2c.demand_miss_rate::cpu1.inst 0.107701 # miss rate for demand accesses 618system.l2c.demand_miss_rate::cpu1.data 0.362041 # miss rate for demand accesses 619system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for demand accesses 620system.l2c.demand_miss_rate::total 0.491753 # miss rate for demand accesses 621system.l2c.overall_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for overall accesses 622system.l2c.overall_miss_rate::cpu0.itb.walker 0.066667 # miss rate for overall accesses 623system.l2c.overall_miss_rate::cpu0.inst 0.197985 # miss rate for overall accesses 624system.l2c.overall_miss_rate::cpu0.data 0.315295 # miss rate for overall accesses 625system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for overall accesses 626system.l2c.overall_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for overall accesses 627system.l2c.overall_miss_rate::cpu1.inst 0.107701 # miss rate for overall accesses 628system.l2c.overall_miss_rate::cpu1.data 0.362041 # miss rate for overall accesses 629system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for overall accesses 630system.l2c.overall_miss_rate::total 0.491753 # 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average overall miss latency 653system.l2c.demand_avg_miss_latency::cpu0.data 74521.600841 # average overall miss latency 654system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average overall miss latency 655system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82125 # average overall miss latency 656system.l2c.demand_avg_miss_latency::cpu1.inst 85529.436860 # average overall miss latency 657system.l2c.demand_avg_miss_latency::cpu1.data 74821.583733 # average overall miss latency 658system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average overall miss latency 659system.l2c.demand_avg_miss_latency::total 95209.752138 # average overall miss latency 660system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 53500 # average overall miss latency 661system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74625 # average overall miss latency 662system.l2c.overall_avg_miss_latency::cpu0.inst 80735.753053 # average overall miss latency 663system.l2c.overall_avg_miss_latency::cpu0.data 74521.600841 # average overall miss latency 664system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average overall miss latency 665system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82125 # average overall miss latency 666system.l2c.overall_avg_miss_latency::cpu1.inst 85529.436860 # average overall miss latency 667system.l2c.overall_avg_miss_latency::cpu1.data 74821.583733 # average overall miss latency 668system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average overall miss latency 669system.l2c.overall_avg_miss_latency::total 95209.752138 # average overall miss latency |
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| 628system.l2c.writebacks::writebacks 64019 # number of writebacks 629system.l2c.writebacks::total 64019 # number of writebacks 630system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits | 678system.l2c.writebacks::writebacks 67188 # number of writebacks 679system.l2c.writebacks::total 67188 # number of writebacks 680system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits |
| 631system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits | 681system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits |
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| 633system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits | 683system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits |
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| 635system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits | 685system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits |
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mshr miss rate for ReadReq accesses 780system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.190550 # mshr miss rate for ReadReq accesses 781system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for ReadReq accesses 782system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for ReadReq accesses 783system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for ReadReq accesses 784system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.243771 # mshr miss rate for ReadReq accesses 785system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for ReadReq accesses 786system.l2c.ReadReq_mshr_miss_rate::total 0.485099 # mshr miss rate for ReadReq accesses 787system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.686385 # mshr miss rate for UpgradeReq accesses 788system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760919 # mshr miss rate for UpgradeReq accesses 789system.l2c.UpgradeReq_mshr_miss_rate::total 0.715100 # mshr miss rate for UpgradeReq accesses 790system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911007 # mshr miss rate for SCUpgradeReq accesses 791system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837772 # mshr miss rate for SCUpgradeReq accesses 792system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.875000 # mshr miss rate for SCUpgradeReq accesses 793system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.657235 # mshr miss rate for ReadExReq accesses 794system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.666098 # mshr miss rate for ReadExReq accesses 795system.l2c.ReadExReq_mshr_miss_rate::total 0.661530 # mshr miss rate for ReadExReq accesses 796system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for demand accesses 797system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for demand accesses 798system.l2c.demand_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for demand accesses 799system.l2c.demand_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for demand accesses 800system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for demand accesses 801system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for demand accesses 802system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for demand accesses 803system.l2c.demand_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for demand accesses 804system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for demand accesses 805system.l2c.demand_mshr_miss_rate::total 0.491750 # mshr miss rate for demand accesses 806system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for overall accesses 807system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for overall accesses 808system.l2c.overall_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for overall accesses 809system.l2c.overall_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for overall accesses 810system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for overall accesses 811system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for overall accesses 812system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for overall accesses 813system.l2c.overall_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for overall accesses 814system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for overall accesses 815system.l2c.overall_mshr_miss_rate::total 0.491750 # mshr miss rate for overall accesses 816system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average ReadReq mshr miss latency |
| 758system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 817system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 759system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average ReadReq mshr miss latency 760system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61536.078404 # average ReadReq mshr miss latency 761system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average ReadReq mshr miss latency 762system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 763system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average ReadReq mshr miss latency 764system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64144.911504 # average ReadReq mshr miss latency 765system.l2c.ReadReq_avg_mshr_miss_latency::total 60422.020983 # average ReadReq mshr miss latency 766system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.865377 # average UpgradeReq mshr miss latency 767system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019 # average UpgradeReq mshr miss latency 768system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.913857 # average UpgradeReq mshr miss latency 769system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.109347 # average SCUpgradeReq mshr miss latency 770system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458 # average SCUpgradeReq mshr miss latency 771system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.548604 # average SCUpgradeReq mshr miss latency 772system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53749.881836 # average ReadExReq mshr miss latency 773system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59393.523292 # average ReadExReq mshr miss latency 774system.l2c.ReadExReq_avg_mshr_miss_latency::total 56679.960281 # average ReadExReq mshr miss latency 775system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency | 818system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average ReadReq mshr miss latency 819system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707 # average ReadReq mshr miss latency 820system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average ReadReq mshr miss latency 821system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average ReadReq mshr miss latency 822system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average ReadReq mshr miss latency 823system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783 # average ReadReq mshr miss latency 824system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average ReadReq mshr miss latency 825system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786 # average ReadReq mshr miss latency 826system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479 # average UpgradeReq mshr miss latency 827system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839 # average UpgradeReq mshr miss latency 828system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400 # average UpgradeReq mshr miss latency 829system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602 # average SCUpgradeReq mshr miss latency 830system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628 # average SCUpgradeReq mshr miss latency 831system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887 # average SCUpgradeReq mshr miss latency 832system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019 # average ReadExReq mshr miss latency 833system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532 # average ReadExReq mshr miss latency 834system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346 # average ReadExReq mshr miss latency 835system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency |
| 776system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 836system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 777system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency 778system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency 779system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency 780system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 781system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency 782system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency 783system.l2c.demand_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency 784system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency | 837system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency 838system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency 839system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency 840system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency 841system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency 842system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency 843system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency 844system.l2c.demand_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency 845system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency |
| 785system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 846system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 786system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency 787system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency 788system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency 789system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 790system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency 791system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency 792system.l2c.overall_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency | 847system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency 848system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency 849system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency 850system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency 851system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency 852system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency 853system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency 854system.l2c.overall_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency |
| 793system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 794system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 795system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 796system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 797system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 798system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 799system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 800system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 805system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 806system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 807system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 808system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 809system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 810system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 811system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 812system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 855system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 856system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 857system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 858system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 859system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 860system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 861system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 862system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 867system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 868system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 869system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 870system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 871system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 872system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 873system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 874system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 813system.toL2Bus.throughput 119643708 # Throughput (bytes/s) 814system.toL2Bus.trans_dist::ReadReq 2534658 # Transaction distribution 815system.toL2Bus.trans_dist::ReadResp 2534658 # Transaction distribution 816system.toL2Bus.trans_dist::WriteReq 767581 # Transaction distribution 817system.toL2Bus.trans_dist::WriteResp 767581 # Transaction distribution 818system.toL2Bus.trans_dist::Writeback 570720 # Transaction distribution 819system.toL2Bus.trans_dist::UpgradeReq 30701 # Transaction distribution 820system.toL2Bus.trans_dist::SCUpgradeReq 17545 # Transaction distribution 821system.toL2Bus.trans_dist::UpgradeResp 48246 # Transaction distribution 822system.toL2Bus.trans_dist::ReadExReq 260694 # Transaction distribution 823system.toL2Bus.trans_dist::ReadExResp 260694 # Transaction distribution 824system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864108 # Packet count per connected master and slave (bytes) 825system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226294 # Packet count per connected master and slave (bytes) 826system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6184 # Packet count per connected master and slave (bytes) 827system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12819 # Packet count per connected master and slave (bytes) 828system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939372 # Packet count per connected master and slave (bytes) 829system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600756 # Packet count per connected master and slave (bytes) 830system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6173 # Packet count per connected master and slave (bytes) 831system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15243 # Packet count per connected master and slave (bytes) 832system.toL2Bus.pkt_count::total 7670949 # Packet count per connected master and slave (bytes) 833system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes) 834system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes) 835system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes) 836system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes) 837system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes) 838system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes) 839system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes) 840system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes) 841system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes) 842system.toL2Bus.data_through_bus 138285501 # Total data (bytes) 843system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes) 844system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks) 845system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 846system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks) 847system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 848system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks) 849system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 850system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks) 851system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 852system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks) 853system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 854system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks) 855system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 856system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks) 857system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 858system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) 859system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 860system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks) 861system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 862system.iobus.throughput 45460895 # Throughput (bytes/s) 863system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution 864system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution 865system.iobus.trans_dist::WriteReq 7962 # Transaction distribution 866system.iobus.trans_dist::WriteResp 7962 # Transaction distribution 867system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes) 868system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes) | 875system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution 876system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution 877system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution 878system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution 879system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution 880system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution 881system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution 882system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution 883system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution 884system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution 885system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution 886system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution 887system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes) 888system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes) 889system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes) 890system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes) 891system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes) 892system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes) 893system.toL2Bus.snoops 171942 # Total snoops (count) 894system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram 895system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 896system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 897system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 898system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 899system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram 900system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 901system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 902system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 903system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 904system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram 905system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks) 906system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 907system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks) 908system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 909system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks) 910system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 911system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution 912system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution 913system.iobus.trans_dist::WriteReq 8087 # Transaction distribution 914system.iobus.trans_dist::WriteResp 8087 # Transaction distribution 915system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes) 916system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes) |
| 869system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 917system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 870system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) | 918system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) |
| 871system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 872system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 919system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 920system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 873system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) | 921system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) |
| 874system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 878system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 879system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 880system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 881system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 882system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 883system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 884system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 885system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 886system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 887system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 888system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 889system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 922system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 923system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 924system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 925system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 926system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 927system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 928system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 929system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 930system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 931system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 932system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 933system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 934system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 935system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 936system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 937system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 890system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes) 891system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 892system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) 893system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes) 895system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 900system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 906system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 907system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 908system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 910system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 911system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 912system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 913system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 914system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 915system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 916system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 917system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes) 918system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 919system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) 920system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes) 921system.iobus.data_through_bus 54294501 # Total data (bytes) 922system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks) | 938system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes) 939system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) 940system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) 941system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes) 942system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes) 943system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes) 944system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 945system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) 946system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 947system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 948system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 949system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 950system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 951system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 952system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 953system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 954system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 955system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 956system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 957system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 958system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 959system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 962system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 963system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 964system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 965system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes) 966system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) 968system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes) 969system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks) |
| 923system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 970system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 924system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks) | 971system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks) |
| 925system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 926system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 927system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 972system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 973system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 974system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 928system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) | 975system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) |
| 929system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 930system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 931system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 932system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 933system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) | 976system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 977system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 978system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 979system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 980system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 934system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) | 981system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) |
| 935system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 936system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) | 982system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 983system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) |
| 937system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) | 984system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 938system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 939system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 940system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 941system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 942system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 943system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 944system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 945system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) --- 14 unchanged lines hidden (view full) --- 960system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 961system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 962system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 963system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 964system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 965system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 966system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 967system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 985system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 986system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 987system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 988system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 989system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 990system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 991system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 992system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) --- 14 unchanged lines hidden (view full) --- 1007system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1008system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1009system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1010system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1011system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1012system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1013system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1014system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 968system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 969system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 970system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks) 971system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) 972system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks) 973system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) | 1015system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) 1016system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) 1017system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks) 1018system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 1019system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks) 1020system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) |
| 974system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 975system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 976system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 977system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 978system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 979system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 980system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 981system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 989system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 990system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 991system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 992system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 993system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 994system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 995system.cpu0.dtb.inst_hits 0 # ITB inst hits 996system.cpu0.dtb.inst_misses 0 # ITB inst misses | 1021system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1022system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1023system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1024system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1025system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1026system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1027system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1028system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1036system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1037system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1038system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1039system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1040system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1041system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1042system.cpu0.dtb.inst_hits 0 # ITB inst hits 1043system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 997system.cpu0.dtb.read_hits 6063582 # DTB read hits 998system.cpu0.dtb.read_misses 3748 # DTB read misses 999system.cpu0.dtb.write_hits 5648980 # DTB write hits 1000system.cpu0.dtb.write_misses 807 # DTB write misses | 1044system.cpu0.dtb.read_hits 7131006 # DTB read hits 1045system.cpu0.dtb.read_misses 3644 # DTB read misses 1046system.cpu0.dtb.write_hits 6127729 # DTB write hits 1047system.cpu0.dtb.write_misses 663 # DTB write misses |
| 1001system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1002system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1003system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1004system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1048system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1049system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1050system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1051system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1005system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB | 1052system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB |
| 1006system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1053system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1007system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch | 1054system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch |
| 1008system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1055system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1009system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1010system.cpu0.dtb.read_accesses 6067330 # DTB read accesses 1011system.cpu0.dtb.write_accesses 5649787 # DTB write accesses | 1056system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1057system.cpu0.dtb.read_accesses 7134650 # DTB read accesses 1058system.cpu0.dtb.write_accesses 6128392 # DTB write accesses |
| 1012system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1059system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1013system.cpu0.dtb.hits 11712562 # DTB hits 1014system.cpu0.dtb.misses 4555 # DTB misses 1015system.cpu0.dtb.accesses 11717117 # DTB accesses | 1060system.cpu0.dtb.hits 13258735 # DTB hits 1061system.cpu0.dtb.misses 4307 # DTB misses 1062system.cpu0.dtb.accesses 13263042 # DTB accesses |
| 1016system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1017system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1018system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1019system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1020system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1021system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1022system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1023system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1029system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1030system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1031system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1032system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1033system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1034system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1035system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1036system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1063system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1064system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1065system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1066system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1067system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1068system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1069system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1070system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1076system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1077system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1078system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1079system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1080system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1081system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1082system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1083system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1037system.cpu0.itb.inst_hits 29557926 # ITB inst hits 1038system.cpu0.itb.inst_misses 2205 # ITB inst misses | 1084system.cpu0.itb.inst_hits 31182741 # ITB inst hits 1085system.cpu0.itb.inst_misses 2176 # ITB inst misses |
| 1039system.cpu0.itb.read_hits 0 # DTB read hits 1040system.cpu0.itb.read_misses 0 # DTB read misses 1041system.cpu0.itb.write_hits 0 # DTB write hits 1042system.cpu0.itb.write_misses 0 # DTB write misses 1043system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1044system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1045system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1046system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1086system.cpu0.itb.read_hits 0 # DTB read hits 1087system.cpu0.itb.read_misses 0 # DTB read misses 1088system.cpu0.itb.write_hits 0 # DTB write hits 1089system.cpu0.itb.write_misses 0 # DTB write misses 1090system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1091system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1092system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1093system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1047system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB | 1094system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB |
| 1048system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1049system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1050system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1051system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1052system.cpu0.itb.read_accesses 0 # DTB read accesses 1053system.cpu0.itb.write_accesses 0 # DTB write accesses | 1095system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1096system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1097system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1098system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1099system.cpu0.itb.read_accesses 0 # DTB read accesses 1100system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1054system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses 1055system.cpu0.itb.hits 29557926 # DTB hits 1056system.cpu0.itb.misses 2205 # DTB misses 1057system.cpu0.itb.accesses 29560131 # DTB accesses 1058system.cpu0.numCycles 2388624356 # number of cpu cycles simulated | 1101system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses 1102system.cpu0.itb.hits 31182741 # DTB hits 1103system.cpu0.itb.misses 2176 # DTB misses 1104system.cpu0.itb.accesses 31184917 # DTB accesses 1105system.cpu0.numCycles 5349463018 # number of cpu cycles simulated |
| 1059system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1060system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1106system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1107system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1061system.cpu0.committedInsts 28859743 # Number of instructions committed 1062system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed 1063system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses 1064system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 1065system.cpu0.num_func_calls 1241573 # number of times a function call or return occured 1066system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls 1067system.cpu0.num_int_insts 30439288 # number of integer instructions 1068system.cpu0.num_fp_insts 3860 # number of float instructions 1069system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read 1070system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written 1071system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1072system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1073system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read 1074system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written 1075system.cpu0.num_mem_refs 12225186 # number of memory refs 1076system.cpu0.num_load_insts 6245915 # Number of load instructions 1077system.cpu0.num_store_insts 5979271 # Number of store instructions 1078system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles 1079system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles 1080system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles 1081system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles 1082system.cpu0.Branches 5599312 # Number of branches fetched 1083system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction 1084system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction 1085system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction 1086system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction 1087system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction 1088system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction 1089system.cpu0.op_class::FloatCvt 0 0.00% 65.31% # Class of executed instruction 1090system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction 1091system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction 1092system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction 1093system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction 1094system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction 1095system.cpu0.op_class::SimdAlu 0 0.00% 65.31% # Class of executed instruction 1096system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction 1097system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction 1098system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction 1099system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction 1100system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction 1101system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction 1102system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction 1103system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction 1104system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction 1105system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction 1106system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction 1107system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction 1108system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction 1109system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction 1110system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction 1111system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction 1112system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction 1113system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction 1114system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction | 1108system.cpu0.committedInsts 30507218 # Number of instructions committed 1109system.cpu0.committedOps 36803230 # Number of ops (including micro ops) committed 1110system.cpu0.num_int_alu_accesses 32859018 # Number of integer alu accesses 1111system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 1112system.cpu0.num_func_calls 1290775 # number of times a function call or return occured 1113system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls 1114system.cpu0.num_int_insts 32859018 # number of integer instructions 1115system.cpu0.num_fp_insts 5449 # number of float instructions 1116system.cpu0.num_int_register_reads 60131579 # number of times the integer registers were read 1117system.cpu0.num_int_register_writes 21902535 # number of times the integer registers were written 1118system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 1119system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 1120system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read 1121system.cpu0.num_cc_register_writes 14490121 # number of times the CC registers were written 1122system.cpu0.num_mem_refs 13795466 # number of memory refs 1123system.cpu0.num_load_insts 7343231 # Number of load instructions 1124system.cpu0.num_store_insts 6452235 # Number of store instructions 1125system.cpu0.num_idle_cycles 4898257252.279955 # Number of idle cycles 1126system.cpu0.num_busy_cycles 451205765.720045 # Number of busy cycles 1127system.cpu0.not_idle_fraction 0.084346 # Percentage of non-idle cycles 1128system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles 1129system.cpu0.Branches 5660514 # Number of branches fetched 1130system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction 1131system.cpu0.op_class::IntAlu 23591543 62.99% 63.03% # Class of executed instruction 1132system.cpu0.op_class::IntMult 47189 0.13% 63.16% # Class of executed instruction 1133system.cpu0.op_class::IntDiv 0 0.00% 63.16% # Class of executed instruction 1134system.cpu0.op_class::FloatAdd 0 0.00% 63.16% # Class of executed instruction 1135system.cpu0.op_class::FloatCmp 0 0.00% 63.16% # Class of executed instruction 1136system.cpu0.op_class::FloatCvt 0 0.00% 63.16% # Class of executed instruction 1137system.cpu0.op_class::FloatMult 0 0.00% 63.16% # Class of executed instruction 1138system.cpu0.op_class::FloatDiv 0 0.00% 63.16% # Class of executed instruction 1139system.cpu0.op_class::FloatSqrt 0 0.00% 63.16% # Class of executed instruction 1140system.cpu0.op_class::SimdAdd 0 0.00% 63.16% # Class of executed instruction 1141system.cpu0.op_class::SimdAddAcc 0 0.00% 63.16% # Class of executed instruction 1142system.cpu0.op_class::SimdAlu 0 0.00% 63.16% # Class of executed instruction 1143system.cpu0.op_class::SimdCmp 0 0.00% 63.16% # Class of executed instruction 1144system.cpu0.op_class::SimdCvt 0 0.00% 63.16% # Class of executed instruction 1145system.cpu0.op_class::SimdMisc 0 0.00% 63.16% # Class of executed instruction 1146system.cpu0.op_class::SimdMult 0 0.00% 63.16% # Class of executed instruction 1147system.cpu0.op_class::SimdMultAcc 0 0.00% 63.16% # Class of executed instruction 1148system.cpu0.op_class::SimdShift 0 0.00% 63.16% # Class of executed instruction 1149system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.16% # Class of executed instruction 1150system.cpu0.op_class::SimdSqrt 0 0.00% 63.16% # Class of executed instruction 1151system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.16% # Class of executed instruction 1152system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.16% # Class of executed instruction 1153system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.16% # Class of executed instruction 1154system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.16% # Class of executed instruction 1155system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.16% # Class of executed instruction 1156system.cpu0.op_class::SimdFloatMisc 1591 0.00% 63.17% # Class of executed instruction 1157system.cpu0.op_class::SimdFloatMult 0 0.00% 63.17% # Class of executed instruction 1158system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.17% # Class of executed instruction 1159system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.17% # Class of executed instruction 1160system.cpu0.op_class::MemRead 7343231 19.61% 82.77% # Class of executed instruction 1161system.cpu0.op_class::MemWrite 6452235 17.23% 100.00% # Class of executed instruction |
| 1115system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1116system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1162system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1163system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1117system.cpu0.op_class::total 35241548 # Class of executed instruction | 1164system.cpu0.op_class::total 37452110 # Class of executed instruction |
| 1118system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1165system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1119system.cpu0.kern.inst.quiesce 47055 # number of quiesce instructions executed 1120system.cpu0.icache.tags.replacements 425168 # number of replacements 1121system.cpu0.icache.tags.tagsinuse 509.375466 # Cycle average of tags in use 1122system.cpu0.icache.tags.total_refs 29132228 # Total number of references to valid blocks. 1123system.cpu0.icache.tags.sampled_refs 425680 # Sample count of references to valid blocks. 1124system.cpu0.icache.tags.avg_refs 68.436920 # Average number of references to valid blocks. 1125system.cpu0.icache.tags.warmup_cycle 75988011000 # Cycle when the warmup percentage was hit. 1126system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.375466 # Average occupied blocks per requestor 1127system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994874 # Average percentage of cache occupancy 1128system.cpu0.icache.tags.occ_percent::total 0.994874 # Average percentage of cache occupancy | 1166system.cpu0.kern.inst.quiesce 51950 # number of quiesce instructions executed 1167system.cpu0.icache.tags.replacements 369506 # number of replacements 1168system.cpu0.icache.tags.tagsinuse 511.465010 # Cycle average of tags in use 1169system.cpu0.icache.tags.total_refs 30812705 # Total number of references to valid blocks. 1170system.cpu0.icache.tags.sampled_refs 370018 # Sample count of references to valid blocks. 1171system.cpu0.icache.tags.avg_refs 83.273530 # Average number of references to valid blocks. 1172system.cpu0.icache.tags.warmup_cycle 10201796750 # Cycle when the warmup percentage was hit. 1173system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.465010 # Average occupied blocks per requestor 1174system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998955 # Average percentage of cache occupancy 1175system.cpu0.icache.tags.occ_percent::total 0.998955 # Average percentage of cache occupancy |
| 1129system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1176system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1130system.cpu0.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 1131system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1132system.cpu0.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id 1133system.cpu0.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id | 1177system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id 1178system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id |
| 1134system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1179system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1135system.cpu0.icache.tags.tag_accesses 29983590 # Number of tag accesses 1136system.cpu0.icache.tags.data_accesses 29983590 # Number of data accesses 1137system.cpu0.icache.ReadReq_hits::cpu0.inst 29132228 # number of ReadReq hits 1138system.cpu0.icache.ReadReq_hits::total 29132228 # number of ReadReq hits 1139system.cpu0.icache.demand_hits::cpu0.inst 29132228 # number of demand (read+write) hits 1140system.cpu0.icache.demand_hits::total 29132228 # number of demand (read+write) hits 1141system.cpu0.icache.overall_hits::cpu0.inst 29132228 # number of overall hits 1142system.cpu0.icache.overall_hits::total 29132228 # number of overall hits 1143system.cpu0.icache.ReadReq_misses::cpu0.inst 425681 # number of ReadReq misses 1144system.cpu0.icache.ReadReq_misses::total 425681 # number of ReadReq misses 1145system.cpu0.icache.demand_misses::cpu0.inst 425681 # number of demand (read+write) misses 1146system.cpu0.icache.demand_misses::total 425681 # number of demand (read+write) misses 1147system.cpu0.icache.overall_misses::cpu0.inst 425681 # number of overall misses 1148system.cpu0.icache.overall_misses::total 425681 # number of overall misses 1149system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899766682 # number of ReadReq miss cycles 1150system.cpu0.icache.ReadReq_miss_latency::total 5899766682 # number of ReadReq miss cycles 1151system.cpu0.icache.demand_miss_latency::cpu0.inst 5899766682 # number of demand (read+write) miss cycles 1152system.cpu0.icache.demand_miss_latency::total 5899766682 # number of demand (read+write) miss cycles 1153system.cpu0.icache.overall_miss_latency::cpu0.inst 5899766682 # number of overall miss cycles 1154system.cpu0.icache.overall_miss_latency::total 5899766682 # number of overall miss cycles 1155system.cpu0.icache.ReadReq_accesses::cpu0.inst 29557909 # number of ReadReq accesses(hits+misses) 1156system.cpu0.icache.ReadReq_accesses::total 29557909 # number of ReadReq accesses(hits+misses) 1157system.cpu0.icache.demand_accesses::cpu0.inst 29557909 # number of demand (read+write) accesses 1158system.cpu0.icache.demand_accesses::total 29557909 # number of demand (read+write) accesses 1159system.cpu0.icache.overall_accesses::cpu0.inst 29557909 # number of overall (read+write) accesses 1160system.cpu0.icache.overall_accesses::total 29557909 # number of overall (read+write) accesses 1161system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014402 # miss rate for ReadReq accesses 1162system.cpu0.icache.ReadReq_miss_rate::total 0.014402 # miss rate for ReadReq accesses 1163system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014402 # miss rate for demand accesses 1164system.cpu0.icache.demand_miss_rate::total 0.014402 # miss rate for demand accesses 1165system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014402 # miss rate for overall accesses 1166system.cpu0.icache.overall_miss_rate::total 0.014402 # miss rate for overall accesses 1167system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993 # average ReadReq miss latency 1168system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993 # average ReadReq miss latency 1169system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency 1170system.cpu0.icache.demand_avg_miss_latency::total 13859.595993 # average overall miss latency 1171system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency 1172system.cpu0.icache.overall_avg_miss_latency::total 13859.595993 # average overall miss latency | 1180system.cpu0.icache.tags.tag_accesses 62735467 # Number of tag accesses 1181system.cpu0.icache.tags.data_accesses 62735467 # Number of data accesses 1182system.cpu0.icache.ReadReq_hits::cpu0.inst 30812705 # number of ReadReq hits 1183system.cpu0.icache.ReadReq_hits::total 30812705 # number of ReadReq hits 1184system.cpu0.icache.demand_hits::cpu0.inst 30812705 # number of demand (read+write) hits 1185system.cpu0.icache.demand_hits::total 30812705 # number of demand (read+write) hits 1186system.cpu0.icache.overall_hits::cpu0.inst 30812705 # number of overall hits 1187system.cpu0.icache.overall_hits::total 30812705 # number of overall hits 1188system.cpu0.icache.ReadReq_misses::cpu0.inst 370019 # number of ReadReq misses 1189system.cpu0.icache.ReadReq_misses::total 370019 # number of ReadReq misses 1190system.cpu0.icache.demand_misses::cpu0.inst 370019 # number of demand (read+write) misses 1191system.cpu0.icache.demand_misses::total 370019 # number of demand (read+write) misses 1192system.cpu0.icache.overall_misses::cpu0.inst 370019 # number of overall misses 1193system.cpu0.icache.overall_misses::total 370019 # number of overall misses 1194system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3209345752 # number of ReadReq miss cycles 1195system.cpu0.icache.ReadReq_miss_latency::total 3209345752 # number of ReadReq miss cycles 1196system.cpu0.icache.demand_miss_latency::cpu0.inst 3209345752 # number of demand (read+write) miss cycles 1197system.cpu0.icache.demand_miss_latency::total 3209345752 # number of demand (read+write) miss cycles 1198system.cpu0.icache.overall_miss_latency::cpu0.inst 3209345752 # number of overall miss cycles 1199system.cpu0.icache.overall_miss_latency::total 3209345752 # number of overall miss cycles 1200system.cpu0.icache.ReadReq_accesses::cpu0.inst 31182724 # number of ReadReq accesses(hits+misses) 1201system.cpu0.icache.ReadReq_accesses::total 31182724 # number of ReadReq accesses(hits+misses) 1202system.cpu0.icache.demand_accesses::cpu0.inst 31182724 # number of demand (read+write) accesses 1203system.cpu0.icache.demand_accesses::total 31182724 # number of demand (read+write) accesses 1204system.cpu0.icache.overall_accesses::cpu0.inst 31182724 # number of overall (read+write) accesses 1205system.cpu0.icache.overall_accesses::total 31182724 # number of overall (read+write) accesses 1206system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011866 # miss rate for ReadReq accesses 1207system.cpu0.icache.ReadReq_miss_rate::total 0.011866 # miss rate for ReadReq accesses 1208system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011866 # miss rate for demand accesses 1209system.cpu0.icache.demand_miss_rate::total 0.011866 # miss rate for demand accesses 1210system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011866 # miss rate for overall accesses 1211system.cpu0.icache.overall_miss_rate::total 0.011866 # miss rate for overall accesses 1212system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8673.462044 # average ReadReq miss latency 1213system.cpu0.icache.ReadReq_avg_miss_latency::total 8673.462044 # average ReadReq miss latency 1214system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency 1215system.cpu0.icache.demand_avg_miss_latency::total 8673.462044 # average overall miss latency 1216system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency 1217system.cpu0.icache.overall_avg_miss_latency::total 8673.462044 # average overall miss latency |
| 1173system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1174system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1175system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1176system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1177system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1178system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1179system.cpu0.icache.fast_writes 0 # number of fast writes performed 1180system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1218system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1219system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1220system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1221system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1222system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1223system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1224system.cpu0.icache.fast_writes 0 # number of fast writes performed 1225system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1181system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425681 # number of ReadReq MSHR misses 1182system.cpu0.icache.ReadReq_mshr_misses::total 425681 # number of ReadReq MSHR misses 1183system.cpu0.icache.demand_mshr_misses::cpu0.inst 425681 # number of demand (read+write) MSHR misses 1184system.cpu0.icache.demand_mshr_misses::total 425681 # number of demand (read+write) MSHR misses 1185system.cpu0.icache.overall_mshr_misses::cpu0.inst 425681 # number of overall MSHR misses 1186system.cpu0.icache.overall_mshr_misses::total 425681 # number of overall MSHR misses 1187system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5046160318 # number of ReadReq MSHR miss cycles 1188system.cpu0.icache.ReadReq_mshr_miss_latency::total 5046160318 # number of ReadReq MSHR miss cycles 1189system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5046160318 # number of demand (read+write) MSHR miss cycles 1190system.cpu0.icache.demand_mshr_miss_latency::total 5046160318 # number of demand (read+write) MSHR miss cycles 1191system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5046160318 # number of overall MSHR miss cycles 1192system.cpu0.icache.overall_mshr_miss_latency::total 5046160318 # number of overall MSHR miss cycles 1193system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442165750 # number of ReadReq MSHR uncacheable cycles 1194system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442165750 # number of ReadReq MSHR uncacheable cycles 1195system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442165750 # number of overall MSHR uncacheable cycles 1196system.cpu0.icache.overall_mshr_uncacheable_latency::total 442165750 # number of overall MSHR uncacheable cycles 1197system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for ReadReq accesses 1198system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014402 # mshr miss rate for ReadReq accesses 1199system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for demand accesses 1200system.cpu0.icache.demand_mshr_miss_rate::total 0.014402 # mshr miss rate for demand accesses 1201system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for overall accesses 1202system.cpu0.icache.overall_mshr_miss_rate::total 0.014402 # mshr miss rate for overall accesses 1203system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average ReadReq mshr miss latency 1204system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11854.323585 # average ReadReq mshr miss latency 1205system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency 1206system.cpu0.icache.demand_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency 1207system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency 1208system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency | 1226system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 370019 # number of ReadReq MSHR misses 1227system.cpu0.icache.ReadReq_mshr_misses::total 370019 # number of ReadReq MSHR misses 1228system.cpu0.icache.demand_mshr_misses::cpu0.inst 370019 # number of demand (read+write) MSHR misses 1229system.cpu0.icache.demand_mshr_misses::total 370019 # number of demand (read+write) MSHR misses 1230system.cpu0.icache.overall_mshr_misses::cpu0.inst 370019 # number of overall MSHR misses 1231system.cpu0.icache.overall_mshr_misses::total 370019 # number of overall MSHR misses 1232system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2653955748 # number of ReadReq MSHR miss cycles 1233system.cpu0.icache.ReadReq_mshr_miss_latency::total 2653955748 # number of ReadReq MSHR miss cycles 1234system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2653955748 # number of demand (read+write) MSHR miss cycles 1235system.cpu0.icache.demand_mshr_miss_latency::total 2653955748 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2653955748 # number of overall MSHR miss cycles 1237system.cpu0.icache.overall_mshr_miss_latency::total 2653955748 # number of overall MSHR miss cycles 1238system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 531257750 # number of ReadReq MSHR uncacheable cycles 1239system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 531257750 # number of ReadReq MSHR uncacheable cycles 1240system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 531257750 # number of overall MSHR uncacheable cycles 1241system.cpu0.icache.overall_mshr_uncacheable_latency::total 531257750 # number of overall MSHR uncacheable cycles 1242system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for ReadReq accesses 1243system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011866 # mshr miss rate for ReadReq accesses 1244system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for demand accesses 1245system.cpu0.icache.demand_mshr_miss_rate::total 0.011866 # mshr miss rate for demand accesses 1246system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for overall accesses 1247system.cpu0.icache.overall_mshr_miss_rate::total 0.011866 # mshr miss rate for overall accesses 1248system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average ReadReq mshr miss latency 1249system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7172.485056 # average ReadReq mshr miss latency 1250system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency 1251system.cpu0.icache.demand_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency 1252system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency 1253system.cpu0.icache.overall_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency |
| 1209system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1210system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1211system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1212system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1213system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1254system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1255system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1256system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1257system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1258system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1214system.cpu0.dcache.tags.replacements 329792 # number of replacements 1215system.cpu0.dcache.tags.tagsinuse 452.041842 # Cycle average of tags in use 1216system.cpu0.dcache.tags.total_refs 11239100 # Total number of references to valid blocks. 1217system.cpu0.dcache.tags.sampled_refs 330304 # Sample count of references to valid blocks. 1218system.cpu0.dcache.tags.avg_refs 34.026533 # Average number of references to valid blocks. 1219system.cpu0.dcache.tags.warmup_cycle 671364250 # Cycle when the warmup percentage was hit. 1220system.cpu0.dcache.tags.occ_blocks::cpu0.data 452.041842 # Average occupied blocks per requestor 1221system.cpu0.dcache.tags.occ_percent::cpu0.data 0.882894 # Average percentage of cache occupancy 1222system.cpu0.dcache.tags.occ_percent::total 0.882894 # Average percentage of cache occupancy 1223system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1224system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 1225system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id 1226system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 1227system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1228system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1229system.cpu0.dcache.tags.tag_accesses 46848154 # Number of tag accesses 1230system.cpu0.dcache.tags.data_accesses 46848154 # Number of data accesses 1231system.cpu0.dcache.ReadReq_hits::cpu0.data 5514035 # number of ReadReq hits 1232system.cpu0.dcache.ReadReq_hits::total 5514035 # number of ReadReq hits 1233system.cpu0.dcache.WriteReq_hits::cpu0.data 5340154 # number of WriteReq hits 1234system.cpu0.dcache.WriteReq_hits::total 5340154 # number of WriteReq hits 1235system.cpu0.dcache.SoftPFReq_hits::cpu0.data 64966 # number of SoftPFReq hits 1236system.cpu0.dcache.SoftPFReq_hits::total 64966 # number of SoftPFReq hits 1237system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148024 # number of LoadLockedReq hits 1238system.cpu0.dcache.LoadLockedReq_hits::total 148024 # number of LoadLockedReq hits 1239system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149636 # number of StoreCondReq hits 1240system.cpu0.dcache.StoreCondReq_hits::total 149636 # number of StoreCondReq hits 1241system.cpu0.dcache.demand_hits::cpu0.data 10854189 # number of demand (read+write) hits 1242system.cpu0.dcache.demand_hits::total 10854189 # number of demand (read+write) hits 1243system.cpu0.dcache.overall_hits::cpu0.data 10919155 # number of overall hits 1244system.cpu0.dcache.overall_hits::total 10919155 # number of overall hits 1245system.cpu0.dcache.ReadReq_misses::cpu0.data 179189 # number of ReadReq misses 1246system.cpu0.dcache.ReadReq_misses::total 179189 # number of ReadReq misses 1247system.cpu0.dcache.WriteReq_misses::cpu0.data 145422 # number of WriteReq misses 1248system.cpu0.dcache.WriteReq_misses::total 145422 # number of WriteReq misses 1249system.cpu0.dcache.SoftPFReq_misses::cpu0.data 62829 # number of SoftPFReq misses 1250system.cpu0.dcache.SoftPFReq_misses::total 62829 # number of SoftPFReq misses 1251system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9439 # number of LoadLockedReq misses 1252system.cpu0.dcache.LoadLockedReq_misses::total 9439 # number of LoadLockedReq misses 1253system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7485 # number of StoreCondReq misses 1254system.cpu0.dcache.StoreCondReq_misses::total 7485 # number of StoreCondReq misses 1255system.cpu0.dcache.demand_misses::cpu0.data 324611 # number of demand (read+write) misses 1256system.cpu0.dcache.demand_misses::total 324611 # number of demand (read+write) misses 1257system.cpu0.dcache.overall_misses::cpu0.data 387440 # number of overall misses 1258system.cpu0.dcache.overall_misses::total 387440 # number of overall misses 1259system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2350643732 # number of ReadReq miss cycles 1260system.cpu0.dcache.ReadReq_miss_latency::total 2350643732 # number of ReadReq miss cycles 1261system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5817567140 # number of WriteReq miss cycles 1262system.cpu0.dcache.WriteReq_miss_latency::total 5817567140 # number of WriteReq miss cycles 1263system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94706749 # number of LoadLockedReq miss cycles 1264system.cpu0.dcache.LoadLockedReq_miss_latency::total 94706749 # number of LoadLockedReq miss cycles 1265system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44450567 # number of StoreCondReq miss cycles 1266system.cpu0.dcache.StoreCondReq_miss_latency::total 44450567 # number of StoreCondReq miss cycles 1267system.cpu0.dcache.demand_miss_latency::cpu0.data 8168210872 # number of demand (read+write) miss cycles 1268system.cpu0.dcache.demand_miss_latency::total 8168210872 # number of demand (read+write) miss cycles 1269system.cpu0.dcache.overall_miss_latency::cpu0.data 8168210872 # number of overall miss cycles 1270system.cpu0.dcache.overall_miss_latency::total 8168210872 # number of overall miss cycles 1271system.cpu0.dcache.ReadReq_accesses::cpu0.data 5693224 # number of ReadReq accesses(hits+misses) 1272system.cpu0.dcache.ReadReq_accesses::total 5693224 # number of ReadReq accesses(hits+misses) 1273system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485576 # number of WriteReq accesses(hits+misses) 1274system.cpu0.dcache.WriteReq_accesses::total 5485576 # number of WriteReq accesses(hits+misses) 1275system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 127795 # number of SoftPFReq accesses(hits+misses) 1276system.cpu0.dcache.SoftPFReq_accesses::total 127795 # number of SoftPFReq accesses(hits+misses) 1277system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157463 # number of LoadLockedReq accesses(hits+misses) 1278system.cpu0.dcache.LoadLockedReq_accesses::total 157463 # number of LoadLockedReq accesses(hits+misses) 1279system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157121 # number of StoreCondReq accesses(hits+misses) 1280system.cpu0.dcache.StoreCondReq_accesses::total 157121 # number of StoreCondReq accesses(hits+misses) 1281system.cpu0.dcache.demand_accesses::cpu0.data 11178800 # number of demand (read+write) accesses 1282system.cpu0.dcache.demand_accesses::total 11178800 # number of demand (read+write) accesses 1283system.cpu0.dcache.overall_accesses::cpu0.data 11306595 # number of overall (read+write) accesses 1284system.cpu0.dcache.overall_accesses::total 11306595 # number of overall (read+write) accesses 1285system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031474 # miss rate for ReadReq accesses 1286system.cpu0.dcache.ReadReq_miss_rate::total 0.031474 # miss rate for ReadReq accesses 1287system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026510 # miss rate for WriteReq accesses 1288system.cpu0.dcache.WriteReq_miss_rate::total 0.026510 # miss rate for WriteReq accesses 1289system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.491639 # miss rate for SoftPFReq accesses 1290system.cpu0.dcache.SoftPFReq_miss_rate::total 0.491639 # miss rate for SoftPFReq accesses 1291system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059944 # miss rate for LoadLockedReq accesses 1292system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059944 # miss rate for LoadLockedReq accesses 1293system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047638 # miss rate for StoreCondReq accesses 1294system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047638 # miss rate for StoreCondReq accesses 1295system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029038 # miss rate for demand accesses 1296system.cpu0.dcache.demand_miss_rate::total 0.029038 # miss rate for demand accesses 1297system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034267 # miss rate for overall accesses 1298system.cpu0.dcache.overall_miss_rate::total 0.034267 # miss rate for overall accesses 1299system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13118.236789 # average ReadReq miss latency 1300system.cpu0.dcache.ReadReq_avg_miss_latency::total 13118.236789 # average ReadReq miss latency 1301system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40004.725145 # average WriteReq miss latency 1302system.cpu0.dcache.WriteReq_avg_miss_latency::total 40004.725145 # average WriteReq miss latency 1303system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474 # average LoadLockedReq miss latency 1304system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474 # average LoadLockedReq miss latency 1305system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5938.619506 # average StoreCondReq miss latency 1306system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5938.619506 # average StoreCondReq miss latency 1307system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794 # average overall miss latency 1308system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794 # average overall miss latency 1309system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253 # average overall miss latency 1310system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253 # average overall miss latency | 1259system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 4129417 # number of hwpf identified 1260system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 113341 # number of hwpf that were already in mshr 1261system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3763718 # number of hwpf that were already in the cache 1262system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 300 # number of hwpf that were already in the prefetch queue 1263system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1264system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 22 # number of hwpf removed because MSHR allocated 1265system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 252036 # number of hwpf issued 1266system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 312183 # number of hwpf spanning a virtual page 1267system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1268system.cpu0.l2cache.tags.replacements 213190 # number of replacements 1269system.cpu0.l2cache.tags.tagsinuse 16168.240053 # Cycle average of tags in use 1270system.cpu0.l2cache.tags.total_refs 848978 # Total number of references to valid blocks. 1271system.cpu0.l2cache.tags.sampled_refs 228702 # Sample count of references to valid blocks. 1272system.cpu0.l2cache.tags.avg_refs 3.712158 # Average number of references to valid blocks. 1273system.cpu0.l2cache.tags.warmup_cycle 7921739000 # Cycle when the warmup percentage was hit. 1274system.cpu0.l2cache.tags.occ_blocks::writebacks 4749.054127 # Average occupied blocks per requestor 1275system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.517230 # Average occupied blocks per requestor 1276system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.260718 # Average occupied blocks per requestor 1277system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 821.211493 # Average occupied blocks per requestor 1278system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1542.145038 # Average occupied blocks per requestor 1279system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9052.051448 # Average occupied blocks per requestor 1280system.cpu0.l2cache.tags.occ_percent::writebacks 0.289859 # Average percentage of cache occupancy 1281system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy 1282system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 1283system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050123 # Average percentage of cache occupancy 1284system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.094125 # Average percentage of cache occupancy 1285system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.552493 # Average percentage of cache occupancy 1286system.cpu0.l2cache.tags.occ_percent::total 0.986831 # Average percentage of cache occupancy 1287system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8284 # Occupied blocks per task id 1288system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1289system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7219 # Occupied blocks per task id 1290system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1260 # Occupied blocks per task id 1291system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1944 # Occupied blocks per task id 1292system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 5080 # Occupied blocks per task id 1293system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1294system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1295system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1775 # Occupied blocks per task id 1296system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id 1297system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3501 # Occupied blocks per task id 1298system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.505615 # Percentage of cache occupancy per task id 1299system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 1300system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.440613 # Percentage of cache occupancy per task id 1301system.cpu0.l2cache.tags.tag_accesses 17864213 # Number of tag accesses 1302system.cpu0.l2cache.tags.data_accesses 17864213 # Number of data accesses 1303system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4737 # number of ReadReq hits 1304system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2374 # number of ReadReq hits 1305system.cpu0.l2cache.ReadReq_hits::cpu0.inst 361048 # number of ReadReq hits 1306system.cpu0.l2cache.ReadReq_hits::cpu0.data 184302 # number of ReadReq hits 1307system.cpu0.l2cache.ReadReq_hits::total 552461 # number of ReadReq hits 1308system.cpu0.l2cache.Writeback_hits::writebacks 286361 # number of Writeback hits 1309system.cpu0.l2cache.Writeback_hits::total 286361 # number of Writeback hits 1310system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 5612 # number of UpgradeReq hits 1311system.cpu0.l2cache.UpgradeReq_hits::total 5612 # number of UpgradeReq hits 1312system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 831 # number of SCUpgradeReq hits 1313system.cpu0.l2cache.SCUpgradeReq_hits::total 831 # number of SCUpgradeReq hits 1314system.cpu0.l2cache.ReadExReq_hits::cpu0.data 133749 # number of ReadExReq hits 1315system.cpu0.l2cache.ReadExReq_hits::total 133749 # number of ReadExReq hits 1316system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4737 # number of demand (read+write) hits 1317system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2374 # number of demand (read+write) hits 1318system.cpu0.l2cache.demand_hits::cpu0.inst 361048 # number of demand (read+write) hits 1319system.cpu0.l2cache.demand_hits::cpu0.data 318051 # number of demand (read+write) hits 1320system.cpu0.l2cache.demand_hits::total 686210 # number of demand (read+write) hits 1321system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4737 # number of overall hits 1322system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2374 # number of overall hits 1323system.cpu0.l2cache.overall_hits::cpu0.inst 361048 # number of overall hits 1324system.cpu0.l2cache.overall_hits::cpu0.data 318051 # number of overall hits 1325system.cpu0.l2cache.overall_hits::total 686210 # number of overall hits 1326system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses 1327system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses 1328system.cpu0.l2cache.ReadReq_misses::cpu0.inst 8693 # number of ReadReq misses 1329system.cpu0.l2cache.ReadReq_misses::cpu0.data 48360 # number of ReadReq misses 1330system.cpu0.l2cache.ReadReq_misses::total 57424 # number of ReadReq misses 1331system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 1332system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses 1333system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 18405 # number of UpgradeReq misses 1334system.cpu0.l2cache.UpgradeReq_misses::total 18405 # number of UpgradeReq misses 1335system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10323 # number of SCUpgradeReq misses 1336system.cpu0.l2cache.SCUpgradeReq_misses::total 10323 # number of SCUpgradeReq misses 1337system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 1338system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1339system.cpu0.l2cache.ReadExReq_misses::cpu0.data 24100 # number of ReadExReq misses 1340system.cpu0.l2cache.ReadExReq_misses::total 24100 # number of ReadExReq misses 1341system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses 1342system.cpu0.l2cache.demand_misses::cpu0.itb.walker 146 # number of demand (read+write) misses 1343system.cpu0.l2cache.demand_misses::cpu0.inst 8693 # number of demand (read+write) misses 1344system.cpu0.l2cache.demand_misses::cpu0.data 72460 # number of demand (read+write) misses 1345system.cpu0.l2cache.demand_misses::total 81524 # number of demand (read+write) misses 1346system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses 1347system.cpu0.l2cache.overall_misses::cpu0.itb.walker 146 # number of overall misses 1348system.cpu0.l2cache.overall_misses::cpu0.inst 8693 # number of overall misses 1349system.cpu0.l2cache.overall_misses::cpu0.data 72460 # number of overall misses 1350system.cpu0.l2cache.overall_misses::total 81524 # number of overall misses 1351system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4897000 # number of ReadReq miss cycles 1352system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3307000 # number of ReadReq miss cycles 1353system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 300815745 # number of ReadReq miss cycles 1354system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1253383203 # number of ReadReq miss cycles 1355system.cpu0.l2cache.ReadReq_miss_latency::total 1562402948 # number of ReadReq miss cycles 1356system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 288253128 # number of UpgradeReq miss cycles 1357system.cpu0.l2cache.UpgradeReq_miss_latency::total 288253128 # number of UpgradeReq miss cycles 1358system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 204026156 # number of SCUpgradeReq miss cycles 1359system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 204026156 # number of SCUpgradeReq miss cycles 1360system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1056000 # number of SCUpgradeFailReq miss cycles 1361system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1056000 # number of SCUpgradeFailReq miss cycles 1362system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 855610215 # number of ReadExReq miss cycles 1363system.cpu0.l2cache.ReadExReq_miss_latency::total 855610215 # number of ReadExReq miss cycles 1364system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4897000 # number of demand (read+write) miss cycles 1365system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3307000 # number of demand (read+write) miss cycles 1366system.cpu0.l2cache.demand_miss_latency::cpu0.inst 300815745 # number of demand (read+write) miss cycles 1367system.cpu0.l2cache.demand_miss_latency::cpu0.data 2108993418 # number of demand (read+write) miss cycles 1368system.cpu0.l2cache.demand_miss_latency::total 2418013163 # number of demand (read+write) miss cycles 1369system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4897000 # number of overall miss cycles 1370system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3307000 # number of overall miss cycles 1371system.cpu0.l2cache.overall_miss_latency::cpu0.inst 300815745 # number of overall miss cycles 1372system.cpu0.l2cache.overall_miss_latency::cpu0.data 2108993418 # number of overall miss cycles 1373system.cpu0.l2cache.overall_miss_latency::total 2418013163 # number of overall miss cycles 1374system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4962 # number of ReadReq accesses(hits+misses) 1375system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2520 # number of ReadReq accesses(hits+misses) 1376system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 369741 # number of ReadReq accesses(hits+misses) 1377system.cpu0.l2cache.ReadReq_accesses::cpu0.data 232662 # number of ReadReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadReq_accesses::total 609885 # number of ReadReq accesses(hits+misses) 1379system.cpu0.l2cache.Writeback_accesses::writebacks 286363 # number of Writeback accesses(hits+misses) 1380system.cpu0.l2cache.Writeback_accesses::total 286363 # number of Writeback accesses(hits+misses) 1381system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 24017 # number of UpgradeReq accesses(hits+misses) 1382system.cpu0.l2cache.UpgradeReq_accesses::total 24017 # number of UpgradeReq accesses(hits+misses) 1383system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11154 # number of SCUpgradeReq accesses(hits+misses) 1384system.cpu0.l2cache.SCUpgradeReq_accesses::total 11154 # number of SCUpgradeReq accesses(hits+misses) 1385system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1386system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1387system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 157849 # number of ReadExReq accesses(hits+misses) 1388system.cpu0.l2cache.ReadExReq_accesses::total 157849 # number of ReadExReq accesses(hits+misses) 1389system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4962 # number of demand (read+write) accesses 1390system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2520 # number of demand (read+write) accesses 1391system.cpu0.l2cache.demand_accesses::cpu0.inst 369741 # number of demand (read+write) accesses 1392system.cpu0.l2cache.demand_accesses::cpu0.data 390511 # number of demand (read+write) accesses 1393system.cpu0.l2cache.demand_accesses::total 767734 # number of demand (read+write) accesses 1394system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4962 # number of overall (read+write) accesses 1395system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2520 # number of overall (read+write) accesses 1396system.cpu0.l2cache.overall_accesses::cpu0.inst 369741 # number of overall (read+write) accesses 1397system.cpu0.l2cache.overall_accesses::cpu0.data 390511 # number of overall (read+write) accesses 1398system.cpu0.l2cache.overall_accesses::total 767734 # number of overall (read+write) accesses 1399system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for ReadReq accesses 1400system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057937 # miss rate for ReadReq accesses 1401system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.023511 # miss rate for ReadReq accesses 1402system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.207855 # miss rate for ReadReq accesses 1403system.cpu0.l2cache.ReadReq_miss_rate::total 0.094155 # miss rate for ReadReq accesses 1404system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses 1405system.cpu0.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses 1406system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.766332 # miss rate for UpgradeReq accesses 1407system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.766332 # miss rate for UpgradeReq accesses 1408system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.925498 # miss rate for SCUpgradeReq accesses 1409system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.925498 # miss rate for SCUpgradeReq accesses 1410system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1411system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1412system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.152678 # miss rate for ReadExReq accesses 1413system.cpu0.l2cache.ReadExReq_miss_rate::total 0.152678 # miss rate for ReadExReq accesses 1414system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for demand accesses 1415system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057937 # miss rate for demand accesses 1416system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.023511 # miss rate for demand accesses 1417system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185552 # miss rate for demand accesses 1418system.cpu0.l2cache.demand_miss_rate::total 0.106188 # miss rate for demand accesses 1419system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for overall accesses 1420system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057937 # miss rate for overall accesses 1421system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.023511 # miss rate for overall accesses 1422system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185552 # miss rate for overall accesses 1423system.cpu0.l2cache.overall_miss_rate::total 0.106188 # miss rate for overall accesses 1424system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average ReadReq miss latency 1425system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22650.684932 # average ReadReq miss latency 1426system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 34604.365006 # average ReadReq miss latency 1427system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25917.766811 # average ReadReq miss latency 1428system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27208.187308 # average ReadReq miss latency 1429system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15661.674980 # average UpgradeReq miss latency 1430system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15661.674980 # average UpgradeReq miss latency 1431system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19764.230941 # average SCUpgradeReq miss latency 1432system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19764.230941 # average SCUpgradeReq miss latency 1433system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528000 # average SCUpgradeFailReq miss latency 1434system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528000 # average SCUpgradeFailReq miss latency 1435system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 35502.498548 # average ReadExReq miss latency 1436system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35502.498548 # average ReadExReq miss latency 1437system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average overall miss latency 1438system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22650.684932 # average overall miss latency 1439system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34604.365006 # average overall miss latency 1440system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29105.622661 # average overall miss latency 1441system.cpu0.l2cache.demand_avg_miss_latency::total 29660.138892 # average overall miss latency 1442system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average overall miss latency 1443system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22650.684932 # average overall miss latency 1444system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34604.365006 # average overall miss latency 1445system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29105.622661 # average overall miss latency 1446system.cpu0.l2cache.overall_avg_miss_latency::total 29660.138892 # average overall miss latency 1447system.cpu0.l2cache.blocked_cycles::no_mshrs 1020 # number of cycles access was blocked 1448system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1449system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked 1450system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1451system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.903226 # average number of cycles each access was blocked 1452system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1453system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1454system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1455system.cpu0.l2cache.writebacks::writebacks 141584 # number of writebacks 1456system.cpu0.l2cache.writebacks::total 141584 # number of writebacks 1457system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1192 # number of ReadReq MSHR hits 1458system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 751 # number of ReadReq MSHR hits 1459system.cpu0.l2cache.ReadReq_mshr_hits::total 1943 # number of ReadReq MSHR hits 1460system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 493 # number of ReadExReq MSHR hits 1461system.cpu0.l2cache.ReadExReq_mshr_hits::total 493 # number of ReadExReq MSHR hits 1462system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1192 # number of demand (read+write) MSHR hits 1463system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits 1464system.cpu0.l2cache.demand_mshr_hits::total 2436 # number of demand (read+write) MSHR hits 1465system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1192 # number of overall MSHR hits 1466system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits 1467system.cpu0.l2cache.overall_mshr_hits::total 2436 # number of overall MSHR hits 1468system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 225 # number of ReadReq MSHR misses 1469system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 146 # number of ReadReq MSHR misses 1470system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 7501 # number of ReadReq MSHR misses 1471system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 47609 # number of ReadReq MSHR misses 1472system.cpu0.l2cache.ReadReq_mshr_misses::total 55481 # number of ReadReq MSHR misses 1473system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses 1474system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses 1475system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 252027 # number of HardPFReq MSHR misses 1476system.cpu0.l2cache.HardPFReq_mshr_misses::total 252027 # number of HardPFReq MSHR misses 1477system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 18405 # number of UpgradeReq MSHR misses 1478system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18405 # number of UpgradeReq MSHR misses 1479system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10323 # number of SCUpgradeReq MSHR misses 1480system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10323 # number of SCUpgradeReq MSHR misses 1481system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1482system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1483system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 23607 # number of ReadExReq MSHR misses 1484system.cpu0.l2cache.ReadExReq_mshr_misses::total 23607 # number of ReadExReq MSHR misses 1485system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 225 # number of demand (read+write) MSHR misses 1486system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 146 # number of demand (read+write) MSHR misses 1487system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 7501 # number of demand (read+write) MSHR misses 1488system.cpu0.l2cache.demand_mshr_misses::cpu0.data 71216 # number of demand (read+write) MSHR misses 1489system.cpu0.l2cache.demand_mshr_misses::total 79088 # number of demand (read+write) MSHR misses 1490system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 225 # number of overall MSHR misses 1491system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 146 # number of overall MSHR misses 1492system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 7501 # number of overall MSHR misses 1493system.cpu0.l2cache.overall_mshr_misses::cpu0.data 71216 # number of overall MSHR misses 1494system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 252027 # number of overall MSHR misses 1495system.cpu0.l2cache.overall_mshr_misses::total 331115 # number of overall MSHR misses 1496system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of ReadReq MSHR miss cycles 1497system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2285000 # number of ReadReq MSHR miss cycles 1498system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 227161754 # number of ReadReq MSHR miss cycles 1499system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 910924475 # number of ReadReq MSHR miss cycles 1500system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1143693229 # number of ReadReq MSHR miss cycles 1501system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of HardPFReq MSHR miss cycles 1502system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 10450561115 # number of HardPFReq MSHR miss cycles 1503system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 330354697 # number of UpgradeReq MSHR miss cycles 1504system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 330354697 # number of UpgradeReq MSHR miss cycles 1505system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 150011322 # number of SCUpgradeReq MSHR miss cycles 1506system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 150011322 # number of SCUpgradeReq MSHR miss cycles 1507system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 888000 # number of SCUpgradeFailReq MSHR miss cycles 1508system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 888000 # number of SCUpgradeFailReq MSHR miss cycles 1509system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 642746273 # number of ReadExReq MSHR miss cycles 1510system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 642746273 # number of ReadExReq MSHR miss cycles 1511system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of demand (read+write) MSHR miss cycles 1512system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2285000 # number of demand (read+write) MSHR miss cycles 1513system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 227161754 # number of demand (read+write) MSHR miss cycles 1514system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1553670748 # number of demand (read+write) MSHR miss cycles 1515system.cpu0.l2cache.demand_mshr_miss_latency::total 1786439502 # number of demand (read+write) MSHR miss cycles 1516system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of overall MSHR miss cycles 1517system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2285000 # number of overall MSHR miss cycles 1518system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 227161754 # number of overall MSHR miss cycles 1519system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1553670748 # number of overall MSHR miss cycles 1520system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of overall MSHR miss cycles 1521system.cpu0.l2cache.overall_mshr_miss_latency::total 12237000617 # number of overall MSHR miss cycles 1522system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 478295250 # number of ReadReq MSHR uncacheable cycles 1523system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 176453658508 # number of ReadReq MSHR uncacheable cycles 1524system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 176931953758 # number of ReadReq MSHR uncacheable cycles 1525system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1575154999 # number of WriteReq MSHR uncacheable cycles 1526system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1575154999 # number of WriteReq MSHR uncacheable cycles 1527system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 478295250 # number of overall MSHR uncacheable cycles 1528system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 178028813507 # number of overall MSHR uncacheable cycles 1529system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 178507108757 # number of overall MSHR uncacheable cycles 1530system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for ReadReq accesses 1531system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for ReadReq accesses 1532system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for ReadReq accesses 1533system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.204627 # mshr miss rate for ReadReq accesses 1534system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.090970 # mshr miss rate for ReadReq accesses 1535system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses 1536system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses 1537system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1538system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1539system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.766332 # mshr miss rate for UpgradeReq accesses 1540system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.766332 # mshr miss rate for UpgradeReq accesses 1541system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.925498 # mshr miss rate for SCUpgradeReq accesses 1542system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.925498 # mshr miss rate for SCUpgradeReq accesses 1543system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1544system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1545system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149554 # mshr miss rate for ReadExReq accesses 1546system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149554 # mshr miss rate for ReadExReq accesses 1547system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for demand accesses 1548system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for demand accesses 1549system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for demand accesses 1550system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for demand accesses 1551system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103015 # mshr miss rate for demand accesses 1552system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for overall accesses 1553system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for overall accesses 1554system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for overall accesses 1555system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for overall accesses 1556system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1557system.cpu0.l2cache.overall_mshr_miss_rate::total 0.431289 # mshr miss rate for overall accesses 1558system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average ReadReq mshr miss latency 1559system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average ReadReq mshr miss latency 1560system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average ReadReq mshr miss latency 1561system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133 # average ReadReq mshr miss latency 1562system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20614.142301 # average ReadReq mshr miss latency 1563system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average HardPFReq mshr miss latency 1564system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825 # average HardPFReq mshr miss latency 1565system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17949.182124 # average UpgradeReq mshr miss latency 1566system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124 # average UpgradeReq mshr miss latency 1567system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466 # average SCUpgradeReq mshr miss latency 1568system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466 # average SCUpgradeReq mshr miss latency 1569system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 444000 # average SCUpgradeFailReq mshr miss latency 1570system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 444000 # average SCUpgradeFailReq mshr miss latency 1571system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 27226.935782 # average ReadExReq mshr miss latency 1572system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27226.935782 # average ReadExReq mshr miss latency 1573system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average overall mshr miss latency 1574system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency 1575system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency 1576system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency 1577system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22587.996940 # average overall mshr miss latency 1578system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average overall mshr miss latency 1579system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency 1580system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency 1581system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency 1582system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average overall mshr miss latency 1583system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356 # average overall mshr miss latency 1584system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1585system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1586system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1587system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1588system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1589system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1590system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1591system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1592system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1593system.cpu0.dcache.tags.replacements 355829 # number of replacements 1594system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use 1595system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks. 1596system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks. 1597system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks. 1598system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit. 1599system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.967445 # Average occupied blocks per requestor 1600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970640 # Average percentage of cache occupancy 1601system.cpu0.dcache.tags.occ_percent::total 0.970640 # Average percentage of cache occupancy 1602system.cpu0.dcache.tags.occ_task_id_blocks::1024 330 # Occupied blocks per task id 1603system.cpu0.dcache.tags.age_task_id_blocks_1024::2 330 # Occupied blocks per task id 1604system.cpu0.dcache.tags.occ_task_id_percent::1024 0.644531 # Percentage of cache occupancy per task id 1605system.cpu0.dcache.tags.tag_accesses 24668842 # Number of tag accesses 1606system.cpu0.dcache.tags.data_accesses 24668842 # Number of data accesses 1607system.cpu0.dcache.ReadReq_hits::cpu0.data 5548461 # number of ReadReq hits 1608system.cpu0.dcache.ReadReq_hits::total 5548461 # number of ReadReq hits 1609system.cpu0.dcache.WriteReq_hits::cpu0.data 5771889 # number of WriteReq hits 1610system.cpu0.dcache.WriteReq_hits::total 5771889 # number of WriteReq hits 1611system.cpu0.dcache.SoftPFReq_hits::cpu0.data 62661 # number of SoftPFReq hits 1612system.cpu0.dcache.SoftPFReq_hits::total 62661 # number of SoftPFReq hits 1613system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 153118 # number of LoadLockedReq hits 1614system.cpu0.dcache.LoadLockedReq_hits::total 153118 # number of LoadLockedReq hits 1615system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152372 # number of StoreCondReq hits 1616system.cpu0.dcache.StoreCondReq_hits::total 152372 # number of StoreCondReq hits 1617system.cpu0.dcache.demand_hits::cpu0.data 11320350 # number of demand (read+write) hits 1618system.cpu0.dcache.demand_hits::total 11320350 # number of demand (read+write) hits 1619system.cpu0.dcache.overall_hits::cpu0.data 11383011 # number of overall hits 1620system.cpu0.dcache.overall_hits::total 11383011 # number of overall hits 1621system.cpu0.dcache.ReadReq_misses::cpu0.data 178532 # number of ReadReq misses 1622system.cpu0.dcache.ReadReq_misses::total 178532 # number of ReadReq misses 1623system.cpu0.dcache.WriteReq_misses::cpu0.data 183693 # number of WriteReq misses 1624system.cpu0.dcache.WriteReq_misses::total 183693 # number of WriteReq misses 1625system.cpu0.dcache.SoftPFReq_misses::cpu0.data 66756 # number of SoftPFReq misses 1626system.cpu0.dcache.SoftPFReq_misses::total 66756 # number of SoftPFReq misses 1627system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10498 # number of LoadLockedReq misses 1628system.cpu0.dcache.LoadLockedReq_misses::total 10498 # number of LoadLockedReq misses 1629system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11173 # number of StoreCondReq misses 1630system.cpu0.dcache.StoreCondReq_misses::total 11173 # number of StoreCondReq misses 1631system.cpu0.dcache.demand_misses::cpu0.data 362225 # number of demand (read+write) misses 1632system.cpu0.dcache.demand_misses::total 362225 # number of demand (read+write) misses 1633system.cpu0.dcache.overall_misses::cpu0.data 428981 # number of overall misses 1634system.cpu0.dcache.overall_misses::total 428981 # number of overall misses 1635system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2139066005 # number of ReadReq miss cycles 1636system.cpu0.dcache.ReadReq_miss_latency::total 2139066005 # number of ReadReq miss cycles 1637system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 2832298001 # number of WriteReq miss cycles 1638system.cpu0.dcache.WriteReq_miss_latency::total 2832298001 # number of WriteReq miss cycles 1639system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 176126000 # number of LoadLockedReq miss cycles 1640system.cpu0.dcache.LoadLockedReq_miss_latency::total 176126000 # number of LoadLockedReq miss cycles 1641system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 261398841 # number of StoreCondReq miss cycles 1642system.cpu0.dcache.StoreCondReq_miss_latency::total 261398841 # number of StoreCondReq miss cycles 1643system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1128000 # number of StoreCondFailReq miss cycles 1644system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1128000 # number of StoreCondFailReq miss cycles 1645system.cpu0.dcache.demand_miss_latency::cpu0.data 4971364006 # number of demand (read+write) miss cycles 1646system.cpu0.dcache.demand_miss_latency::total 4971364006 # number of demand (read+write) miss cycles 1647system.cpu0.dcache.overall_miss_latency::cpu0.data 4971364006 # number of overall miss cycles 1648system.cpu0.dcache.overall_miss_latency::total 4971364006 # number of overall miss cycles 1649system.cpu0.dcache.ReadReq_accesses::cpu0.data 5726993 # number of ReadReq accesses(hits+misses) 1650system.cpu0.dcache.ReadReq_accesses::total 5726993 # number of ReadReq accesses(hits+misses) 1651system.cpu0.dcache.WriteReq_accesses::cpu0.data 5955582 # number of WriteReq accesses(hits+misses) 1652system.cpu0.dcache.WriteReq_accesses::total 5955582 # number of WriteReq accesses(hits+misses) 1653system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129417 # number of SoftPFReq accesses(hits+misses) 1654system.cpu0.dcache.SoftPFReq_accesses::total 129417 # number of SoftPFReq accesses(hits+misses) 1655system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163616 # number of LoadLockedReq accesses(hits+misses) 1656system.cpu0.dcache.LoadLockedReq_accesses::total 163616 # number of LoadLockedReq accesses(hits+misses) 1657system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 163545 # number of StoreCondReq accesses(hits+misses) 1658system.cpu0.dcache.StoreCondReq_accesses::total 163545 # number of StoreCondReq accesses(hits+misses) 1659system.cpu0.dcache.demand_accesses::cpu0.data 11682575 # number of demand (read+write) accesses 1660system.cpu0.dcache.demand_accesses::total 11682575 # number of demand (read+write) accesses 1661system.cpu0.dcache.overall_accesses::cpu0.data 11811992 # number of overall (read+write) accesses 1662system.cpu0.dcache.overall_accesses::total 11811992 # number of overall (read+write) accesses 1663system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031174 # miss rate for ReadReq accesses 1664system.cpu0.dcache.ReadReq_miss_rate::total 0.031174 # miss rate for ReadReq accesses 1665system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030844 # miss rate for WriteReq accesses 1666system.cpu0.dcache.WriteReq_miss_rate::total 0.030844 # miss rate for WriteReq accesses 1667system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.515821 # miss rate for SoftPFReq accesses 1668system.cpu0.dcache.SoftPFReq_miss_rate::total 0.515821 # miss rate for SoftPFReq accesses 1669system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064162 # miss rate for LoadLockedReq accesses 1670system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064162 # miss rate for LoadLockedReq accesses 1671system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068318 # miss rate for StoreCondReq accesses 1672system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068318 # miss rate for StoreCondReq accesses 1673system.cpu0.dcache.demand_miss_rate::cpu0.data 0.031006 # miss rate for demand accesses 1674system.cpu0.dcache.demand_miss_rate::total 0.031006 # miss rate for demand accesses 1675system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036317 # miss rate for overall accesses 1676system.cpu0.dcache.overall_miss_rate::total 0.036317 # miss rate for overall accesses 1677system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11981.415124 # average ReadReq miss latency 1678system.cpu0.dcache.ReadReq_avg_miss_latency::total 11981.415124 # average ReadReq miss latency 1679system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15418.649600 # average WriteReq miss latency 1680system.cpu0.dcache.WriteReq_avg_miss_latency::total 15418.649600 # average WriteReq miss latency 1681system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16777.100400 # average LoadLockedReq miss latency 1682system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16777.100400 # average LoadLockedReq miss latency 1683system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23395.582297 # average StoreCondReq miss latency 1684system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297 # average StoreCondReq miss latency 1685system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1686system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1687system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13724.519307 # average overall miss latency 1688system.cpu0.dcache.demand_avg_miss_latency::total 13724.519307 # average overall miss latency 1689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11588.774342 # average overall miss latency 1690system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342 # average overall miss latency |
| 1311system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1312system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1313system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1314system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1315system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1316system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1317system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1318system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1697system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1698system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1319system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks 1320system.cpu0.dcache.writebacks::total 305747 # number of writebacks 1321system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits 1322system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits 1323system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 4042 # number of WriteReq MSHR hits 1324system.cpu0.dcache.WriteReq_mshr_hits::total 4042 # number of WriteReq MSHR hits 1325system.cpu0.dcache.demand_mshr_hits::cpu0.data 4318 # number of demand (read+write) MSHR hits 1326system.cpu0.dcache.demand_mshr_hits::total 4318 # number of demand (read+write) MSHR hits 1327system.cpu0.dcache.overall_mshr_hits::cpu0.data 4318 # number of overall MSHR hits 1328system.cpu0.dcache.overall_mshr_hits::total 4318 # number of overall MSHR hits 1329system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 178913 # number of ReadReq MSHR misses 1330system.cpu0.dcache.ReadReq_mshr_misses::total 178913 # number of ReadReq MSHR misses 1331system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141380 # number of WriteReq MSHR misses 1332system.cpu0.dcache.WriteReq_mshr_misses::total 141380 # number of WriteReq MSHR misses 1333system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 48508 # number of SoftPFReq MSHR misses 1334system.cpu0.dcache.SoftPFReq_mshr_misses::total 48508 # number of SoftPFReq MSHR misses 1335system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9439 # number of LoadLockedReq MSHR misses 1336system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9439 # number of LoadLockedReq MSHR misses 1337system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses 1338system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses 1339system.cpu0.dcache.demand_mshr_misses::cpu0.data 320293 # number of demand (read+write) MSHR misses 1340system.cpu0.dcache.demand_mshr_misses::total 320293 # number of demand (read+write) MSHR misses 1341system.cpu0.dcache.overall_mshr_misses::cpu0.data 368801 # number of overall MSHR misses 1342system.cpu0.dcache.overall_mshr_misses::total 368801 # number of overall MSHR misses 1343system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1988652518 # number of ReadReq MSHR miss cycles 1344system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1988652518 # number of ReadReq MSHR miss cycles 1345system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5320324110 # number of WriteReq MSHR miss cycles 1346system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5320324110 # number of WriteReq MSHR miss cycles 1347system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 853626758 # number of SoftPFReq MSHR miss cycles 1348system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 853626758 # number of SoftPFReq MSHR miss cycles 1349system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 75777251 # number of LoadLockedReq MSHR miss cycles 1350system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 75777251 # number of LoadLockedReq MSHR miss cycles 1351system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29483433 # number of StoreCondReq MSHR miss cycles 1352system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29483433 # number of StoreCondReq MSHR miss cycles 1353system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7308976628 # number of demand (read+write) MSHR miss cycles 1354system.cpu0.dcache.demand_mshr_miss_latency::total 7308976628 # number of demand (read+write) MSHR miss cycles 1355system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8162603386 # number of overall MSHR miss cycles 1356system.cpu0.dcache.overall_mshr_miss_latency::total 8162603386 # number of overall MSHR miss cycles 1357system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564535750 # number of ReadReq MSHR uncacheable cycles 1358system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564535750 # number of ReadReq MSHR uncacheable cycles 1359system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170801000 # number of WriteReq MSHR uncacheable cycles 1360system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170801000 # number of WriteReq MSHR uncacheable cycles 1361system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14735336750 # number of overall MSHR uncacheable cycles 1362system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14735336750 # number of overall MSHR uncacheable cycles 1363system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031426 # mshr miss rate for ReadReq accesses 1364system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031426 # mshr miss rate for ReadReq accesses 1365system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses 1366system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses 1367system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.379577 # mshr miss rate for SoftPFReq accesses 1368system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.379577 # mshr miss rate for SoftPFReq accesses 1369system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059944 # mshr miss rate for LoadLockedReq accesses 1370system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059944 # mshr miss rate for LoadLockedReq accesses 1371system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047626 # mshr miss rate for StoreCondReq accesses 1372system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047626 # mshr miss rate for StoreCondReq accesses 1373system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028652 # mshr miss rate for demand accesses 1374system.cpu0.dcache.demand_mshr_miss_rate::total 0.028652 # mshr miss rate for demand accesses 1375system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032618 # mshr miss rate for overall accesses 1376system.cpu0.dcache.overall_mshr_miss_rate::total 0.032618 # mshr miss rate for overall accesses 1377system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960 # average ReadReq mshr miss latency 1378system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960 # average ReadReq mshr miss latency 1379system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210 # average WriteReq mshr miss latency 1380system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210 # average WriteReq mshr miss latency 1381system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006 # average SoftPFReq mshr miss latency 1382system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006 # average SoftPFReq mshr miss latency 1383system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8028.101600 # average LoadLockedReq mshr miss latency 1384system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8028.101600 # average LoadLockedReq mshr miss latency 1385system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3940.055192 # average StoreCondReq mshr miss latency 1386system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3940.055192 # average StoreCondReq mshr miss latency 1387system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713 # average overall mshr miss latency 1388system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713 # average overall mshr miss latency 1389system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509 # average overall mshr miss latency 1390system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509 # average overall mshr miss latency | 1699system.cpu0.dcache.writebacks::writebacks 286365 # number of writebacks 1700system.cpu0.dcache.writebacks::total 286365 # number of writebacks 1701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3418 # number of ReadReq MSHR hits 1702system.cpu0.dcache.ReadReq_mshr_hits::total 3418 # number of ReadReq MSHR hits 1703system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2438 # number of WriteReq MSHR hits 1704system.cpu0.dcache.WriteReq_mshr_hits::total 2438 # number of WriteReq MSHR hits 1705system.cpu0.dcache.demand_mshr_hits::cpu0.data 5856 # number of demand (read+write) MSHR hits 1706system.cpu0.dcache.demand_mshr_hits::total 5856 # number of demand (read+write) MSHR hits 1707system.cpu0.dcache.overall_mshr_hits::cpu0.data 5856 # number of overall MSHR hits 1708system.cpu0.dcache.overall_mshr_hits::total 5856 # number of overall MSHR hits 1709system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 175114 # number of ReadReq MSHR misses 1710system.cpu0.dcache.ReadReq_mshr_misses::total 175114 # number of ReadReq MSHR misses 1711system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 181255 # number of WriteReq MSHR misses 1712system.cpu0.dcache.WriteReq_mshr_misses::total 181255 # number of WriteReq MSHR misses 1713system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 47050 # number of SoftPFReq MSHR misses 1714system.cpu0.dcache.SoftPFReq_mshr_misses::total 47050 # number of SoftPFReq MSHR misses 1715system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 10498 # number of LoadLockedReq MSHR misses 1716system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10498 # number of LoadLockedReq MSHR misses 1717system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11156 # number of StoreCondReq MSHR misses 1718system.cpu0.dcache.StoreCondReq_mshr_misses::total 11156 # number of StoreCondReq MSHR misses 1719system.cpu0.dcache.demand_mshr_misses::cpu0.data 356369 # number of demand (read+write) MSHR misses 1720system.cpu0.dcache.demand_mshr_misses::total 356369 # number of demand (read+write) MSHR misses 1721system.cpu0.dcache.overall_mshr_misses::cpu0.data 403419 # number of overall MSHR misses 1722system.cpu0.dcache.overall_mshr_misses::total 403419 # number of overall MSHR misses 1723system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1737360745 # number of ReadReq MSHR miss cycles 1724system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1737360745 # number of ReadReq MSHR miss cycles 1725system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2335118999 # number of WriteReq MSHR miss cycles 1726system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2335118999 # number of WriteReq MSHR miss cycles 1727system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 699675494 # number of SoftPFReq MSHR miss cycles 1728system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 699675494 # number of SoftPFReq MSHR miss cycles 1729system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 155125000 # number of LoadLockedReq MSHR miss cycles 1730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 155125000 # number of LoadLockedReq MSHR miss cycles 1731system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 237977159 # number of StoreCondReq MSHR miss cycles 1732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 237977159 # number of StoreCondReq MSHR miss cycles 1733system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1080000 # number of StoreCondFailReq MSHR miss cycles 1734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1080000 # number of StoreCondFailReq MSHR miss cycles 1735system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 4072479744 # number of demand (read+write) MSHR miss cycles 1736system.cpu0.dcache.demand_mshr_miss_latency::total 4072479744 # number of demand (read+write) MSHR miss cycles 1737system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4772155238 # number of overall MSHR miss cycles 1738system.cpu0.dcache.overall_mshr_miss_latency::total 4772155238 # number of overall MSHR miss cycles 1739system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990 # number of ReadReq MSHR uncacheable cycles 1740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990 # number of ReadReq MSHR uncacheable cycles 1741system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1669232496 # number of WriteReq MSHR uncacheable cycles 1742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1669232496 # number of WriteReq MSHR uncacheable cycles 1743system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486 # number of overall MSHR uncacheable cycles 1744system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486 # number of overall MSHR uncacheable cycles 1745system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030577 # mshr miss rate for ReadReq accesses 1746system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030577 # mshr miss rate for ReadReq accesses 1747system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030434 # mshr miss rate for WriteReq accesses 1748system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030434 # mshr miss rate for WriteReq accesses 1749system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.363553 # mshr miss rate for SoftPFReq accesses 1750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.363553 # mshr miss rate for SoftPFReq accesses 1751system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064162 # mshr miss rate for LoadLockedReq accesses 1752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses 1753system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.068214 # mshr miss rate for StoreCondReq accesses 1754system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.068214 # mshr miss rate for StoreCondReq accesses 1755system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030504 # mshr miss rate for demand accesses 1756system.cpu0.dcache.demand_mshr_miss_rate::total 0.030504 # mshr miss rate for demand accesses 1757system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034153 # mshr miss rate for overall accesses 1758system.cpu0.dcache.overall_mshr_miss_rate::total 0.034153 # mshr miss rate for overall accesses 1759system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 9921.312659 # average ReadReq mshr miss latency 1760system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9921.312659 # average ReadReq mshr miss latency 1761system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772 # average WriteReq mshr miss latency 1762system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772 # average WriteReq mshr miss latency 1763system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540 # average SoftPFReq mshr miss latency 1764system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency 1765system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119 # average LoadLockedReq mshr miss latency 1766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency 1767system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984 # average StoreCondReq mshr miss latency 1768system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency 1769system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1771system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency 1772system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency 1773system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency 1774system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency |
| 1391system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1392system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1393system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1394system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1395system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1396system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1397system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1775system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1777system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1779system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1781system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1782system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution 1783system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution 1784system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution 1785system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution 1786system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution 1787system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution 1788system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution 1789system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution 1790system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution 1791system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution 1792system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution 1793system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution 1794system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution 1795system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes) 1796system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes) 1797system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes) 1798system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes) 1799system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes) 1800system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes) 1801system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes) 1802system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes) 1803system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes) 1804system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes) 1805system.cpu0.toL2Bus.snoops 631972 # Total snoops (count) 1806system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram 1807system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram 1808system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram 1809system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1810system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1811system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1812system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1813system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1814system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1815system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram 1816system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram 1817system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1818system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1819system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1820system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram 1821system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks) 1822system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1823system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks) 1824system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1825system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks) 1826system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1827system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks) 1828system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1829system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks) 1830system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1831system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks) 1832system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
|
| 1398system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1399system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1400system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1401system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1402system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1403system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1404system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1405system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1413system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1414system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1415system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1416system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1417system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1418system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1419system.cpu1.dtb.inst_hits 0 # ITB inst hits 1420system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1833system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1834system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1835system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1836system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1837system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1838system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1839system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1840system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1848system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1849system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1850system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1851system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1852system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1853system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1854system.cpu1.dtb.inst_hits 0 # ITB inst hits 1855system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1421system.cpu1.dtb.read_hits 7408792 # DTB read hits 1422system.cpu1.dtb.read_misses 3640 # DTB read misses 1423system.cpu1.dtb.write_hits 5825509 # DTB write hits 1424system.cpu1.dtb.write_misses 1435 # DTB write misses | 1856system.cpu1.dtb.read_hits 6599972 # DTB read hits 1857system.cpu1.dtb.read_misses 3720 # DTB read misses 1858system.cpu1.dtb.write_hits 5539858 # DTB write hits 1859system.cpu1.dtb.write_misses 1581 # DTB write misses |
| 1425system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1426system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1427system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1428system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1860system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1861system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1862system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1863system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1429system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB | 1864system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB |
| 1430system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1865system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1431system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch | 1866system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch |
| 1432system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1867system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1433system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1434system.cpu1.dtb.read_accesses 7412432 # DTB read accesses 1435system.cpu1.dtb.write_accesses 5826944 # DTB write accesses | 1868system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1869system.cpu1.dtb.read_accesses 6603692 # DTB read accesses 1870system.cpu1.dtb.write_accesses 5541439 # DTB write accesses |
| 1436system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1871system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1437system.cpu1.dtb.hits 13234301 # DTB hits 1438system.cpu1.dtb.misses 5075 # DTB misses 1439system.cpu1.dtb.accesses 13239376 # DTB accesses | 1872system.cpu1.dtb.hits 12139830 # DTB hits 1873system.cpu1.dtb.misses 5301 # DTB misses 1874system.cpu1.dtb.accesses 12145131 # DTB accesses |
| 1440system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1441system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1442system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1443system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1444system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1445system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1446system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1447system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1453system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1454system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1455system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1456system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1457system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1458system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1459system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1460system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1875system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1876system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1877system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1878system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1879system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1880system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1881system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1882system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1888system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1889system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1890system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1891system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1892system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1893system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1894system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1895system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1461system.cpu1.itb.inst_hits 33190882 # ITB inst hits 1462system.cpu1.itb.inst_misses 2171 # ITB inst misses | 1896system.cpu1.itb.inst_hits 32728613 # ITB inst hits 1897system.cpu1.itb.inst_misses 2200 # ITB inst misses |
| 1463system.cpu1.itb.read_hits 0 # DTB read hits 1464system.cpu1.itb.read_misses 0 # DTB read misses 1465system.cpu1.itb.write_hits 0 # DTB write hits 1466system.cpu1.itb.write_misses 0 # DTB write misses 1467system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1468system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1469system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1470system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1898system.cpu1.itb.read_hits 0 # DTB read hits 1899system.cpu1.itb.read_misses 0 # DTB read misses 1900system.cpu1.itb.write_hits 0 # DTB write hits 1901system.cpu1.itb.write_misses 0 # DTB write misses 1902system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1903system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1904system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1905system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1471system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB | 1906system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB |
| 1472system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1473system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1474system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1475system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1476system.cpu1.itb.read_accesses 0 # DTB read accesses 1477system.cpu1.itb.write_accesses 0 # DTB write accesses | 1907system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1908system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1909system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1910system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1911system.cpu1.itb.read_accesses 0 # DTB read accesses 1912system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1478system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses 1479system.cpu1.itb.hits 33190882 # DTB hits 1480system.cpu1.itb.misses 2171 # DTB misses 1481system.cpu1.itb.accesses 33193053 # DTB accesses 1482system.cpu1.numCycles 2387219429 # number of cpu cycles simulated | 1913system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses 1914system.cpu1.itb.hits 32728613 # DTB hits 1915system.cpu1.itb.misses 2200 # DTB misses 1916system.cpu1.itb.accesses 32730813 # DTB accesses 1917system.cpu1.numCycles 5350361558 # number of cpu cycles simulated |
| 1483system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1484system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1918system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1919system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1485system.cpu1.committedInsts 32579955 # Number of instructions committed 1486system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed 1487system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses 1488system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1489system.cpu1.num_func_calls 962341 # number of times a function call or return occured 1490system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls 1491system.cpu1.num_int_insts 35167643 # number of integer instructions 1492system.cpu1.num_fp_insts 6793 # number of float instructions 1493system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read 1494system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written 1495system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1496system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1497system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read 1498system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written 1499system.cpu1.num_mem_refs 13620676 # number of memory refs 1500system.cpu1.num_load_insts 7578910 # Number of load instructions 1501system.cpu1.num_store_insts 6041766 # Number of store instructions 1502system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles 1503system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles 1504system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles 1505system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles 1506system.cpu1.Branches 4944984 # Number of branches fetched 1507system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction 1508system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction 1509system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction 1510system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction 1511system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction 1512system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction 1513system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction 1514system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction 1515system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction 1516system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction 1517system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction 1518system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction 1519system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction 1520system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction 1521system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction 1522system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction 1523system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction 1524system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction 1525system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction 1526system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction 1527system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction 1528system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction 1529system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction 1530system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction 1531system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction 1532system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction 1533system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction 1534system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction 1535system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction 1536system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction 1537system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction 1538system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction | 1920system.cpu1.committedInsts 32086754 # Number of instructions committed 1921system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed 1922system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses 1923system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 1924system.cpu1.num_func_calls 973285 # number of times a function call or return occured 1925system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls 1926system.cpu1.num_int_insts 33961237 # number of integer instructions 1927system.cpu1.num_fp_insts 4436 # number of float instructions 1928system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read 1929system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written 1930system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 1931system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 1932system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read 1933system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written 1934system.cpu1.num_mem_refs 12531559 # number of memory refs 1935system.cpu1.num_load_insts 6744563 # Number of load instructions 1936system.cpu1.num_store_insts 5786996 # Number of store instructions 1937system.cpu1.num_idle_cycles 5182201093.372063 # Number of idle cycles 1938system.cpu1.num_busy_cycles 168160464.627937 # Number of busy cycles 1939system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles 1940system.cpu1.idle_fraction 0.968570 # Percentage of idle cycles 1941system.cpu1.Branches 5094014 # Number of branches fetched 1942system.cpu1.op_class::No_OpClass 12501 0.03% 0.03% # Class of executed instruction 1943system.cpu1.op_class::IntAlu 25826807 67.22% 67.25% # Class of executed instruction 1944system.cpu1.op_class::IntMult 50699 0.13% 67.38% # Class of executed instruction 1945system.cpu1.op_class::IntDiv 0 0.00% 67.38% # Class of executed instruction 1946system.cpu1.op_class::FloatAdd 0 0.00% 67.38% # Class of executed instruction 1947system.cpu1.op_class::FloatCmp 0 0.00% 67.38% # Class of executed instruction 1948system.cpu1.op_class::FloatCvt 0 0.00% 67.38% # Class of executed instruction 1949system.cpu1.op_class::FloatMult 0 0.00% 67.38% # Class of executed instruction 1950system.cpu1.op_class::FloatDiv 0 0.00% 67.38% # Class of executed instruction 1951system.cpu1.op_class::FloatSqrt 0 0.00% 67.38% # Class of executed instruction 1952system.cpu1.op_class::SimdAdd 0 0.00% 67.38% # Class of executed instruction 1953system.cpu1.op_class::SimdAddAcc 0 0.00% 67.38% # Class of executed instruction 1954system.cpu1.op_class::SimdAlu 0 0.00% 67.38% # Class of executed instruction 1955system.cpu1.op_class::SimdCmp 0 0.00% 67.38% # Class of executed instruction 1956system.cpu1.op_class::SimdCvt 0 0.00% 67.38% # Class of executed instruction 1957system.cpu1.op_class::SimdMisc 0 0.00% 67.38% # Class of executed instruction 1958system.cpu1.op_class::SimdMult 0 0.00% 67.38% # Class of executed instruction 1959system.cpu1.op_class::SimdMultAcc 0 0.00% 67.38% # Class of executed instruction 1960system.cpu1.op_class::SimdShift 0 0.00% 67.38% # Class of executed instruction 1961system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.38% # Class of executed instruction 1962system.cpu1.op_class::SimdSqrt 0 0.00% 67.38% # Class of executed instruction 1963system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.38% # Class of executed instruction 1964system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.38% # Class of executed instruction 1965system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.38% # Class of executed instruction 1966system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.38% # Class of executed instruction 1967system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.38% # Class of executed instruction 1968system.cpu1.op_class::SimdFloatMisc 745 0.00% 67.38% # Class of executed instruction 1969system.cpu1.op_class::SimdFloatMult 0 0.00% 67.38% # Class of executed instruction 1970system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.38% # Class of executed instruction 1971system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.38% # Class of executed instruction 1972system.cpu1.op_class::MemRead 6744563 17.55% 84.94% # Class of executed instruction 1973system.cpu1.op_class::MemWrite 5786996 15.06% 100.00% # Class of executed instruction |
| 1539system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1540system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1974system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1975system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1541system.cpu1.op_class::total 39250579 # Class of executed instruction | 1976system.cpu1.op_class::total 38422311 # Class of executed instruction |
| 1542system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1977system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1543system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed 1544system.cpu1.icache.tags.replacements 469324 # number of replacements 1545system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use 1546system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks. 1547system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks. 1548system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks. 1549system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit. 1550system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor 1551system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934848 # Average percentage of cache occupancy 1552system.cpu1.icache.tags.occ_percent::total 0.934848 # Average percentage of cache occupancy | 1978system.cpu1.kern.inst.quiesce 40934 # number of quiesce instructions executed 1979system.cpu1.icache.tags.replacements 375227 # number of replacements 1980system.cpu1.icache.tags.tagsinuse 498.528279 # Cycle average of tags in use 1981system.cpu1.icache.tags.total_refs 32352870 # Total number of references to valid blocks. 1982system.cpu1.icache.tags.sampled_refs 375739 # Sample count of references to valid blocks. 1983system.cpu1.icache.tags.avg_refs 86.104636 # Average number of references to valid blocks. 1984system.cpu1.icache.tags.warmup_cycle 79843888000 # Cycle when the warmup percentage was hit. 1985system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.528279 # Average occupied blocks per requestor 1986system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973688 # Average percentage of cache occupancy 1987system.cpu1.icache.tags.occ_percent::total 0.973688 # Average percentage of cache occupancy |
| 1553system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1988system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1554system.cpu1.icache.tags.age_task_id_blocks_1024::2 456 # Occupied blocks per task id 1555system.cpu1.icache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id | 1989system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 1990system.cpu1.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 1991system.cpu1.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id 1992system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id |
| 1556system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1993system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1557system.cpu1.icache.tags.tag_accesses 33660714 # Number of tag accesses 1558system.cpu1.icache.tags.data_accesses 33660714 # Number of data accesses 1559system.cpu1.icache.ReadReq_hits::cpu1.inst 32721042 # number of ReadReq hits 1560system.cpu1.icache.ReadReq_hits::total 32721042 # number of ReadReq hits 1561system.cpu1.icache.demand_hits::cpu1.inst 32721042 # number of demand (read+write) hits 1562system.cpu1.icache.demand_hits::total 32721042 # number of demand (read+write) hits 1563system.cpu1.icache.overall_hits::cpu1.inst 32721042 # number of overall hits 1564system.cpu1.icache.overall_hits::total 32721042 # number of overall hits 1565system.cpu1.icache.ReadReq_misses::cpu1.inst 469836 # number of ReadReq misses 1566system.cpu1.icache.ReadReq_misses::total 469836 # number of ReadReq misses 1567system.cpu1.icache.demand_misses::cpu1.inst 469836 # number of demand (read+write) misses 1568system.cpu1.icache.demand_misses::total 469836 # number of demand (read+write) misses 1569system.cpu1.icache.overall_misses::cpu1.inst 469836 # number of overall misses 1570system.cpu1.icache.overall_misses::total 469836 # number of overall misses 1571system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6435695955 # number of ReadReq miss cycles 1572system.cpu1.icache.ReadReq_miss_latency::total 6435695955 # number of ReadReq miss cycles 1573system.cpu1.icache.demand_miss_latency::cpu1.inst 6435695955 # number of demand (read+write) miss cycles 1574system.cpu1.icache.demand_miss_latency::total 6435695955 # number of demand (read+write) miss cycles 1575system.cpu1.icache.overall_miss_latency::cpu1.inst 6435695955 # number of overall miss cycles 1576system.cpu1.icache.overall_miss_latency::total 6435695955 # number of overall miss cycles 1577system.cpu1.icache.ReadReq_accesses::cpu1.inst 33190878 # number of ReadReq accesses(hits+misses) 1578system.cpu1.icache.ReadReq_accesses::total 33190878 # number of ReadReq accesses(hits+misses) 1579system.cpu1.icache.demand_accesses::cpu1.inst 33190878 # number of demand (read+write) accesses 1580system.cpu1.icache.demand_accesses::total 33190878 # number of demand (read+write) accesses 1581system.cpu1.icache.overall_accesses::cpu1.inst 33190878 # number of overall (read+write) accesses 1582system.cpu1.icache.overall_accesses::total 33190878 # number of overall (read+write) accesses 1583system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014156 # miss rate for ReadReq accesses 1584system.cpu1.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses 1585system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014156 # miss rate for demand accesses 1586system.cpu1.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses 1587system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014156 # miss rate for overall accesses 1588system.cpu1.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses 1589system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757 # average ReadReq miss latency 1590system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757 # average ReadReq miss latency 1591system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency 1592system.cpu1.icache.demand_avg_miss_latency::total 13697.749757 # average overall miss latency 1593system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency 1594system.cpu1.icache.overall_avg_miss_latency::total 13697.749757 # average overall miss latency | 1994system.cpu1.icache.tags.tag_accesses 65832957 # Number of tag accesses 1995system.cpu1.icache.tags.data_accesses 65832957 # Number of data accesses 1996system.cpu1.icache.ReadReq_hits::cpu1.inst 32352870 # number of ReadReq hits 1997system.cpu1.icache.ReadReq_hits::total 32352870 # number of ReadReq hits 1998system.cpu1.icache.demand_hits::cpu1.inst 32352870 # number of demand (read+write) hits 1999system.cpu1.icache.demand_hits::total 32352870 # number of demand (read+write) hits 2000system.cpu1.icache.overall_hits::cpu1.inst 32352870 # number of overall hits 2001system.cpu1.icache.overall_hits::total 32352870 # number of overall hits 2002system.cpu1.icache.ReadReq_misses::cpu1.inst 375739 # number of ReadReq misses 2003system.cpu1.icache.ReadReq_misses::total 375739 # number of ReadReq misses 2004system.cpu1.icache.demand_misses::cpu1.inst 375739 # number of demand (read+write) misses 2005system.cpu1.icache.demand_misses::total 375739 # number of demand (read+write) misses 2006system.cpu1.icache.overall_misses::cpu1.inst 375739 # number of overall misses 2007system.cpu1.icache.overall_misses::total 375739 # number of overall misses 2008system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3159151510 # number of ReadReq miss cycles 2009system.cpu1.icache.ReadReq_miss_latency::total 3159151510 # number of ReadReq miss cycles 2010system.cpu1.icache.demand_miss_latency::cpu1.inst 3159151510 # number of demand (read+write) miss cycles 2011system.cpu1.icache.demand_miss_latency::total 3159151510 # number of demand (read+write) miss cycles 2012system.cpu1.icache.overall_miss_latency::cpu1.inst 3159151510 # number of overall miss cycles 2013system.cpu1.icache.overall_miss_latency::total 3159151510 # number of overall miss cycles 2014system.cpu1.icache.ReadReq_accesses::cpu1.inst 32728609 # number of ReadReq accesses(hits+misses) 2015system.cpu1.icache.ReadReq_accesses::total 32728609 # number of ReadReq accesses(hits+misses) 2016system.cpu1.icache.demand_accesses::cpu1.inst 32728609 # number of demand (read+write) accesses 2017system.cpu1.icache.demand_accesses::total 32728609 # number of demand (read+write) accesses 2018system.cpu1.icache.overall_accesses::cpu1.inst 32728609 # number of overall (read+write) accesses 2019system.cpu1.icache.overall_accesses::total 32728609 # number of overall (read+write) accesses 2020system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011480 # miss rate for ReadReq accesses 2021system.cpu1.icache.ReadReq_miss_rate::total 0.011480 # miss rate for ReadReq accesses 2022system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011480 # miss rate for demand accesses 2023system.cpu1.icache.demand_miss_rate::total 0.011480 # miss rate for demand accesses 2024system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011480 # miss rate for overall accesses 2025system.cpu1.icache.overall_miss_rate::total 0.011480 # miss rate for overall accesses 2026system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8407.834987 # average ReadReq miss latency 2027system.cpu1.icache.ReadReq_avg_miss_latency::total 8407.834987 # average ReadReq miss latency 2028system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency 2029system.cpu1.icache.demand_avg_miss_latency::total 8407.834987 # average overall miss latency 2030system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency 2031system.cpu1.icache.overall_avg_miss_latency::total 8407.834987 # average overall miss latency |
| 1595system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1596system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1597system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1598system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1599system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1600system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1601system.cpu1.icache.fast_writes 0 # number of fast writes performed 1602system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2032system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2033system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2034system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2035system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 2036system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2037system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2038system.cpu1.icache.fast_writes 0 # number of fast writes performed 2039system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1603system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469836 # number of ReadReq MSHR misses 1604system.cpu1.icache.ReadReq_mshr_misses::total 469836 # number of ReadReq MSHR misses 1605system.cpu1.icache.demand_mshr_misses::cpu1.inst 469836 # number of demand (read+write) MSHR misses 1606system.cpu1.icache.demand_mshr_misses::total 469836 # number of demand (read+write) MSHR misses 1607system.cpu1.icache.overall_mshr_misses::cpu1.inst 469836 # number of overall MSHR misses 1608system.cpu1.icache.overall_mshr_misses::total 469836 # number of overall MSHR misses 1609system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5494111045 # number of ReadReq MSHR miss cycles 1610system.cpu1.icache.ReadReq_mshr_miss_latency::total 5494111045 # number of ReadReq MSHR miss cycles 1611system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5494111045 # number of demand (read+write) MSHR miss cycles 1612system.cpu1.icache.demand_mshr_miss_latency::total 5494111045 # number of demand (read+write) MSHR miss cycles 1613system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5494111045 # number of overall MSHR miss cycles 1614system.cpu1.icache.overall_mshr_miss_latency::total 5494111045 # number of overall MSHR miss cycles 1615system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6835750 # number of ReadReq MSHR uncacheable cycles 1616system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6835750 # number of ReadReq MSHR uncacheable cycles 1617system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6835750 # number of overall MSHR uncacheable cycles 1618system.cpu1.icache.overall_mshr_uncacheable_latency::total 6835750 # number of overall MSHR uncacheable cycles 1619system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for ReadReq accesses 1620system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses 1621system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for demand accesses 1622system.cpu1.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses 1623system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for overall accesses 1624system.cpu1.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses 1625system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average ReadReq mshr miss latency 1626system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11693.678315 # average ReadReq mshr miss latency 1627system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency 1628system.cpu1.icache.demand_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency 1629system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency 1630system.cpu1.icache.overall_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency | 2040system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 375739 # number of ReadReq MSHR misses 2041system.cpu1.icache.ReadReq_mshr_misses::total 375739 # number of ReadReq MSHR misses 2042system.cpu1.icache.demand_mshr_misses::cpu1.inst 375739 # number of demand (read+write) MSHR misses 2043system.cpu1.icache.demand_mshr_misses::total 375739 # number of demand (read+write) MSHR misses 2044system.cpu1.icache.overall_mshr_misses::cpu1.inst 375739 # number of overall MSHR misses 2045system.cpu1.icache.overall_mshr_misses::total 375739 # number of overall MSHR misses 2046system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2595414990 # number of ReadReq MSHR miss cycles 2047system.cpu1.icache.ReadReq_mshr_miss_latency::total 2595414990 # number of ReadReq MSHR miss cycles 2048system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2595414990 # number of demand (read+write) MSHR miss cycles 2049system.cpu1.icache.demand_mshr_miss_latency::total 2595414990 # number of demand (read+write) MSHR miss cycles 2050system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2595414990 # number of overall MSHR miss cycles 2051system.cpu1.icache.overall_mshr_miss_latency::total 2595414990 # number of overall MSHR miss cycles 2052system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8511750 # number of ReadReq MSHR uncacheable cycles 2053system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8511750 # number of ReadReq MSHR uncacheable cycles 2054system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8511750 # number of overall MSHR uncacheable cycles 2055system.cpu1.icache.overall_mshr_uncacheable_latency::total 8511750 # number of overall MSHR uncacheable cycles 2056system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for ReadReq accesses 2057system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011480 # mshr miss rate for ReadReq accesses 2058system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for demand accesses 2059system.cpu1.icache.demand_mshr_miss_rate::total 0.011480 # mshr miss rate for demand accesses 2060system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for overall accesses 2061system.cpu1.icache.overall_mshr_miss_rate::total 0.011480 # mshr miss rate for overall accesses 2062system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average ReadReq mshr miss latency 2063system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6907.494271 # average ReadReq mshr miss latency 2064system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency 2065system.cpu1.icache.demand_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency 2066system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency 2067system.cpu1.icache.overall_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency |
| 1631system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1632system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1633system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1634system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1635system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2068system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2069system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2070system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2071system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2072system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1636system.cpu1.dcache.tags.replacements 292234 # number of replacements 1637system.cpu1.dcache.tags.tagsinuse 471.923930 # Cycle average of tags in use 1638system.cpu1.dcache.tags.total_refs 11040887 # Total number of references to valid blocks. 1639system.cpu1.dcache.tags.sampled_refs 292603 # Sample count of references to valid blocks. 1640system.cpu1.dcache.tags.avg_refs 37.733335 # Average number of references to valid blocks. 1641system.cpu1.dcache.tags.warmup_cycle 84705826250 # Cycle when the warmup percentage was hit. 1642system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.923930 # Average occupied blocks per requestor 1643system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921726 # Average percentage of cache occupancy 1644system.cpu1.dcache.tags.occ_percent::total 0.921726 # Average percentage of cache occupancy 1645system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id 1646system.cpu1.dcache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id 1647system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1648system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id 1649system.cpu1.dcache.tags.tag_accesses 45818347 # Number of tag accesses 1650system.cpu1.dcache.tags.data_accesses 45818347 # Number of data accesses 1651system.cpu1.dcache.ReadReq_hits::cpu1.data 6006097 # number of ReadReq hits 1652system.cpu1.dcache.ReadReq_hits::total 6006097 # number of ReadReq hits 1653system.cpu1.dcache.WriteReq_hits::cpu1.data 4823101 # number of WriteReq hits 1654system.cpu1.dcache.WriteReq_hits::total 4823101 # number of WriteReq hits 1655system.cpu1.dcache.SoftPFReq_hits::cpu1.data 22483 # number of SoftPFReq hits 1656system.cpu1.dcache.SoftPFReq_hits::total 22483 # number of SoftPFReq hits 1657system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81936 # number of LoadLockedReq hits 1658system.cpu1.dcache.LoadLockedReq_hits::total 81936 # number of LoadLockedReq hits 1659system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82707 # number of StoreCondReq hits 1660system.cpu1.dcache.StoreCondReq_hits::total 82707 # number of StoreCondReq hits 1661system.cpu1.dcache.demand_hits::cpu1.data 10829198 # number of demand (read+write) hits 1662system.cpu1.dcache.demand_hits::total 10829198 # number of demand (read+write) hits 1663system.cpu1.dcache.overall_hits::cpu1.data 10851681 # number of overall hits 1664system.cpu1.dcache.overall_hits::total 10851681 # number of overall hits 1665system.cpu1.dcache.ReadReq_misses::cpu1.data 144053 # number of ReadReq misses 1666system.cpu1.dcache.ReadReq_misses::total 144053 # number of ReadReq misses 1667system.cpu1.dcache.WriteReq_misses::cpu1.data 152082 # number of WriteReq misses 1668system.cpu1.dcache.WriteReq_misses::total 152082 # number of WriteReq misses 1669system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41875 # number of SoftPFReq misses 1670system.cpu1.dcache.SoftPFReq_misses::total 41875 # number of SoftPFReq misses 1671system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11222 # number of LoadLockedReq misses 1672system.cpu1.dcache.LoadLockedReq_misses::total 11222 # number of LoadLockedReq misses 1673system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10064 # number of StoreCondReq misses 1674system.cpu1.dcache.StoreCondReq_misses::total 10064 # number of StoreCondReq misses 1675system.cpu1.dcache.demand_misses::cpu1.data 296135 # number of demand (read+write) misses 1676system.cpu1.dcache.demand_misses::total 296135 # number of demand (read+write) misses 1677system.cpu1.dcache.overall_misses::cpu1.data 338010 # number of overall misses 1678system.cpu1.dcache.overall_misses::total 338010 # number of overall misses 1679system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1718496498 # number of ReadReq miss cycles 1680system.cpu1.dcache.ReadReq_miss_latency::total 1718496498 # number of ReadReq miss cycles 1681system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6437170330 # number of WriteReq miss cycles 1682system.cpu1.dcache.WriteReq_miss_latency::total 6437170330 # number of WriteReq miss cycles 1683system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96291249 # number of LoadLockedReq miss cycles 1684system.cpu1.dcache.LoadLockedReq_miss_latency::total 96291249 # number of LoadLockedReq miss cycles 1685system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52005971 # number of StoreCondReq miss cycles 1686system.cpu1.dcache.StoreCondReq_miss_latency::total 52005971 # number of StoreCondReq miss cycles 1687system.cpu1.dcache.demand_miss_latency::cpu1.data 8155666828 # number of demand (read+write) miss cycles 1688system.cpu1.dcache.demand_miss_latency::total 8155666828 # number of demand (read+write) miss cycles 1689system.cpu1.dcache.overall_miss_latency::cpu1.data 8155666828 # number of overall miss cycles 1690system.cpu1.dcache.overall_miss_latency::total 8155666828 # number of overall miss cycles 1691system.cpu1.dcache.ReadReq_accesses::cpu1.data 6150150 # number of ReadReq accesses(hits+misses) 1692system.cpu1.dcache.ReadReq_accesses::total 6150150 # number of ReadReq accesses(hits+misses) 1693system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975183 # number of WriteReq accesses(hits+misses) 1694system.cpu1.dcache.WriteReq_accesses::total 4975183 # number of WriteReq accesses(hits+misses) 1695system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 64358 # number of SoftPFReq accesses(hits+misses) 1696system.cpu1.dcache.SoftPFReq_accesses::total 64358 # number of SoftPFReq accesses(hits+misses) 1697system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93158 # number of LoadLockedReq accesses(hits+misses) 1698system.cpu1.dcache.LoadLockedReq_accesses::total 93158 # number of LoadLockedReq accesses(hits+misses) 1699system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92771 # number of StoreCondReq accesses(hits+misses) 1700system.cpu1.dcache.StoreCondReq_accesses::total 92771 # number of StoreCondReq accesses(hits+misses) 1701system.cpu1.dcache.demand_accesses::cpu1.data 11125333 # number of demand (read+write) accesses 1702system.cpu1.dcache.demand_accesses::total 11125333 # number of demand (read+write) accesses 1703system.cpu1.dcache.overall_accesses::cpu1.data 11189691 # number of overall (read+write) accesses 1704system.cpu1.dcache.overall_accesses::total 11189691 # number of overall (read+write) accesses 1705system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023423 # miss rate for ReadReq accesses 1706system.cpu1.dcache.ReadReq_miss_rate::total 0.023423 # miss rate for ReadReq accesses 1707system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030568 # miss rate for WriteReq accesses 1708system.cpu1.dcache.WriteReq_miss_rate::total 0.030568 # miss rate for WriteReq accesses 1709system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.650657 # miss rate for SoftPFReq accesses 1710system.cpu1.dcache.SoftPFReq_miss_rate::total 0.650657 # miss rate for SoftPFReq accesses 1711system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120462 # miss rate for LoadLockedReq accesses 1712system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120462 # miss rate for LoadLockedReq accesses 1713system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108482 # miss rate for StoreCondReq accesses 1714system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108482 # miss rate for StoreCondReq accesses 1715system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026618 # miss rate for demand accesses 1716system.cpu1.dcache.demand_miss_rate::total 0.026618 # miss rate for demand accesses 1717system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030207 # miss rate for overall accesses 1718system.cpu1.dcache.overall_miss_rate::total 0.030207 # miss rate for overall accesses 1719system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698 # average ReadReq miss latency 1720system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698 # average ReadReq miss latency 1721system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516 # average WriteReq miss latency 1722system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516 # average WriteReq miss latency 1723system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8580.578239 # average LoadLockedReq miss latency 1724system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8580.578239 # average LoadLockedReq miss latency 1725system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5167.524940 # average StoreCondReq miss latency 1726system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5167.524940 # average StoreCondReq miss latency 1727system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832 # average overall miss latency 1728system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832 # average overall miss latency 1729system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939 # average overall miss latency 1730system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939 # average overall miss latency 1731system.cpu1.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked | 2073system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 3539349 # number of hwpf identified 2074system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 109722 # number of hwpf that were already in mshr 2075system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3291325 # number of hwpf that were already in the cache 2076system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 217 # number of hwpf that were already in the prefetch queue 2077system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 2078system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 15 # number of hwpf removed because MSHR allocated 2079system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 138070 # number of hwpf issued 2080system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 329563 # number of hwpf spanning a virtual page 2081system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 2082system.cpu1.l2cache.tags.replacements 122650 # number of replacements 2083system.cpu1.l2cache.tags.tagsinuse 15477.303394 # Cycle average of tags in use 2084system.cpu1.l2cache.tags.total_refs 769651 # Total number of references to valid blocks. 2085system.cpu1.l2cache.tags.sampled_refs 138796 # Sample count of references to valid blocks. 2086system.cpu1.l2cache.tags.avg_refs 5.545196 # Average number of references to valid blocks. 2087system.cpu1.l2cache.tags.warmup_cycle 2606454315500 # Cycle when the warmup percentage was hit. 2088system.cpu1.l2cache.tags.occ_blocks::writebacks 5482.269126 # Average occupied blocks per requestor 2089system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.040765 # Average occupied blocks per requestor 2090system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.187836 # Average occupied blocks per requestor 2091system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 603.787912 # Average occupied blocks per requestor 2092system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2723.851785 # Average occupied blocks per requestor 2093system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6655.165971 # Average occupied blocks per requestor 2094system.cpu1.l2cache.tags.occ_percent::writebacks 0.334611 # Average percentage of cache occupancy 2095system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000735 # Average percentage of cache occupancy 2096system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000011 # Average percentage of cache occupancy 2097system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036852 # Average percentage of cache occupancy 2098system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.166251 # Average percentage of cache occupancy 2099system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.406199 # Average percentage of cache occupancy 2100system.cpu1.l2cache.tags.occ_percent::total 0.944660 # Average percentage of cache occupancy 2101system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7087 # Occupied blocks per task id 2102system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 2103system.cpu1.l2cache.tags.occ_task_id_blocks::1024 9051 # Occupied blocks per task id 2104system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id 2105system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id 2106system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 481 # Occupied blocks per task id 2107system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4215 # Occupied blocks per task id 2108system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2330 # Occupied blocks per task id 2109system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 2110system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 2111system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 2112system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 2113system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 2114system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1744 # Occupied blocks per task id 2115system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5747 # Occupied blocks per task id 2116system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id 2117system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.432556 # Percentage of cache occupancy per task id 2118system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 2119system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.552429 # Percentage of cache occupancy per task id 2120system.cpu1.l2cache.tags.tag_accesses 16022455 # Number of tag accesses 2121system.cpu1.l2cache.tags.data_accesses 16022455 # Number of data accesses 2122system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 6174 # number of ReadReq hits 2123system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2268 # number of ReadReq hits 2124system.cpu1.l2cache.ReadReq_hits::cpu1.inst 369218 # number of ReadReq hits 2125system.cpu1.l2cache.ReadReq_hits::cpu1.data 169436 # number of ReadReq hits 2126system.cpu1.l2cache.ReadReq_hits::total 547096 # number of ReadReq hits 2127system.cpu1.l2cache.Writeback_hits::writebacks 225255 # number of Writeback hits 2128system.cpu1.l2cache.Writeback_hits::total 225255 # number of Writeback hits 2129system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1340 # number of UpgradeReq hits 2130system.cpu1.l2cache.UpgradeReq_hits::total 1340 # number of UpgradeReq hits 2131system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits 2132system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits 2133system.cpu1.l2cache.ReadExReq_hits::cpu1.data 86607 # number of ReadExReq hits 2134system.cpu1.l2cache.ReadExReq_hits::total 86607 # number of ReadExReq hits 2135system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 6174 # number of demand (read+write) hits 2136system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2268 # number of demand (read+write) hits 2137system.cpu1.l2cache.demand_hits::cpu1.inst 369218 # number of demand (read+write) hits 2138system.cpu1.l2cache.demand_hits::cpu1.data 256043 # number of demand (read+write) hits 2139system.cpu1.l2cache.demand_hits::total 633703 # number of demand (read+write) hits 2140system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 6174 # number of overall hits 2141system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2268 # number of overall hits 2142system.cpu1.l2cache.overall_hits::cpu1.inst 369218 # number of overall hits 2143system.cpu1.l2cache.overall_hits::cpu1.data 256043 # number of overall hits 2144system.cpu1.l2cache.overall_hits::total 633703 # number of overall hits 2145system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 268 # number of ReadReq misses 2146system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 169 # number of ReadReq misses 2147system.cpu1.l2cache.ReadReq_misses::cpu1.inst 6377 # number of ReadReq misses 2148system.cpu1.l2cache.ReadReq_misses::cpu1.data 56923 # number of ReadReq misses 2149system.cpu1.l2cache.ReadReq_misses::total 63737 # number of ReadReq misses 2150system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20417 # number of UpgradeReq misses 2151system.cpu1.l2cache.UpgradeReq_misses::total 20417 # number of UpgradeReq misses 2152system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 12784 # number of SCUpgradeReq misses 2153system.cpu1.l2cache.SCUpgradeReq_misses::total 12784 # number of SCUpgradeReq misses 2154system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 2155system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 2156system.cpu1.l2cache.ReadExReq_misses::cpu1.data 23524 # number of ReadExReq misses 2157system.cpu1.l2cache.ReadExReq_misses::total 23524 # number of ReadExReq misses 2158system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 268 # number of demand (read+write) misses 2159system.cpu1.l2cache.demand_misses::cpu1.itb.walker 169 # number of demand (read+write) misses 2160system.cpu1.l2cache.demand_misses::cpu1.inst 6377 # number of demand (read+write) misses 2161system.cpu1.l2cache.demand_misses::cpu1.data 80447 # number of demand (read+write) misses 2162system.cpu1.l2cache.demand_misses::total 87261 # number of demand (read+write) misses 2163system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 268 # number of overall misses 2164system.cpu1.l2cache.overall_misses::cpu1.itb.walker 169 # number of overall misses 2165system.cpu1.l2cache.overall_misses::cpu1.inst 6377 # number of overall misses 2166system.cpu1.l2cache.overall_misses::cpu1.data 80447 # number of overall misses 2167system.cpu1.l2cache.overall_misses::total 87261 # number of overall misses 2168system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5694000 # number of ReadReq miss cycles 2169system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3369000 # number of ReadReq miss cycles 2170system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191106990 # number of ReadReq miss cycles 2171system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1462989443 # number of ReadReq miss cycles 2172system.cpu1.l2cache.ReadReq_miss_latency::total 1663159433 # number of ReadReq miss cycles 2173system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 341145571 # number of UpgradeReq miss cycles 2174system.cpu1.l2cache.UpgradeReq_miss_latency::total 341145571 # number of UpgradeReq miss cycles 2175system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 259918262 # number of SCUpgradeReq miss cycles 2176system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 259918262 # number of SCUpgradeReq miss cycles 2177system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 478999 # number of SCUpgradeFailReq miss cycles 2178system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 478999 # number of SCUpgradeFailReq miss cycles 2179system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 892976093 # number of ReadExReq miss cycles 2180system.cpu1.l2cache.ReadExReq_miss_latency::total 892976093 # number of ReadExReq miss cycles 2181system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5694000 # number of demand (read+write) miss cycles 2182system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3369000 # number of demand (read+write) miss cycles 2183system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191106990 # number of demand (read+write) miss cycles 2184system.cpu1.l2cache.demand_miss_latency::cpu1.data 2355965536 # number of demand (read+write) miss cycles 2185system.cpu1.l2cache.demand_miss_latency::total 2556135526 # number of demand (read+write) miss cycles 2186system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5694000 # number of overall miss cycles 2187system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3369000 # number of overall miss cycles 2188system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191106990 # number of overall miss cycles 2189system.cpu1.l2cache.overall_miss_latency::cpu1.data 2355965536 # number of overall miss cycles 2190system.cpu1.l2cache.overall_miss_latency::total 2556135526 # number of overall miss cycles 2191system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6442 # number of ReadReq accesses(hits+misses) 2192system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2437 # number of ReadReq accesses(hits+misses) 2193system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 375595 # number of ReadReq accesses(hits+misses) 2194system.cpu1.l2cache.ReadReq_accesses::cpu1.data 226359 # number of ReadReq accesses(hits+misses) 2195system.cpu1.l2cache.ReadReq_accesses::total 610833 # number of ReadReq accesses(hits+misses) 2196system.cpu1.l2cache.Writeback_accesses::writebacks 225255 # number of Writeback accesses(hits+misses) 2197system.cpu1.l2cache.Writeback_accesses::total 225255 # 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number of demand (read+write) accesses 2208system.cpu1.l2cache.demand_accesses::cpu1.inst 375595 # number of demand (read+write) accesses 2209system.cpu1.l2cache.demand_accesses::cpu1.data 336490 # number of demand (read+write) accesses 2210system.cpu1.l2cache.demand_accesses::total 720964 # number of demand (read+write) accesses 2211system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6442 # number of overall (read+write) accesses 2212system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2437 # number of overall (read+write) accesses 2213system.cpu1.l2cache.overall_accesses::cpu1.inst 375595 # number of overall (read+write) accesses 2214system.cpu1.l2cache.overall_accesses::cpu1.data 336490 # number of overall (read+write) accesses 2215system.cpu1.l2cache.overall_accesses::total 720964 # number of overall (read+write) accesses 2216system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for ReadReq accesses 2217system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.069348 # miss rate for ReadReq accesses 2218system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.016978 # miss rate for ReadReq accesses 2219system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.251472 # miss rate for ReadReq accesses 2220system.cpu1.l2cache.ReadReq_miss_rate::total 0.104344 # miss rate for ReadReq accesses 2221system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938411 # miss rate for UpgradeReq accesses 2222system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938411 # miss rate for UpgradeReq accesses 2223system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.935255 # miss rate for SCUpgradeReq accesses 2224system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.935255 # miss rate for SCUpgradeReq accesses 2225system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2226system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2227system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.213600 # miss rate for ReadExReq accesses 2228system.cpu1.l2cache.ReadExReq_miss_rate::total 0.213600 # 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average ReadReq miss latency 2240system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19934.911243 # average ReadReq miss latency 2241system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29968.165281 # average ReadReq miss latency 2242system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 25701.200622 # average ReadReq miss latency 2243system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26094.096569 # average ReadReq miss latency 2244system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16708.898026 # average UpgradeReq miss latency 2245system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16708.898026 # average UpgradeReq miss latency 2246system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20331.528630 # average SCUpgradeReq miss latency 2247system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20331.528630 # average SCUpgradeReq miss latency 2248system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 239499.500000 # average SCUpgradeFailReq miss latency 2249system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 239499.500000 # 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average overall miss latency 2260system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29285.934044 # average overall miss latency 2261system.cpu1.l2cache.overall_avg_miss_latency::total 29292.989148 # average overall miss latency 2262system.cpu1.l2cache.blocked_cycles::no_mshrs 579 # number of cycles access was blocked 2263system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2264system.cpu1.l2cache.blocked::no_mshrs 19 # number of cycles access was blocked 2265system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2266system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.473684 # average number of cycles each access was blocked 2267system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2268system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2269system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2270system.cpu1.l2cache.writebacks::writebacks 66455 # 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number of overall MSHR misses 2304system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 169 # number of overall MSHR misses 2305system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 5610 # number of overall MSHR misses 2306system.cpu1.l2cache.overall_mshr_misses::cpu1.data 79023 # number of overall MSHR misses 2307system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 138069 # number of overall MSHR misses 2308system.cpu1.l2cache.overall_mshr_misses::total 223139 # number of overall MSHR misses 2309system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of ReadReq MSHR miss cycles 2310system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2186000 # number of ReadReq MSHR miss cycles 2311system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 137414260 # number of ReadReq MSHR miss cycles 2312system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1062900207 # number of ReadReq MSHR miss cycles 2313system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206317967 # 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number of overall MSHR miss cycles 2332system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1654304086 # number of overall MSHR miss cycles 2333system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7048181570 # number of overall MSHR miss cycles 2334system.cpu1.l2cache.overall_mshr_miss_latency::total 8845903416 # number of overall MSHR miss cycles 2335system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7648750 # number of ReadReq MSHR uncacheable cycles 2336system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 12231230753 # number of ReadReq MSHR uncacheable cycles 2337system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 12238879503 # number of ReadReq MSHR uncacheable cycles 2338system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 28539732155 # number of WriteReq MSHR uncacheable cycles 2339system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28539732155 # number of WriteReq MSHR uncacheable cycles 2340system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7648750 # number of overall MSHR uncacheable cycles 2341system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 40770962908 # number of overall MSHR uncacheable cycles 2342system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 40778611658 # number of overall MSHR uncacheable cycles 2343system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for ReadReq accesses 2344system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for ReadReq accesses 2345system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for ReadReq accesses 2346system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.251119 # mshr miss rate for ReadReq accesses 2347system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.102958 # mshr miss rate for ReadReq accesses 2348system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2349system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2350system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938411 # mshr miss rate for UpgradeReq accesses 2351system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses 2352system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935255 # mshr miss rate for SCUpgradeReq accesses 2353system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.935255 # mshr miss rate for SCUpgradeReq accesses 2354system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2355system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2356system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.201397 # mshr miss rate for ReadExReq accesses 2357system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.201397 # mshr miss rate for ReadExReq accesses 2358system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for demand accesses 2359system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for demand accesses 2360system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for demand accesses 2361system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for demand accesses 2362system.cpu1.l2cache.demand_mshr_miss_rate::total 0.117995 # mshr miss rate for demand accesses 2363system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for overall accesses 2364system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for overall accesses 2365system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for overall accesses 2366system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for overall accesses 2367system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2368system.cpu1.l2cache.overall_mshr_miss_rate::total 0.309501 # mshr miss rate for overall accesses 2369system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average ReadReq mshr miss latency 2370system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average ReadReq mshr miss latency 2371system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average ReadReq mshr miss latency 2372system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 18698.875974 # average ReadReq mshr miss latency 2373system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 19181.395564 # average ReadReq mshr miss latency 2374system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average HardPFReq mshr miss latency 2375system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365 # average HardPFReq mshr miss latency 2376system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832 # average UpgradeReq mshr miss latency 2377system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency 2378system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726 # average SCUpgradeReq mshr miss latency 2379system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726 # average SCUpgradeReq mshr miss latency 2380system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000 # average SCUpgradeFailReq mshr miss latency 2381system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000 # average SCUpgradeFailReq mshr miss latency 2382system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843 # average ReadExReq mshr miss latency 2383system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # average ReadExReq mshr miss latency 2384system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency 2385system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency 2386system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency 2387system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency 2388system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21132.265734 # average overall mshr miss latency 2389system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency 2390system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency 2391system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency 2392system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency 2393system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average overall mshr miss latency 2394system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101 # average overall mshr miss latency 2395system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2396system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2397system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2398system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2399system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2400system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2401system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2402system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2403system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2404system.cpu1.dcache.tags.replacements 313601 # number of replacements 2405system.cpu1.dcache.tags.tagsinuse 474.302028 # Cycle average of tags in use 2406system.cpu1.dcache.tags.total_refs 10949850 # Total number of references to valid blocks. 2407system.cpu1.dcache.tags.sampled_refs 314113 # Sample count of references to valid blocks. 2408system.cpu1.dcache.tags.avg_refs 34.859589 # Average number of references to valid blocks. 2409system.cpu1.dcache.tags.warmup_cycle 76456711000 # Cycle when the warmup percentage was hit. 2410system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.302028 # Average occupied blocks per requestor 2411system.cpu1.dcache.tags.occ_percent::cpu1.data 0.926371 # Average percentage of cache occupancy 2412system.cpu1.dcache.tags.occ_percent::total 0.926371 # Average percentage of cache occupancy 2413system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2414system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 2415system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id 2416system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id 2417system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2418system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses 2419system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses 2420system.cpu1.dcache.ReadReq_hits::cpu1.data 6183420 # number of ReadReq hits 2421system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits 2422system.cpu1.dcache.WriteReq_hits::cpu1.data 4558750 # number of WriteReq hits 2423system.cpu1.dcache.WriteReq_hits::total 4558750 # number of WriteReq hits 2424system.cpu1.dcache.SoftPFReq_hits::cpu1.data 19290 # number of SoftPFReq hits 2425system.cpu1.dcache.SoftPFReq_hits::total 19290 # number of SoftPFReq hits 2426system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77402 # number of LoadLockedReq hits 2427system.cpu1.dcache.LoadLockedReq_hits::total 77402 # number of LoadLockedReq hits 2428system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75753 # number of StoreCondReq hits 2429system.cpu1.dcache.StoreCondReq_hits::total 75753 # number of StoreCondReq hits 2430system.cpu1.dcache.demand_hits::cpu1.data 10742170 # number of demand (read+write) hits 2431system.cpu1.dcache.demand_hits::total 10742170 # number of demand (read+write) hits 2432system.cpu1.dcache.overall_hits::cpu1.data 10761460 # number of overall hits 2433system.cpu1.dcache.overall_hits::total 10761460 # number of overall hits 2434system.cpu1.dcache.ReadReq_misses::cpu1.data 187243 # number of ReadReq misses 2435system.cpu1.dcache.ReadReq_misses::total 187243 # number of ReadReq misses 2436system.cpu1.dcache.WriteReq_misses::cpu1.data 134937 # number of WriteReq misses 2437system.cpu1.dcache.WriteReq_misses::total 134937 # number of WriteReq misses 2438system.cpu1.dcache.SoftPFReq_misses::cpu1.data 43327 # number of SoftPFReq misses 2439system.cpu1.dcache.SoftPFReq_misses::total 43327 # number of SoftPFReq misses 2440system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12089 # number of LoadLockedReq misses 2441system.cpu1.dcache.LoadLockedReq_misses::total 12089 # number of LoadLockedReq misses 2442system.cpu1.dcache.StoreCondReq_misses::cpu1.data 13673 # number of StoreCondReq misses 2443system.cpu1.dcache.StoreCondReq_misses::total 13673 # number of StoreCondReq misses 2444system.cpu1.dcache.demand_misses::cpu1.data 322180 # number of demand (read+write) misses 2445system.cpu1.dcache.demand_misses::total 322180 # number of demand (read+write) misses 2446system.cpu1.dcache.overall_misses::cpu1.data 365507 # number of overall misses 2447system.cpu1.dcache.overall_misses::total 365507 # number of overall misses 2448system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2299329756 # number of ReadReq miss cycles 2449system.cpu1.dcache.ReadReq_miss_latency::total 2299329756 # number of ReadReq miss cycles 2450system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2509975628 # number of WriteReq miss cycles 2451system.cpu1.dcache.WriteReq_miss_latency::total 2509975628 # number of WriteReq miss cycles 2452system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 218034000 # number of LoadLockedReq miss cycles 2453system.cpu1.dcache.LoadLockedReq_miss_latency::total 218034000 # number of LoadLockedReq miss cycles 2454system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 317344970 # number of StoreCondReq miss cycles 2455system.cpu1.dcache.StoreCondReq_miss_latency::total 317344970 # number of StoreCondReq miss cycles 2456system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 524000 # number of StoreCondFailReq miss cycles 2457system.cpu1.dcache.StoreCondFailReq_miss_latency::total 524000 # number of StoreCondFailReq miss cycles 2458system.cpu1.dcache.demand_miss_latency::cpu1.data 4809305384 # number of demand (read+write) miss cycles 2459system.cpu1.dcache.demand_miss_latency::total 4809305384 # number of demand (read+write) miss cycles 2460system.cpu1.dcache.overall_miss_latency::cpu1.data 4809305384 # number of overall miss cycles 2461system.cpu1.dcache.overall_miss_latency::total 4809305384 # number of overall miss cycles 2462system.cpu1.dcache.ReadReq_accesses::cpu1.data 6370663 # number of ReadReq accesses(hits+misses) 2463system.cpu1.dcache.ReadReq_accesses::total 6370663 # number of ReadReq accesses(hits+misses) 2464system.cpu1.dcache.WriteReq_accesses::cpu1.data 4693687 # number of WriteReq accesses(hits+misses) 2465system.cpu1.dcache.WriteReq_accesses::total 4693687 # number of WriteReq accesses(hits+misses) 2466system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 62617 # number of SoftPFReq accesses(hits+misses) 2467system.cpu1.dcache.SoftPFReq_accesses::total 62617 # number of SoftPFReq accesses(hits+misses) 2468system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89491 # number of LoadLockedReq accesses(hits+misses) 2469system.cpu1.dcache.LoadLockedReq_accesses::total 89491 # number of LoadLockedReq accesses(hits+misses) 2470system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89426 # number of StoreCondReq accesses(hits+misses) 2471system.cpu1.dcache.StoreCondReq_accesses::total 89426 # number of StoreCondReq accesses(hits+misses) 2472system.cpu1.dcache.demand_accesses::cpu1.data 11064350 # number of demand (read+write) accesses 2473system.cpu1.dcache.demand_accesses::total 11064350 # number of demand (read+write) accesses 2474system.cpu1.dcache.overall_accesses::cpu1.data 11126967 # number of overall (read+write) accesses 2475system.cpu1.dcache.overall_accesses::total 11126967 # number of overall (read+write) accesses 2476system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029391 # miss rate for ReadReq accesses 2477system.cpu1.dcache.ReadReq_miss_rate::total 0.029391 # miss rate for ReadReq accesses 2478system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028749 # miss rate for WriteReq accesses 2479system.cpu1.dcache.WriteReq_miss_rate::total 0.028749 # miss rate for WriteReq accesses 2480system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.691937 # miss rate for SoftPFReq accesses 2481system.cpu1.dcache.SoftPFReq_miss_rate::total 0.691937 # miss rate for SoftPFReq accesses 2482system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135086 # miss rate for LoadLockedReq accesses 2483system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135086 # miss rate for LoadLockedReq accesses 2484system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.152897 # miss rate for StoreCondReq accesses 2485system.cpu1.dcache.StoreCondReq_miss_rate::total 0.152897 # miss rate for StoreCondReq accesses 2486system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029119 # miss rate for demand accesses 2487system.cpu1.dcache.demand_miss_rate::total 0.029119 # miss rate for demand accesses 2488system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032849 # miss rate for overall accesses 2489system.cpu1.dcache.overall_miss_rate::total 0.032849 # miss rate for overall accesses 2490system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency 2491system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency 2492system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency 2493system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency 2494system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966 # average LoadLockedReq miss latency 2495system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency 2496system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987 # average StoreCondReq miss latency 2497system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency 2498system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2499system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2500system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency 2501system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency 2502system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency 2503system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency 2504system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1732system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2505system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1733system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked | 2506system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1734system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 2507system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1735system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked | 2508system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1736system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1737system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1738system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2509system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2510system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2511system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1739system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks 1740system.cpu1.dcache.writebacks::total 264973 # number of writebacks 1741system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits 1742system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits 1743system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits 1744system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits 1745system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits 1746system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits 1747system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits 1748system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits 1749system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses 1750system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses 1751system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses 1752system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses 1753system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses 1754system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses 1755system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses 1756system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses 1757system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses 1758system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses 1759system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses 1760system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses 1761system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses 1762system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses 1763system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles 1764system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles 1765system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles 1766system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles 1767system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles 1768system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles 1769system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles 1770system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles 1771system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles 1772system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles 1773system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles 1774system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles 1775system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles 1776system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles 1777system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles 1778system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles 1779system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles 1780system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles 1781system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles 1782system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles 1783system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses 1784system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses 1785system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses 1786system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses 1787system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses 1788system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses 1789system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses 1790system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses 1791system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses 1792system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses 1793system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses 1794system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses 1795system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses 1796system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses 1797system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency 1798system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency 1799system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency 1800system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency 1801system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency 1802system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency 1803system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency 1804system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency 1805system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency 1806system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency 1807system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency 1808system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency 1809system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency 1810system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency | 2512system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks 2513system.cpu1.dcache.writebacks::total 225255 # number of writebacks 2514system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits 2515system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits 2516system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits 2517system.cpu1.dcache.WriteReq_mshr_hits::total 3242 # number of WriteReq MSHR hits 2518system.cpu1.dcache.demand_mshr_hits::cpu1.data 4036 # number of demand (read+write) MSHR hits 2519system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits 2520system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits 2521system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits 2522system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 186449 # number of ReadReq MSHR misses 2523system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses 2524system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 131695 # number of WriteReq MSHR misses 2525system.cpu1.dcache.WriteReq_mshr_misses::total 131695 # number of WriteReq MSHR misses 2526system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 27821 # number of SoftPFReq MSHR misses 2527system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses 2528system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses 2529system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12089 # number of LoadLockedReq MSHR misses 2530system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses 2531system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses 2532system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses 2533system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses 2534system.cpu1.dcache.overall_mshr_misses::cpu1.data 345965 # number of overall MSHR misses 2535system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses 2536system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles 2537system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1916001744 # number of ReadReq MSHR miss cycles 2538system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles 2539system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2027549872 # number of WriteReq MSHR miss cycles 2540system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 596503999 # number of SoftPFReq MSHR miss cycles 2541system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 596503999 # number of SoftPFReq MSHR miss cycles 2542system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles 2543system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles 2544system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 289002030 # number of StoreCondReq MSHR miss cycles 2545system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 289002030 # number of StoreCondReq MSHR miss cycles 2546system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 494000 # number of StoreCondFailReq MSHR miss cycles 2547system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 494000 # number of StoreCondFailReq MSHR miss cycles 2548system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles 2549system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles 2550system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles 2551system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles 2552system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles 2553system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles 2554system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles 2555system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles 2556system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 47062844087 # number of overall MSHR uncacheable cycles 2557system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles 2558system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses 2559system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses 2560system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses 2561system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028058 # mshr miss rate for WriteReq accesses 2562system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses 2563system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses 2564system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses 2565system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses 2566system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.152875 # mshr miss rate for StoreCondReq accesses 2567system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses 2568system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028754 # mshr miss rate for demand accesses 2569system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses 2570system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses 2571system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses 2572system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency 2573system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency 2574system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency 2575system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency 2576system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency 2577system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency 2578system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency 2579system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency 2580system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency 2581system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency 2582system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2583system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2584system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency 2585system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency 2586system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency 2587system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency |
| 1811system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1812system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1813system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1814system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1815system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1816system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1817system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2588system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2589system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2590system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2591system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2592system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2593system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2594system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2595system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution 2596system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution 2597system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution 2598system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution 2599system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution 2600system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution 2601system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution 2602system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution 2603system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution 2604system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution 2605system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution 2606system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution 2607system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution 2608system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes) 2609system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes) 2610system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes) 2611system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes) 2612system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes) 2613system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes) 2614system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes) 2615system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes) 2616system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes) 2617system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes) 2618system.cpu1.toL2Bus.snoops 549743 # Total snoops (count) 2619system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram 2620system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram 2621system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram 2622system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2623system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2624system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2625system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2626system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2627system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2628system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram 2629system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram 2630system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2631system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2632system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2633system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram 2634system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks) 2635system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2636system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks) 2637system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2638system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks) 2639system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2640system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks) 2641system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2642system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks) 2643system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2644system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks) 2645system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
|
| 1818system.iocache.tags.replacements 0 # number of replacements 1819system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1820system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1821system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1822system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1823system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1824system.iocache.tags.tag_accesses 0 # Number of tag accesses 1825system.iocache.tags.data_accesses 0 # Number of data accesses 1826system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1827system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1828system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1829system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1830system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1831system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1832system.iocache.fast_writes 0 # number of fast writes performed 1833system.iocache.cache_copies 0 # number of cache copies performed | 2646system.iocache.tags.replacements 0 # number of replacements 2647system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 2648system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2649system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2650system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2651system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2652system.iocache.tags.tag_accesses 0 # Number of tag accesses 2653system.iocache.tags.data_accesses 0 # Number of data accesses 2654system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2655system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2656system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2657system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2658system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2659system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2660system.iocache.fast_writes 0 # number of fast writes performed 2661system.iocache.cache_copies 0 # number of cache copies performed |
| 1834system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles 1835system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles 1836system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles 1837system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles | 2662system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles 2663system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles 2664system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles 2665system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles |
| 1838system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1839system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1840system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1841system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1842system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1843 1844---------- End Simulation Statistics ---------- | 2666system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2667system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2668system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2669system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2670system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2671 2672---------- End Simulation Statistics ---------- |