| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.196225 # Number of seconds simulated 4sim_ticks 1196225147500 # Number of ticks simulated 5final_tick 1196225147500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.195945 # Number of seconds simulated 4sim_ticks 1195945260000 # Number of ticks simulated 5final_tick 1195945260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 669591 # Simulator instruction rate (inst/s) 8host_op_rate 853186 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13029857543 # Simulator tick rate (ticks/s) 10host_mem_usage 426076 # Number of bytes of host memory used 11host_seconds 91.81 # Real time elapsed on the host 12sim_insts 61472758 # Number of instructions simulated 13sim_ops 78327958 # Number of ops (including micro ops) simulated | 7host_inst_rate 424891 # Simulator instruction rate (inst/s) 8host_op_rate 541366 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8267957779 # Simulator tick rate (ticks/s) 10host_mem_usage 468940 # Number of bytes of host memory used 11host_seconds 144.65 # Real time elapsed on the host 12sim_insts 61459750 # Number of instructions simulated 13sim_ops 78307634 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) | |
| 34system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory |
| 36system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 378508 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 4532924 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 393612 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 4714684 # Number of bytes read from this memory |
| 39system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory |
| 40system.physmem.bytes_read::cpu1.inst 337988 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.data 4964984 # Number of bytes read from this memory 42system.physmem.bytes_read::total 62119428 # Number of bytes read from this memory 43system.physmem.bytes_inst_read::cpu0.inst 378508 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::cpu1.inst 337988 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::total 716496 # Number of instructions bytes read from this memory 46system.physmem.bytes_written::writebacks 4092288 # Number of bytes written to this memory | 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 4804472 # Number of bytes read from this memory 25system.physmem.bytes_read::total 62142468 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 393612 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 718288 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 4110592 # Number of bytes written to this memory |
| 47system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 48system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 30system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 49system.physmem.bytes_written::total 7119632 # Number of bytes written to this memory | 32system.physmem.bytes_written::total 7137936 # Number of bytes written to this memory |
| 50system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory | 33system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory |
| 52system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.inst 12142 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu0.data 70901 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 12378 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 73741 # Number of read requests responded to by this memory |
| 55system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory | 38system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory |
| 56system.physmem.num_reads::cpu1.inst 5372 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.data 77606 # Number of read requests responded to by this memory 58system.physmem.num_reads::total 6654093 # Number of read requests responded to by this memory 59system.physmem.num_writes::writebacks 63942 # Number of write requests responded to by this memory | 39system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 75098 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 6654453 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 64228 # Number of write requests responded to by this memory |
| 60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 61system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 44system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 62system.physmem.num_writes::total 820778 # Number of write requests responded to by this memory 63system.physmem.bw_read::realview.clcd 43390253 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.num_writes::total 821064 # Number of write requests responded to by this memory 47system.physmem.bw_read::realview.clcd 43400408 # Total read bandwidth from this memory (bytes/s) |
| 64system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) |
| 65system.physmem.bw_read::cpu0.itb.walker 161 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.inst 316419 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.data 3789357 # Total read bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 329122 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 3942224 # Total read bandwidth from this memory (bytes/s) |
| 68system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) | 52system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_read::cpu1.inst 282545 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.data 4150543 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::total 51929545 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::cpu0.inst 316419 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_inst_read::cpu1.inst 282545 # Instruction read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::total 598964 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_write::writebacks 3421001 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::cpu0.data 14211 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_write::cpu1.data 2516536 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::total 5951749 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_total::writebacks 3421001 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::realview.clcd 43390253 # Total bandwidth to/from this memory (bytes/s) | 53system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.inst 271481 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.data 4017301 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 51960963 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 329122 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 271481 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 600603 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 3437107 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 14215 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 2517125 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 5968447 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 3437107 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.clcd 43400408 # Total bandwidth to/from this memory (bytes/s) |
| 81system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) |
| 82system.physmem.bw_total::cpu0.itb.walker 161 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu0.inst 316419 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.data 3803568 # Total bandwidth to/from this memory (bytes/s) | 67system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 329122 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 3956439 # Total bandwidth to/from this memory (bytes/s) |
| 85system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) |
| 86system.physmem.bw_total::cpu1.inst 282545 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.data 6667079 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::total 57881294 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.readReqs 6654093 # Number of read requests accepted 90system.physmem.writeReqs 820778 # Number of write requests accepted 91system.physmem.readBursts 6654093 # Number of DRAM read bursts, including those serviced by the write queue 92system.physmem.writeBursts 820778 # Number of DRAM write bursts, including those merged in the write queue 93system.physmem.bytesReadDRAM 425823936 # Total number of bytes read from DRAM 94system.physmem.bytesReadWrQ 38016 # Total number of bytes read from write queue 95system.physmem.bytesWritten 7142848 # Total number of bytes written to DRAM 96system.physmem.bytesReadSys 62119428 # Total read bytes from the system interface side 97system.physmem.bytesWrittenSys 7119632 # Total written bytes from the system interface side 98system.physmem.servicedByWrQ 594 # Number of DRAM read bursts serviced by the write queue 99system.physmem.mergedWrBursts 709146 # Number of DRAM write bursts merged with an existing one 100system.physmem.neitherReadNorWriteReqs 11979 # Number of requests that are neither read nor write 101system.physmem.perBankRdBursts::0 415258 # Per bank write bursts 102system.physmem.perBankRdBursts::1 415304 # Per bank write bursts 103system.physmem.perBankRdBursts::2 415298 # Per bank write bursts 104system.physmem.perBankRdBursts::3 415715 # Per bank write bursts 105system.physmem.perBankRdBursts::4 422332 # Per bank write bursts 106system.physmem.perBankRdBursts::5 415542 # Per bank write bursts 107system.physmem.perBankRdBursts::6 415821 # Per bank write bursts 108system.physmem.perBankRdBursts::7 415579 # Per bank write bursts 109system.physmem.perBankRdBursts::8 415943 # Per bank write bursts 110system.physmem.perBankRdBursts::9 415582 # Per bank write bursts 111system.physmem.perBankRdBursts::10 415396 # Per bank write bursts 112system.physmem.perBankRdBursts::11 414885 # Per bank write bursts 113system.physmem.perBankRdBursts::12 414891 # Per bank write bursts 114system.physmem.perBankRdBursts::13 415396 # Per bank write bursts 115system.physmem.perBankRdBursts::14 415532 # Per bank write bursts 116system.physmem.perBankRdBursts::15 415025 # Per bank write bursts 117system.physmem.perBankWrBursts::0 6797 # Per bank write bursts 118system.physmem.perBankWrBursts::1 6838 # Per bank write bursts 119system.physmem.perBankWrBursts::2 6874 # Per bank write bursts 120system.physmem.perBankWrBursts::3 7108 # Per bank write bursts 121system.physmem.perBankWrBursts::4 7245 # Per bank write bursts 122system.physmem.perBankWrBursts::5 7088 # Per bank write bursts 123system.physmem.perBankWrBursts::6 7332 # Per bank write bursts 124system.physmem.perBankWrBursts::7 7150 # Per bank write bursts 125system.physmem.perBankWrBursts::8 7392 # Per bank write bursts 126system.physmem.perBankWrBursts::9 7114 # Per bank write bursts 127system.physmem.perBankWrBursts::10 7008 # Per bank write bursts 128system.physmem.perBankWrBursts::11 6578 # Per bank write bursts 129system.physmem.perBankWrBursts::12 6732 # Per bank write bursts 130system.physmem.perBankWrBursts::13 6801 # Per bank write bursts 131system.physmem.perBankWrBursts::14 7004 # Per bank write bursts 132system.physmem.perBankWrBursts::15 6546 # Per bank write bursts | 71system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 271481 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.data 6534426 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 57929411 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 6654453 # Number of read requests accepted 76system.physmem.writeReqs 821064 # Number of write requests accepted 77system.physmem.readBursts 6654453 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 821064 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 425841472 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 43520 # Total number of bytes read from write queue 81system.physmem.bytesWritten 7149184 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 62142468 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 7137936 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 680 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 709327 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 12098 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 415328 # Per bank write bursts 88system.physmem.perBankRdBursts::1 415212 # Per bank write bursts 89system.physmem.perBankRdBursts::2 415403 # Per bank write bursts 90system.physmem.perBankRdBursts::3 415611 # Per bank write bursts 91system.physmem.perBankRdBursts::4 422397 # Per bank write bursts 92system.physmem.perBankRdBursts::5 415577 # Per bank write bursts 93system.physmem.perBankRdBursts::6 415747 # Per bank write bursts 94system.physmem.perBankRdBursts::7 415496 # Per bank write bursts 95system.physmem.perBankRdBursts::8 416027 # Per bank write bursts 96system.physmem.perBankRdBursts::9 415632 # Per bank write bursts 97system.physmem.perBankRdBursts::10 415426 # Per bank write bursts 98system.physmem.perBankRdBursts::11 414842 # Per bank write bursts 99system.physmem.perBankRdBursts::12 414820 # Per bank write bursts 100system.physmem.perBankRdBursts::13 415557 # Per bank write bursts 101system.physmem.perBankRdBursts::14 415554 # Per bank write bursts 102system.physmem.perBankRdBursts::15 415144 # Per bank write bursts 103system.physmem.perBankWrBursts::0 6840 # Per bank write bursts 104system.physmem.perBankWrBursts::1 6732 # Per bank write bursts 105system.physmem.perBankWrBursts::2 6969 # Per bank write bursts 106system.physmem.perBankWrBursts::3 7025 # Per bank write bursts 107system.physmem.perBankWrBursts::4 7326 # Per bank write bursts 108system.physmem.perBankWrBursts::5 7107 # Per bank write bursts 109system.physmem.perBankWrBursts::6 7317 # Per bank write bursts 110system.physmem.perBankWrBursts::7 7078 # Per bank write bursts 111system.physmem.perBankWrBursts::8 7464 # Per bank write bursts 112system.physmem.perBankWrBursts::9 7155 # Per bank write bursts 113system.physmem.perBankWrBursts::10 7023 # Per bank write bursts 114system.physmem.perBankWrBursts::11 6543 # Per bank write bursts 115system.physmem.perBankWrBursts::12 6616 # Per bank write bursts 116system.physmem.perBankWrBursts::13 6901 # Per bank write bursts 117system.physmem.perBankWrBursts::14 6977 # Per bank write bursts 118system.physmem.perBankWrBursts::15 6633 # Per bank write bursts |
| 133system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 134system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 120system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 135system.physmem.totGap 1196220625500 # Total gap between requests | 121system.physmem.totGap 1195940759000 # Total gap between requests |
| 136system.physmem.readPktSize::0 0 # Read request sizes (log2) 137system.physmem.readPktSize::1 0 # Read request sizes (log2) 138system.physmem.readPktSize::2 6849 # Read request sizes (log2) 139system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 140system.physmem.readPktSize::4 0 # Read request sizes (log2) 141system.physmem.readPktSize::5 0 # Read request sizes (log2) | 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 6849 # Read request sizes (log2) 125system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 142system.physmem.readPktSize::6 159180 # Read request sizes (log2) | 128system.physmem.readPktSize::6 159540 # Read request sizes (log2) |
| 143system.physmem.writePktSize::0 0 # Write request sizes (log2) 144system.physmem.writePktSize::1 0 # Write request sizes (log2) 145system.physmem.writePktSize::2 756836 # Write request sizes (log2) 146system.physmem.writePktSize::3 0 # Write request sizes (log2) 147system.physmem.writePktSize::4 0 # Write request sizes (log2) 148system.physmem.writePktSize::5 0 # Write request sizes (log2) | 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 756836 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 149system.physmem.writePktSize::6 63942 # Write request sizes (log2) 150system.physmem.rdQLenPdf::0 568386 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::1 406756 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::2 406740 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::3 413202 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::4 408903 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::5 410926 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::6 1188562 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::7 1189774 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::8 1562236 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::9 22558 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::10 14685 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::11 15166 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::12 13714 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::13 12546 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::14 9828 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::15 9386 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see | 135system.physmem.writePktSize::6 64228 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 572493 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 410656 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 412880 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 461685 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 417933 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 446395 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 1149366 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 1113988 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 1438120 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 64577 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 50343 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 45843 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 44044 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 8771 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 8319 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 8183 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 162 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see |
| 168system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 197system.physmem.wrQLenPdf::15 2656 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::16 2719 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::17 3656 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::18 5124 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::19 5129 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::20 5125 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::21 5127 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::24 5159 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::25 6206 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::26 5353 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::27 5316 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::28 6283 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::29 5251 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::30 5231 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::31 5217 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::32 5137 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::34 1090 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::35 1087 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::36 1087 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::38 1076 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::39 1074 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::40 1072 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::41 1074 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::42 1072 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::43 1070 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::44 1069 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::45 1069 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::46 1067 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::47 1067 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::48 1065 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::49 1065 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::50 1064 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::51 1064 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::52 1064 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::53 1064 # What write queue length does an incoming req see | 183system.physmem.wrQLenPdf::15 3947 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 4027 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 6482 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 6483 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 6487 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 6490 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 6486 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 6486 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 6484 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 6500 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 6486 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 6488 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 6485 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| 236system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 222system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 246system.physmem.bytesPerActivate::samples 427748 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::mean 996.884371 # Bytes accessed per row activation 248system.physmem.bytesPerActivate::gmean 962.233746 # Bytes accessed per row activation 249system.physmem.bytesPerActivate::stdev 147.681447 # Bytes accessed per row activation 250system.physmem.bytesPerActivate::0-127 5003 1.17% 1.17% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::128-255 3928 0.92% 2.09% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::256-383 2092 0.49% 2.58% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::384-511 1312 0.31% 2.88% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::512-639 1079 0.25% 3.14% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::640-767 787 0.18% 3.32% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::768-895 742 0.17% 3.49% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::896-1023 447 0.10% 3.60% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::1024-1151 412358 96.40% 100.00% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::total 427748 # Bytes accessed per row activation 260system.physmem.rdPerTurnAround::samples 5121 # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::mean 1299.254638 # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::stdev 29808.283067 # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::0-65535 5114 99.86% 99.86% # Reads before turning the bus around for writes 264system.physmem.rdPerTurnAround::196608-262143 3 0.06% 99.92% # Reads before turning the bus around for writes 265system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.94% # Reads before turning the bus around for writes 266system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.96% # Reads before turning the bus around for writes 267system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 268system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 269system.physmem.rdPerTurnAround::total 5121 # Reads before turning the bus around for writes 270system.physmem.wrPerTurnAround::samples 5121 # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::mean 21.793986 # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::gmean 20.383938 # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::stdev 9.006526 # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::16 2131 41.61% 41.61% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::17 296 5.78% 47.39% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::18 286 5.58% 52.98% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::19 1314 25.66% 78.64% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::20 15 0.29% 78.93% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::21 5 0.10% 79.03% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::22 2 0.04% 79.07% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::24 2 0.04% 79.11% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::25 1 0.02% 79.13% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::28 3 0.06% 79.18% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::34 1 0.02% 79.20% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::35 1 0.02% 79.22% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::39 953 18.61% 97.83% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::40 61 1.19% 99.02% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::41 17 0.33% 99.36% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::42 33 0.64% 100.00% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::total 5121 # Writes before turning the bus around for reads 291system.physmem.totQLat 249828830750 # Total ticks spent queuing 292system.physmem.totMemAccLat 297299498250 # Total ticks spent from burst creation until serviced by the DRAM 293system.physmem.totBusLat 33267495000 # Total ticks spent in databus transfers 294system.physmem.totBankLat 14203172500 # Total ticks spent accessing banks 295system.physmem.avgQLat 37548.49 # Average queueing delay per DRAM burst 296system.physmem.avgBankLat 2134.69 # Average bank access latency per DRAM burst | 232system.physmem.bytesPerActivate::samples 473596 # Bytes accessed per row activation 233system.physmem.bytesPerActivate::mean 914.261641 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::gmean 784.047795 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::stdev 289.306705 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::0-127 25239 5.33% 5.33% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::128-255 21585 4.56% 9.89% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::256-383 5945 1.26% 11.14% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::384-511 2453 0.52% 11.66% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::512-639 2290 0.48% 12.14% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::640-767 1636 0.35% 12.49% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::768-895 4075 0.86% 13.35% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::896-1023 899 0.19% 13.54% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1024-1151 409474 86.46% 100.00% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::total 473596 # Bytes accessed per row activation 246system.physmem.rdPerTurnAround::samples 6482 # Reads before turning the bus around for writes 247system.physmem.rdPerTurnAround::mean 1026.497532 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::stdev 34346.134147 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::0-131071 6476 99.91% 99.91% # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::131072-262143 3 0.05% 99.95% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::524288-655359 1 0.02% 99.97% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::786432-917503 1 0.02% 99.98% # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::total 6482 # Reads before turning the bus around for writes 255system.physmem.wrPerTurnAround::samples 6482 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::mean 17.233261 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::gmean 17.205432 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::stdev 0.970583 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::16 2453 37.84% 37.84% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::17 80 1.23% 39.08% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::18 3936 60.72% 99.80% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::19 11 0.17% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::20 1 0.02% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 6482 # Writes before turning the bus around for reads 266system.physmem.totQLat 171035006500 # Total ticks spent queuing 267system.physmem.totMemAccLat 295793250250 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 33268865000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 25704.97 # Average queueing delay per DRAM burst |
| 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 298system.physmem.avgMemAccLat 44683.18 # Average memory access latency per DRAM burst 299system.physmem.avgRdBW 355.97 # Average DRAM read bandwidth in MiByte/s 300system.physmem.avgWrBW 5.97 # Average achieved write bandwidth in MiByte/s 301system.physmem.avgRdBWSys 51.93 # Average system read bandwidth in MiByte/s 302system.physmem.avgWrBWSys 5.95 # Average system write bandwidth in MiByte/s | 271system.physmem.avgMemAccLat 44454.97 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 356.07 # Average DRAM read bandwidth in MiByte/s 273system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s 274system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s 275system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s |
| 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 2.83 # Data bus utilization in percentage 305system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes | 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 277system.physmem.busUtil 2.83 # Data bus utilization in percentage 278system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 279system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes |
| 307system.physmem.avgRdQLen 4.56 # Average read queue length when enqueuing 308system.physmem.avgWrQLen 29.44 # Average write queue length when enqueuing 309system.physmem.readRowHits 6202256 # Number of row buffer hits during reads 310system.physmem.writeRowHits 93908 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 93.22 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 84.12 # Row buffer hit rate for writes 313system.physmem.avgGap 160032.28 # Average gap between requests 314system.physmem.pageHitRate 93.07 # Row buffer hit rate, read and write combined 315system.physmem.prechargeAllPercent 6.14 # Percentage of time for which DRAM has all the banks in precharge state 316system.membus.throughput 59898120 # Throughput (bytes/s) 317system.membus.trans_dist::ReadReq 7703395 # Transaction distribution 318system.membus.trans_dist::ReadResp 7703395 # Transaction distribution 319system.membus.trans_dist::WriteReq 767585 # Transaction distribution 320system.membus.trans_dist::WriteResp 767585 # Transaction distribution 321system.membus.trans_dist::Writeback 63942 # Transaction distribution 322system.membus.trans_dist::UpgradeReq 31730 # Transaction distribution 323system.membus.trans_dist::SCUpgradeReq 17317 # Transaction distribution 324system.membus.trans_dist::UpgradeResp 11979 # Transaction distribution 325system.membus.trans_dist::ReadExReq 137317 # Transaction distribution 326system.membus.trans_dist::ReadExResp 136921 # Transaction distribution 327system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382690 # Packet count per connected master and slave (bytes) | 280system.physmem.avgRdQLen 4.89 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 27.45 # Average write queue length when enqueuing 282system.physmem.readRowHits 6199461 # Number of row buffer hits during reads 283system.physmem.writeRowHits 92422 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 82.71 # Row buffer hit rate for writes 286system.physmem.avgGap 159981.01 # Average gap between requests 287system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined 288system.physmem.memoryStateTime::IDLE 947634468500 # Time in different power states 289system.physmem.memoryStateTime::REF 39935220000 # Time in different power states 290system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem.memoryStateTime::ACT 208375212750 # Time in different power states 292system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 294system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 295system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 296system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 297system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 298system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 299system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 300system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 301system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 302system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 303system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 304system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 305system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 306system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 307system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 308system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 309system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 310system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 311system.membus.throughput 59946686 # Throughput (bytes/s) 312system.membus.trans_dist::ReadReq 7703403 # Transaction distribution 313system.membus.trans_dist::ReadResp 7703403 # Transaction distribution 314system.membus.trans_dist::WriteReq 767582 # Transaction distribution 315system.membus.trans_dist::WriteResp 767582 # Transaction distribution 316system.membus.trans_dist::Writeback 64228 # Transaction distribution 317system.membus.trans_dist::UpgradeReq 31700 # Transaction distribution 318system.membus.trans_dist::SCUpgradeReq 17261 # Transaction distribution 319system.membus.trans_dist::UpgradeResp 12098 # Transaction distribution 320system.membus.trans_dist::ReadExReq 137709 # Transaction distribution 321system.membus.trans_dist::ReadExResp 137266 # Transaction distribution 322system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382666 # Packet count per connected master and slave (bytes) |
| 328system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 323system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 329system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) | 324system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10310 # Packet count per connected master and slave (bytes) |
| 330system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) | 325system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) |
| 331system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 914 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971094 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count_system.l2c.mem_side::total 4365038 # Packet count per connected master and slave (bytes) | 326system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972180 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.l2c.mem_side::total 4366104 # Packet count per connected master and slave (bytes) |
| 334system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 335system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) | 329system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) |
| 336system.membus.pkt_count::total 17341166 # Packet count per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390070 # Cumulative packet size per connected master and slave (bytes) | 331system.membus.pkt_count::total 17342232 # Packet count per connected master and slave (bytes) 332system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390035 # Cumulative packet size per connected master and slave (bytes) |
| 338system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) | 333system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) |
| 339system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) | 334system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20620 # Cumulative packet size per connected master and slave (bytes) |
| 340system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) | 335system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) |
| 341system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1828 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17334548 # Cumulative packet size per connected master and slave (bytes) 343system.membus.tot_pkt_size_system.l2c.mem_side::total 19747126 # Cumulative packet size per connected master and slave (bytes) | 336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375892 # Cumulative packet size per connected master and slave (bytes) 338system.membus.tot_pkt_size_system.l2c.mem_side::total 19788443 # Cumulative packet size per connected master and slave (bytes) |
| 344system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 345system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 339system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 340system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 346system.membus.tot_pkt_size::total 71651638 # Cumulative packet size per connected master and slave (bytes) 347system.membus.data_through_bus 71651638 # Total data (bytes) | 341system.membus.tot_pkt_size::total 71692955 # Cumulative packet size per connected master and slave (bytes) 342system.membus.data_through_bus 71692955 # Total data (bytes) |
| 348system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 343system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 349system.membus.reqLayer0.occupancy 1224825500 # Layer occupancy (ticks) | 344system.membus.reqLayer0.occupancy 1224801000 # Layer occupancy (ticks) |
| 350system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 351system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 352system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 345system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 346system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 347system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 353system.membus.reqLayer2.occupancy 9234000 # Layer occupancy (ticks) | 348system.membus.reqLayer2.occupancy 9242500 # Layer occupancy (ticks) |
| 354system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 355system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 356system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 349system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 350system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 351system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 357system.membus.reqLayer5.occupancy 786000 # Layer occupancy (ticks) | 352system.membus.reqLayer5.occupancy 784500 # Layer occupancy (ticks) |
| 358system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 353system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 359system.membus.reqLayer6.occupancy 9208108500 # Layer occupancy (ticks) | 354system.membus.reqLayer6.occupancy 9211274000 # Layer occupancy (ticks) |
| 360system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) | 355system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) |
| 361system.membus.respLayer1.occupancy 5075173558 # Layer occupancy (ticks) | 356system.membus.respLayer1.occupancy 5078680829 # Layer occupancy (ticks) |
| 362system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 357system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 363system.membus.respLayer2.occupancy 16181474500 # Layer occupancy (ticks) 364system.membus.respLayer2.utilization 1.4 # Layer utilization (%) | 358system.membus.respLayer2.occupancy 16046108250 # Layer occupancy (ticks) 359system.membus.respLayer2.utilization 1.3 # Layer utilization (%) |
| 365system.cpu_clk_domain.clock 500 # Clock period in ticks | 360system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 366system.l2c.tags.replacements 69062 # number of replacements 367system.l2c.tags.tagsinuse 52959.899517 # Cycle average of tags in use 368system.l2c.tags.total_refs 1674433 # Total number of references to valid blocks. 369system.l2c.tags.sampled_refs 134270 # Sample count of references to valid blocks. 370system.l2c.tags.avg_refs 12.470641 # Average number of references to valid blocks. | 361system.l2c.tags.replacements 69421 # number of replacements 362system.l2c.tags.tagsinuse 53012.823108 # Cycle average of tags in use 363system.l2c.tags.total_refs 1672128 # Total number of references to valid blocks. 364system.l2c.tags.sampled_refs 134609 # Sample count of references to valid blocks. 365system.l2c.tags.avg_refs 12.422111 # Average number of references to valid blocks. |
| 371system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 366system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 372system.l2c.tags.occ_blocks::writebacks 40142.433744 # Average occupied blocks per requestor | 367system.l2c.tags.occ_blocks::writebacks 40185.217534 # Average occupied blocks per requestor |
| 373system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor | 368system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor |
| 374system.l2c.tags.occ_blocks::cpu0.itb.walker 0.003238 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu0.inst 3707.808501 # Average occupied blocks per requestor 376system.l2c.tags.occ_blocks::cpu0.data 4231.213775 # Average occupied blocks per requestor 377system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742447 # Average occupied blocks per requestor 378system.l2c.tags.occ_blocks::cpu1.inst 2816.465022 # Average occupied blocks per requestor 379system.l2c.tags.occ_blocks::cpu1.data 2059.232379 # Average occupied blocks per requestor 380system.l2c.tags.occ_percent::writebacks 0.612525 # Average percentage of cache occupancy | 369system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor 370system.l2c.tags.occ_blocks::cpu0.inst 3710.755623 # Average occupied blocks per requestor 371system.l2c.tags.occ_blocks::cpu0.data 4242.358437 # Average occupied blocks per requestor 372system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742287 # Average occupied blocks per requestor 373system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor 374system.l2c.tags.occ_blocks::cpu1.inst 2808.724549 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu1.data 2063.021033 # Average occupied blocks per requestor 376system.l2c.tags.occ_percent::writebacks 0.613178 # Average percentage of cache occupancy |
| 381system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 382system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 377system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 378system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 383system.l2c.tags.occ_percent::cpu0.inst 0.056577 # Average percentage of cache occupancy 384system.l2c.tags.occ_percent::cpu0.data 0.064563 # Average percentage of cache occupancy | 379system.l2c.tags.occ_percent::cpu0.inst 0.056622 # Average percentage of cache occupancy 380system.l2c.tags.occ_percent::cpu0.data 0.064733 # Average percentage of cache occupancy |
| 385system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy | 381system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy |
| 386system.l2c.tags.occ_percent::cpu1.inst 0.042976 # Average percentage of cache occupancy 387system.l2c.tags.occ_percent::cpu1.data 0.031421 # Average percentage of cache occupancy 388system.l2c.tags.occ_percent::total 0.808104 # Average percentage of cache occupancy | 382system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 383system.l2c.tags.occ_percent::cpu1.inst 0.042858 # Average percentage of cache occupancy 384system.l2c.tags.occ_percent::cpu1.data 0.031479 # Average percentage of cache occupancy 385system.l2c.tags.occ_percent::total 0.808911 # Average percentage of cache occupancy |
| 389system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id | 386system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id |
| 390system.l2c.tags.occ_task_id_blocks::1024 65203 # Occupied blocks per task id | 387system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id |
| 391system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 392system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id | 388system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 389system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id |
| 393system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 394system.l2c.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 395system.l2c.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id 396system.l2c.tags.age_task_id_blocks_1024::3 7908 # Occupied blocks per task id 397system.l2c.tags.age_task_id_blocks_1024::4 55276 # Occupied blocks per task id | 390system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 391system.l2c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id 392system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id 393system.l2c.tags.age_task_id_blocks_1024::3 8039 # Occupied blocks per task id 394system.l2c.tags.age_task_id_blocks_1024::4 55163 # Occupied blocks per task id |
| 398system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id | 395system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id |
| 399system.l2c.tags.occ_task_id_percent::1024 0.994919 # Percentage of cache occupancy per task id 400system.l2c.tags.tag_accesses 17240213 # Number of tag accesses 401system.l2c.tags.data_accesses 17240213 # Number of data accesses 402system.l2c.ReadReq_hits::cpu0.dtb.walker 2997 # number of ReadReq hits 403system.l2c.ReadReq_hits::cpu0.itb.walker 1656 # number of ReadReq hits 404system.l2c.ReadReq_hits::cpu0.inst 349452 # number of ReadReq hits 405system.l2c.ReadReq_hits::cpu0.data 169925 # number of ReadReq hits 406system.l2c.ReadReq_hits::cpu1.dtb.walker 6371 # number of ReadReq hits 407system.l2c.ReadReq_hits::cpu1.itb.walker 1905 # number of ReadReq hits 408system.l2c.ReadReq_hits::cpu1.inst 535287 # number of ReadReq hits 409system.l2c.ReadReq_hits::cpu1.data 180837 # number of ReadReq hits 410system.l2c.ReadReq_hits::total 1248430 # number of ReadReq hits 411system.l2c.Writeback_hits::writebacks 572475 # number of Writeback hits 412system.l2c.Writeback_hits::total 572475 # number of Writeback hits 413system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits 414system.l2c.UpgradeReq_hits::cpu1.data 587 # number of UpgradeReq hits 415system.l2c.UpgradeReq_hits::total 1630 # number of UpgradeReq hits 416system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits 417system.l2c.SCUpgradeReq_hits::cpu1.data 84 # number of SCUpgradeReq hits 418system.l2c.SCUpgradeReq_hits::total 304 # number of SCUpgradeReq hits 419system.l2c.ReadExReq_hits::cpu0.data 47236 # number of ReadExReq hits 420system.l2c.ReadExReq_hits::cpu1.data 62412 # number of ReadExReq hits 421system.l2c.ReadExReq_hits::total 109648 # number of ReadExReq hits 422system.l2c.demand_hits::cpu0.dtb.walker 2997 # number of demand (read+write) hits 423system.l2c.demand_hits::cpu0.itb.walker 1656 # number of demand (read+write) hits 424system.l2c.demand_hits::cpu0.inst 349452 # number of demand (read+write) hits 425system.l2c.demand_hits::cpu0.data 217161 # number of demand (read+write) hits 426system.l2c.demand_hits::cpu1.dtb.walker 6371 # number of demand (read+write) hits 427system.l2c.demand_hits::cpu1.itb.walker 1905 # number of demand (read+write) hits 428system.l2c.demand_hits::cpu1.inst 535287 # number of demand (read+write) hits 429system.l2c.demand_hits::cpu1.data 243249 # number of demand (read+write) hits 430system.l2c.demand_hits::total 1358078 # number of demand (read+write) hits 431system.l2c.overall_hits::cpu0.dtb.walker 2997 # number of overall hits 432system.l2c.overall_hits::cpu0.itb.walker 1656 # number of overall hits 433system.l2c.overall_hits::cpu0.inst 349452 # number of overall hits 434system.l2c.overall_hits::cpu0.data 217161 # number of overall hits 435system.l2c.overall_hits::cpu1.dtb.walker 6371 # number of overall hits 436system.l2c.overall_hits::cpu1.itb.walker 1905 # number of overall hits 437system.l2c.overall_hits::cpu1.inst 535287 # number of overall hits 438system.l2c.overall_hits::cpu1.data 243249 # number of overall hits 439system.l2c.overall_hits::total 1358078 # number of overall hits | 396system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id 397system.l2c.tags.tag_accesses 17207703 # Number of tag accesses 398system.l2c.tags.data_accesses 17207703 # Number of data accesses 399system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits 400system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits 401system.l2c.ReadReq_hits::cpu0.inst 419090 # number of ReadReq hits 402system.l2c.ReadReq_hits::cpu0.data 205762 # number of ReadReq hits 403system.l2c.ReadReq_hits::cpu1.dtb.walker 5504 # number of ReadReq hits 404system.l2c.ReadReq_hits::cpu1.itb.walker 1909 # number of ReadReq hits 405system.l2c.ReadReq_hits::cpu1.inst 464812 # number of ReadReq hits 406system.l2c.ReadReq_hits::cpu1.data 143326 # number of ReadReq hits 407system.l2c.ReadReq_hits::total 1245952 # number of ReadReq hits 408system.l2c.Writeback_hits::writebacks 570869 # number of Writeback hits 409system.l2c.Writeback_hits::total 570869 # number of Writeback hits 410system.l2c.UpgradeReq_hits::cpu0.data 1175 # number of UpgradeReq hits 411system.l2c.UpgradeReq_hits::cpu1.data 561 # number of UpgradeReq hits 412system.l2c.UpgradeReq_hits::total 1736 # number of UpgradeReq hits 413system.l2c.SCUpgradeReq_hits::cpu0.data 218 # number of SCUpgradeReq hits 414system.l2c.SCUpgradeReq_hits::cpu1.data 106 # number of SCUpgradeReq hits 415system.l2c.SCUpgradeReq_hits::total 324 # number of SCUpgradeReq hits 416system.l2c.ReadExReq_hits::cpu0.data 56320 # number of ReadExReq hits 417system.l2c.ReadExReq_hits::cpu1.data 52713 # number of ReadExReq hits 418system.l2c.ReadExReq_hits::total 109033 # number of ReadExReq hits 419system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits 420system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits 421system.l2c.demand_hits::cpu0.inst 419090 # number of demand (read+write) hits 422system.l2c.demand_hits::cpu0.data 262082 # number of demand (read+write) hits 423system.l2c.demand_hits::cpu1.dtb.walker 5504 # number of demand (read+write) hits 424system.l2c.demand_hits::cpu1.itb.walker 1909 # number of demand (read+write) hits 425system.l2c.demand_hits::cpu1.inst 464812 # number of demand (read+write) hits 426system.l2c.demand_hits::cpu1.data 196039 # number of demand (read+write) hits 427system.l2c.demand_hits::total 1354985 # number of demand (read+write) hits 428system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits 429system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits 430system.l2c.overall_hits::cpu0.inst 419090 # number of overall hits 431system.l2c.overall_hits::cpu0.data 262082 # number of overall hits 432system.l2c.overall_hits::cpu1.dtb.walker 5504 # number of overall hits 433system.l2c.overall_hits::cpu1.itb.walker 1909 # number of overall hits 434system.l2c.overall_hits::cpu1.inst 464812 # number of overall hits 435system.l2c.overall_hits::cpu1.data 196039 # number of overall hits 436system.l2c.overall_hits::total 1354985 # number of overall hits |
| 440system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 437system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses |
| 441system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 442system.l2c.ReadReq_misses::cpu0.inst 5500 # number of ReadReq misses 443system.l2c.ReadReq_misses::cpu0.data 7825 # number of ReadReq misses | 438system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 439system.l2c.ReadReq_misses::cpu0.inst 5736 # number of ReadReq misses 440system.l2c.ReadReq_misses::cpu0.data 7851 # number of ReadReq misses |
| 444system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses | 441system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses |
| 445system.l2c.ReadReq_misses::cpu1.inst 5275 # number of ReadReq misses 446system.l2c.ReadReq_misses::cpu1.data 3652 # number of ReadReq misses 447system.l2c.ReadReq_misses::total 22260 # number of ReadReq misses 448system.l2c.UpgradeReq_misses::cpu0.data 3753 # number of UpgradeReq misses 449system.l2c.UpgradeReq_misses::cpu1.data 4772 # number of UpgradeReq misses 450system.l2c.UpgradeReq_misses::total 8525 # number of UpgradeReq misses 451system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses 452system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses 453system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses 454system.l2c.ReadExReq_misses::cpu0.data 63889 # number of ReadExReq misses 455system.l2c.ReadExReq_misses::cpu1.data 75455 # number of ReadExReq misses 456system.l2c.ReadExReq_misses::total 139344 # number of ReadExReq misses | 442system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 443system.l2c.ReadReq_misses::cpu1.inst 5067 # number of ReadReq misses 444system.l2c.ReadReq_misses::cpu1.data 3613 # number of ReadReq misses 445system.l2c.ReadReq_misses::total 22275 # number of ReadReq misses 446system.l2c.UpgradeReq_misses::cpu0.data 4950 # number of UpgradeReq misses 447system.l2c.UpgradeReq_misses::cpu1.data 3658 # number of UpgradeReq misses 448system.l2c.UpgradeReq_misses::total 8608 # number of UpgradeReq misses 449system.l2c.SCUpgradeReq_misses::cpu0.data 565 # number of SCUpgradeReq misses 450system.l2c.SCUpgradeReq_misses::cpu1.data 478 # number of SCUpgradeReq misses 451system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses 452system.l2c.ReadExReq_misses::cpu0.data 67127 # number of ReadExReq misses 453system.l2c.ReadExReq_misses::cpu1.data 72586 # number of ReadExReq misses 454system.l2c.ReadExReq_misses::total 139713 # number of ReadExReq misses |
| 457system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 455system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses |
| 458system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 459system.l2c.demand_misses::cpu0.inst 5500 # number of demand (read+write) misses 460system.l2c.demand_misses::cpu0.data 71714 # number of demand (read+write) misses | 456system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 457system.l2c.demand_misses::cpu0.inst 5736 # number of demand (read+write) misses 458system.l2c.demand_misses::cpu0.data 74978 # number of demand (read+write) misses |
| 461system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses | 459system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses |
| 462system.l2c.demand_misses::cpu1.inst 5275 # number of demand (read+write) misses 463system.l2c.demand_misses::cpu1.data 79107 # number of demand (read+write) misses 464system.l2c.demand_misses::total 161604 # number of demand (read+write) misses | 460system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 461system.l2c.demand_misses::cpu1.inst 5067 # number of demand (read+write) misses 462system.l2c.demand_misses::cpu1.data 76199 # number of demand (read+write) misses 463system.l2c.demand_misses::total 161988 # number of demand (read+write) misses |
| 465system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 464system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses |
| 466system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 467system.l2c.overall_misses::cpu0.inst 5500 # number of overall misses 468system.l2c.overall_misses::cpu0.data 71714 # number of overall misses | 465system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 466system.l2c.overall_misses::cpu0.inst 5736 # number of overall misses 467system.l2c.overall_misses::cpu0.data 74978 # number of overall misses |
| 469system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses | 468system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses |
| 470system.l2c.overall_misses::cpu1.inst 5275 # number of overall misses 471system.l2c.overall_misses::cpu1.data 79107 # number of overall misses 472system.l2c.overall_misses::total 161604 # number of overall misses | 469system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 470system.l2c.overall_misses::cpu1.inst 5067 # number of overall misses 471system.l2c.overall_misses::cpu1.data 76199 # number of overall misses 472system.l2c.overall_misses::total 161988 # number of overall misses |
| 473system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles | 473system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles |
| 474system.l2c.ReadReq_miss_latency::cpu0.itb.walker 224500 # number of ReadReq miss cycles 475system.l2c.ReadReq_miss_latency::cpu0.inst 385138750 # number of ReadReq miss cycles 476system.l2c.ReadReq_miss_latency::cpu0.data 587705249 # number of ReadReq miss cycles | 474system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 475system.l2c.ReadReq_miss_latency::cpu0.inst 404696000 # number of ReadReq miss cycles 476system.l2c.ReadReq_miss_latency::cpu0.data 578862249 # number of ReadReq miss cycles |
| 477system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 334500 # number of ReadReq miss cycles | 477system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 334500 # number of ReadReq miss cycles |
| 478system.l2c.ReadReq_miss_latency::cpu1.inst 381420250 # number of ReadReq miss cycles 479system.l2c.ReadReq_miss_latency::cpu1.data 283658250 # number of ReadReq miss cycles 480system.l2c.ReadReq_miss_latency::total 1638513499 # number of ReadReq miss cycles 481system.l2c.UpgradeReq_miss_latency::cpu0.data 11041523 # number of UpgradeReq miss cycles 482system.l2c.UpgradeReq_miss_latency::cpu1.data 13954898 # number of UpgradeReq miss cycles 483system.l2c.UpgradeReq_miss_latency::total 24996421 # number of UpgradeReq miss cycles 484system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1841422 # number of SCUpgradeReq miss cycles 485system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2322900 # number of SCUpgradeReq miss cycles 486system.l2c.SCUpgradeReq_miss_latency::total 4164322 # number of SCUpgradeReq miss cycles 487system.l2c.ReadExReq_miss_latency::cpu0.data 4291032858 # number of ReadExReq miss cycles 488system.l2c.ReadExReq_miss_latency::cpu1.data 5578462720 # number of ReadExReq miss cycles 489system.l2c.ReadExReq_miss_latency::total 9869495578 # number of ReadExReq miss cycles | 478system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 479system.l2c.ReadReq_miss_latency::cpu1.inst 361943250 # number of ReadReq miss cycles 480system.l2c.ReadReq_miss_latency::cpu1.data 276382250 # number of ReadReq miss cycles 481system.l2c.ReadReq_miss_latency::total 1622474249 # number of ReadReq miss cycles 482system.l2c.UpgradeReq_miss_latency::cpu0.data 13480917 # number of UpgradeReq miss cycles 483system.l2c.UpgradeReq_miss_latency::cpu1.data 12005984 # number of UpgradeReq miss cycles 484system.l2c.UpgradeReq_miss_latency::total 25486901 # number of UpgradeReq miss cycles 485system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1698427 # number of SCUpgradeReq miss cycles 486system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2508392 # number of SCUpgradeReq miss cycles 487system.l2c.SCUpgradeReq_miss_latency::total 4206819 # number of SCUpgradeReq miss cycles 488system.l2c.ReadExReq_miss_latency::cpu0.data 4495992931 # number of ReadExReq miss cycles 489system.l2c.ReadExReq_miss_latency::cpu1.data 5253472119 # number of ReadExReq miss cycles 490system.l2c.ReadExReq_miss_latency::total 9749465050 # number of ReadExReq miss cycles |
| 490system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles | 491system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles |
| 491system.l2c.demand_miss_latency::cpu0.itb.walker 224500 # number of demand (read+write) miss cycles 492system.l2c.demand_miss_latency::cpu0.inst 385138750 # number of demand (read+write) miss cycles 493system.l2c.demand_miss_latency::cpu0.data 4878738107 # number of demand (read+write) miss cycles | 492system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 493system.l2c.demand_miss_latency::cpu0.inst 404696000 # number of demand (read+write) miss cycles 494system.l2c.demand_miss_latency::cpu0.data 5074855180 # number of demand (read+write) miss cycles |
| 494system.l2c.demand_miss_latency::cpu1.dtb.walker 334500 # number of demand (read+write) miss cycles | 495system.l2c.demand_miss_latency::cpu1.dtb.walker 334500 # number of demand (read+write) miss cycles |
| 495system.l2c.demand_miss_latency::cpu1.inst 381420250 # number of demand (read+write) miss cycles 496system.l2c.demand_miss_latency::cpu1.data 5862120970 # number of demand (read+write) miss cycles 497system.l2c.demand_miss_latency::total 11508009077 # number of demand (read+write) miss cycles | 496system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 497system.l2c.demand_miss_latency::cpu1.inst 361943250 # number of demand (read+write) miss cycles 498system.l2c.demand_miss_latency::cpu1.data 5529854369 # number of demand (read+write) miss cycles 499system.l2c.demand_miss_latency::total 11371939299 # number of demand (read+write) miss cycles |
| 498system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles | 500system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles |
| 499system.l2c.overall_miss_latency::cpu0.itb.walker 224500 # number of overall miss cycles 500system.l2c.overall_miss_latency::cpu0.inst 385138750 # number of overall miss cycles 501system.l2c.overall_miss_latency::cpu0.data 4878738107 # number of overall miss cycles | 501system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 502system.l2c.overall_miss_latency::cpu0.inst 404696000 # number of overall miss cycles 503system.l2c.overall_miss_latency::cpu0.data 5074855180 # number of overall miss cycles |
| 502system.l2c.overall_miss_latency::cpu1.dtb.walker 334500 # number of overall miss cycles | 504system.l2c.overall_miss_latency::cpu1.dtb.walker 334500 # number of overall miss cycles |
| 503system.l2c.overall_miss_latency::cpu1.inst 381420250 # number of overall miss cycles 504system.l2c.overall_miss_latency::cpu1.data 5862120970 # number of overall miss cycles 505system.l2c.overall_miss_latency::total 11508009077 # number of overall miss cycles 506system.l2c.ReadReq_accesses::cpu0.dtb.walker 2998 # number of ReadReq accesses(hits+misses) 507system.l2c.ReadReq_accesses::cpu0.itb.walker 1659 # number of ReadReq accesses(hits+misses) 508system.l2c.ReadReq_accesses::cpu0.inst 354952 # number of ReadReq accesses(hits+misses) 509system.l2c.ReadReq_accesses::cpu0.data 177750 # number of ReadReq accesses(hits+misses) 510system.l2c.ReadReq_accesses::cpu1.dtb.walker 6375 # number of ReadReq accesses(hits+misses) 511system.l2c.ReadReq_accesses::cpu1.itb.walker 1905 # number of ReadReq accesses(hits+misses) 512system.l2c.ReadReq_accesses::cpu1.inst 540562 # number of ReadReq accesses(hits+misses) 513system.l2c.ReadReq_accesses::cpu1.data 184489 # number of ReadReq accesses(hits+misses) 514system.l2c.ReadReq_accesses::total 1270690 # number of ReadReq accesses(hits+misses) 515system.l2c.Writeback_accesses::writebacks 572475 # number of Writeback accesses(hits+misses) 516system.l2c.Writeback_accesses::total 572475 # number of Writeback accesses(hits+misses) 517system.l2c.UpgradeReq_accesses::cpu0.data 4796 # number of UpgradeReq accesses(hits+misses) 518system.l2c.UpgradeReq_accesses::cpu1.data 5359 # number of UpgradeReq accesses(hits+misses) 519system.l2c.UpgradeReq_accesses::total 10155 # number of UpgradeReq accesses(hits+misses) 520system.l2c.SCUpgradeReq_accesses::cpu0.data 791 # number of SCUpgradeReq accesses(hits+misses) 521system.l2c.SCUpgradeReq_accesses::cpu1.data 544 # number of SCUpgradeReq accesses(hits+misses) 522system.l2c.SCUpgradeReq_accesses::total 1335 # number of SCUpgradeReq accesses(hits+misses) 523system.l2c.ReadExReq_accesses::cpu0.data 111125 # number of ReadExReq accesses(hits+misses) 524system.l2c.ReadExReq_accesses::cpu1.data 137867 # number of ReadExReq accesses(hits+misses) 525system.l2c.ReadExReq_accesses::total 248992 # number of ReadExReq accesses(hits+misses) 526system.l2c.demand_accesses::cpu0.dtb.walker 2998 # number of demand (read+write) accesses 527system.l2c.demand_accesses::cpu0.itb.walker 1659 # number of demand (read+write) accesses 528system.l2c.demand_accesses::cpu0.inst 354952 # number of demand (read+write) accesses 529system.l2c.demand_accesses::cpu0.data 288875 # number of demand (read+write) accesses 530system.l2c.demand_accesses::cpu1.dtb.walker 6375 # number of demand (read+write) accesses 531system.l2c.demand_accesses::cpu1.itb.walker 1905 # number of demand (read+write) accesses 532system.l2c.demand_accesses::cpu1.inst 540562 # number of demand (read+write) accesses 533system.l2c.demand_accesses::cpu1.data 322356 # number of demand (read+write) accesses 534system.l2c.demand_accesses::total 1519682 # number of demand (read+write) accesses 535system.l2c.overall_accesses::cpu0.dtb.walker 2998 # number of overall (read+write) accesses 536system.l2c.overall_accesses::cpu0.itb.walker 1659 # number of overall (read+write) accesses 537system.l2c.overall_accesses::cpu0.inst 354952 # number of overall (read+write) accesses 538system.l2c.overall_accesses::cpu0.data 288875 # number of overall (read+write) accesses 539system.l2c.overall_accesses::cpu1.dtb.walker 6375 # number of overall (read+write) accesses 540system.l2c.overall_accesses::cpu1.itb.walker 1905 # number of overall (read+write) accesses 541system.l2c.overall_accesses::cpu1.inst 540562 # number of overall (read+write) accesses 542system.l2c.overall_accesses::cpu1.data 322356 # number of overall (read+write) accesses 543system.l2c.overall_accesses::total 1519682 # number of overall (read+write) accesses 544system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for ReadReq accesses 545system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001808 # miss rate for ReadReq accesses 546system.l2c.ReadReq_miss_rate::cpu0.inst 0.015495 # miss rate for ReadReq accesses 547system.l2c.ReadReq_miss_rate::cpu0.data 0.044023 # miss rate for ReadReq accesses 548system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for ReadReq accesses 549system.l2c.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses 550system.l2c.ReadReq_miss_rate::cpu1.data 0.019795 # miss rate for ReadReq accesses 551system.l2c.ReadReq_miss_rate::total 0.017518 # miss rate for ReadReq accesses 552system.l2c.UpgradeReq_miss_rate::cpu0.data 0.782527 # miss rate for UpgradeReq accesses 553system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890465 # miss rate for UpgradeReq accesses 554system.l2c.UpgradeReq_miss_rate::total 0.839488 # miss rate for UpgradeReq accesses 555system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721871 # miss rate for SCUpgradeReq accesses 556system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.845588 # miss rate for SCUpgradeReq accesses 557system.l2c.SCUpgradeReq_miss_rate::total 0.772285 # miss rate for SCUpgradeReq accesses 558system.l2c.ReadExReq_miss_rate::cpu0.data 0.574929 # miss rate for ReadExReq accesses 559system.l2c.ReadExReq_miss_rate::cpu1.data 0.547303 # miss rate for ReadExReq accesses 560system.l2c.ReadExReq_miss_rate::total 0.559632 # miss rate for ReadExReq accesses 561system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for demand accesses 562system.l2c.demand_miss_rate::cpu0.itb.walker 0.001808 # miss rate for demand accesses 563system.l2c.demand_miss_rate::cpu0.inst 0.015495 # miss rate for demand accesses 564system.l2c.demand_miss_rate::cpu0.data 0.248253 # miss rate for demand accesses 565system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for demand accesses 566system.l2c.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses 567system.l2c.demand_miss_rate::cpu1.data 0.245403 # miss rate for demand accesses 568system.l2c.demand_miss_rate::total 0.106341 # miss rate for demand accesses 569system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for overall accesses 570system.l2c.overall_miss_rate::cpu0.itb.walker 0.001808 # miss rate for overall accesses 571system.l2c.overall_miss_rate::cpu0.inst 0.015495 # miss rate for overall accesses 572system.l2c.overall_miss_rate::cpu0.data 0.248253 # miss rate for overall accesses 573system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for overall accesses 574system.l2c.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses 575system.l2c.overall_miss_rate::cpu1.data 0.245403 # miss rate for overall accesses 576system.l2c.overall_miss_rate::total 0.106341 # miss rate for overall accesses | 505system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 506system.l2c.overall_miss_latency::cpu1.inst 361943250 # number of overall miss cycles 507system.l2c.overall_miss_latency::cpu1.data 5529854369 # number of overall miss cycles 508system.l2c.overall_miss_latency::total 11371939299 # number of overall miss cycles 509system.l2c.ReadReq_accesses::cpu0.dtb.walker 3811 # number of ReadReq accesses(hits+misses) 510system.l2c.ReadReq_accesses::cpu0.itb.walker 1741 # number of ReadReq accesses(hits+misses) 511system.l2c.ReadReq_accesses::cpu0.inst 424826 # number of ReadReq accesses(hits+misses) 512system.l2c.ReadReq_accesses::cpu0.data 213613 # number of ReadReq accesses(hits+misses) 513system.l2c.ReadReq_accesses::cpu1.dtb.walker 5508 # number of ReadReq accesses(hits+misses) 514system.l2c.ReadReq_accesses::cpu1.itb.walker 1910 # number of ReadReq accesses(hits+misses) 515system.l2c.ReadReq_accesses::cpu1.inst 469879 # number of ReadReq accesses(hits+misses) 516system.l2c.ReadReq_accesses::cpu1.data 146939 # number of ReadReq accesses(hits+misses) 517system.l2c.ReadReq_accesses::total 1268227 # number of ReadReq accesses(hits+misses) 518system.l2c.Writeback_accesses::writebacks 570869 # number of Writeback accesses(hits+misses) 519system.l2c.Writeback_accesses::total 570869 # number of Writeback accesses(hits+misses) 520system.l2c.UpgradeReq_accesses::cpu0.data 6125 # number of UpgradeReq accesses(hits+misses) 521system.l2c.UpgradeReq_accesses::cpu1.data 4219 # number of UpgradeReq accesses(hits+misses) 522system.l2c.UpgradeReq_accesses::total 10344 # number of UpgradeReq accesses(hits+misses) 523system.l2c.SCUpgradeReq_accesses::cpu0.data 783 # number of SCUpgradeReq accesses(hits+misses) 524system.l2c.SCUpgradeReq_accesses::cpu1.data 584 # number of SCUpgradeReq accesses(hits+misses) 525system.l2c.SCUpgradeReq_accesses::total 1367 # number of SCUpgradeReq accesses(hits+misses) 526system.l2c.ReadExReq_accesses::cpu0.data 123447 # number of ReadExReq accesses(hits+misses) 527system.l2c.ReadExReq_accesses::cpu1.data 125299 # number of ReadExReq accesses(hits+misses) 528system.l2c.ReadExReq_accesses::total 248746 # number of ReadExReq accesses(hits+misses) 529system.l2c.demand_accesses::cpu0.dtb.walker 3811 # number of demand (read+write) accesses 530system.l2c.demand_accesses::cpu0.itb.walker 1741 # number of demand (read+write) accesses 531system.l2c.demand_accesses::cpu0.inst 424826 # number of demand (read+write) accesses 532system.l2c.demand_accesses::cpu0.data 337060 # number of demand (read+write) accesses 533system.l2c.demand_accesses::cpu1.dtb.walker 5508 # number of demand (read+write) accesses 534system.l2c.demand_accesses::cpu1.itb.walker 1910 # number of demand (read+write) accesses 535system.l2c.demand_accesses::cpu1.inst 469879 # number of demand (read+write) accesses 536system.l2c.demand_accesses::cpu1.data 272238 # number of demand (read+write) accesses 537system.l2c.demand_accesses::total 1516973 # number of demand (read+write) accesses 538system.l2c.overall_accesses::cpu0.dtb.walker 3811 # number of overall (read+write) accesses 539system.l2c.overall_accesses::cpu0.itb.walker 1741 # number of overall (read+write) accesses 540system.l2c.overall_accesses::cpu0.inst 424826 # number of overall (read+write) accesses 541system.l2c.overall_accesses::cpu0.data 337060 # number of overall (read+write) accesses 542system.l2c.overall_accesses::cpu1.dtb.walker 5508 # number of overall (read+write) accesses 543system.l2c.overall_accesses::cpu1.itb.walker 1910 # number of overall (read+write) accesses 544system.l2c.overall_accesses::cpu1.inst 469879 # number of overall (read+write) accesses 545system.l2c.overall_accesses::cpu1.data 272238 # number of overall (read+write) accesses 546system.l2c.overall_accesses::total 1516973 # number of overall (read+write) accesses 547system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for ReadReq accesses 548system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001149 # miss rate for ReadReq accesses 549system.l2c.ReadReq_miss_rate::cpu0.inst 0.013502 # miss rate for ReadReq accesses 550system.l2c.ReadReq_miss_rate::cpu0.data 0.036753 # miss rate for ReadReq accesses 551system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses 552system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000524 # miss rate for ReadReq accesses 553system.l2c.ReadReq_miss_rate::cpu1.inst 0.010784 # miss rate for ReadReq accesses 554system.l2c.ReadReq_miss_rate::cpu1.data 0.024588 # miss rate for ReadReq accesses 555system.l2c.ReadReq_miss_rate::total 0.017564 # miss rate for ReadReq accesses 556system.l2c.UpgradeReq_miss_rate::cpu0.data 0.808163 # miss rate for UpgradeReq accesses 557system.l2c.UpgradeReq_miss_rate::cpu1.data 0.867030 # miss rate for UpgradeReq accesses 558system.l2c.UpgradeReq_miss_rate::total 0.832173 # miss rate for UpgradeReq accesses 559system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721584 # miss rate for SCUpgradeReq accesses 560system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.818493 # miss rate for SCUpgradeReq accesses 561system.l2c.SCUpgradeReq_miss_rate::total 0.762985 # miss rate for SCUpgradeReq accesses 562system.l2c.ReadExReq_miss_rate::cpu0.data 0.543772 # miss rate for ReadExReq accesses 563system.l2c.ReadExReq_miss_rate::cpu1.data 0.579302 # miss rate for ReadExReq accesses 564system.l2c.ReadExReq_miss_rate::total 0.561669 # miss rate for ReadExReq accesses 565system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for demand accesses 566system.l2c.demand_miss_rate::cpu0.itb.walker 0.001149 # miss rate for demand accesses 567system.l2c.demand_miss_rate::cpu0.inst 0.013502 # miss rate for demand accesses 568system.l2c.demand_miss_rate::cpu0.data 0.222447 # miss rate for demand accesses 569system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses 570system.l2c.demand_miss_rate::cpu1.itb.walker 0.000524 # miss rate for demand accesses 571system.l2c.demand_miss_rate::cpu1.inst 0.010784 # miss rate for demand accesses 572system.l2c.demand_miss_rate::cpu1.data 0.279898 # miss rate for demand accesses 573system.l2c.demand_miss_rate::total 0.106784 # miss rate for demand accesses 574system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for overall accesses 575system.l2c.overall_miss_rate::cpu0.itb.walker 0.001149 # miss rate for overall accesses 576system.l2c.overall_miss_rate::cpu0.inst 0.013502 # miss rate for overall accesses 577system.l2c.overall_miss_rate::cpu0.data 0.222447 # miss rate for overall accesses 578system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses 579system.l2c.overall_miss_rate::cpu1.itb.walker 0.000524 # miss rate for overall accesses 580system.l2c.overall_miss_rate::cpu1.inst 0.010784 # miss rate for overall accesses 581system.l2c.overall_miss_rate::cpu1.data 0.279898 # miss rate for overall accesses 582system.l2c.overall_miss_rate::total 0.106784 # miss rate for overall accesses |
| 577system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency | 583system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency |
| 578system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74833.333333 # average ReadReq miss latency 579system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70025.227273 # average ReadReq miss latency 580system.l2c.ReadReq_avg_miss_latency::cpu0.data 75106.102109 # average ReadReq miss latency | 584system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 585system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70553.695955 # average ReadReq miss latency 586system.l2c.ReadReq_avg_miss_latency::cpu0.data 73731.021399 # average ReadReq miss latency |
| 581system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83625 # average ReadReq miss latency | 587system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83625 # average ReadReq miss latency |
| 582system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72307.156398 # average ReadReq miss latency 583system.l2c.ReadReq_avg_miss_latency::cpu1.data 77672.029025 # average ReadReq miss latency 584system.l2c.ReadReq_avg_miss_latency::total 73607.973899 # average ReadReq miss latency 585system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2942.052491 # average UpgradeReq miss latency 586system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2924.329003 # average UpgradeReq miss latency 587system.l2c.UpgradeReq_avg_miss_latency::total 2932.131496 # average UpgradeReq miss latency 588system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3224.907180 # average SCUpgradeReq miss latency 589system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5049.782609 # average SCUpgradeReq miss latency 590system.l2c.SCUpgradeReq_avg_miss_latency::total 4039.109602 # average SCUpgradeReq miss latency 591system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67163.875753 # average ReadExReq miss latency 592system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73930.988271 # average ReadExReq miss latency 593system.l2c.ReadExReq_avg_miss_latency::total 70828.278060 # average ReadExReq miss latency | 588system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 589system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71431.468324 # average ReadReq miss latency 590system.l2c.ReadReq_avg_miss_latency::cpu1.data 76496.609466 # average ReadReq miss latency 591system.l2c.ReadReq_avg_miss_latency::total 72838.350123 # average ReadReq miss latency 592system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2723.417576 # average UpgradeReq miss latency 593system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3282.117004 # average UpgradeReq miss latency 594system.l2c.UpgradeReq_avg_miss_latency::total 2960.838871 # average UpgradeReq miss latency 595system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3006.065487 # average SCUpgradeReq miss latency 596system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5247.682008 # average SCUpgradeReq miss latency 597system.l2c.SCUpgradeReq_avg_miss_latency::total 4033.383509 # average SCUpgradeReq miss latency 598system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66977.414915 # average ReadExReq miss latency 599system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72375.831689 # average ReadExReq miss latency 600system.l2c.ReadExReq_avg_miss_latency::total 69782.089355 # average ReadExReq miss latency |
| 594system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency | 601system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency |
| 595system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency 596system.l2c.demand_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency 597system.l2c.demand_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency | 602system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 603system.l2c.demand_avg_miss_latency::cpu0.inst 70553.695955 # average overall miss latency 604system.l2c.demand_avg_miss_latency::cpu0.data 67684.589880 # average overall miss latency |
| 598system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency | 605system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency |
| 599system.l2c.demand_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency 600system.l2c.demand_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency 601system.l2c.demand_avg_miss_latency::total 71211.164804 # average overall miss latency | 606system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 607system.l2c.demand_avg_miss_latency::cpu1.inst 71431.468324 # average overall miss latency 608system.l2c.demand_avg_miss_latency::cpu1.data 72571.219688 # average overall miss latency 609system.l2c.demand_avg_miss_latency::total 70202.356341 # average overall miss latency |
| 602system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency | 610system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency |
| 603system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency 604system.l2c.overall_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency 605system.l2c.overall_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency | 611system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 612system.l2c.overall_avg_miss_latency::cpu0.inst 70553.695955 # average overall miss latency 613system.l2c.overall_avg_miss_latency::cpu0.data 67684.589880 # average overall miss latency |
| 606system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency | 614system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency |
| 607system.l2c.overall_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency 608system.l2c.overall_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency 609system.l2c.overall_avg_miss_latency::total 71211.164804 # average overall miss latency | 615system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 616system.l2c.overall_avg_miss_latency::cpu1.inst 71431.468324 # average overall miss latency 617system.l2c.overall_avg_miss_latency::cpu1.data 72571.219688 # average overall miss latency 618system.l2c.overall_avg_miss_latency::total 70202.356341 # average overall miss latency |
| 610system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 611system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 612system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 613system.l2c.blocked::no_targets 0 # number of cycles access was blocked 614system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 615system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 616system.l2c.fast_writes 0 # number of fast writes performed 617system.l2c.cache_copies 0 # number of cache copies performed | 619system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 620system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 621system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 622system.l2c.blocked::no_targets 0 # number of cycles access was blocked 623system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 624system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 625system.l2c.fast_writes 0 # number of fast writes performed 626system.l2c.cache_copies 0 # number of cache copies performed |
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| 655system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses | 666system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses |
| 656system.l2c.overall_mshr_misses::cpu1.inst 5275 # number of overall MSHR misses 657system.l2c.overall_mshr_misses::cpu1.data 79107 # number of overall MSHR misses 658system.l2c.overall_mshr_misses::total 161603 # number of overall MSHR misses | 667system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 668system.l2c.overall_mshr_misses::cpu1.inst 5067 # number of overall MSHR misses 669system.l2c.overall_mshr_misses::cpu1.data 76199 # number of overall MSHR misses 670system.l2c.overall_mshr_misses::total 161987 # number of overall MSHR misses |
| 659system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles | 671system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles |
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| 684system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles | 698system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles |
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| 689system.l2c.overall_mshr_miss_latency::cpu1.inst 314655750 # number of overall MSHR miss cycles 690system.l2c.overall_mshr_miss_latency::cpu1.data 4856567030 # number of overall MSHR miss cycles 691system.l2c.overall_mshr_miss_latency::total 9446292169 # number of overall MSHR miss cycles 692system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 352326000 # number of ReadReq MSHR uncacheable cycles 693system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11221595994 # number of ReadReq MSHR uncacheable cycles 694system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5508250 # number of ReadReq MSHR uncacheable cycles 695system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155529668246 # number of ReadReq MSHR uncacheable cycles 696system.l2c.ReadReq_mshr_uncacheable_latency::total 167109098490 # number of ReadReq MSHR uncacheable cycles 697system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1041121994 # number of WriteReq MSHR uncacheable cycles 698system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15728911223 # number of WriteReq MSHR uncacheable cycles 699system.l2c.WriteReq_mshr_uncacheable_latency::total 16770033217 # number of WriteReq MSHR uncacheable cycles 700system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 352326000 # number of overall MSHR uncacheable cycles 701system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12262717988 # number of overall MSHR uncacheable cycles 702system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5508250 # number of overall MSHR uncacheable cycles 703system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171258579469 # number of overall MSHR uncacheable cycles 704system.l2c.overall_mshr_uncacheable_latency::total 183879131707 # number of overall MSHR uncacheable cycles 705system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for ReadReq accesses 706system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for ReadReq accesses 707system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for ReadReq accesses 708system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044023 # mshr miss rate for ReadReq accesses 709system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for ReadReq accesses 710system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for ReadReq accesses 711system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019795 # mshr miss rate for ReadReq accesses 712system.l2c.ReadReq_mshr_miss_rate::total 0.017517 # mshr miss rate for ReadReq accesses 713system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782527 # mshr miss rate for UpgradeReq accesses 714system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890465 # mshr miss rate for UpgradeReq accesses 715system.l2c.UpgradeReq_mshr_miss_rate::total 0.839488 # mshr miss rate for UpgradeReq accesses 716system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721871 # mshr miss rate for SCUpgradeReq accesses 717system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845588 # mshr miss rate for SCUpgradeReq accesses 718system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.772285 # mshr miss rate for SCUpgradeReq accesses 719system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.574929 # mshr miss rate for ReadExReq accesses 720system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.547303 # mshr miss rate for ReadExReq accesses 721system.l2c.ReadExReq_mshr_miss_rate::total 0.559632 # mshr miss rate for ReadExReq accesses 722system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for demand accesses 723system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for demand accesses 724system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for demand accesses 725system.l2c.demand_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for demand accesses 726system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for demand accesses 727system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for demand accesses 728system.l2c.demand_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for demand accesses 729system.l2c.demand_mshr_miss_rate::total 0.106340 # mshr miss rate for demand accesses 730system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000334 # 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number of overall MSHR uncacheable cycles 716system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13503283986 # number of overall MSHR uncacheable cycles 717system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5624750 # number of overall MSHR uncacheable cycles 718system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015038084 # number of overall MSHR uncacheable cycles 719system.l2c.overall_mshr_uncacheable_latency::total 183874521570 # number of overall MSHR uncacheable cycles 720system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for ReadReq accesses 721system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for ReadReq accesses 722system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013500 # mshr miss rate for ReadReq accesses 723system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036753 # mshr miss rate for ReadReq accesses 724system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses 725system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for ReadReq accesses 726system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010784 # mshr miss rate for ReadReq accesses 727system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024588 # mshr miss rate for ReadReq accesses 728system.l2c.ReadReq_mshr_miss_rate::total 0.017563 # mshr miss rate for ReadReq accesses 729system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.808163 # mshr miss rate for UpgradeReq accesses 730system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.867030 # mshr miss rate for UpgradeReq accesses 731system.l2c.UpgradeReq_mshr_miss_rate::total 0.832173 # mshr miss rate for UpgradeReq accesses 732system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721584 # mshr miss rate for SCUpgradeReq accesses 733system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.818493 # mshr miss rate for SCUpgradeReq accesses 734system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.762985 # mshr miss rate for SCUpgradeReq accesses 735system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543772 # mshr miss rate for ReadExReq accesses 736system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579302 # mshr miss rate for ReadExReq accesses 737system.l2c.ReadExReq_mshr_miss_rate::total 0.561669 # mshr miss rate for ReadExReq accesses 738system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for demand accesses 739system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for demand accesses 740system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013500 # mshr miss rate for demand accesses 741system.l2c.demand_mshr_miss_rate::cpu0.data 0.222447 # mshr miss rate for demand accesses 742system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses 743system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for demand accesses 744system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010784 # mshr miss rate for demand accesses 745system.l2c.demand_mshr_miss_rate::cpu1.data 0.279898 # mshr miss rate for demand accesses 746system.l2c.demand_mshr_miss_rate::total 0.106783 # mshr miss rate for demand accesses 747system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for overall accesses 748system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for overall accesses 749system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013500 # mshr miss rate for overall accesses 750system.l2c.overall_mshr_miss_rate::cpu0.data 0.222447 # mshr miss rate for overall accesses 751system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses 752system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for overall accesses 753system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010784 # mshr miss rate for overall accesses 754system.l2c.overall_mshr_miss_rate::cpu1.data 0.279898 # mshr miss rate for overall accesses 755system.l2c.overall_mshr_miss_rate::total 0.106783 # mshr miss rate for overall accesses |
| 738system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency 739system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 756system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency 757system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 740system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average ReadReq mshr miss latency 741system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898 # average ReadReq mshr miss latency | 758system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57887.227550 # average ReadReq mshr miss latency 759system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61256.750605 # average ReadReq mshr miss latency |
| 742system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency | 760system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency |
| 743system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average ReadReq mshr miss latency 744system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117 # average ReadReq mshr miss latency 745system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425 # average ReadReq mshr miss latency 746system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270 # average UpgradeReq mshr miss latency 747system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207 # average UpgradeReq mshr miss latency 748system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255 # average UpgradeReq mshr miss latency 749system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284 # average SCUpgradeReq mshr miss latency 750system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261 # average SCUpgradeReq mshr miss latency 751system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403 # average SCUpgradeReq mshr miss latency 752system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803 # average ReadExReq mshr miss latency 753system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133 # average ReadExReq mshr miss latency 754system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616 # average ReadExReq mshr miss latency | 761system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 762system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average ReadReq mshr miss latency 763system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64062.621091 # average ReadReq mshr miss latency 764system.l2c.ReadReq_avg_mshr_miss_latency::total 60278.328949 # average ReadReq mshr miss latency 765system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.058990 # average UpgradeReq mshr miss latency 766system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.803445 # average UpgradeReq mshr miss latency 767system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10010.350023 # average UpgradeReq mshr miss latency 768system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.651327 # average SCUpgradeReq mshr miss latency 769system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.225941 # average SCUpgradeReq mshr miss latency 770system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10004.831256 # average SCUpgradeReq mshr miss latency 771system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54106.359006 # average ReadExReq mshr miss latency 772system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59659.237029 # average ReadExReq mshr miss latency 773system.l2c.ReadExReq_avg_mshr_miss_latency::total 56991.281699 # average ReadExReq mshr miss latency |
| 755system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 756system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 774system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 775system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 757system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency 758system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency | 776system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57887.227550 # average overall mshr miss latency 777system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54855.081624 # average overall mshr miss latency |
| 759system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency | 778system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency |
| 760system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency 761system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency 762system.l2c.demand_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency | 779system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 780system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average overall mshr miss latency 781system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59868.024895 # average overall mshr miss latency 782system.l2c.demand_avg_mshr_miss_latency::total 57443.266676 # average overall mshr miss latency |
| 763system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 764system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 783system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 784system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 765system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency 766system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency | 785system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57887.227550 # average overall mshr miss latency 786system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54855.081624 # average overall mshr miss latency |
| 767system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency | 787system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency |
| 768system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency 769system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency 770system.l2c.overall_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency | 788system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 789system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average overall mshr miss latency 790system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59868.024895 # average overall mshr miss latency 791system.l2c.overall_avg_mshr_miss_latency::total 57443.266676 # average overall mshr miss latency |
| 771system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 772system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 773system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 774system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 775system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 776system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 777system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 778system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 783system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 784system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 786system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 787system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 788system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 789system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 790system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 792system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 793system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 794system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 795system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 796system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 797system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 798system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 799system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 804system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 805system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 807system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 808system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 809system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 810system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 811system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 791system.toL2Bus.throughput 119642613 # Throughput (bytes/s) 792system.toL2Bus.trans_dist::ReadReq 2536412 # Transaction distribution 793system.toL2Bus.trans_dist::ReadResp 2536412 # Transaction distribution 794system.toL2Bus.trans_dist::WriteReq 767585 # Transaction distribution 795system.toL2Bus.trans_dist::WriteResp 767585 # Transaction distribution 796system.toL2Bus.trans_dist::Writeback 572475 # Transaction distribution 797system.toL2Bus.trans_dist::UpgradeReq 30937 # Transaction distribution 798system.toL2Bus.trans_dist::SCUpgradeReq 17621 # Transaction distribution 799system.toL2Bus.trans_dist::UpgradeResp 48558 # Transaction distribution 800system.toL2Bus.trans_dist::ReadExReq 260776 # Transaction distribution 801system.toL2Bus.trans_dist::ReadExResp 260776 # Transaction distribution 802system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 723469 # Packet count per connected master and slave (bytes) 803system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1059051 # Packet count per connected master and slave (bytes) 804system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4339 # Packet count per connected master and slave (bytes) 805system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7907 # Packet count per connected master and slave (bytes) 806system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1082141 # Packet count per connected master and slave (bytes) 807system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4772543 # Packet count per connected master and slave (bytes) 808system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7929 # Packet count per connected master and slave (bytes) 809system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 20256 # Packet count per connected master and slave (bytes) 810system.toL2Bus.pkt_count::total 7677635 # Packet count per connected master and slave (bytes) 811system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 22743520 # Cumulative packet size per connected master and slave (bytes) 812system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35146882 # Cumulative packet size per connected master and slave (bytes) 813system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6636 # Cumulative packet size per connected master and slave (bytes) 814system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 11992 # Cumulative packet size per connected master and slave (bytes) 815system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34596404 # Cumulative packet size per connected master and slave (bytes) 816system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 46050592 # Cumulative packet size per connected master and slave (bytes) 817system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7620 # Cumulative packet size per connected master and slave (bytes) 818system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 25500 # Cumulative packet size per connected master and slave (bytes) 819system.toL2Bus.tot_pkt_size::total 138589146 # Cumulative packet size per connected master and slave (bytes) 820system.toL2Bus.data_through_bus 138589146 # Total data (bytes) 821system.toL2Bus.snoop_data_through_bus 4530356 # Total snoop data (bytes) 822system.toL2Bus.reqLayer0.occupancy 4766758175 # Layer occupancy (ticks) | 812system.toL2Bus.throughput 119513329 # Throughput (bytes/s) 813system.toL2Bus.trans_dist::ReadReq 2535217 # Transaction distribution 814system.toL2Bus.trans_dist::ReadResp 2535217 # Transaction distribution 815system.toL2Bus.trans_dist::WriteReq 767582 # Transaction distribution 816system.toL2Bus.trans_dist::WriteResp 767582 # Transaction distribution 817system.toL2Bus.trans_dist::Writeback 570869 # Transaction distribution 818system.toL2Bus.trans_dist::UpgradeReq 30989 # Transaction distribution 819system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution 820system.toL2Bus.trans_dist::UpgradeResp 48574 # Transaction distribution 821system.toL2Bus.trans_dist::ReadExReq 260651 # Transaction distribution 822system.toL2Bus.trans_dist::ReadExResp 260651 # Transaction distribution 823system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863496 # Packet count per connected master and slave (bytes) 824system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226215 # Packet count per connected master and slave (bytes) 825system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) 826system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12691 # Packet count per connected master and slave (bytes) 827system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940498 # Packet count per connected master and slave (bytes) 828system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601530 # Packet count per connected master and slave (bytes) 829system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6236 # Packet count per connected master and slave (bytes) 830system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15421 # Packet count per connected master and slave (bytes) 831system.toL2Bus.pkt_count::total 7672224 # Packet count per connected master and slave (bytes) 832system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27215456 # Cumulative packet size per connected master and slave (bytes) 833system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41348685 # Cumulative packet size per connected master and slave (bytes) 834system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) 835system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) 836system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30072692 # Cumulative packet size per connected master and slave (bytes) 837system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39622266 # Cumulative packet size per connected master and slave (bytes) 838system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7640 # Cumulative packet size per connected master and slave (bytes) 839system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22032 # Cumulative packet size per connected master and slave (bytes) 840system.toL2Bus.tot_pkt_size::total 138310979 # Cumulative packet size per connected master and slave (bytes) 841system.toL2Bus.data_through_bus 138310979 # Total data (bytes) 842system.toL2Bus.snoop_data_through_bus 4620420 # Total snoop data (bytes) 843system.toL2Bus.reqLayer0.occupancy 4758868690 # Layer occupancy (ticks) |
| 823system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) | 844system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) |
| 824system.toL2Bus.respLayer0.occupancy 1607753214 # Layer occupancy (ticks) 825system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 826system.toL2Bus.respLayer1.occupancy 1517597206 # Layer occupancy (ticks) | 845system.toL2Bus.respLayer0.occupancy 1923485226 # Layer occupancy (ticks) 846system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 847system.toL2Bus.respLayer1.occupancy 1752589322 # Layer occupancy (ticks) |
| 827system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 848system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 828system.toL2Bus.respLayer2.occupancy 2680000 # Layer occupancy (ticks) | 849system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) |
| 829system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 850system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 830system.toL2Bus.respLayer3.occupancy 4909499 # Layer occupancy (ticks) | 851system.toL2Bus.respLayer3.occupancy 8880000 # Layer occupancy (ticks) |
| 831system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 852system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 832system.toL2Bus.respLayer6.occupancy 2437223968 # Layer occupancy (ticks) | 853system.toL2Bus.respLayer6.occupancy 2117887474 # Layer occupancy (ticks) |
| 833system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) | 854system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) |
| 834system.toL2Bus.respLayer7.occupancy 3163938724 # Layer occupancy (ticks) 835system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) 836system.toL2Bus.respLayer8.occupancy 6024000 # Layer occupancy (ticks) | 855system.toL2Bus.respLayer7.occupancy 2927028338 # Layer occupancy (ticks) 856system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 857system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) |
| 837system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) | 858system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) |
| 838system.toL2Bus.respLayer9.occupancy 13881500 # Layer occupancy (ticks) | 859system.toL2Bus.respLayer9.occupancy 9913999 # Layer occupancy (ticks) |
| 839system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) | 860system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) |
| 840system.iobus.throughput 45388263 # Throughput (bytes/s) 841system.iobus.trans_dist::ReadReq 7671442 # Transaction distribution 842system.iobus.trans_dist::ReadResp 7671442 # Transaction distribution 843system.iobus.trans_dist::WriteReq 7967 # Transaction distribution 844system.iobus.trans_dist::WriteResp 7967 # Transaction distribution 845system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) 846system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8070 # Packet count per connected master and slave (bytes) | 861system.iobus.throughput 45398856 # Throughput (bytes/s) 862system.iobus.trans_dist::ReadReq 7671434 # Transaction distribution 863system.iobus.trans_dist::ReadResp 7671434 # Transaction distribution 864system.iobus.trans_dist::WriteReq 7963 # Transaction distribution 865system.iobus.trans_dist::WriteResp 7963 # Transaction distribution 866system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) |
| 847system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 848system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) 849system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 850system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) | 868system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 869system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 871system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
| 851system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) | 872system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) |
| 852system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 853system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 854system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 855system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 856system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 857system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 858system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 859system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 860system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 861system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 862system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 863system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 864system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 865system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 866system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 873system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 874system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 875system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 876system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 877system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 878system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 879system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 880system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 881system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 882system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 883system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 884system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 885system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 886system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 887system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 888system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 868system.iobus.pkt_count_system.bridge.master::total 2382690 # Packet count per connected master and slave (bytes) | 889system.iobus.pkt_count_system.bridge.master::total 2382666 # Packet count per connected master and slave (bytes) |
| 869system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) | 890system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 891system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) |
| 871system.iobus.pkt_count::total 15358818 # Packet count per connected master and slave (bytes) 872system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) 873system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16140 # Cumulative packet size per connected master and slave (bytes) | 892system.iobus.pkt_count::total 15358794 # Packet count per connected master and slave (bytes) 893system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) |
| 874system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 875system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) 876system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 877system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) | 895system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 896system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 898system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
| 878system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) | 899system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) |
| 879system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 880system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 881system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 882system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 883system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 884system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 885system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 886system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 887system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 888system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 889system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 890system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 891system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 892system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 893system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 900system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 901system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 902system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 903system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 904system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 905system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 906system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 907system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 908system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 909system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 910system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 911system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 912system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 913system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 914system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 915system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 895system.iobus.tot_pkt_size_system.bridge.master::total 2390070 # Cumulative packet size per connected master and slave (bytes) | 916system.iobus.tot_pkt_size_system.bridge.master::total 2390035 # Cumulative packet size per connected master and slave (bytes) |
| 896system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 917system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 918system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 898system.iobus.tot_pkt_size::total 54294582 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.data_through_bus 54294582 # Total data (bytes) 900system.iobus.reqLayer0.occupancy 21430000 # Layer occupancy (ticks) | 919system.iobus.tot_pkt_size::total 54294547 # Cumulative packet size per connected master and slave (bytes) 920system.iobus.data_through_bus 54294547 # Total data (bytes) 921system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) |
| 901system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 922system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 902system.iobus.reqLayer1.occupancy 4041000 # Layer occupancy (ticks) | 923system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) |
| 903system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 904system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 905system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 906system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) 907system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 908system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 909system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 910system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 911system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) | 924system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 925system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 926system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 927system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) 928system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 929system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 930system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 931system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 932system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 912system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) | 933system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) |
| 913system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 914system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 915system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 916system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 917system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 918system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 919system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 920system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) --- 19 unchanged lines hidden (view full) --- 940system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 941system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 942system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 943system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 944system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 945system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 946system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 947system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) | 934system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 935system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 936system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 937system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 938system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 939system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 940system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 941system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) --- 19 unchanged lines hidden (view full) --- 961system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 962system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 963system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 964system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 965system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 966system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 967system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 968system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) |
| 948system.iobus.respLayer0.occupancy 2374723000 # Layer occupancy (ticks) | 969system.iobus.respLayer0.occupancy 2374703000 # Layer occupancy (ticks) |
| 949system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) | 970system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 950system.iobus.respLayer1.occupancy 16195242500 # Layer occupancy (ticks) | 971system.iobus.respLayer1.occupancy 16368811750 # Layer occupancy (ticks) |
| 951system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) 952system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 953system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 954system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 955system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 956system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 957system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 958system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 967system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 968system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 969system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 970system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 971system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 972system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 973system.cpu0.dtb.inst_hits 0 # ITB inst hits 974system.cpu0.dtb.inst_misses 0 # ITB inst misses | 972system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) 973system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 974system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 975system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 976system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 977system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 978system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 979system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 988system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 989system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 990system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 991system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 992system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 993system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 994system.cpu0.dtb.inst_hits 0 # ITB inst hits 995system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 975system.cpu0.dtb.read_hits 5879584 # DTB read hits 976system.cpu0.dtb.read_misses 2138 # DTB read misses 977system.cpu0.dtb.write_hits 4838515 # DTB write hits 978system.cpu0.dtb.write_misses 406 # DTB write misses | 996system.cpu0.dtb.read_hits 7064335 # DTB read hits 997system.cpu0.dtb.read_misses 3758 # DTB read misses 998system.cpu0.dtb.write_hits 5649339 # DTB write hits 999system.cpu0.dtb.write_misses 802 # DTB write misses |
| 979system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 980system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 981system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 982system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1000system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1001system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1002system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1003system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 983system.cpu0.dtb.flush_entries 1387 # Number of entries that have been flushed from TLB | 1004system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB |
| 984system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1005system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 985system.cpu0.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch | 1006system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch |
| 986system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1007system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 987system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions 988system.cpu0.dtb.read_accesses 5881722 # DTB read accesses 989system.cpu0.dtb.write_accesses 4838921 # DTB write accesses | 1008system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1009system.cpu0.dtb.read_accesses 7068093 # DTB read accesses 1010system.cpu0.dtb.write_accesses 5650141 # DTB write accesses |
| 990system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 1011system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 991system.cpu0.dtb.hits 10718099 # DTB hits 992system.cpu0.dtb.misses 2544 # DTB misses 993system.cpu0.dtb.accesses 10720643 # DTB accesses | 1012system.cpu0.dtb.hits 12713674 # DTB hits 1013system.cpu0.dtb.misses 4560 # DTB misses 1014system.cpu0.dtb.accesses 12718234 # DTB accesses |
| 994system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 995system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 996system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 997system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 998system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 999system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1000system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1001system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1007system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1008system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1009system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1010system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1011system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1012system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1013system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1014system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1015system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1016system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1017system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1018system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1019system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1020system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1021system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1022system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1028system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1029system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1030system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1031system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1032system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1033system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1034system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1035system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1015system.cpu0.itb.inst_hits 24773464 # ITB inst hits 1016system.cpu0.itb.inst_misses 1350 # ITB inst misses | 1036system.cpu0.itb.inst_hits 29562995 # ITB inst hits 1037system.cpu0.itb.inst_misses 2205 # ITB inst misses |
| 1017system.cpu0.itb.read_hits 0 # DTB read hits 1018system.cpu0.itb.read_misses 0 # DTB read misses 1019system.cpu0.itb.write_hits 0 # DTB write hits 1020system.cpu0.itb.write_misses 0 # DTB write misses 1021system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1022system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1023system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1024system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1038system.cpu0.itb.read_hits 0 # DTB read hits 1039system.cpu0.itb.read_misses 0 # DTB read misses 1040system.cpu0.itb.write_hits 0 # DTB write hits 1041system.cpu0.itb.write_misses 0 # DTB write misses 1042system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1043system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1044system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1045system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1025system.cpu0.itb.flush_entries 963 # Number of entries that have been flushed from TLB | 1046system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB |
| 1026system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1027system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1028system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1029system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1030system.cpu0.itb.read_accesses 0 # DTB read accesses 1031system.cpu0.itb.write_accesses 0 # DTB write accesses | 1047system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1048system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1049system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1050system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1051system.cpu0.itb.read_accesses 0 # DTB read accesses 1052system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1032system.cpu0.itb.inst_accesses 24774814 # ITB inst accesses 1033system.cpu0.itb.hits 24773464 # DTB hits 1034system.cpu0.itb.misses 1350 # DTB misses 1035system.cpu0.itb.accesses 24774814 # DTB accesses 1036system.cpu0.numCycles 2391604989 # number of cpu cycles simulated | 1053system.cpu0.itb.inst_accesses 29565200 # ITB inst accesses 1054system.cpu0.itb.hits 29562995 # DTB hits 1055system.cpu0.itb.misses 2205 # DTB misses 1056system.cpu0.itb.accesses 29565200 # DTB accesses 1057system.cpu0.numCycles 2391890520 # number of cpu cycles simulated |
| 1037system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1038system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1058system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1059system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1039system.cpu0.committedInsts 24375312 # Number of instructions committed 1040system.cpu0.committedOps 31460856 # Number of ops (including micro ops) committed 1041system.cpu0.num_int_alu_accesses 28085533 # Number of integer alu accesses 1042system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses 1043system.cpu0.num_func_calls 1070699 # number of times a function call or return occured 1044system.cpu0.num_conditional_control_insts 3751745 # number of instructions that are conditional controls 1045system.cpu0.num_int_insts 28085533 # number of integer instructions 1046system.cpu0.num_fp_insts 4364 # number of float instructions 1047system.cpu0.num_int_register_reads 162520351 # number of times the integer registers were read 1048system.cpu0.num_int_register_writes 30535592 # number of times the integer registers were written 1049system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read 1050system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written 1051system.cpu0.num_mem_refs 11309766 # number of memory refs 1052system.cpu0.num_load_insts 6158982 # Number of load instructions 1053system.cpu0.num_store_insts 5150784 # Number of store instructions 1054system.cpu0.num_idle_cycles 2265857607.135565 # Number of idle cycles 1055system.cpu0.num_busy_cycles 125747381.864435 # Number of busy cycles 1056system.cpu0.not_idle_fraction 0.052579 # Percentage of non-idle cycles 1057system.cpu0.idle_fraction 0.947421 # Percentage of idle cycles 1058system.cpu0.Branches 4778581 # Number of branches fetched | 1060system.cpu0.committedInsts 28864889 # Number of instructions committed 1061system.cpu0.committedOps 37190899 # Number of ops (including micro ops) committed 1062system.cpu0.num_int_alu_accesses 33115613 # Number of integer alu accesses 1063system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 1064system.cpu0.num_func_calls 1241798 # number of times a function call or return occured 1065system.cpu0.num_conditional_control_insts 4372441 # number of instructions that are conditional controls 1066system.cpu0.num_int_insts 33115613 # number of integer instructions 1067system.cpu0.num_fp_insts 3860 # number of float instructions 1068system.cpu0.num_int_register_reads 192173380 # number of times the integer registers were read 1069system.cpu0.num_int_register_writes 36248506 # number of times the integer registers were written 1070system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1071system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1072system.cpu0.num_mem_refs 13380838 # number of memory refs 1073system.cpu0.num_load_insts 7401595 # Number of load instructions 1074system.cpu0.num_store_insts 5979243 # Number of store instructions 1075system.cpu0.num_idle_cycles 2246179687.500122 # Number of idle cycles 1076system.cpu0.num_busy_cycles 145710832.499878 # Number of busy cycles 1077system.cpu0.not_idle_fraction 0.060919 # Percentage of non-idle cycles 1078system.cpu0.idle_fraction 0.939081 # Percentage of idle cycles 1079system.cpu0.Branches 5600259 # Number of branches fetched 1080system.cpu0.op_class::No_OpClass 14567 0.04% 0.04% # Class of executed instruction 1081system.cpu0.op_class::IntAlu 24478507 64.56% 64.59% # Class of executed instruction 1082system.cpu0.op_class::IntMult 43773 0.12% 64.71% # Class of executed instruction 1083system.cpu0.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction 1084system.cpu0.op_class::FloatAdd 0 0.00% 64.71% # Class of executed instruction 1085system.cpu0.op_class::FloatCmp 0 0.00% 64.71% # Class of executed instruction 1086system.cpu0.op_class::FloatCvt 0 0.00% 64.71% # Class of executed instruction 1087system.cpu0.op_class::FloatMult 0 0.00% 64.71% # Class of executed instruction 1088system.cpu0.op_class::FloatDiv 0 0.00% 64.71% # Class of executed instruction 1089system.cpu0.op_class::FloatSqrt 0 0.00% 64.71% # Class of executed instruction 1090system.cpu0.op_class::SimdAdd 0 0.00% 64.71% # Class of executed instruction 1091system.cpu0.op_class::SimdAddAcc 0 0.00% 64.71% # Class of executed instruction 1092system.cpu0.op_class::SimdAlu 0 0.00% 64.71% # Class of executed instruction 1093system.cpu0.op_class::SimdCmp 0 0.00% 64.71% # Class of executed instruction 1094system.cpu0.op_class::SimdCvt 0 0.00% 64.71% # Class of executed instruction 1095system.cpu0.op_class::SimdMisc 0 0.00% 64.71% # Class of executed instruction 1096system.cpu0.op_class::SimdMult 0 0.00% 64.71% # Class of executed instruction 1097system.cpu0.op_class::SimdMultAcc 0 0.00% 64.71% # Class of executed instruction 1098system.cpu0.op_class::SimdShift 0 0.00% 64.71% # Class of executed instruction 1099system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.71% # Class of executed instruction 1100system.cpu0.op_class::SimdSqrt 0 0.00% 64.71% # Class of executed instruction 1101system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.71% # Class of executed instruction 1102system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.71% # Class of executed instruction 1103system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.71% # Class of executed instruction 1104system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.71% # Class of executed instruction 1105system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.71% # Class of executed instruction 1106system.cpu0.op_class::SimdFloatMisc 694 0.00% 64.71% # Class of executed instruction 1107system.cpu0.op_class::SimdFloatMult 0 0.00% 64.71% # Class of executed instruction 1108system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.71% # Class of executed instruction 1109system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.71% # Class of executed instruction 1110system.cpu0.op_class::MemRead 7401595 19.52% 84.23% # Class of executed instruction 1111system.cpu0.op_class::MemWrite 5979243 15.77% 100.00% # Class of executed instruction 1112system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1113system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1114system.cpu0.op_class::total 37918379 # Class of executed instruction |
| 1059system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1115system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1060system.cpu0.kern.inst.quiesce 39137 # number of quiesce instructions executed 1061system.cpu0.icache.tags.replacements 354708 # number of replacements 1062system.cpu0.icache.tags.tagsinuse 509.352361 # Cycle average of tags in use 1063system.cpu0.icache.tags.total_refs 24418226 # Total number of references to valid blocks. 1064system.cpu0.icache.tags.sampled_refs 355220 # Sample count of references to valid blocks. 1065system.cpu0.icache.tags.avg_refs 68.741135 # Average number of references to valid blocks. 1066system.cpu0.icache.tags.warmup_cycle 76254991000 # Cycle when the warmup percentage was hit. 1067system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352361 # Average occupied blocks per requestor 1068system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994829 # Average percentage of cache occupancy 1069system.cpu0.icache.tags.occ_percent::total 0.994829 # Average percentage of cache occupancy | 1116system.cpu0.kern.inst.quiesce 46956 # number of quiesce instructions executed 1117system.cpu0.icache.tags.replacements 424861 # number of replacements 1118system.cpu0.icache.tags.tagsinuse 509.353809 # Cycle average of tags in use 1119system.cpu0.icache.tags.total_refs 29137604 # Total number of references to valid blocks. 1120system.cpu0.icache.tags.sampled_refs 425373 # Sample count of references to valid blocks. 1121system.cpu0.icache.tags.avg_refs 68.498950 # Average number of references to valid blocks. 1122system.cpu0.icache.tags.warmup_cycle 76246574000 # Cycle when the warmup percentage was hit. 1123system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.353809 # Average occupied blocks per requestor 1124system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994832 # Average percentage of cache occupancy 1125system.cpu0.icache.tags.occ_percent::total 0.994832 # Average percentage of cache occupancy |
| 1070system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1126system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1071system.cpu0.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id 1072system.cpu0.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 1073system.cpu0.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id | 1127system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 1128system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 1129system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 1130system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id |
| 1074system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1131system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1075system.cpu0.icache.tags.tag_accesses 25128668 # Number of tag accesses 1076system.cpu0.icache.tags.data_accesses 25128668 # Number of data accesses 1077system.cpu0.icache.ReadReq_hits::cpu0.inst 24418226 # number of ReadReq hits 1078system.cpu0.icache.ReadReq_hits::total 24418226 # number of ReadReq hits 1079system.cpu0.icache.demand_hits::cpu0.inst 24418226 # number of demand (read+write) hits 1080system.cpu0.icache.demand_hits::total 24418226 # number of demand (read+write) hits 1081system.cpu0.icache.overall_hits::cpu0.inst 24418226 # number of overall hits 1082system.cpu0.icache.overall_hits::total 24418226 # number of overall hits 1083system.cpu0.icache.ReadReq_misses::cpu0.inst 355221 # number of ReadReq misses 1084system.cpu0.icache.ReadReq_misses::total 355221 # number of ReadReq misses 1085system.cpu0.icache.demand_misses::cpu0.inst 355221 # number of demand (read+write) misses 1086system.cpu0.icache.demand_misses::total 355221 # number of demand (read+write) misses 1087system.cpu0.icache.overall_misses::cpu0.inst 355221 # number of overall misses 1088system.cpu0.icache.overall_misses::total 355221 # number of overall misses 1089system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4963623214 # number of ReadReq miss cycles 1090system.cpu0.icache.ReadReq_miss_latency::total 4963623214 # number of ReadReq miss cycles 1091system.cpu0.icache.demand_miss_latency::cpu0.inst 4963623214 # number of demand (read+write) miss cycles 1092system.cpu0.icache.demand_miss_latency::total 4963623214 # number of demand (read+write) miss cycles 1093system.cpu0.icache.overall_miss_latency::cpu0.inst 4963623214 # number of overall miss cycles 1094system.cpu0.icache.overall_miss_latency::total 4963623214 # number of overall miss cycles 1095system.cpu0.icache.ReadReq_accesses::cpu0.inst 24773447 # number of ReadReq accesses(hits+misses) 1096system.cpu0.icache.ReadReq_accesses::total 24773447 # number of ReadReq accesses(hits+misses) 1097system.cpu0.icache.demand_accesses::cpu0.inst 24773447 # number of demand (read+write) accesses 1098system.cpu0.icache.demand_accesses::total 24773447 # number of demand (read+write) accesses 1099system.cpu0.icache.overall_accesses::cpu0.inst 24773447 # number of overall (read+write) accesses 1100system.cpu0.icache.overall_accesses::total 24773447 # number of overall (read+write) accesses 1101system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014339 # miss rate for ReadReq accesses 1102system.cpu0.icache.ReadReq_miss_rate::total 0.014339 # miss rate for ReadReq accesses 1103system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014339 # miss rate for demand accesses 1104system.cpu0.icache.demand_miss_rate::total 0.014339 # miss rate for demand accesses 1105system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014339 # miss rate for overall accesses 1106system.cpu0.icache.overall_miss_rate::total 0.014339 # miss rate for overall accesses 1107system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327 # average ReadReq miss latency 1108system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327 # average ReadReq miss latency 1109system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency 1110system.cpu0.icache.demand_avg_miss_latency::total 13973.338327 # average overall miss latency 1111system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency 1112system.cpu0.icache.overall_avg_miss_latency::total 13973.338327 # average overall miss latency | 1132system.cpu0.icache.tags.tag_accesses 29988352 # Number of tag accesses 1133system.cpu0.icache.tags.data_accesses 29988352 # Number of data accesses 1134system.cpu0.icache.ReadReq_hits::cpu0.inst 29137604 # number of ReadReq hits 1135system.cpu0.icache.ReadReq_hits::total 29137604 # number of ReadReq hits 1136system.cpu0.icache.demand_hits::cpu0.inst 29137604 # number of demand (read+write) hits 1137system.cpu0.icache.demand_hits::total 29137604 # number of demand (read+write) hits 1138system.cpu0.icache.overall_hits::cpu0.inst 29137604 # number of overall hits 1139system.cpu0.icache.overall_hits::total 29137604 # number of overall hits 1140system.cpu0.icache.ReadReq_misses::cpu0.inst 425374 # number of ReadReq misses 1141system.cpu0.icache.ReadReq_misses::total 425374 # number of ReadReq misses 1142system.cpu0.icache.demand_misses::cpu0.inst 425374 # number of demand (read+write) misses 1143system.cpu0.icache.demand_misses::total 425374 # number of demand (read+write) misses 1144system.cpu0.icache.overall_misses::cpu0.inst 425374 # number of overall misses 1145system.cpu0.icache.overall_misses::total 425374 # number of overall misses 1146system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5893447476 # number of ReadReq miss cycles 1147system.cpu0.icache.ReadReq_miss_latency::total 5893447476 # number of ReadReq miss cycles 1148system.cpu0.icache.demand_miss_latency::cpu0.inst 5893447476 # number of demand (read+write) miss cycles 1149system.cpu0.icache.demand_miss_latency::total 5893447476 # number of demand (read+write) miss cycles 1150system.cpu0.icache.overall_miss_latency::cpu0.inst 5893447476 # number of overall miss cycles 1151system.cpu0.icache.overall_miss_latency::total 5893447476 # number of overall miss cycles 1152system.cpu0.icache.ReadReq_accesses::cpu0.inst 29562978 # number of ReadReq accesses(hits+misses) 1153system.cpu0.icache.ReadReq_accesses::total 29562978 # number of ReadReq accesses(hits+misses) 1154system.cpu0.icache.demand_accesses::cpu0.inst 29562978 # number of demand (read+write) accesses 1155system.cpu0.icache.demand_accesses::total 29562978 # number of demand (read+write) accesses 1156system.cpu0.icache.overall_accesses::cpu0.inst 29562978 # number of overall (read+write) accesses 1157system.cpu0.icache.overall_accesses::total 29562978 # number of overall (read+write) accesses 1158system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014389 # miss rate for ReadReq accesses 1159system.cpu0.icache.ReadReq_miss_rate::total 0.014389 # miss rate for ReadReq accesses 1160system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014389 # miss rate for demand accesses 1161system.cpu0.icache.demand_miss_rate::total 0.014389 # miss rate for demand accesses 1162system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014389 # miss rate for overall accesses 1163system.cpu0.icache.overall_miss_rate::total 0.014389 # miss rate for overall accesses 1164system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13854.743064 # average ReadReq miss latency 1165system.cpu0.icache.ReadReq_avg_miss_latency::total 13854.743064 # average ReadReq miss latency 1166system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13854.743064 # average overall miss latency 1167system.cpu0.icache.demand_avg_miss_latency::total 13854.743064 # average overall miss latency 1168system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13854.743064 # average overall miss latency 1169system.cpu0.icache.overall_avg_miss_latency::total 13854.743064 # average overall miss latency |
| 1113system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1114system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1115system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1116system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1117system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1118system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1119system.cpu0.icache.fast_writes 0 # number of fast writes performed 1120system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1170system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1171system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1172system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1173system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1174system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1175system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1176system.cpu0.icache.fast_writes 0 # number of fast writes performed 1177system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1121system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355221 # number of ReadReq MSHR misses 1122system.cpu0.icache.ReadReq_mshr_misses::total 355221 # number of ReadReq MSHR misses 1123system.cpu0.icache.demand_mshr_misses::cpu0.inst 355221 # number of demand (read+write) MSHR misses 1124system.cpu0.icache.demand_mshr_misses::total 355221 # number of demand (read+write) MSHR misses 1125system.cpu0.icache.overall_mshr_misses::cpu0.inst 355221 # number of overall MSHR misses 1126system.cpu0.icache.overall_mshr_misses::total 355221 # number of overall MSHR misses 1127system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4251043786 # number of ReadReq MSHR miss cycles 1128system.cpu0.icache.ReadReq_mshr_miss_latency::total 4251043786 # number of ReadReq MSHR miss cycles 1129system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4251043786 # number of demand (read+write) MSHR miss cycles 1130system.cpu0.icache.demand_mshr_miss_latency::total 4251043786 # number of demand (read+write) MSHR miss cycles 1131system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4251043786 # number of overall MSHR miss cycles 1132system.cpu0.icache.overall_mshr_miss_latency::total 4251043786 # number of overall MSHR miss cycles 1133system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 443885000 # number of ReadReq MSHR uncacheable cycles 1134system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles 1135system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 443885000 # number of overall MSHR uncacheable cycles 1136system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles 1137system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for ReadReq accesses 1138system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014339 # mshr miss rate for ReadReq accesses 1139system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for demand accesses 1140system.cpu0.icache.demand_mshr_miss_rate::total 0.014339 # mshr miss rate for demand accesses 1141system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for overall accesses 1142system.cpu0.icache.overall_mshr_miss_rate::total 0.014339 # mshr miss rate for overall accesses 1143system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average ReadReq mshr miss latency 1144system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149 # average ReadReq mshr miss latency 1145system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency 1146system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency 1147system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency 1148system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency | 1178system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425374 # number of ReadReq MSHR misses 1179system.cpu0.icache.ReadReq_mshr_misses::total 425374 # number of ReadReq MSHR misses 1180system.cpu0.icache.demand_mshr_misses::cpu0.inst 425374 # number of demand (read+write) MSHR misses 1181system.cpu0.icache.demand_mshr_misses::total 425374 # number of demand (read+write) MSHR misses 1182system.cpu0.icache.overall_mshr_misses::cpu0.inst 425374 # number of overall MSHR misses 1183system.cpu0.icache.overall_mshr_misses::total 425374 # number of overall MSHR misses 1184system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5040497524 # number of ReadReq MSHR miss cycles 1185system.cpu0.icache.ReadReq_mshr_miss_latency::total 5040497524 # number of ReadReq MSHR miss cycles 1186system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5040497524 # number of demand (read+write) MSHR miss cycles 1187system.cpu0.icache.demand_mshr_miss_latency::total 5040497524 # number of demand (read+write) MSHR miss cycles 1188system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5040497524 # number of overall MSHR miss cycles 1189system.cpu0.icache.overall_mshr_miss_latency::total 5040497524 # number of overall MSHR miss cycles 1190system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442131250 # number of ReadReq MSHR uncacheable cycles 1191system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442131250 # number of ReadReq MSHR uncacheable cycles 1192system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442131250 # number of overall MSHR uncacheable cycles 1193system.cpu0.icache.overall_mshr_uncacheable_latency::total 442131250 # number of overall MSHR uncacheable cycles 1194system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for ReadReq accesses 1195system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014389 # mshr miss rate for ReadReq accesses 1196system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for demand accesses 1197system.cpu0.icache.demand_mshr_miss_rate::total 0.014389 # mshr miss rate for demand accesses 1198system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for overall accesses 1199system.cpu0.icache.overall_mshr_miss_rate::total 0.014389 # mshr miss rate for overall accesses 1200system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average ReadReq mshr miss latency 1201system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11849.566556 # average ReadReq mshr miss latency 1202system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average overall mshr miss latency 1203system.cpu0.icache.demand_avg_mshr_miss_latency::total 11849.566556 # average overall mshr miss latency 1204system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average overall mshr miss latency 1205system.cpu0.icache.overall_avg_mshr_miss_latency::total 11849.566556 # average overall mshr miss latency |
| 1149system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1150system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1151system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1152system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1153system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1206system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1207system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1208system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1209system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1210system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1154system.cpu0.dcache.tags.replacements 278858 # number of replacements 1155system.cpu0.dcache.tags.tagsinuse 453.142717 # Cycle average of tags in use 1156system.cpu0.dcache.tags.total_refs 10319958 # Total number of references to valid blocks. 1157system.cpu0.dcache.tags.sampled_refs 279247 # Sample count of references to valid blocks. 1158system.cpu0.dcache.tags.avg_refs 36.956379 # Average number of references to valid blocks. 1159system.cpu0.dcache.tags.warmup_cycle 673996250 # Cycle when the warmup percentage was hit. 1160system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.142717 # Average occupied blocks per requestor 1161system.cpu0.dcache.tags.occ_percent::cpu0.data 0.885044 # Average percentage of cache occupancy 1162system.cpu0.dcache.tags.occ_percent::total 0.885044 # Average percentage of cache occupancy 1163system.cpu0.dcache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id 1164system.cpu0.dcache.tags.age_task_id_blocks_1024::2 379 # Occupied blocks per task id 1165system.cpu0.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 1166system.cpu0.dcache.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id 1167system.cpu0.dcache.tags.tag_accesses 42855830 # Number of tag accesses 1168system.cpu0.dcache.tags.data_accesses 42855830 # Number of data accesses 1169system.cpu0.dcache.ReadReq_hits::cpu0.data 5473702 # number of ReadReq hits 1170system.cpu0.dcache.ReadReq_hits::total 5473702 # number of ReadReq hits 1171system.cpu0.dcache.WriteReq_hits::cpu0.data 4567964 # number of WriteReq hits 1172system.cpu0.dcache.WriteReq_hits::total 4567964 # number of WriteReq hits 1173system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129389 # number of LoadLockedReq hits 1174system.cpu0.dcache.LoadLockedReq_hits::total 129389 # number of LoadLockedReq hits 1175system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130155 # number of StoreCondReq hits 1176system.cpu0.dcache.StoreCondReq_hits::total 130155 # number of StoreCondReq hits 1177system.cpu0.dcache.demand_hits::cpu0.data 10041666 # number of demand (read+write) hits 1178system.cpu0.dcache.demand_hits::total 10041666 # number of demand (read+write) hits 1179system.cpu0.dcache.overall_hits::cpu0.data 10041666 # number of overall hits 1180system.cpu0.dcache.overall_hits::total 10041666 # number of overall hits 1181system.cpu0.dcache.ReadReq_misses::cpu0.data 191503 # number of ReadReq misses 1182system.cpu0.dcache.ReadReq_misses::total 191503 # number of ReadReq misses 1183system.cpu0.dcache.WriteReq_misses::cpu0.data 126416 # number of WriteReq misses 1184system.cpu0.dcache.WriteReq_misses::total 126416 # number of WriteReq misses 1185system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8708 # number of LoadLockedReq misses 1186system.cpu0.dcache.LoadLockedReq_misses::total 8708 # number of LoadLockedReq misses 1187system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7742 # number of StoreCondReq misses 1188system.cpu0.dcache.StoreCondReq_misses::total 7742 # number of StoreCondReq misses 1189system.cpu0.dcache.demand_misses::cpu0.data 317919 # number of demand (read+write) misses 1190system.cpu0.dcache.demand_misses::total 317919 # number of demand (read+write) misses 1191system.cpu0.dcache.overall_misses::cpu0.data 317919 # number of overall misses 1192system.cpu0.dcache.overall_misses::total 317919 # number of overall misses 1193system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2845005745 # number of ReadReq miss cycles 1194system.cpu0.dcache.ReadReq_miss_latency::total 2845005745 # number of ReadReq miss cycles 1195system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5278408391 # number of WriteReq miss cycles 1196system.cpu0.dcache.WriteReq_miss_latency::total 5278408391 # number of WriteReq miss cycles 1197system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82648500 # number of LoadLockedReq miss cycles 1198system.cpu0.dcache.LoadLockedReq_miss_latency::total 82648500 # number of LoadLockedReq miss cycles 1199system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45599070 # number of StoreCondReq miss cycles 1200system.cpu0.dcache.StoreCondReq_miss_latency::total 45599070 # number of StoreCondReq miss cycles 1201system.cpu0.dcache.demand_miss_latency::cpu0.data 8123414136 # number of demand (read+write) miss cycles 1202system.cpu0.dcache.demand_miss_latency::total 8123414136 # number of demand (read+write) miss cycles 1203system.cpu0.dcache.overall_miss_latency::cpu0.data 8123414136 # number of overall miss cycles 1204system.cpu0.dcache.overall_miss_latency::total 8123414136 # number of overall miss cycles 1205system.cpu0.dcache.ReadReq_accesses::cpu0.data 5665205 # number of ReadReq accesses(hits+misses) 1206system.cpu0.dcache.ReadReq_accesses::total 5665205 # number of ReadReq accesses(hits+misses) 1207system.cpu0.dcache.WriteReq_accesses::cpu0.data 4694380 # number of WriteReq accesses(hits+misses) 1208system.cpu0.dcache.WriteReq_accesses::total 4694380 # number of WriteReq accesses(hits+misses) 1209system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138097 # number of LoadLockedReq accesses(hits+misses) 1210system.cpu0.dcache.LoadLockedReq_accesses::total 138097 # number of LoadLockedReq accesses(hits+misses) 1211system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137897 # number of StoreCondReq accesses(hits+misses) 1212system.cpu0.dcache.StoreCondReq_accesses::total 137897 # number of StoreCondReq accesses(hits+misses) 1213system.cpu0.dcache.demand_accesses::cpu0.data 10359585 # number of demand (read+write) accesses 1214system.cpu0.dcache.demand_accesses::total 10359585 # number of demand (read+write) accesses 1215system.cpu0.dcache.overall_accesses::cpu0.data 10359585 # number of overall (read+write) accesses 1216system.cpu0.dcache.overall_accesses::total 10359585 # number of overall (read+write) accesses 1217system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033803 # miss rate for ReadReq accesses 1218system.cpu0.dcache.ReadReq_miss_rate::total 0.033803 # miss rate for ReadReq accesses 1219system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses 1220system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses 1221system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063057 # miss rate for LoadLockedReq accesses 1222system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063057 # miss rate for LoadLockedReq accesses 1223system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056143 # miss rate for StoreCondReq accesses 1224system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056143 # miss rate for StoreCondReq accesses 1225system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030688 # miss rate for demand accesses 1226system.cpu0.dcache.demand_miss_rate::total 0.030688 # miss rate for demand accesses 1227system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030688 # miss rate for overall accesses 1228system.cpu0.dcache.overall_miss_rate::total 0.030688 # miss rate for overall accesses 1229system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133 # average ReadReq miss latency 1230system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133 # average ReadReq miss latency 1231system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704 # average WriteReq miss latency 1232system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704 # average WriteReq miss latency 1233system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9491.100138 # average LoadLockedReq miss latency 1234system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9491.100138 # average LoadLockedReq miss latency 1235system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5889.830793 # average StoreCondReq miss latency 1236system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5889.830793 # average StoreCondReq miss latency 1237system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency 1238system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958 # average overall miss latency 1239system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency 1240system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958 # average overall miss latency | 1211system.cpu0.dcache.tags.replacements 329701 # number of replacements 1212system.cpu0.dcache.tags.tagsinuse 455.940244 # Cycle average of tags in use 1213system.cpu0.dcache.tags.total_refs 12258862 # Total number of references to valid blocks. 1214system.cpu0.dcache.tags.sampled_refs 330213 # Sample count of references to valid blocks. 1215system.cpu0.dcache.tags.avg_refs 37.124105 # Average number of references to valid blocks. 1216system.cpu0.dcache.tags.warmup_cycle 671876250 # Cycle when the warmup percentage was hit. 1217system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.940244 # Average occupied blocks per requestor 1218system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890508 # Average percentage of cache occupancy 1219system.cpu0.dcache.tags.occ_percent::total 0.890508 # Average percentage of cache occupancy 1220system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1221system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 1222system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id 1223system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id 1224system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1225system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1226system.cpu0.dcache.tags.tag_accesses 50852546 # Number of tag accesses 1227system.cpu0.dcache.tags.data_accesses 50852546 # Number of data accesses 1228system.cpu0.dcache.ReadReq_hits::cpu0.data 6594319 # number of ReadReq hits 1229system.cpu0.dcache.ReadReq_hits::total 6594319 # number of ReadReq hits 1230system.cpu0.dcache.WriteReq_hits::cpu0.data 5344510 # number of WriteReq hits 1231system.cpu0.dcache.WriteReq_hits::total 5344510 # number of WriteReq hits 1232system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148000 # number of LoadLockedReq hits 1233system.cpu0.dcache.LoadLockedReq_hits::total 148000 # number of LoadLockedReq hits 1234system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149609 # number of StoreCondReq hits 1235system.cpu0.dcache.StoreCondReq_hits::total 149609 # number of StoreCondReq hits 1236system.cpu0.dcache.demand_hits::cpu0.data 11938829 # number of demand (read+write) hits 1237system.cpu0.dcache.demand_hits::total 11938829 # number of demand (read+write) hits 1238system.cpu0.dcache.overall_hits::cpu0.data 11938829 # number of overall hits 1239system.cpu0.dcache.overall_hits::total 11938829 # number of overall hits 1240system.cpu0.dcache.ReadReq_misses::cpu0.data 227548 # number of ReadReq misses 1241system.cpu0.dcache.ReadReq_misses::total 227548 # number of ReadReq misses 1242system.cpu0.dcache.WriteReq_misses::cpu0.data 141421 # number of WriteReq misses 1243system.cpu0.dcache.WriteReq_misses::total 141421 # number of WriteReq misses 1244system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9358 # number of LoadLockedReq misses 1245system.cpu0.dcache.LoadLockedReq_misses::total 9358 # number of LoadLockedReq misses 1246system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7517 # number of StoreCondReq misses 1247system.cpu0.dcache.StoreCondReq_misses::total 7517 # number of StoreCondReq misses 1248system.cpu0.dcache.demand_misses::cpu0.data 368969 # number of demand (read+write) misses 1249system.cpu0.dcache.demand_misses::total 368969 # number of demand (read+write) misses 1250system.cpu0.dcache.overall_misses::cpu0.data 368969 # number of overall misses 1251system.cpu0.dcache.overall_misses::total 368969 # number of overall misses 1252system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3297192496 # number of ReadReq miss cycles 1253system.cpu0.dcache.ReadReq_miss_latency::total 3297192496 # number of ReadReq miss cycles 1254system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5650617511 # number of WriteReq miss cycles 1255system.cpu0.dcache.WriteReq_miss_latency::total 5650617511 # number of WriteReq miss cycles 1256system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92814250 # number of LoadLockedReq miss cycles 1257system.cpu0.dcache.LoadLockedReq_miss_latency::total 92814250 # number of LoadLockedReq miss cycles 1258system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44512065 # number of StoreCondReq miss cycles 1259system.cpu0.dcache.StoreCondReq_miss_latency::total 44512065 # number of StoreCondReq miss cycles 1260system.cpu0.dcache.demand_miss_latency::cpu0.data 8947810007 # number of demand (read+write) miss cycles 1261system.cpu0.dcache.demand_miss_latency::total 8947810007 # number of demand (read+write) miss cycles 1262system.cpu0.dcache.overall_miss_latency::cpu0.data 8947810007 # number of overall miss cycles 1263system.cpu0.dcache.overall_miss_latency::total 8947810007 # number of overall miss cycles 1264system.cpu0.dcache.ReadReq_accesses::cpu0.data 6821867 # number of ReadReq accesses(hits+misses) 1265system.cpu0.dcache.ReadReq_accesses::total 6821867 # number of ReadReq accesses(hits+misses) 1266system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485931 # number of WriteReq accesses(hits+misses) 1267system.cpu0.dcache.WriteReq_accesses::total 5485931 # number of WriteReq accesses(hits+misses) 1268system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157358 # number of LoadLockedReq accesses(hits+misses) 1269system.cpu0.dcache.LoadLockedReq_accesses::total 157358 # number of LoadLockedReq accesses(hits+misses) 1270system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157126 # number of StoreCondReq accesses(hits+misses) 1271system.cpu0.dcache.StoreCondReq_accesses::total 157126 # number of StoreCondReq accesses(hits+misses) 1272system.cpu0.dcache.demand_accesses::cpu0.data 12307798 # number of demand (read+write) accesses 1273system.cpu0.dcache.demand_accesses::total 12307798 # number of demand (read+write) accesses 1274system.cpu0.dcache.overall_accesses::cpu0.data 12307798 # number of overall (read+write) accesses 1275system.cpu0.dcache.overall_accesses::total 12307798 # number of overall (read+write) accesses 1276system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033356 # miss rate for ReadReq accesses 1277system.cpu0.dcache.ReadReq_miss_rate::total 0.033356 # miss rate for ReadReq accesses 1278system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025779 # miss rate for WriteReq accesses 1279system.cpu0.dcache.WriteReq_miss_rate::total 0.025779 # miss rate for WriteReq accesses 1280system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059469 # miss rate for LoadLockedReq accesses 1281system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059469 # miss rate for LoadLockedReq accesses 1282system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047841 # miss rate for StoreCondReq accesses 1283system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047841 # miss rate for StoreCondReq accesses 1284system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029978 # miss rate for demand accesses 1285system.cpu0.dcache.demand_miss_rate::total 0.029978 # miss rate for demand accesses 1286system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029978 # miss rate for overall accesses 1287system.cpu0.dcache.overall_miss_rate::total 0.029978 # miss rate for overall accesses 1288system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577 # average ReadReq miss latency 1289system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577 # average ReadReq miss latency 1290system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247 # average WriteReq miss latency 1291system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247 # average WriteReq miss latency 1292system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9918.171618 # average LoadLockedReq miss latency 1293system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9918.171618 # average LoadLockedReq miss latency 1294system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5921.519888 # average StoreCondReq miss latency 1295system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5921.519888 # average StoreCondReq miss latency 1296system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency 1297system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941 # average overall miss latency 1298system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency 1299system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941 # average overall miss latency |
| 1241system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1242system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1243system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1244system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1245system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1246system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1247system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1248system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1300system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1301system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1302system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1303system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1304system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1305system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1306system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1307system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1249system.cpu0.dcache.writebacks::writebacks 257140 # number of writebacks 1250system.cpu0.dcache.writebacks::total 257140 # number of writebacks 1251system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191503 # number of ReadReq MSHR misses 1252system.cpu0.dcache.ReadReq_mshr_misses::total 191503 # number of ReadReq MSHR misses 1253system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126416 # number of WriteReq MSHR misses 1254system.cpu0.dcache.WriteReq_mshr_misses::total 126416 # number of WriteReq MSHR misses 1255system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8708 # number of LoadLockedReq MSHR misses 1256system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8708 # number of LoadLockedReq MSHR misses 1257system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7738 # number of StoreCondReq MSHR misses 1258system.cpu0.dcache.StoreCondReq_mshr_misses::total 7738 # number of StoreCondReq MSHR misses 1259system.cpu0.dcache.demand_mshr_misses::cpu0.data 317919 # number of demand (read+write) MSHR misses 1260system.cpu0.dcache.demand_mshr_misses::total 317919 # number of demand (read+write) MSHR misses 1261system.cpu0.dcache.overall_mshr_misses::cpu0.data 317919 # number of overall MSHR misses 1262system.cpu0.dcache.overall_mshr_misses::total 317919 # number of overall MSHR misses 1263system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2460118255 # number of ReadReq MSHR miss cycles 1264system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460118255 # number of ReadReq MSHR miss cycles 1265system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4997663609 # number of WriteReq MSHR miss cycles 1266system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4997663609 # number of WriteReq MSHR miss cycles 1267system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65185500 # number of LoadLockedReq MSHR miss cycles 1268system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65185500 # number of LoadLockedReq MSHR miss cycles 1269system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30121930 # number of StoreCondReq MSHR miss cycles 1270system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30121930 # number of StoreCondReq MSHR miss cycles 1271system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7457781864 # number of demand (read+write) MSHR miss cycles 1272system.cpu0.dcache.demand_mshr_miss_latency::total 7457781864 # number of demand (read+write) MSHR miss cycles 1273system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7457781864 # number of overall MSHR miss cycles 1274system.cpu0.dcache.overall_mshr_miss_latency::total 7457781864 # number of overall MSHR miss cycles 1275system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12214482000 # number of ReadReq MSHR uncacheable cycles 1276system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12214482000 # number of ReadReq MSHR uncacheable cycles 1277system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1164635000 # number of WriteReq MSHR uncacheable cycles 1278system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1164635000 # number of WriteReq MSHR uncacheable cycles 1279system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13379117000 # number of overall MSHR uncacheable cycles 1280system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13379117000 # number of overall MSHR uncacheable cycles 1281system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033803 # mshr miss rate for ReadReq accesses 1282system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033803 # mshr miss rate for ReadReq accesses 1283system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses 1284system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses 1285system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063057 # mshr miss rate for LoadLockedReq accesses 1286system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063057 # mshr miss rate for LoadLockedReq accesses 1287system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056114 # mshr miss rate for StoreCondReq accesses 1288system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056114 # mshr miss rate for StoreCondReq accesses 1289system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for demand accesses 1290system.cpu0.dcache.demand_mshr_miss_rate::total 0.030688 # mshr miss rate for demand accesses 1291system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for overall accesses 1292system.cpu0.dcache.overall_mshr_miss_rate::total 0.030688 # mshr miss rate for overall accesses 1293system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274 # average ReadReq mshr miss latency 1294system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274 # average ReadReq mshr miss latency 1295system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682 # average WriteReq mshr miss latency 1296system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682 # average WriteReq mshr miss latency 1297system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7485.702802 # average LoadLockedReq mshr miss latency 1298system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7485.702802 # average LoadLockedReq mshr miss latency 1299system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3892.728095 # average StoreCondReq mshr miss latency 1300system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3892.728095 # average StoreCondReq mshr miss latency 1301system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency 1302system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency 1303system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency 1304system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency | 1308system.cpu0.dcache.writebacks::writebacks 305583 # number of writebacks 1309system.cpu0.dcache.writebacks::total 305583 # number of writebacks 1310system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227548 # number of ReadReq MSHR misses 1311system.cpu0.dcache.ReadReq_mshr_misses::total 227548 # number of ReadReq MSHR misses 1312system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141421 # number of WriteReq MSHR misses 1313system.cpu0.dcache.WriteReq_mshr_misses::total 141421 # number of WriteReq MSHR misses 1314system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9358 # number of LoadLockedReq MSHR misses 1315system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9358 # number of LoadLockedReq MSHR misses 1316system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7515 # number of StoreCondReq MSHR misses 1317system.cpu0.dcache.StoreCondReq_mshr_misses::total 7515 # number of StoreCondReq MSHR misses 1318system.cpu0.dcache.demand_mshr_misses::cpu0.data 368969 # number of demand (read+write) MSHR misses 1319system.cpu0.dcache.demand_mshr_misses::total 368969 # number of demand (read+write) MSHR misses 1320system.cpu0.dcache.overall_mshr_misses::cpu0.data 368969 # number of overall MSHR misses 1321system.cpu0.dcache.overall_mshr_misses::total 368969 # number of overall MSHR misses 1322system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2840145504 # number of ReadReq MSHR miss cycles 1323system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2840145504 # number of ReadReq MSHR miss cycles 1324system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338354489 # number of WriteReq MSHR miss cycles 1325system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338354489 # number of WriteReq MSHR miss cycles 1326system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74046750 # number of LoadLockedReq MSHR miss cycles 1327system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74046750 # number of LoadLockedReq MSHR miss cycles 1328system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29480935 # number of StoreCondReq MSHR miss cycles 1329system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29480935 # number of StoreCondReq MSHR miss cycles 1330system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8178499993 # number of demand (read+write) MSHR miss cycles 1331system.cpu0.dcache.demand_mshr_miss_latency::total 8178499993 # number of demand (read+write) MSHR miss cycles 1332system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8178499993 # number of overall MSHR miss cycles 1333system.cpu0.dcache.overall_mshr_miss_latency::total 8178499993 # number of overall MSHR miss cycles 1334system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564071000 # number of ReadReq MSHR uncacheable cycles 1335system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564071000 # number of ReadReq MSHR uncacheable cycles 1336system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170919500 # number of WriteReq MSHR uncacheable cycles 1337system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170919500 # number of WriteReq MSHR uncacheable cycles 1338system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14734990500 # number of overall MSHR uncacheable cycles 1339system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14734990500 # number of overall MSHR uncacheable cycles 1340system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033356 # mshr miss rate for ReadReq accesses 1341system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033356 # mshr miss rate for ReadReq accesses 1342system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025779 # mshr miss rate for WriteReq accesses 1343system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025779 # mshr miss rate for WriteReq accesses 1344system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059469 # mshr miss rate for LoadLockedReq accesses 1345system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059469 # mshr miss rate for LoadLockedReq accesses 1346system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047828 # mshr miss rate for StoreCondReq accesses 1347system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047828 # mshr miss rate for StoreCondReq accesses 1348system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for demand accesses 1349system.cpu0.dcache.demand_mshr_miss_rate::total 0.029978 # mshr miss rate for demand accesses 1350system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for overall accesses 1351system.cpu0.dcache.overall_mshr_miss_rate::total 0.029978 # mshr miss rate for overall accesses 1352system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597 # average ReadReq mshr miss latency 1353system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597 # average ReadReq mshr miss latency 1354system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682 # average WriteReq mshr miss latency 1355system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682 # average WriteReq mshr miss latency 1356system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.668305 # average LoadLockedReq mshr miss latency 1357system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.668305 # average LoadLockedReq mshr miss latency 1358system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3922.945442 # average StoreCondReq mshr miss latency 1359system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3922.945442 # average StoreCondReq mshr miss latency 1360system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency 1361system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency 1362system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency 1363system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency |
| 1305system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1306system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1307system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1308system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1309system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1310system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1311system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1312system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits --- 14 unchanged lines hidden (view full) --- 1327system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1328system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1329system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1330system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1331system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1332system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1333system.cpu1.dtb.inst_hits 0 # ITB inst hits 1334system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1364system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1365system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1366system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1367system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1368system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1369system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1370system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1371system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits --- 14 unchanged lines hidden (view full) --- 1386system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1387system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1388system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1389system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1390system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1391system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1392system.cpu1.dtb.inst_hits 0 # ITB inst hits 1393system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1335system.cpu1.dtb.read_hits 9507781 # DTB read hits 1336system.cpu1.dtb.read_misses 5255 # DTB read misses 1337system.cpu1.dtb.write_hits 6647969 # DTB write hits 1338system.cpu1.dtb.write_misses 1834 # DTB write misses | 1394system.cpu1.dtb.read_hits 8317790 # DTB read hits 1395system.cpu1.dtb.read_misses 3645 # DTB read misses 1396system.cpu1.dtb.write_hits 5833574 # DTB write hits 1397system.cpu1.dtb.write_misses 1433 # DTB write misses |
| 1339system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1340system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1341system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1342system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1398system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1399system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1400system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1401system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1343system.cpu1.dtb.flush_entries 2187 # Number of entries that have been flushed from TLB | 1402system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB |
| 1344system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1403system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1345system.cpu1.dtb.prefetch_faults 188 # Number of TLB faults due to prefetch | 1404system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch |
| 1346system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1405system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1347system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions 1348system.cpu1.dtb.read_accesses 9513036 # DTB read accesses 1349system.cpu1.dtb.write_accesses 6649803 # DTB write accesses | 1406system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1407system.cpu1.dtb.read_accesses 8321435 # DTB read accesses 1408system.cpu1.dtb.write_accesses 5835007 # DTB write accesses |
| 1350system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1409system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1351system.cpu1.dtb.hits 16155750 # DTB hits 1352system.cpu1.dtb.misses 7089 # DTB misses 1353system.cpu1.dtb.accesses 16162839 # DTB accesses | 1410system.cpu1.dtb.hits 14151364 # DTB hits 1411system.cpu1.dtb.misses 5078 # DTB misses 1412system.cpu1.dtb.accesses 14156442 # DTB accesses |
| 1354system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1355system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1356system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1357system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1358system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1359system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1360system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1361system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1367system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1368system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1369system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1370system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1371system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1372system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1373system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1374system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1413system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1414system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1415system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1416system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1417system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1418system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1419system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1420system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1426system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1427system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1428system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1429system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1430system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1431system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1432system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1433system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1375system.cpu1.itb.inst_hits 38008437 # ITB inst hits 1376system.cpu1.itb.inst_misses 3017 # ITB inst misses | 1434system.cpu1.itb.inst_hits 33205963 # ITB inst hits 1435system.cpu1.itb.inst_misses 2171 # ITB inst misses |
| 1377system.cpu1.itb.read_hits 0 # DTB read hits 1378system.cpu1.itb.read_misses 0 # DTB read misses 1379system.cpu1.itb.write_hits 0 # DTB write hits 1380system.cpu1.itb.write_misses 0 # DTB write misses 1381system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1382system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1383system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1384system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1436system.cpu1.itb.read_hits 0 # DTB read hits 1437system.cpu1.itb.read_misses 0 # DTB read misses 1438system.cpu1.itb.write_hits 0 # DTB write hits 1439system.cpu1.itb.write_misses 0 # DTB write misses 1440system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1441system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1442system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1443system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1385system.cpu1.itb.flush_entries 1485 # Number of entries that have been flushed from TLB | 1444system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB |
| 1386system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1387system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1388system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1389system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1390system.cpu1.itb.read_accesses 0 # DTB read accesses 1391system.cpu1.itb.write_accesses 0 # DTB write accesses | 1445system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1446system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1447system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1448system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1449system.cpu1.itb.read_accesses 0 # DTB read accesses 1450system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1392system.cpu1.itb.inst_accesses 38011454 # ITB inst accesses 1393system.cpu1.itb.hits 38008437 # DTB hits 1394system.cpu1.itb.misses 3017 # DTB misses 1395system.cpu1.itb.accesses 38011454 # DTB accesses 1396system.cpu1.numCycles 2392450295 # number of cpu cycles simulated | 1451system.cpu1.itb.inst_accesses 33208134 # ITB inst accesses 1452system.cpu1.itb.hits 33205963 # DTB hits 1453system.cpu1.itb.misses 2171 # DTB misses 1454system.cpu1.itb.accesses 33208134 # DTB accesses 1455system.cpu1.numCycles 2390414629 # number of cpu cycles simulated |
| 1397system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1398system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1456system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1457system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1399system.cpu1.committedInsts 37097446 # Number of instructions committed 1400system.cpu1.committedOps 46867102 # Number of ops (including micro ops) committed 1401system.cpu1.num_int_alu_accesses 42687988 # Number of integer alu accesses 1402system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses 1403system.cpu1.num_func_calls 1134316 # number of times a function call or return occured 1404system.cpu1.num_conditional_control_insts 4357000 # number of instructions that are conditional controls 1405system.cpu1.num_int_insts 42687988 # number of integer instructions 1406system.cpu1.num_fp_insts 5457 # number of float instructions 1407system.cpu1.num_int_register_reads 248074220 # number of times the integer registers were read 1408system.cpu1.num_int_register_writes 45509439 # number of times the integer registers were written 1409system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read 1410system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written 1411system.cpu1.num_mem_refs 16770062 # number of memory refs 1412system.cpu1.num_load_insts 9887948 # Number of load instructions 1413system.cpu1.num_store_insts 6882114 # Number of store instructions 1414system.cpu1.num_idle_cycles 1855714829.552449 # Number of idle cycles 1415system.cpu1.num_busy_cycles 536735465.447551 # Number of busy cycles 1416system.cpu1.not_idle_fraction 0.224346 # Percentage of non-idle cycles 1417system.cpu1.idle_fraction 0.775654 # Percentage of idle cycles 1418system.cpu1.Branches 5771094 # Number of branches fetched | 1458system.cpu1.committedInsts 32594861 # Number of instructions committed 1459system.cpu1.committedOps 41116735 # Number of ops (including micro ops) committed 1460system.cpu1.num_int_alu_accesses 37639270 # Number of integer alu accesses 1461system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1462system.cpu1.num_func_calls 962738 # number of times a function call or return occured 1463system.cpu1.num_conditional_control_insts 3734786 # number of instructions that are conditional controls 1464system.cpu1.num_int_insts 37639270 # number of integer instructions 1465system.cpu1.num_fp_insts 6793 # number of float instructions 1466system.cpu1.num_int_register_reads 218315433 # number of times the integer registers were read 1467system.cpu1.num_int_register_writes 39777331 # number of times the integer registers were written 1468system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1469system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1470system.cpu1.num_mem_refs 14690124 # number of memory refs 1471system.cpu1.num_load_insts 8639728 # Number of load instructions 1472system.cpu1.num_store_insts 6050396 # Number of store instructions 1473system.cpu1.num_idle_cycles 1874297798.309079 # Number of idle cycles 1474system.cpu1.num_busy_cycles 516116830.690921 # Number of busy cycles 1475system.cpu1.not_idle_fraction 0.215911 # Percentage of non-idle cycles 1476system.cpu1.idle_fraction 0.784089 # Percentage of idle cycles 1477system.cpu1.Branches 4947313 # Number of branches fetched 1478system.cpu1.op_class::No_OpClass 14267 0.03% 0.03% # Class of executed instruction 1479system.cpu1.op_class::IntAlu 26968126 64.63% 64.67% # Class of executed instruction 1480system.cpu1.op_class::IntMult 50231 0.12% 64.79% # Class of executed instruction 1481system.cpu1.op_class::IntDiv 0 0.00% 64.79% # Class of executed instruction 1482system.cpu1.op_class::FloatAdd 0 0.00% 64.79% # Class of executed instruction 1483system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction 1484system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction 1485system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction 1486system.cpu1.op_class::FloatDiv 0 0.00% 64.79% # Class of executed instruction 1487system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction 1488system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction 1489system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction 1490system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction 1491system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction 1492system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction 1493system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction 1494system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction 1495system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction 1496system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction 1497system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction 1498system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction 1499system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction 1500system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction 1501system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction 1502system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction 1503system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction 1504system.cpu1.op_class::SimdFloatMisc 1470 0.00% 64.79% # Class of executed instruction 1505system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction 1506system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction 1507system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction 1508system.cpu1.op_class::MemRead 8639728 20.71% 85.50% # Class of executed instruction 1509system.cpu1.op_class::MemWrite 6050396 14.50% 100.00% # Class of executed instruction 1510system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1511system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1512system.cpu1.op_class::total 41724218 # Class of executed instruction |
| 1419system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1513system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1420system.cpu1.kern.inst.quiesce 52097 # number of quiesce instructions executed 1421system.cpu1.icache.tags.replacements 540849 # number of replacements 1422system.cpu1.icache.tags.tagsinuse 478.554171 # Cycle average of tags in use 1423system.cpu1.icache.tags.total_refs 37467072 # Total number of references to valid blocks. 1424system.cpu1.icache.tags.sampled_refs 541361 # Sample count of references to valid blocks. 1425system.cpu1.icache.tags.avg_refs 69.209034 # Average number of references to valid blocks. 1426system.cpu1.icache.tags.warmup_cycle 94011084500 # Cycle when the warmup percentage was hit. 1427system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.554171 # Average occupied blocks per requestor 1428system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934676 # Average percentage of cache occupancy 1429system.cpu1.icache.tags.occ_percent::total 0.934676 # Average percentage of cache occupancy | 1514system.cpu1.kern.inst.quiesce 44363 # number of quiesce instructions executed 1515system.cpu1.icache.tags.replacements 469889 # number of replacements 1516system.cpu1.icache.tags.tagsinuse 478.549875 # Cycle average of tags in use 1517system.cpu1.icache.tags.total_refs 32735558 # Total number of references to valid blocks. 1518system.cpu1.icache.tags.sampled_refs 470401 # Sample count of references to valid blocks. 1519system.cpu1.icache.tags.avg_refs 69.590749 # Average number of references to valid blocks. 1520system.cpu1.icache.tags.warmup_cycle 93998064500 # Cycle when the warmup percentage was hit. 1521system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.549875 # Average occupied blocks per requestor 1522system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934668 # Average percentage of cache occupancy 1523system.cpu1.icache.tags.occ_percent::total 0.934668 # Average percentage of cache occupancy |
| 1430system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1524system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1431system.cpu1.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 1432system.cpu1.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 1433system.cpu1.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id 1434system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id | 1525system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 1526system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1527system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id |
| 1435system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1528system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1436system.cpu1.icache.tags.tag_accesses 38549794 # Number of tag accesses 1437system.cpu1.icache.tags.data_accesses 38549794 # Number of data accesses 1438system.cpu1.icache.ReadReq_hits::cpu1.inst 37467072 # number of ReadReq hits 1439system.cpu1.icache.ReadReq_hits::total 37467072 # number of ReadReq hits 1440system.cpu1.icache.demand_hits::cpu1.inst 37467072 # number of demand (read+write) hits 1441system.cpu1.icache.demand_hits::total 37467072 # number of demand (read+write) hits 1442system.cpu1.icache.overall_hits::cpu1.inst 37467072 # number of overall hits 1443system.cpu1.icache.overall_hits::total 37467072 # number of overall hits 1444system.cpu1.icache.ReadReq_misses::cpu1.inst 541361 # number of ReadReq misses 1445system.cpu1.icache.ReadReq_misses::total 541361 # number of ReadReq misses 1446system.cpu1.icache.demand_misses::cpu1.inst 541361 # number of demand (read+write) misses 1447system.cpu1.icache.demand_misses::total 541361 # number of demand (read+write) misses 1448system.cpu1.icache.overall_misses::cpu1.inst 541361 # number of overall misses 1449system.cpu1.icache.overall_misses::total 541361 # number of overall misses 1450system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7383473218 # number of ReadReq miss cycles 1451system.cpu1.icache.ReadReq_miss_latency::total 7383473218 # number of ReadReq miss cycles 1452system.cpu1.icache.demand_miss_latency::cpu1.inst 7383473218 # number of demand (read+write) miss cycles 1453system.cpu1.icache.demand_miss_latency::total 7383473218 # number of demand (read+write) miss cycles 1454system.cpu1.icache.overall_miss_latency::cpu1.inst 7383473218 # number of overall miss cycles 1455system.cpu1.icache.overall_miss_latency::total 7383473218 # number of overall miss cycles 1456system.cpu1.icache.ReadReq_accesses::cpu1.inst 38008433 # number of ReadReq accesses(hits+misses) 1457system.cpu1.icache.ReadReq_accesses::total 38008433 # number of ReadReq accesses(hits+misses) 1458system.cpu1.icache.demand_accesses::cpu1.inst 38008433 # number of demand (read+write) accesses 1459system.cpu1.icache.demand_accesses::total 38008433 # number of demand (read+write) accesses 1460system.cpu1.icache.overall_accesses::cpu1.inst 38008433 # number of overall (read+write) accesses 1461system.cpu1.icache.overall_accesses::total 38008433 # number of overall (read+write) accesses 1462system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014243 # miss rate for ReadReq accesses 1463system.cpu1.icache.ReadReq_miss_rate::total 0.014243 # miss rate for ReadReq accesses 1464system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014243 # miss rate for demand accesses 1465system.cpu1.icache.demand_miss_rate::total 0.014243 # miss rate for demand accesses 1466system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014243 # miss rate for overall accesses 1467system.cpu1.icache.overall_miss_rate::total 0.014243 # miss rate for overall accesses 1468system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13638.723916 # average ReadReq miss latency 1469system.cpu1.icache.ReadReq_avg_miss_latency::total 13638.723916 # average ReadReq miss latency 1470system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency 1471system.cpu1.icache.demand_avg_miss_latency::total 13638.723916 # average overall miss latency 1472system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency 1473system.cpu1.icache.overall_avg_miss_latency::total 13638.723916 # average overall miss latency | 1529system.cpu1.icache.tags.tag_accesses 33676360 # Number of tag accesses 1530system.cpu1.icache.tags.data_accesses 33676360 # Number of data accesses 1531system.cpu1.icache.ReadReq_hits::cpu1.inst 32735558 # number of ReadReq hits 1532system.cpu1.icache.ReadReq_hits::total 32735558 # number of ReadReq hits 1533system.cpu1.icache.demand_hits::cpu1.inst 32735558 # number of demand (read+write) hits 1534system.cpu1.icache.demand_hits::total 32735558 # number of demand (read+write) hits 1535system.cpu1.icache.overall_hits::cpu1.inst 32735558 # number of overall hits 1536system.cpu1.icache.overall_hits::total 32735558 # number of overall hits 1537system.cpu1.icache.ReadReq_misses::cpu1.inst 470401 # number of ReadReq misses 1538system.cpu1.icache.ReadReq_misses::total 470401 # number of ReadReq misses 1539system.cpu1.icache.demand_misses::cpu1.inst 470401 # number of demand (read+write) misses 1540system.cpu1.icache.demand_misses::total 470401 # number of demand (read+write) misses 1541system.cpu1.icache.overall_misses::cpu1.inst 470401 # number of overall misses 1542system.cpu1.icache.overall_misses::total 470401 # number of overall misses 1543system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443025224 # number of ReadReq miss cycles 1544system.cpu1.icache.ReadReq_miss_latency::total 6443025224 # number of ReadReq miss cycles 1545system.cpu1.icache.demand_miss_latency::cpu1.inst 6443025224 # number of demand (read+write) miss cycles 1546system.cpu1.icache.demand_miss_latency::total 6443025224 # number of demand (read+write) miss cycles 1547system.cpu1.icache.overall_miss_latency::cpu1.inst 6443025224 # number of overall miss cycles 1548system.cpu1.icache.overall_miss_latency::total 6443025224 # number of overall miss cycles 1549system.cpu1.icache.ReadReq_accesses::cpu1.inst 33205959 # number of ReadReq accesses(hits+misses) 1550system.cpu1.icache.ReadReq_accesses::total 33205959 # number of ReadReq accesses(hits+misses) 1551system.cpu1.icache.demand_accesses::cpu1.inst 33205959 # number of demand (read+write) accesses 1552system.cpu1.icache.demand_accesses::total 33205959 # number of demand (read+write) accesses 1553system.cpu1.icache.overall_accesses::cpu1.inst 33205959 # number of overall (read+write) accesses 1554system.cpu1.icache.overall_accesses::total 33205959 # number of overall (read+write) accesses 1555system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses 1556system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses 1557system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses 1558system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses 1559system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses 1560system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses 1561system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13696.878246 # average ReadReq miss latency 1562system.cpu1.icache.ReadReq_avg_miss_latency::total 13696.878246 # average ReadReq miss latency 1563system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13696.878246 # average overall miss latency 1564system.cpu1.icache.demand_avg_miss_latency::total 13696.878246 # average overall miss latency 1565system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13696.878246 # average overall miss latency 1566system.cpu1.icache.overall_avg_miss_latency::total 13696.878246 # average overall miss latency |
| 1474system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1475system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1476system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1477system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1478system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1479system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1480system.cpu1.icache.fast_writes 0 # number of fast writes performed 1481system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1567system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1568system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1569system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1570system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1571system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1572system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1573system.cpu1.icache.fast_writes 0 # number of fast writes performed 1574system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1482system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 541361 # number of ReadReq MSHR misses 1483system.cpu1.icache.ReadReq_mshr_misses::total 541361 # number of ReadReq MSHR misses 1484system.cpu1.icache.demand_mshr_misses::cpu1.inst 541361 # number of demand (read+write) MSHR misses 1485system.cpu1.icache.demand_mshr_misses::total 541361 # number of demand (read+write) MSHR misses 1486system.cpu1.icache.overall_mshr_misses::cpu1.inst 541361 # number of overall MSHR misses 1487system.cpu1.icache.overall_mshr_misses::total 541361 # number of overall MSHR misses 1488system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6298814782 # number of ReadReq MSHR miss cycles 1489system.cpu1.icache.ReadReq_mshr_miss_latency::total 6298814782 # number of ReadReq MSHR miss cycles 1490system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6298814782 # number of demand (read+write) MSHR miss cycles 1491system.cpu1.icache.demand_mshr_miss_latency::total 6298814782 # number of demand (read+write) MSHR miss cycles 1492system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6298814782 # number of overall MSHR miss cycles 1493system.cpu1.icache.overall_mshr_miss_latency::total 6298814782 # number of overall MSHR miss cycles 1494system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6977250 # number of ReadReq MSHR uncacheable cycles 1495system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6977250 # number of ReadReq MSHR uncacheable cycles 1496system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6977250 # number of overall MSHR uncacheable cycles 1497system.cpu1.icache.overall_mshr_uncacheable_latency::total 6977250 # number of overall MSHR uncacheable cycles 1498system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for ReadReq accesses 1499system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014243 # mshr miss rate for ReadReq accesses 1500system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for demand accesses 1501system.cpu1.icache.demand_mshr_miss_rate::total 0.014243 # mshr miss rate for demand accesses 1502system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for overall accesses 1503system.cpu1.icache.overall_mshr_miss_rate::total 0.014243 # mshr miss rate for overall accesses 1504system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average ReadReq mshr miss latency 1505system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939 # average ReadReq mshr miss latency 1506system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency 1507system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency 1508system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency 1509system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency | 1575system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470401 # number of ReadReq MSHR misses 1576system.cpu1.icache.ReadReq_mshr_misses::total 470401 # number of ReadReq MSHR misses 1577system.cpu1.icache.demand_mshr_misses::cpu1.inst 470401 # number of demand (read+write) MSHR misses 1578system.cpu1.icache.demand_mshr_misses::total 470401 # number of demand (read+write) MSHR misses 1579system.cpu1.icache.overall_mshr_misses::cpu1.inst 470401 # number of overall MSHR misses 1580system.cpu1.icache.overall_mshr_misses::total 470401 # number of overall MSHR misses 1581system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5500320776 # number of ReadReq MSHR miss cycles 1582system.cpu1.icache.ReadReq_mshr_miss_latency::total 5500320776 # number of ReadReq MSHR miss cycles 1583system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5500320776 # number of demand (read+write) MSHR miss cycles 1584system.cpu1.icache.demand_mshr_miss_latency::total 5500320776 # number of demand (read+write) MSHR miss cycles 1585system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5500320776 # number of overall MSHR miss cycles 1586system.cpu1.icache.overall_mshr_miss_latency::total 5500320776 # number of overall MSHR miss cycles 1587system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7094750 # number of ReadReq MSHR uncacheable cycles 1588system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7094750 # number of ReadReq MSHR uncacheable cycles 1589system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7094750 # number of overall MSHR uncacheable cycles 1590system.cpu1.icache.overall_mshr_uncacheable_latency::total 7094750 # number of overall MSHR uncacheable cycles 1591system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for ReadReq accesses 1592system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014166 # mshr miss rate for ReadReq accesses 1593system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for demand accesses 1594system.cpu1.icache.demand_mshr_miss_rate::total 0.014166 # mshr miss rate for demand accesses 1595system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for overall accesses 1596system.cpu1.icache.overall_mshr_miss_rate::total 0.014166 # mshr miss rate for overall accesses 1597system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11692.833935 # average ReadReq mshr miss latency 1598system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11692.833935 # average ReadReq mshr miss latency 1599system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11692.833935 # average overall mshr miss latency 1600system.cpu1.icache.demand_avg_mshr_miss_latency::total 11692.833935 # average overall mshr miss latency 1601system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11692.833935 # average overall mshr miss latency 1602system.cpu1.icache.overall_avg_mshr_miss_latency::total 11692.833935 # average overall mshr miss latency |
| 1510system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1511system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1512system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1513system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1514system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1603system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1604system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1605system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1606system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1607system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1515system.cpu1.dcache.tags.replacements 343803 # number of replacements 1516system.cpu1.dcache.tags.tagsinuse 472.607785 # Cycle average of tags in use 1517system.cpu1.dcache.tags.total_refs 13921652 # Total number of references to valid blocks. 1518system.cpu1.dcache.tags.sampled_refs 344315 # Sample count of references to valid blocks. 1519system.cpu1.dcache.tags.avg_refs 40.432894 # Average number of references to valid blocks. 1520system.cpu1.dcache.tags.warmup_cycle 85311468250 # Cycle when the warmup percentage was hit. 1521system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.607785 # Average occupied blocks per requestor 1522system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923062 # Average percentage of cache occupancy 1523system.cpu1.dcache.tags.occ_percent::total 0.923062 # Average percentage of cache occupancy 1524system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1525system.cpu1.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 1526system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 1527system.cpu1.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 1528system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1529system.cpu1.dcache.tags.tag_accesses 57519242 # Number of tag accesses 1530system.cpu1.dcache.tags.data_accesses 57519242 # Number of data accesses 1531system.cpu1.dcache.ReadReq_hits::cpu1.data 8078143 # number of ReadReq hits 1532system.cpu1.dcache.ReadReq_hits::total 8078143 # number of ReadReq hits 1533system.cpu1.dcache.WriteReq_hits::cpu1.data 5612875 # number of WriteReq hits 1534system.cpu1.dcache.WriteReq_hits::total 5612875 # number of WriteReq hits 1535system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100617 # number of LoadLockedReq hits 1536system.cpu1.dcache.LoadLockedReq_hits::total 100617 # number of LoadLockedReq hits 1537system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102310 # number of StoreCondReq hits 1538system.cpu1.dcache.StoreCondReq_hits::total 102310 # number of StoreCondReq hits 1539system.cpu1.dcache.demand_hits::cpu1.data 13691018 # number of demand (read+write) hits 1540system.cpu1.dcache.demand_hits::total 13691018 # number of demand (read+write) hits 1541system.cpu1.dcache.overall_hits::cpu1.data 13691018 # number of overall hits 1542system.cpu1.dcache.overall_hits::total 13691018 # number of overall hits 1543system.cpu1.dcache.ReadReq_misses::cpu1.data 207066 # number of ReadReq misses 1544system.cpu1.dcache.ReadReq_misses::total 207066 # number of ReadReq misses 1545system.cpu1.dcache.WriteReq_misses::cpu1.data 165297 # number of WriteReq misses 1546system.cpu1.dcache.WriteReq_misses::total 165297 # number of WriteReq misses 1547system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11987 # number of LoadLockedReq misses 1548system.cpu1.dcache.LoadLockedReq_misses::total 11987 # number of LoadLockedReq misses 1549system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9884 # number of StoreCondReq misses 1550system.cpu1.dcache.StoreCondReq_misses::total 9884 # number of StoreCondReq misses 1551system.cpu1.dcache.demand_misses::cpu1.data 372363 # number of demand (read+write) misses 1552system.cpu1.dcache.demand_misses::total 372363 # number of demand (read+write) misses 1553system.cpu1.dcache.overall_misses::cpu1.data 372363 # number of overall misses 1554system.cpu1.dcache.overall_misses::total 372363 # number of overall misses 1555system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2696827750 # number of ReadReq miss cycles 1556system.cpu1.dcache.ReadReq_miss_latency::total 2696827750 # number of ReadReq miss cycles 1557system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6860807042 # number of WriteReq miss cycles 1558system.cpu1.dcache.WriteReq_miss_latency::total 6860807042 # number of WriteReq miss cycles 1559system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 107474000 # number of LoadLockedReq miss cycles 1560system.cpu1.dcache.LoadLockedReq_miss_latency::total 107474000 # number of LoadLockedReq miss cycles 1561system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50841959 # number of StoreCondReq miss cycles 1562system.cpu1.dcache.StoreCondReq_miss_latency::total 50841959 # number of StoreCondReq miss cycles 1563system.cpu1.dcache.demand_miss_latency::cpu1.data 9557634792 # number of demand (read+write) miss cycles 1564system.cpu1.dcache.demand_miss_latency::total 9557634792 # number of demand (read+write) miss cycles 1565system.cpu1.dcache.overall_miss_latency::cpu1.data 9557634792 # number of overall miss cycles 1566system.cpu1.dcache.overall_miss_latency::total 9557634792 # number of overall miss cycles 1567system.cpu1.dcache.ReadReq_accesses::cpu1.data 8285209 # number of ReadReq accesses(hits+misses) 1568system.cpu1.dcache.ReadReq_accesses::total 8285209 # number of ReadReq accesses(hits+misses) 1569system.cpu1.dcache.WriteReq_accesses::cpu1.data 5778172 # number of WriteReq accesses(hits+misses) 1570system.cpu1.dcache.WriteReq_accesses::total 5778172 # number of WriteReq accesses(hits+misses) 1571system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112604 # number of LoadLockedReq accesses(hits+misses) 1572system.cpu1.dcache.LoadLockedReq_accesses::total 112604 # number of LoadLockedReq accesses(hits+misses) 1573system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112194 # number of StoreCondReq accesses(hits+misses) 1574system.cpu1.dcache.StoreCondReq_accesses::total 112194 # number of StoreCondReq accesses(hits+misses) 1575system.cpu1.dcache.demand_accesses::cpu1.data 14063381 # number of demand (read+write) accesses 1576system.cpu1.dcache.demand_accesses::total 14063381 # number of demand (read+write) accesses 1577system.cpu1.dcache.overall_accesses::cpu1.data 14063381 # number of overall (read+write) accesses 1578system.cpu1.dcache.overall_accesses::total 14063381 # number of overall (read+write) accesses 1579system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024992 # miss rate for ReadReq accesses 1580system.cpu1.dcache.ReadReq_miss_rate::total 0.024992 # miss rate for ReadReq accesses 1581system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses 1582system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses 1583system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106453 # miss rate for LoadLockedReq accesses 1584system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106453 # miss rate for LoadLockedReq accesses 1585system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088097 # miss rate for StoreCondReq accesses 1586system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088097 # miss rate for StoreCondReq accesses 1587system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026477 # miss rate for demand accesses 1588system.cpu1.dcache.demand_miss_rate::total 0.026477 # miss rate for demand accesses 1589system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026477 # miss rate for overall accesses 1590system.cpu1.dcache.overall_miss_rate::total 0.026477 # miss rate for overall accesses 1591system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802 # average ReadReq miss latency 1592system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802 # average ReadReq miss latency 1593system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051 # average WriteReq miss latency 1594system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051 # average WriteReq miss latency 1595system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8965.879703 # average LoadLockedReq miss latency 1596system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8965.879703 # average LoadLockedReq miss latency 1597system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5143.864731 # average StoreCondReq miss latency 1598system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5143.864731 # average StoreCondReq miss latency 1599system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency 1600system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113 # average overall miss latency 1601system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency 1602system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113 # average overall miss latency | 1608system.cpu1.dcache.tags.replacements 292396 # number of replacements 1609system.cpu1.dcache.tags.tagsinuse 471.340913 # Cycle average of tags in use 1610system.cpu1.dcache.tags.total_refs 11973732 # Total number of references to valid blocks. 1611system.cpu1.dcache.tags.sampled_refs 292744 # Sample count of references to valid blocks. 1612system.cpu1.dcache.tags.avg_refs 40.901716 # Average number of references to valid blocks. 1613system.cpu1.dcache.tags.warmup_cycle 85301409250 # Cycle when the warmup percentage was hit. 1614system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.340913 # Average occupied blocks per requestor 1615system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920588 # Average percentage of cache occupancy 1616system.cpu1.dcache.tags.occ_percent::total 0.920588 # Average percentage of cache occupancy 1617system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 1618system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 1619system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id 1620system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id 1621system.cpu1.dcache.tags.tag_accesses 49486795 # Number of tag accesses 1622system.cpu1.dcache.tags.data_accesses 49486795 # Number of data accesses 1623system.cpu1.dcache.ReadReq_hits::cpu1.data 6952689 # number of ReadReq hits 1624system.cpu1.dcache.ReadReq_hits::total 6952689 # number of ReadReq hits 1625system.cpu1.dcache.WriteReq_hits::cpu1.data 4832965 # number of WriteReq hits 1626system.cpu1.dcache.WriteReq_hits::total 4832965 # number of WriteReq hits 1627system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82012 # number of LoadLockedReq hits 1628system.cpu1.dcache.LoadLockedReq_hits::total 82012 # number of LoadLockedReq hits 1629system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82761 # number of StoreCondReq hits 1630system.cpu1.dcache.StoreCondReq_hits::total 82761 # number of StoreCondReq hits 1631system.cpu1.dcache.demand_hits::cpu1.data 11785654 # number of demand (read+write) hits 1632system.cpu1.dcache.demand_hits::total 11785654 # number of demand (read+write) hits 1633system.cpu1.dcache.overall_hits::cpu1.data 11785654 # number of overall hits 1634system.cpu1.dcache.overall_hits::total 11785654 # number of overall hits 1635system.cpu1.dcache.ReadReq_misses::cpu1.data 170655 # number of ReadReq misses 1636system.cpu1.dcache.ReadReq_misses::total 170655 # number of ReadReq misses 1637system.cpu1.dcache.WriteReq_misses::cpu1.data 150219 # number of WriteReq misses 1638system.cpu1.dcache.WriteReq_misses::total 150219 # number of WriteReq misses 1639system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11301 # number of LoadLockedReq misses 1640system.cpu1.dcache.LoadLockedReq_misses::total 11301 # number of LoadLockedReq misses 1641system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10073 # number of StoreCondReq misses 1642system.cpu1.dcache.StoreCondReq_misses::total 10073 # number of StoreCondReq misses 1643system.cpu1.dcache.demand_misses::cpu1.data 320874 # number of demand (read+write) misses 1644system.cpu1.dcache.demand_misses::total 320874 # number of demand (read+write) misses 1645system.cpu1.dcache.overall_misses::cpu1.data 320874 # number of overall misses 1646system.cpu1.dcache.overall_misses::total 320874 # number of overall misses 1647system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2212742497 # number of ReadReq miss cycles 1648system.cpu1.dcache.ReadReq_miss_latency::total 2212742497 # number of ReadReq miss cycles 1649system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6365695527 # number of WriteReq miss cycles 1650system.cpu1.dcache.WriteReq_miss_latency::total 6365695527 # number of WriteReq miss cycles 1651system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97206750 # number of LoadLockedReq miss cycles 1652system.cpu1.dcache.LoadLockedReq_miss_latency::total 97206750 # number of LoadLockedReq miss cycles 1653system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52182477 # number of StoreCondReq miss cycles 1654system.cpu1.dcache.StoreCondReq_miss_latency::total 52182477 # number of StoreCondReq miss cycles 1655system.cpu1.dcache.demand_miss_latency::cpu1.data 8578438024 # number of demand (read+write) miss cycles 1656system.cpu1.dcache.demand_miss_latency::total 8578438024 # number of demand (read+write) miss cycles 1657system.cpu1.dcache.overall_miss_latency::cpu1.data 8578438024 # number of overall miss cycles 1658system.cpu1.dcache.overall_miss_latency::total 8578438024 # number of overall miss cycles 1659system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123344 # number of ReadReq accesses(hits+misses) 1660system.cpu1.dcache.ReadReq_accesses::total 7123344 # number of ReadReq accesses(hits+misses) 1661system.cpu1.dcache.WriteReq_accesses::cpu1.data 4983184 # number of WriteReq accesses(hits+misses) 1662system.cpu1.dcache.WriteReq_accesses::total 4983184 # number of WriteReq accesses(hits+misses) 1663system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93313 # number of LoadLockedReq accesses(hits+misses) 1664system.cpu1.dcache.LoadLockedReq_accesses::total 93313 # number of LoadLockedReq accesses(hits+misses) 1665system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92834 # number of StoreCondReq accesses(hits+misses) 1666system.cpu1.dcache.StoreCondReq_accesses::total 92834 # number of StoreCondReq accesses(hits+misses) 1667system.cpu1.dcache.demand_accesses::cpu1.data 12106528 # number of demand (read+write) accesses 1668system.cpu1.dcache.demand_accesses::total 12106528 # number of demand (read+write) accesses 1669system.cpu1.dcache.overall_accesses::cpu1.data 12106528 # number of overall (read+write) accesses 1670system.cpu1.dcache.overall_accesses::total 12106528 # number of overall (read+write) accesses 1671system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023957 # miss rate for ReadReq accesses 1672system.cpu1.dcache.ReadReq_miss_rate::total 0.023957 # miss rate for ReadReq accesses 1673system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses 1674system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses 1675system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121109 # miss rate for LoadLockedReq accesses 1676system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121109 # miss rate for LoadLockedReq accesses 1677system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108506 # miss rate for StoreCondReq accesses 1678system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108506 # miss rate for StoreCondReq accesses 1679system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026504 # miss rate for demand accesses 1680system.cpu1.dcache.demand_miss_rate::total 0.026504 # miss rate for demand accesses 1681system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026504 # miss rate for overall accesses 1682system.cpu1.dcache.overall_miss_rate::total 0.026504 # miss rate for overall accesses 1683system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12966.174428 # average ReadReq miss latency 1684system.cpu1.dcache.ReadReq_avg_miss_latency::total 12966.174428 # average ReadReq miss latency 1685system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42376.101072 # average WriteReq miss latency 1686system.cpu1.dcache.WriteReq_avg_miss_latency::total 42376.101072 # average WriteReq miss latency 1687system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8601.606053 # average LoadLockedReq miss latency 1688system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8601.606053 # average LoadLockedReq miss latency 1689system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5180.430557 # average StoreCondReq miss latency 1690system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5180.430557 # average StoreCondReq miss latency 1691system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency 1692system.cpu1.dcache.demand_avg_miss_latency::total 26734.599949 # average overall miss latency 1693system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency 1694system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949 # average overall miss latency |
| 1603system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1604system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1605system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1606system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1607system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1608system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1609system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1610system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1695system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1696system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1697system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1698system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1699system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1700system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1701system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1702system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1611system.cpu1.dcache.writebacks::writebacks 315335 # number of writebacks 1612system.cpu1.dcache.writebacks::total 315335 # number of writebacks 1613system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207066 # number of ReadReq MSHR misses 1614system.cpu1.dcache.ReadReq_mshr_misses::total 207066 # number of ReadReq MSHR misses 1615system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165297 # number of WriteReq MSHR misses 1616system.cpu1.dcache.WriteReq_mshr_misses::total 165297 # number of WriteReq MSHR misses 1617system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11987 # number of LoadLockedReq MSHR misses 1618system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11987 # number of LoadLockedReq MSHR misses 1619system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9883 # number of StoreCondReq MSHR misses 1620system.cpu1.dcache.StoreCondReq_mshr_misses::total 9883 # number of StoreCondReq MSHR misses 1621system.cpu1.dcache.demand_mshr_misses::cpu1.data 372363 # number of demand (read+write) MSHR misses 1622system.cpu1.dcache.demand_mshr_misses::total 372363 # number of demand (read+write) MSHR misses 1623system.cpu1.dcache.overall_mshr_misses::cpu1.data 372363 # number of overall MSHR misses 1624system.cpu1.dcache.overall_mshr_misses::total 372363 # number of overall MSHR misses 1625system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2282040250 # number of ReadReq MSHR miss cycles 1626system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2282040250 # number of ReadReq MSHR miss cycles 1627system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6506824958 # number of WriteReq MSHR miss cycles 1628system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6506824958 # number of WriteReq MSHR miss cycles 1629system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83489000 # number of LoadLockedReq MSHR miss cycles 1630system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83489000 # number of LoadLockedReq MSHR miss cycles 1631system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31075041 # number of StoreCondReq MSHR miss cycles 1632system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31075041 # number of StoreCondReq MSHR miss cycles 1633system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8788865208 # number of demand (read+write) MSHR miss cycles 1634system.cpu1.dcache.demand_mshr_miss_latency::total 8788865208 # number of demand (read+write) MSHR miss cycles 1635system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8788865208 # number of overall MSHR miss cycles 1636system.cpu1.dcache.overall_mshr_miss_latency::total 8788865208 # number of overall MSHR miss cycles 1637system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250 # number of ReadReq MSHR uncacheable cycles 1638system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250 # number of ReadReq MSHR uncacheable cycles 1639system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25194386277 # number of WriteReq MSHR uncacheable cycles 1640system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25194386277 # number of WriteReq MSHR uncacheable cycles 1641system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527 # number of overall MSHR uncacheable cycles 1642system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527 # number of overall MSHR uncacheable cycles 1643system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024992 # mshr miss rate for ReadReq accesses 1644system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024992 # mshr miss rate for ReadReq accesses 1645system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses 1646system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses 1647system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106453 # mshr miss rate for LoadLockedReq accesses 1648system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106453 # mshr miss rate for LoadLockedReq accesses 1649system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088088 # mshr miss rate for StoreCondReq accesses 1650system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088088 # mshr miss rate for StoreCondReq accesses 1651system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for demand accesses 1652system.cpu1.dcache.demand_mshr_miss_rate::total 0.026477 # mshr miss rate for demand accesses 1653system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for overall accesses 1654system.cpu1.dcache.overall_mshr_miss_rate::total 0.026477 # mshr miss rate for overall accesses 1655system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144 # average ReadReq mshr miss latency 1656system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144 # average ReadReq mshr miss latency 1657system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772 # average WriteReq mshr miss latency 1658system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772 # average WriteReq mshr miss latency 1659system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6964.962042 # average LoadLockedReq mshr miss latency 1660system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6964.962042 # average LoadLockedReq mshr miss latency 1661system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3144.292320 # average StoreCondReq mshr miss latency 1662system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3144.292320 # average StoreCondReq mshr miss latency 1663system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency 1664system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency 1665system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency 1666system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency | 1703system.cpu1.dcache.writebacks::writebacks 265286 # number of writebacks 1704system.cpu1.dcache.writebacks::total 265286 # number of writebacks 1705system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170655 # number of ReadReq MSHR misses 1706system.cpu1.dcache.ReadReq_mshr_misses::total 170655 # number of ReadReq MSHR misses 1707system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150219 # number of WriteReq MSHR misses 1708system.cpu1.dcache.WriteReq_mshr_misses::total 150219 # number of WriteReq MSHR misses 1709system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11301 # number of LoadLockedReq MSHR misses 1710system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11301 # number of LoadLockedReq MSHR misses 1711system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses 1712system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses 1713system.cpu1.dcache.demand_mshr_misses::cpu1.data 320874 # number of demand (read+write) MSHR misses 1714system.cpu1.dcache.demand_mshr_misses::total 320874 # number of demand (read+write) MSHR misses 1715system.cpu1.dcache.overall_mshr_misses::cpu1.data 320874 # number of overall MSHR misses 1716system.cpu1.dcache.overall_mshr_misses::total 320874 # number of overall MSHR misses 1717system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1870737503 # number of ReadReq MSHR miss cycles 1718system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1870737503 # number of ReadReq MSHR miss cycles 1719system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6042583473 # number of WriteReq MSHR miss cycles 1720system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6042583473 # number of WriteReq MSHR miss cycles 1721system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74594250 # number of LoadLockedReq MSHR miss cycles 1722system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74594250 # number of LoadLockedReq MSHR miss cycles 1723system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32041523 # number of StoreCondReq MSHR miss cycles 1724system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32041523 # number of StoreCondReq MSHR miss cycles 1725system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7913320976 # number of demand (read+write) MSHR miss cycles 1726system.cpu1.dcache.demand_mshr_miss_latency::total 7913320976 # number of demand (read+write) MSHR miss cycles 1727system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7913320976 # number of overall MSHR miss cycles 1728system.cpu1.dcache.overall_mshr_miss_latency::total 7913320976 # number of overall MSHR miss cycles 1729system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750 # number of ReadReq MSHR uncacheable cycles 1730system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750 # number of ReadReq MSHR uncacheable cycles 1731system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187494163 # number of WriteReq MSHR uncacheable cycles 1732system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187494163 # number of WriteReq MSHR uncacheable cycles 1733system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913 # number of overall MSHR uncacheable cycles 1734system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913 # number of overall MSHR uncacheable cycles 1735system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023957 # mshr miss rate for ReadReq accesses 1736system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023957 # mshr miss rate for ReadReq accesses 1737system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses 1738system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses 1739system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121109 # mshr miss rate for LoadLockedReq accesses 1740system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121109 # mshr miss rate for LoadLockedReq accesses 1741system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108473 # mshr miss rate for StoreCondReq accesses 1742system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108473 # mshr miss rate for StoreCondReq accesses 1743system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for demand accesses 1744system.cpu1.dcache.demand_mshr_miss_rate::total 0.026504 # mshr miss rate for demand accesses 1745system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for overall accesses 1746system.cpu1.dcache.overall_mshr_miss_rate::total 0.026504 # mshr miss rate for overall accesses 1747system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919 # average ReadReq mshr miss latency 1748system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919 # average ReadReq mshr miss latency 1749system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085 # average WriteReq mshr miss latency 1750system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085 # average WriteReq mshr miss latency 1751system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6600.676931 # average LoadLockedReq mshr miss latency 1752system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6600.676931 # average LoadLockedReq mshr miss latency 1753system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3181.879146 # average StoreCondReq mshr miss latency 1754system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3181.879146 # average StoreCondReq mshr miss latency 1755system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency 1756system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency 1757system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency 1758system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency |
| 1667system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1668system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1669system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1670system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1671system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1672system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1673system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1674system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1682system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1683system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1684system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1685system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1686system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1687system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1688system.iocache.fast_writes 0 # number of fast writes performed 1689system.iocache.cache_copies 0 # number of cache copies performed | 1759system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1760system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1761system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1762system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1763system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1764system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1765system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1766system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1774system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1775system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1776system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1777system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1778system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1779system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1780system.iocache.fast_writes 0 # number of fast writes performed 1781system.iocache.cache_copies 0 # number of cache copies performed |
| 1690system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500 # number of ReadReq MSHR uncacheable cycles 1691system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500 # number of ReadReq MSHR uncacheable cycles 1692system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500 # number of overall MSHR uncacheable cycles 1693system.iocache.overall_mshr_uncacheable_latency::total 746722879500 # number of overall MSHR uncacheable cycles | 1782system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750 # number of ReadReq MSHR uncacheable cycles 1783system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750 # number of ReadReq MSHR uncacheable cycles 1784system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750 # number of overall MSHR uncacheable cycles 1785system.iocache.overall_mshr_uncacheable_latency::total 745373562750 # number of overall MSHR uncacheable cycles |
| 1694system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1695system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1696system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1697system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1698system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1699 1700---------- End Simulation Statistics ---------- | 1786system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1787system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1788system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1789system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1790system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1791 1792---------- End Simulation Statistics ---------- |