| stats.txt (10072:fa5c8a8a7bab) | stats.txt (10148:4574d5882066) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.196143 # Number of seconds simulated 4sim_ticks 1196142873000 # Number of ticks simulated 5final_tick 1196142873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.196225 # Number of seconds simulated 4sim_ticks 1196225147500 # Number of ticks simulated 5final_tick 1196225147500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 497666 # Simulator instruction rate (inst/s) 8host_op_rate 634118 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9685782626 # Simulator tick rate (ticks/s) 10host_mem_usage 425428 # Number of bytes of host memory used 11host_seconds 123.49 # Real time elapsed on the host 12sim_insts 61459155 # Number of instructions simulated 13sim_ops 78310163 # Number of ops (including micro ops) simulated | 7host_inst_rate 669591 # Simulator instruction rate (inst/s) 8host_op_rate 853186 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 13029857543 # Simulator tick rate (ticks/s) 10host_mem_usage 426076 # Number of bytes of host memory used 11host_seconds 91.81 # Real time elapsed on the host 12sim_insts 61472758 # Number of instructions simulated 13sim_ops 78327958 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory --- 6 unchanged lines hidden (view full) --- 28system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory --- 6 unchanged lines hidden (view full) --- 28system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory |
| 36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 393356 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 4724988 # Number of bytes read from this memory | 36system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 378508 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 4532924 # Number of bytes read from this memory |
| 39system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory | 39system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory |
| 40system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.inst 324292 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.data 4798584 # Number of bytes read from this memory 43system.physmem.bytes_read::total 62146244 # Number of bytes read from this memory 44system.physmem.bytes_inst_read::cpu0.inst 393356 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::cpu1.inst 324292 # Number of instructions bytes read from this memory 46system.physmem.bytes_inst_read::total 717648 # Number of instructions bytes read from this memory 47system.physmem.bytes_written::writebacks 4113152 # Number of bytes written to this memory | 40system.physmem.bytes_read::cpu1.inst 337988 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.data 4964984 # Number of bytes read from this memory 42system.physmem.bytes_read::total 62119428 # Number of bytes read from this memory 43system.physmem.bytes_inst_read::cpu0.inst 378508 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::cpu1.inst 337988 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::total 716496 # Number of instructions bytes read from this memory 46system.physmem.bytes_written::writebacks 4092288 # Number of bytes written to this memory |
| 48system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 49system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory | 47system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 48system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory |
| 50system.physmem.bytes_written::total 7140496 # Number of bytes written to this memory | 49system.physmem.bytes_written::total 7119632 # Number of bytes written to this memory |
| 51system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory | 50system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory |
| 53system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu0.inst 12374 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.data 73902 # Number of read requests responded to by this memory | 52system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.inst 12142 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu0.data 70901 # Number of read requests responded to by this memory |
| 56system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory | 55system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory |
| 57system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.inst 5158 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu1.data 75006 # Number of read requests responded to by this memory 60system.physmem.num_reads::total 6654512 # Number of read requests responded to by this memory 61system.physmem.num_writes::writebacks 64268 # Number of write requests responded to by this memory | 56system.physmem.num_reads::cpu1.inst 5372 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.data 77606 # Number of read requests responded to by this memory 58system.physmem.num_reads::total 6654093 # Number of read requests responded to by this memory 59system.physmem.num_writes::writebacks 63942 # Number of write requests responded to by this memory |
| 62system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 63system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory | 60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 61system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory |
| 64system.physmem.num_writes::total 821104 # Number of write requests responded to by this memory 65system.physmem.bw_read::realview.clcd 43393238 # Total read bandwidth from this memory (bytes/s) | 62system.physmem.num_writes::total 820778 # Number of write requests responded to by this memory 63system.physmem.bw_read::realview.clcd 43390253 # Total read bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) | 64system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) |
| 67system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu0.inst 328854 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.data 3950187 # Total read bandwidth from this memory (bytes/s) | 65system.physmem.bw_read::cpu0.itb.walker 161 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.inst 316419 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.data 3789357 # Total read bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) | 68system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) |
| 71system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu1.inst 271115 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu1.data 4011715 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::total 51955536 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::cpu0.inst 328854 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_inst_read::cpu1.inst 271115 # Instruction read bandwidth from this memory (bytes/s) 77system.physmem.bw_inst_read::total 599968 # Instruction read bandwidth from this memory (bytes/s) 78system.physmem.bw_write::writebacks 3438680 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_write::cpu1.data 2516709 # Write bandwidth from this memory (bytes/s) 81system.physmem.bw_write::total 5969601 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_total::writebacks 3438680 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::realview.clcd 43393238 # Total bandwidth to/from this memory (bytes/s) | 69system.physmem.bw_read::cpu1.inst 282545 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.data 4150543 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::total 51929545 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::cpu0.inst 316419 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_inst_read::cpu1.inst 282545 # Instruction read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::total 598964 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_write::writebacks 3421001 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::cpu0.data 14211 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_write::cpu1.data 2516536 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::total 5951749 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_total::writebacks 3421001 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::realview.clcd 43390253 # Total bandwidth to/from this memory (bytes/s) |
| 84system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) | 81system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) |
| 85system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu0.inst 328854 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.data 3964399 # Total bandwidth to/from this memory (bytes/s) | 82system.physmem.bw_total::cpu0.itb.walker 161 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu0.inst 316419 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.data 3803568 # Total bandwidth to/from this memory (bytes/s) |
| 88system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) | 85system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) |
| 89system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu1.inst 271115 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::cpu1.data 6528424 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::total 57925137 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.readReqs 6654512 # Number of read requests accepted 94system.physmem.writeReqs 821104 # Number of write requests accepted 95system.physmem.readBursts 6654512 # Number of DRAM read bursts, including those serviced by the write queue 96system.physmem.writeBursts 821104 # Number of DRAM write bursts, including those merged in the write queue 97system.physmem.bytesReadDRAM 425857728 # Total number of bytes read from DRAM 98system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue 99system.physmem.bytesWritten 7268800 # Total number of bytes written to DRAM 100system.physmem.bytesReadSys 62146244 # Total read bytes from the system interface side 101system.physmem.bytesWrittenSys 7140496 # Total written bytes from the system interface side 102system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue 103system.physmem.mergedWrBursts 707525 # Number of DRAM write bursts merged with an existing one 104system.physmem.neitherReadNorWriteReqs 12040 # Number of requests that are neither read nor write 105system.physmem.perBankRdBursts::0 415388 # Per bank write bursts 106system.physmem.perBankRdBursts::1 415219 # Per bank write bursts 107system.physmem.perBankRdBursts::2 415339 # Per bank write bursts 108system.physmem.perBankRdBursts::3 415675 # Per bank write bursts 109system.physmem.perBankRdBursts::4 422392 # Per bank write bursts | 86system.physmem.bw_total::cpu1.inst 282545 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.data 6667079 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::total 57881294 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.readReqs 6654093 # Number of read requests accepted 90system.physmem.writeReqs 820778 # Number of write requests accepted 91system.physmem.readBursts 6654093 # Number of DRAM read bursts, including those serviced by the write queue 92system.physmem.writeBursts 820778 # Number of DRAM write bursts, including those merged in the write queue 93system.physmem.bytesReadDRAM 425823936 # Total number of bytes read from DRAM 94system.physmem.bytesReadWrQ 38016 # Total number of bytes read from write queue 95system.physmem.bytesWritten 7142848 # Total number of bytes written to DRAM 96system.physmem.bytesReadSys 62119428 # Total read bytes from the system interface side 97system.physmem.bytesWrittenSys 7119632 # Total written bytes from the system interface side 98system.physmem.servicedByWrQ 594 # Number of DRAM read bursts serviced by the write queue 99system.physmem.mergedWrBursts 709146 # Number of DRAM write bursts merged with an existing one 100system.physmem.neitherReadNorWriteReqs 11979 # Number of requests that are neither read nor write 101system.physmem.perBankRdBursts::0 415258 # Per bank write bursts 102system.physmem.perBankRdBursts::1 415304 # Per bank write bursts 103system.physmem.perBankRdBursts::2 415298 # Per bank write bursts 104system.physmem.perBankRdBursts::3 415715 # Per bank write bursts 105system.physmem.perBankRdBursts::4 422332 # Per bank write bursts |
| 110system.physmem.perBankRdBursts::5 415542 # Per bank write bursts | 106system.physmem.perBankRdBursts::5 415542 # Per bank write bursts |
| 111system.physmem.perBankRdBursts::6 415783 # Per bank write bursts 112system.physmem.perBankRdBursts::7 415483 # Per bank write bursts 113system.physmem.perBankRdBursts::8 416074 # Per bank write bursts 114system.physmem.perBankRdBursts::9 415577 # Per bank write bursts 115system.physmem.perBankRdBursts::10 415249 # Per bank write bursts 116system.physmem.perBankRdBursts::11 414844 # Per bank write bursts 117system.physmem.perBankRdBursts::12 415143 # Per bank write bursts 118system.physmem.perBankRdBursts::13 415555 # Per bank write bursts 119system.physmem.perBankRdBursts::14 415561 # Per bank write bursts 120system.physmem.perBankRdBursts::15 415203 # Per bank write bursts 121system.physmem.perBankWrBursts::0 6999 # Per bank write bursts 122system.physmem.perBankWrBursts::1 6843 # Per bank write bursts 123system.physmem.perBankWrBursts::2 7018 # Per bank write bursts 124system.physmem.perBankWrBursts::3 7170 # Per bank write bursts 125system.physmem.perBankWrBursts::4 7419 # Per bank write bursts 126system.physmem.perBankWrBursts::5 7182 # Per bank write bursts 127system.physmem.perBankWrBursts::6 7433 # Per bank write bursts 128system.physmem.perBankWrBursts::7 7180 # Per bank write bursts 129system.physmem.perBankWrBursts::8 7611 # Per bank write bursts 130system.physmem.perBankWrBursts::9 7217 # Per bank write bursts 131system.physmem.perBankWrBursts::10 7107 # Per bank write bursts 132system.physmem.perBankWrBursts::11 6660 # Per bank write bursts 133system.physmem.perBankWrBursts::12 6804 # Per bank write bursts 134system.physmem.perBankWrBursts::13 7009 # Per bank write bursts 135system.physmem.perBankWrBursts::14 7096 # Per bank write bursts 136system.physmem.perBankWrBursts::15 6827 # Per bank write bursts | 107system.physmem.perBankRdBursts::6 415821 # Per bank write bursts 108system.physmem.perBankRdBursts::7 415579 # Per bank write bursts 109system.physmem.perBankRdBursts::8 415943 # Per bank write bursts 110system.physmem.perBankRdBursts::9 415582 # Per bank write bursts 111system.physmem.perBankRdBursts::10 415396 # Per bank write bursts 112system.physmem.perBankRdBursts::11 414885 # Per bank write bursts 113system.physmem.perBankRdBursts::12 414891 # Per bank write bursts 114system.physmem.perBankRdBursts::13 415396 # Per bank write bursts 115system.physmem.perBankRdBursts::14 415532 # Per bank write bursts 116system.physmem.perBankRdBursts::15 415025 # Per bank write bursts 117system.physmem.perBankWrBursts::0 6797 # Per bank write bursts 118system.physmem.perBankWrBursts::1 6838 # Per bank write bursts 119system.physmem.perBankWrBursts::2 6874 # Per bank write bursts 120system.physmem.perBankWrBursts::3 7108 # Per bank write bursts 121system.physmem.perBankWrBursts::4 7245 # Per bank write bursts 122system.physmem.perBankWrBursts::5 7088 # Per bank write bursts 123system.physmem.perBankWrBursts::6 7332 # Per bank write bursts 124system.physmem.perBankWrBursts::7 7150 # Per bank write bursts 125system.physmem.perBankWrBursts::8 7392 # Per bank write bursts 126system.physmem.perBankWrBursts::9 7114 # Per bank write bursts 127system.physmem.perBankWrBursts::10 7008 # Per bank write bursts 128system.physmem.perBankWrBursts::11 6578 # Per bank write bursts 129system.physmem.perBankWrBursts::12 6732 # Per bank write bursts 130system.physmem.perBankWrBursts::13 6801 # Per bank write bursts 131system.physmem.perBankWrBursts::14 7004 # Per bank write bursts 132system.physmem.perBankWrBursts::15 6546 # Per bank write bursts |
| 137system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 138system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 133system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 134system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 139system.physmem.totGap 1196138285000 # Total gap between requests | 135system.physmem.totGap 1196220625500 # Total gap between requests |
| 140system.physmem.readPktSize::0 0 # Read request sizes (log2) 141system.physmem.readPktSize::1 0 # Read request sizes (log2) 142system.physmem.readPktSize::2 6849 # Read request sizes (log2) 143system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 144system.physmem.readPktSize::4 0 # Read request sizes (log2) 145system.physmem.readPktSize::5 0 # Read request sizes (log2) | 136system.physmem.readPktSize::0 0 # Read request sizes (log2) 137system.physmem.readPktSize::1 0 # Read request sizes (log2) 138system.physmem.readPktSize::2 6849 # Read request sizes (log2) 139system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 140system.physmem.readPktSize::4 0 # Read request sizes (log2) 141system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 146system.physmem.readPktSize::6 159599 # Read request sizes (log2) | 142system.physmem.readPktSize::6 159180 # Read request sizes (log2) |
| 147system.physmem.writePktSize::0 0 # Write request sizes (log2) 148system.physmem.writePktSize::1 0 # Write request sizes (log2) 149system.physmem.writePktSize::2 756836 # Write request sizes (log2) 150system.physmem.writePktSize::3 0 # Write request sizes (log2) 151system.physmem.writePktSize::4 0 # Write request sizes (log2) 152system.physmem.writePktSize::5 0 # Write request sizes (log2) | 143system.physmem.writePktSize::0 0 # Write request sizes (log2) 144system.physmem.writePktSize::1 0 # Write request sizes (log2) 145system.physmem.writePktSize::2 756836 # Write request sizes (log2) 146system.physmem.writePktSize::3 0 # Write request sizes (log2) 147system.physmem.writePktSize::4 0 # Write request sizes (log2) 148system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 153system.physmem.writePktSize::6 64268 # Write request sizes (log2) 154system.physmem.rdQLenPdf::0 628282 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::1 475071 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::2 476093 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::3 1580129 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::4 1132007 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::5 1126499 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::6 1123122 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::7 25082 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::8 24371 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::9 9325 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::10 9268 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::11 9185 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::12 8944 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::13 8860 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::14 8817 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::15 8783 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see | 149system.physmem.writePktSize::6 63942 # Write request sizes (log2) 150system.physmem.rdQLenPdf::0 568386 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::1 406756 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::2 406740 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::3 413202 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::4 408903 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::5 410926 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::6 1188562 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::7 1189774 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::8 1562236 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::9 22558 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::10 14685 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::11 15166 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::12 13714 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::13 12546 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::14 9828 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::15 9386 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see |
| 172system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 168system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 186system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::1 5166 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::2 5163 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::3 5163 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::7 5163 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::9 5161 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::13 5161 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::15 5162 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::17 5164 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::18 5166 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::19 5163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 218system.physmem.bytesPerActivate::samples 74541 # Bytes accessed per row activation 219system.physmem.bytesPerActivate::mean 5810.577695 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::gmean 397.196541 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::stdev 13066.067638 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::64-71 25758 34.56% 34.56% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::128-135 15237 20.44% 55.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::192-199 3243 4.35% 59.35% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-263 2416 3.24% 62.59% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::320-327 1619 2.17% 64.76% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::384-391 1307 1.75% 66.51% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::448-455 1041 1.40% 67.91% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::512-519 1103 1.48% 69.39% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::576-583 718 0.96% 70.35% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::640-647 614 0.82% 71.18% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::704-711 577 0.77% 71.95% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::768-775 705 0.95% 72.90% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::832-839 343 0.46% 73.36% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::896-903 280 0.38% 73.73% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::960-967 211 0.28% 74.02% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::1024-1031 365 0.49% 74.51% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::1088-1095 178 0.24% 74.74% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::1152-1159 141 0.19% 74.93% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.12% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::1280-1287 160 0.21% 75.34% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.50% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::1408-1415 2248 3.02% 78.52% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1472-1479 145 0.19% 78.71% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1536-1543 165 0.22% 78.93% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::1600-1607 59 0.08% 79.01% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::1664-1671 66 0.09% 79.10% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.16% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1792-1799 116 0.16% 79.32% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.39% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::1920-1927 27 0.04% 79.42% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1984-1991 17 0.02% 79.45% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::2048-2055 120 0.16% 79.61% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.63% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.66% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::2240-2247 29 0.04% 79.70% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::2304-2311 31 0.04% 79.74% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::2368-2375 12 0.02% 79.75% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::2432-2439 26 0.03% 79.79% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::2496-2503 23 0.03% 79.82% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.94% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::2624-2631 24 0.03% 79.97% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::2688-2695 12 0.02% 79.99% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::2752-2759 29 0.04% 80.03% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.08% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::2880-2887 10 0.01% 80.09% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::2944-2951 25 0.03% 80.12% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.14% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::3072-3079 133 0.18% 80.32% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.34% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::3200-3207 12 0.02% 80.36% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::3264-3271 14 0.02% 80.38% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::3328-3335 45 0.06% 80.44% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::3392-3399 4 0.01% 80.44% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.46% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::3520-3527 21 0.03% 80.48% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.60% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::3648-3655 4 0.01% 80.61% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::3712-3719 17 0.02% 80.63% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::3776-3783 31 0.04% 80.67% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::3840-3847 79 0.11% 80.78% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.80% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::3968-3975 3 0.00% 80.81% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::4096-4103 183 0.25% 81.06% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::4160-4167 2 0.00% 81.06% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.06% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.09% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::4352-4359 24 0.03% 81.12% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::4416-4423 3 0.00% 81.12% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.15% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.15% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::4608-4615 17 0.02% 81.17% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::4672-4679 18 0.02% 81.20% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.20% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.20% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::4864-4871 95 0.13% 81.33% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::4928-4935 11 0.01% 81.35% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::4992-4999 5 0.01% 81.35% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.37% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::5120-5127 100 0.13% 81.51% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.51% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.54% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::5312-5319 4 0.01% 81.54% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::5376-5383 16 0.02% 81.56% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::5440-5447 174 0.23% 81.80% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.88% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::5632-5639 9 0.01% 81.89% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.89% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::5888-5895 93 0.12% 82.02% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::6016-6023 3 0.00% 82.02% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::6144-6151 214 0.29% 82.31% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::6400-6407 32 0.04% 82.35% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.35% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::6592-6599 2 0.00% 82.35% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::6656-6663 12 0.02% 82.37% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.39% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::7168-7175 160 0.21% 82.61% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::7232-7239 1 0.00% 82.61% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::7424-7431 23 0.03% 82.64% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.64% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::7680-7687 12 0.02% 82.66% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.66% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::7936-7943 24 0.03% 82.69% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.70% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::8192-8199 265 0.36% 83.05% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::8448-8455 29 0.04% 83.09% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.09% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::8704-8711 17 0.02% 83.11% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::8960-8967 27 0.04% 83.15% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.15% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::9216-9223 153 0.21% 83.36% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::9472-9479 18 0.02% 83.38% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.38% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::9728-9735 16 0.02% 83.40% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::9984-9991 33 0.04% 83.45% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.45% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.45% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::10240-10247 214 0.29% 83.74% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.74% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::10496-10503 86 0.12% 83.85% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.86% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.86% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::10752-10759 12 0.02% 83.87% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::11008-11015 17 0.02% 83.90% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.90% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::11264-11271 106 0.14% 84.04% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.04% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.04% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::11520-11527 81 0.11% 84.15% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::11776-11783 14 0.02% 84.17% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::12032-12039 16 0.02% 84.19% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::12096-12103 3 0.00% 84.20% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.20% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::12288-12295 158 0.21% 84.41% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.41% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.41% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::12544-12551 76 0.10% 84.51% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::12800-12807 84 0.11% 84.63% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::13056-13063 29 0.04% 84.67% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.67% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::13312-13319 105 0.14% 84.81% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::13376-13383 1 0.00% 84.81% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::13568-13575 26 0.03% 84.84% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.95% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::14080-14087 13 0.02% 84.97% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::14336-14343 92 0.12% 85.10% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::14592-14599 80 0.11% 85.20% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::14848-14855 81 0.11% 85.31% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.31% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::15104-15111 16 0.02% 85.33% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::15360-15367 110 0.15% 85.48% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.48% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::15616-15623 77 0.10% 85.59% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15808-15815 1 0.00% 85.59% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::15872-15879 13 0.02% 85.61% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::16128-16135 82 0.11% 85.72% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.72% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::16384-16391 155 0.21% 85.93% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::16640-16647 83 0.11% 86.04% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::16896-16903 8 0.01% 86.05% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.05% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::17152-17159 77 0.10% 86.16% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::17408-17415 119 0.16% 86.31% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::17664-17671 21 0.03% 86.34% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::17920-17927 82 0.11% 86.45% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::17984-17991 1 0.00% 86.45% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::18176-18183 80 0.11% 86.56% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.56% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::18432-18439 83 0.11% 86.67% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::18496-18503 3 0.00% 86.68% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::18688-18695 10 0.01% 86.69% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::18880-18887 1 0.00% 86.69% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::18944-18951 83 0.11% 86.80% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.84% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.84% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::19456-19463 103 0.14% 86.98% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::19584-19591 1 0.00% 86.98% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::19648-19655 1 0.00% 86.98% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::19712-19719 25 0.03% 87.02% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.02% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::19968-19975 80 0.11% 87.13% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::20160-20167 1 0.00% 87.13% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::20224-20231 73 0.10% 87.22% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::20480-20487 155 0.21% 87.43% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.43% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::20736-20743 19 0.03% 87.46% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::20992-20999 16 0.02% 87.48% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::21248-21255 81 0.11% 87.59% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.59% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::21504-21511 95 0.13% 87.72% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::21760-21767 10 0.01% 87.73% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::22016-22023 9 0.01% 87.74% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.86% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.87% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::22464-22471 1 0.00% 87.87% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::22528-22535 219 0.29% 88.16% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::22784-22791 30 0.04% 88.20% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.20% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.22% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.25% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.45% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::23808-23815 22 0.03% 88.48% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::23872-23879 1 0.00% 88.48% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.48% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::24064-24071 13 0.02% 88.50% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.53% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::24384-24391 3 0.00% 88.53% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::24576-24583 273 0.37% 88.90% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::24832-24839 26 0.03% 88.93% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::24896-24903 2 0.00% 88.93% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::24960-24967 1 0.00% 88.94% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.96% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::25344-25351 24 0.03% 88.99% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.99% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::25600-25607 143 0.19% 89.18% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.18% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.21% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::26112-26119 12 0.02% 89.23% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::26368-26375 28 0.04% 89.26% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.26% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.27% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::26624-26631 214 0.29% 89.55% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::26880-26887 90 0.12% 89.68% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.69% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.69% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.69% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::27392-27399 13 0.02% 89.71% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.71% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.71% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::27648-27655 92 0.12% 89.84% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::27904-27911 79 0.11% 89.94% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::28160-28167 14 0.02% 89.96% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::28352-28359 1 0.00% 89.96% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::28416-28423 19 0.03% 89.99% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.99% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::28608-28615 1 0.00% 89.99% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::28672-28679 159 0.21% 90.21% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.21% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::28928-28935 74 0.10% 90.31% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.31% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::29184-29191 82 0.11% 90.42% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::29440-29447 26 0.03% 90.45% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::29504-29511 2 0.00% 90.45% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::29696-29703 92 0.12% 90.58% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.58% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::29952-29959 27 0.04% 90.62% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::30208-30215 80 0.11% 90.72% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.72% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::30464-30471 9 0.01% 90.74% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.74% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::30720-30727 85 0.11% 90.85% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::30976-30983 81 0.11% 90.96% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.96% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::31232-31239 79 0.11% 91.07% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::31488-31495 18 0.02% 91.09% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.10% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::31744-31751 112 0.15% 91.25% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.25% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::32000-32007 76 0.10% 91.35% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::32256-32263 8 0.01% 91.36% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.36% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.36% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.36% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::32512-32519 82 0.11% 91.47% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::32768-32775 154 0.21% 91.68% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::33024-33031 83 0.11% 91.79% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::33088-33095 1 0.00% 91.79% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.80% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::33216-33223 2 0.00% 91.80% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::33280-33287 23 0.03% 91.83% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::33344-33351 1 0.00% 91.83% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::33536-33543 76 0.10% 91.93% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.93% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::33792-33799 112 0.15% 92.08% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::33920-33927 2 0.00% 92.09% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.09% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::34048-34055 18 0.02% 92.11% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::34304-34311 79 0.11% 92.22% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.22% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::34560-34567 80 0.11% 92.33% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::34816-34823 78 0.10% 92.43% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.43% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::35008-35015 2 0.00% 92.44% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::35072-35079 8 0.01% 92.45% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::35328-35335 80 0.11% 92.55% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::35584-35591 27 0.04% 92.59% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.59% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::35840-35847 91 0.12% 92.71% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.71% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.75% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.75% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::36352-36359 82 0.11% 92.86% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::36608-36615 73 0.10% 92.96% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::36864-36871 149 0.20% 93.16% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::37120-37127 15 0.02% 93.18% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::37376-37383 14 0.02% 93.19% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::37632-37639 80 0.11% 93.30% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::37888-37895 93 0.12% 93.43% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.43% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.43% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::38144-38151 10 0.01% 93.44% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.44% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.45% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::38400-38407 11 0.01% 93.46% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.46% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::38656-38663 90 0.12% 93.58% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::38912-38919 212 0.28% 93.87% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::39040-39047 1 0.00% 93.87% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.87% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::39168-39175 27 0.04% 93.91% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::39424-39431 11 0.01% 93.92% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::39552-39559 1 0.00% 93.92% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.95% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::39872-39879 1 0.00% 93.95% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::39936-39943 144 0.19% 94.14% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::40192-40199 21 0.03% 94.17% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.19% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::40576-40583 1 0.00% 94.19% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.19% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::40704-40711 25 0.03% 94.23% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::40960-40967 269 0.36% 94.59% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::41152-41159 2 0.00% 94.59% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.62% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::41472-41479 10 0.01% 94.63% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.64% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::41728-41735 23 0.03% 94.67% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.67% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.86% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::42240-42247 21 0.03% 94.89% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::42496-42503 11 0.01% 94.91% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::42624-42631 1 0.00% 94.91% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::42688-42695 1 0.00% 94.91% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::42752-42759 31 0.04% 94.95% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::43008-43015 219 0.29% 95.24% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::43072-43079 1 0.00% 95.25% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::43264-43271 87 0.12% 95.36% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.37% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.38% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::43776-43783 11 0.01% 95.39% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.51% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::44288-44295 80 0.11% 95.62% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::44544-44551 18 0.02% 95.65% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.67% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.67% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::45056-45063 149 0.20% 95.87% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::45312-45319 71 0.10% 95.96% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::45568-45575 78 0.10% 96.07% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::45696-45703 1 0.00% 96.07% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::45824-45831 27 0.04% 96.11% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.11% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.11% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::46080-46087 99 0.13% 96.24% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.28% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::46592-46599 83 0.11% 96.39% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::46656-46663 1 0.00% 96.39% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::46848-46855 11 0.01% 96.41% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::47104-47111 90 0.12% 96.53% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.53% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::47360-47367 82 0.11% 96.64% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::47552-47559 1 0.00% 96.64% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::47616-47623 83 0.11% 96.75% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.75% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.78% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.78% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::48128-48135 130 0.17% 96.95% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.95% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.96% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::48320-48327 2 0.00% 96.96% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::48384-48391 100 0.13% 97.09% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::48576-48583 1 0.00% 97.09% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::48640-48647 6 0.01% 97.10% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.12% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::48896-48903 79 0.11% 97.23% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.23% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::49024-49031 5 0.01% 97.24% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.25% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::49152-49159 2052 2.75% 100.00% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::total 74541 # Bytes accessed per row activation 605system.physmem.totQLat 159547739500 # Total ticks spent queuing 606system.physmem.totMemAccLat 202481649500 # Total ticks spent from burst creation until serviced by the DRAM 607system.physmem.totBusLat 33270135000 # Total ticks spent in databus transfers 608system.physmem.totBankLat 9663775000 # Total ticks spent accessing banks 609system.physmem.avgQLat 23977.62 # Average queueing delay per DRAM burst 610system.physmem.avgBankLat 1452.32 # Average bank access latency per DRAM burst | 182system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::15 2656 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::16 2719 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::17 3656 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::18 5124 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::19 5129 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::20 5125 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::21 5127 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::24 5159 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::25 6206 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::26 5353 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::27 5316 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::28 6283 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::29 5251 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::30 5231 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::31 5217 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::32 5137 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::34 1090 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::35 1087 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::36 1087 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::38 1076 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::39 1074 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::40 1072 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::41 1074 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::42 1072 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::43 1070 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::44 1069 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::45 1069 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::46 1067 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::47 1067 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::48 1065 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::49 1065 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::50 1064 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::51 1064 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::52 1064 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::53 1064 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 241system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 242system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 243system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 244system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 245system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 246system.physmem.bytesPerActivate::samples 427748 # Bytes accessed per row activation 247system.physmem.bytesPerActivate::mean 996.884371 # Bytes accessed per row activation 248system.physmem.bytesPerActivate::gmean 962.233746 # Bytes accessed per row activation 249system.physmem.bytesPerActivate::stdev 147.681447 # Bytes accessed per row activation 250system.physmem.bytesPerActivate::0-127 5003 1.17% 1.17% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::128-255 3928 0.92% 2.09% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::256-383 2092 0.49% 2.58% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::384-511 1312 0.31% 2.88% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::512-639 1079 0.25% 3.14% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::640-767 787 0.18% 3.32% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::768-895 742 0.17% 3.49% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::896-1023 447 0.10% 3.60% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::1024-1151 412358 96.40% 100.00% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::total 427748 # Bytes accessed per row activation 260system.physmem.rdPerTurnAround::samples 5121 # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::mean 1299.254638 # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::stdev 29808.283067 # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::0-65535 5114 99.86% 99.86% # Reads before turning the bus around for writes 264system.physmem.rdPerTurnAround::196608-262143 3 0.06% 99.92% # Reads before turning the bus around for writes 265system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.94% # Reads before turning the bus around for writes 266system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.96% # Reads before turning the bus around for writes 267system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 268system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 269system.physmem.rdPerTurnAround::total 5121 # Reads before turning the bus around for writes 270system.physmem.wrPerTurnAround::samples 5121 # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::mean 21.793986 # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::gmean 20.383938 # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::stdev 9.006526 # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::16 2131 41.61% 41.61% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::17 296 5.78% 47.39% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::18 286 5.58% 52.98% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::19 1314 25.66% 78.64% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::20 15 0.29% 78.93% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::21 5 0.10% 79.03% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::22 2 0.04% 79.07% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::24 2 0.04% 79.11% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::25 1 0.02% 79.13% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::28 3 0.06% 79.18% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::34 1 0.02% 79.20% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::35 1 0.02% 79.22% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::39 953 18.61% 97.83% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::40 61 1.19% 99.02% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::41 17 0.33% 99.36% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::42 33 0.64% 100.00% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::total 5121 # Writes before turning the bus around for reads 291system.physmem.totQLat 249828830750 # Total ticks spent queuing 292system.physmem.totMemAccLat 297299498250 # Total ticks spent from burst creation until serviced by the DRAM 293system.physmem.totBusLat 33267495000 # Total ticks spent in databus transfers 294system.physmem.totBankLat 14203172500 # Total ticks spent accessing banks 295system.physmem.avgQLat 37548.49 # Average queueing delay per DRAM burst 296system.physmem.avgBankLat 2134.69 # Average bank access latency per DRAM burst |
| 611system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 612system.physmem.avgMemAccLat 30429.94 # Average memory access latency per DRAM burst 613system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s 614system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s 615system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s 616system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s | 298system.physmem.avgMemAccLat 44683.18 # Average memory access latency per DRAM burst 299system.physmem.avgRdBW 355.97 # Average DRAM read bandwidth in MiByte/s 300system.physmem.avgWrBW 5.97 # Average achieved write bandwidth in MiByte/s 301system.physmem.avgRdBWSys 51.93 # Average system read bandwidth in MiByte/s 302system.physmem.avgWrBWSys 5.95 # Average system write bandwidth in MiByte/s |
| 617system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 618system.physmem.busUtil 2.83 # Data bus utilization in percentage 619system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 620system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes | 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 2.83 # Data bus utilization in percentage 305system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes |
| 621system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing 622system.physmem.avgWrQLen 12.60 # Average write queue length when enqueuing 623system.physmem.readRowHits 6598250 # Number of row buffer hits during reads 624system.physmem.writeRowHits 94811 # Number of row buffer hits during writes 625system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads 626system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes 627system.physmem.avgGap 160005.31 # Average gap between requests 628system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined 629system.physmem.prechargeAllPercent 4.94 # Percentage of time for which DRAM has all the banks in precharge state 630system.membus.throughput 59942042 # Throughput (bytes/s) 631system.membus.trans_dist::ReadReq 7703387 # Transaction distribution 632system.membus.trans_dist::ReadResp 7703387 # Transaction distribution 633system.membus.trans_dist::WriteReq 767577 # Transaction distribution 634system.membus.trans_dist::WriteResp 767577 # Transaction distribution 635system.membus.trans_dist::Writeback 64268 # Transaction distribution 636system.membus.trans_dist::UpgradeReq 31533 # Transaction distribution 637system.membus.trans_dist::SCUpgradeReq 17272 # Transaction distribution 638system.membus.trans_dist::UpgradeResp 12040 # Transaction distribution 639system.membus.trans_dist::ReadExReq 137758 # Transaction distribution 640system.membus.trans_dist::ReadExResp 137334 # Transaction distribution 641system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382660 # Packet count per connected master and slave (bytes) | 307system.physmem.avgRdQLen 4.56 # Average read queue length when enqueuing 308system.physmem.avgWrQLen 29.44 # Average write queue length when enqueuing 309system.physmem.readRowHits 6202256 # Number of row buffer hits during reads 310system.physmem.writeRowHits 93908 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 93.22 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 84.12 # Row buffer hit rate for writes 313system.physmem.avgGap 160032.28 # Average gap between requests 314system.physmem.pageHitRate 93.07 # Row buffer hit rate, read and write combined 315system.physmem.prechargeAllPercent 6.14 # Percentage of time for which DRAM has all the banks in precharge state 316system.membus.throughput 59898120 # Throughput (bytes/s) 317system.membus.trans_dist::ReadReq 7703395 # Transaction distribution 318system.membus.trans_dist::ReadResp 7703395 # Transaction distribution 319system.membus.trans_dist::WriteReq 767585 # Transaction distribution 320system.membus.trans_dist::WriteResp 767585 # Transaction distribution 321system.membus.trans_dist::Writeback 63942 # Transaction distribution 322system.membus.trans_dist::UpgradeReq 31730 # Transaction distribution 323system.membus.trans_dist::SCUpgradeReq 17317 # Transaction distribution 324system.membus.trans_dist::UpgradeResp 11979 # Transaction distribution 325system.membus.trans_dist::ReadExReq 137317 # Transaction distribution 326system.membus.trans_dist::ReadExResp 136921 # Transaction distribution 327system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382690 # Packet count per connected master and slave (bytes) |
| 642system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) | 328system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) |
| 643system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10292 # Packet count per connected master and slave (bytes) | 329system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) |
| 644system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) | 330system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) |
| 645system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972105 # Packet count per connected master and slave (bytes) 647system.membus.pkt_count_system.l2c.mem_side::total 4366005 # Packet count per connected master and slave (bytes) | 331system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 914 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971094 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count_system.l2c.mem_side::total 4365038 # Packet count per connected master and slave (bytes) |
| 648system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 649system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) | 334system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 335system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) |
| 650system.membus.pkt_count::total 17342133 # Packet count per connected master and slave (bytes) 651system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390026 # Cumulative packet size per connected master and slave (bytes) | 336system.membus.pkt_count::total 17341166 # Packet count per connected master and slave (bytes) 337system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390070 # Cumulative packet size per connected master and slave (bytes) |
| 652system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) | 338system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) |
| 653system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20584 # Cumulative packet size per connected master and slave (bytes) | 339system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) |
| 654system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) | 340system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) |
| 655system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) 656system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17382228 # Cumulative packet size per connected master and slave (bytes) 657system.membus.tot_pkt_size_system.l2c.mem_side::total 19794734 # Cumulative packet size per connected master and slave (bytes) | 341system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1828 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17334548 # Cumulative packet size per connected master and slave (bytes) 343system.membus.tot_pkt_size_system.l2c.mem_side::total 19747126 # Cumulative packet size per connected master and slave (bytes) |
| 658system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 659system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 344system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 345system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 660system.membus.tot_pkt_size::total 71699246 # Cumulative packet size per connected master and slave (bytes) 661system.membus.data_through_bus 71699246 # Total data (bytes) | 346system.membus.tot_pkt_size::total 71651638 # Cumulative packet size per connected master and slave (bytes) 347system.membus.data_through_bus 71651638 # Total data (bytes) |
| 662system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 348system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 663system.membus.reqLayer0.occupancy 1224801500 # Layer occupancy (ticks) | 349system.membus.reqLayer0.occupancy 1224825500 # Layer occupancy (ticks) |
| 664system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 665system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 666system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 350system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 351system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 352system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 667system.membus.reqLayer2.occupancy 9220500 # Layer occupancy (ticks) | 353system.membus.reqLayer2.occupancy 9234000 # Layer occupancy (ticks) |
| 668system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 669system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 670system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 354system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 355system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 356system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 671system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) | 357system.membus.reqLayer5.occupancy 786000 # Layer occupancy (ticks) |
| 672system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 358system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 673system.membus.reqLayer6.occupancy 9211496500 # Layer occupancy (ticks) | 359system.membus.reqLayer6.occupancy 9208108500 # Layer occupancy (ticks) |
| 674system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) | 360system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) |
| 675system.membus.respLayer1.occupancy 5081612097 # Layer occupancy (ticks) | 361system.membus.respLayer1.occupancy 5075173558 # Layer occupancy (ticks) |
| 676system.membus.respLayer1.utilization 0.4 # Layer utilization (%) | 362system.membus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 677system.membus.respLayer2.occupancy 14657936499 # Layer occupancy (ticks) 678system.membus.respLayer2.utilization 1.2 # Layer utilization (%) | 363system.membus.respLayer2.occupancy 16181474500 # Layer occupancy (ticks) 364system.membus.respLayer2.utilization 1.4 # Layer utilization (%) |
| 679system.cpu_clk_domain.clock 500 # Clock period in ticks | 365system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 680system.l2c.tags.replacements 69480 # number of replacements 681system.l2c.tags.tagsinuse 52958.538682 # Cycle average of tags in use 682system.l2c.tags.total_refs 1674406 # Total number of references to valid blocks. 683system.l2c.tags.sampled_refs 134639 # Sample count of references to valid blocks. 684system.l2c.tags.avg_refs 12.436263 # Average number of references to valid blocks. | 366system.l2c.tags.replacements 69062 # number of replacements 367system.l2c.tags.tagsinuse 52959.899517 # Cycle average of tags in use 368system.l2c.tags.total_refs 1674433 # Total number of references to valid blocks. 369system.l2c.tags.sampled_refs 134270 # Sample count of references to valid blocks. 370system.l2c.tags.avg_refs 12.470641 # Average number of references to valid blocks. |
| 685system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 371system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 686system.l2c.tags.occ_blocks::writebacks 40140.336267 # Average occupied blocks per requestor 687system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor 688system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001545 # Average occupied blocks per requestor 689system.l2c.tags.occ_blocks::cpu0.inst 3711.388388 # Average occupied blocks per requestor 690system.l2c.tags.occ_blocks::cpu0.data 4232.378884 # Average occupied blocks per requestor 691system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742427 # Average occupied blocks per requestor 692system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor 693system.l2c.tags.occ_blocks::cpu1.inst 2812.770235 # Average occupied blocks per requestor 694system.l2c.tags.occ_blocks::cpu1.data 2058.918835 # Average occupied blocks per requestor 695system.l2c.tags.occ_percent::writebacks 0.612493 # Average percentage of cache occupancy | 372system.l2c.tags.occ_blocks::writebacks 40142.433744 # Average occupied blocks per requestor 373system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor 374system.l2c.tags.occ_blocks::cpu0.itb.walker 0.003238 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu0.inst 3707.808501 # Average occupied blocks per requestor 376system.l2c.tags.occ_blocks::cpu0.data 4231.213775 # Average occupied blocks per requestor 377system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742447 # Average occupied blocks per requestor 378system.l2c.tags.occ_blocks::cpu1.inst 2816.465022 # Average occupied blocks per requestor 379system.l2c.tags.occ_blocks::cpu1.data 2059.232379 # Average occupied blocks per requestor 380system.l2c.tags.occ_percent::writebacks 0.612525 # Average percentage of cache occupancy |
| 696system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 697system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 381system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 382system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 698system.l2c.tags.occ_percent::cpu0.inst 0.056631 # Average percentage of cache occupancy 699system.l2c.tags.occ_percent::cpu0.data 0.064581 # Average percentage of cache occupancy | 383system.l2c.tags.occ_percent::cpu0.inst 0.056577 # Average percentage of cache occupancy 384system.l2c.tags.occ_percent::cpu0.data 0.064563 # Average percentage of cache occupancy |
| 700system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy | 385system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy |
| 701system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 702system.l2c.tags.occ_percent::cpu1.inst 0.042919 # Average percentage of cache occupancy 703system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy 704system.l2c.tags.occ_percent::total 0.808083 # Average percentage of cache occupancy | 386system.l2c.tags.occ_percent::cpu1.inst 0.042976 # Average percentage of cache occupancy 387system.l2c.tags.occ_percent::cpu1.data 0.031421 # Average percentage of cache occupancy 388system.l2c.tags.occ_percent::total 0.808104 # Average percentage of cache occupancy |
| 705system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id | 389system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id |
| 706system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id | 390system.l2c.tags.occ_task_id_blocks::1024 65203 # Occupied blocks per task id |
| 707system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 708system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id | 391system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 392system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id |
| 709system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 710system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id 711system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id 712system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id 713system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id | 393system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 394system.l2c.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id 395system.l2c.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id 396system.l2c.tags.age_task_id_blocks_1024::3 7908 # Occupied blocks per task id 397system.l2c.tags.age_task_id_blocks_1024::4 55276 # Occupied blocks per task id |
| 714system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id | 398system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id |
| 715system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id 716system.l2c.tags.tag_accesses 17216542 # Number of tag accesses 717system.l2c.tags.data_accesses 17216542 # Number of data accesses 718system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits 719system.l2c.ReadReq_hits::cpu0.itb.walker 1731 # number of ReadReq hits 720system.l2c.ReadReq_hits::cpu0.inst 419647 # number of ReadReq hits 721system.l2c.ReadReq_hits::cpu0.data 206017 # number of ReadReq hits 722system.l2c.ReadReq_hits::cpu1.dtb.walker 5550 # number of ReadReq hits 723system.l2c.ReadReq_hits::cpu1.itb.walker 1931 # number of ReadReq hits 724system.l2c.ReadReq_hits::cpu1.inst 464603 # number of ReadReq hits 725system.l2c.ReadReq_hits::cpu1.data 143237 # number of ReadReq hits 726system.l2c.ReadReq_hits::total 1246526 # number of ReadReq hits 727system.l2c.Writeback_hits::writebacks 570959 # number of Writeback hits 728system.l2c.Writeback_hits::total 570959 # number of Writeback hits 729system.l2c.UpgradeReq_hits::cpu0.data 1148 # number of UpgradeReq hits 730system.l2c.UpgradeReq_hits::cpu1.data 589 # number of UpgradeReq hits 731system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits | 399system.l2c.tags.occ_task_id_percent::1024 0.994919 # Percentage of cache occupancy per task id 400system.l2c.tags.tag_accesses 17240213 # Number of tag accesses 401system.l2c.tags.data_accesses 17240213 # Number of data accesses 402system.l2c.ReadReq_hits::cpu0.dtb.walker 2997 # number of ReadReq hits 403system.l2c.ReadReq_hits::cpu0.itb.walker 1656 # number of ReadReq hits 404system.l2c.ReadReq_hits::cpu0.inst 349452 # number of ReadReq hits 405system.l2c.ReadReq_hits::cpu0.data 169925 # number of ReadReq hits 406system.l2c.ReadReq_hits::cpu1.dtb.walker 6371 # number of ReadReq hits 407system.l2c.ReadReq_hits::cpu1.itb.walker 1905 # number of ReadReq hits 408system.l2c.ReadReq_hits::cpu1.inst 535287 # number of ReadReq hits 409system.l2c.ReadReq_hits::cpu1.data 180837 # number of ReadReq hits 410system.l2c.ReadReq_hits::total 1248430 # number of ReadReq hits 411system.l2c.Writeback_hits::writebacks 572475 # number of Writeback hits 412system.l2c.Writeback_hits::total 572475 # number of Writeback hits 413system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits 414system.l2c.UpgradeReq_hits::cpu1.data 587 # number of UpgradeReq hits 415system.l2c.UpgradeReq_hits::total 1630 # number of UpgradeReq hits |
| 732system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits | 416system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits |
| 733system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits 734system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits 735system.l2c.ReadExReq_hits::cpu0.data 56693 # number of ReadExReq hits 736system.l2c.ReadExReq_hits::cpu1.data 52725 # number of ReadExReq hits 737system.l2c.ReadExReq_hits::total 109418 # number of ReadExReq hits 738system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits 739system.l2c.demand_hits::cpu0.itb.walker 1731 # number of demand (read+write) hits 740system.l2c.demand_hits::cpu0.inst 419647 # number of demand (read+write) hits 741system.l2c.demand_hits::cpu0.data 262710 # number of demand (read+write) hits 742system.l2c.demand_hits::cpu1.dtb.walker 5550 # number of demand (read+write) hits 743system.l2c.demand_hits::cpu1.itb.walker 1931 # number of demand (read+write) hits 744system.l2c.demand_hits::cpu1.inst 464603 # number of demand (read+write) hits 745system.l2c.demand_hits::cpu1.data 195962 # number of demand (read+write) hits 746system.l2c.demand_hits::total 1355944 # number of demand (read+write) hits 747system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits 748system.l2c.overall_hits::cpu0.itb.walker 1731 # number of overall hits 749system.l2c.overall_hits::cpu0.inst 419647 # number of overall hits 750system.l2c.overall_hits::cpu0.data 262710 # number of overall hits 751system.l2c.overall_hits::cpu1.dtb.walker 5550 # number of overall hits 752system.l2c.overall_hits::cpu1.itb.walker 1931 # number of overall hits 753system.l2c.overall_hits::cpu1.inst 464603 # number of overall hits 754system.l2c.overall_hits::cpu1.data 195962 # number of overall hits 755system.l2c.overall_hits::total 1355944 # number of overall hits | 417system.l2c.SCUpgradeReq_hits::cpu1.data 84 # number of SCUpgradeReq hits 418system.l2c.SCUpgradeReq_hits::total 304 # number of SCUpgradeReq hits 419system.l2c.ReadExReq_hits::cpu0.data 47236 # number of ReadExReq hits 420system.l2c.ReadExReq_hits::cpu1.data 62412 # number of ReadExReq hits 421system.l2c.ReadExReq_hits::total 109648 # number of ReadExReq hits 422system.l2c.demand_hits::cpu0.dtb.walker 2997 # number of demand (read+write) hits 423system.l2c.demand_hits::cpu0.itb.walker 1656 # number of demand (read+write) hits 424system.l2c.demand_hits::cpu0.inst 349452 # number of demand (read+write) hits 425system.l2c.demand_hits::cpu0.data 217161 # number of demand (read+write) hits 426system.l2c.demand_hits::cpu1.dtb.walker 6371 # number of demand (read+write) hits 427system.l2c.demand_hits::cpu1.itb.walker 1905 # number of demand (read+write) hits 428system.l2c.demand_hits::cpu1.inst 535287 # number of demand (read+write) hits 429system.l2c.demand_hits::cpu1.data 243249 # number of demand (read+write) hits 430system.l2c.demand_hits::total 1358078 # number of demand (read+write) hits 431system.l2c.overall_hits::cpu0.dtb.walker 2997 # number of overall hits 432system.l2c.overall_hits::cpu0.itb.walker 1656 # number of overall hits 433system.l2c.overall_hits::cpu0.inst 349452 # number of overall hits 434system.l2c.overall_hits::cpu0.data 217161 # number of overall hits 435system.l2c.overall_hits::cpu1.dtb.walker 6371 # number of overall hits 436system.l2c.overall_hits::cpu1.itb.walker 1905 # number of overall hits 437system.l2c.overall_hits::cpu1.inst 535287 # number of overall hits 438system.l2c.overall_hits::cpu1.data 243249 # number of overall hits 439system.l2c.overall_hits::total 1358078 # number of overall hits |
| 756system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 440system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses |
| 757system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 758system.l2c.ReadReq_misses::cpu0.inst 5732 # number of ReadReq misses 759system.l2c.ReadReq_misses::cpu0.data 7847 # number of ReadReq misses | 441system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 442system.l2c.ReadReq_misses::cpu0.inst 5500 # number of ReadReq misses 443system.l2c.ReadReq_misses::cpu0.data 7825 # number of ReadReq misses |
| 760system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses | 444system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses |
| 761system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 762system.l2c.ReadReq_misses::cpu1.inst 5061 # number of ReadReq misses 763system.l2c.ReadReq_misses::cpu1.data 3618 # number of ReadReq misses 764system.l2c.ReadReq_misses::total 22266 # number of ReadReq misses 765system.l2c.UpgradeReq_misses::cpu0.data 4882 # number of UpgradeReq misses 766system.l2c.UpgradeReq_misses::cpu1.data 3680 # number of UpgradeReq misses 767system.l2c.UpgradeReq_misses::total 8562 # number of UpgradeReq misses | 445system.l2c.ReadReq_misses::cpu1.inst 5275 # number of ReadReq misses 446system.l2c.ReadReq_misses::cpu1.data 3652 # number of ReadReq misses 447system.l2c.ReadReq_misses::total 22260 # number of ReadReq misses 448system.l2c.UpgradeReq_misses::cpu0.data 3753 # number of UpgradeReq misses 449system.l2c.UpgradeReq_misses::cpu1.data 4772 # number of UpgradeReq misses 450system.l2c.UpgradeReq_misses::total 8525 # number of UpgradeReq misses |
| 768system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses | 451system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses |
| 769system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses 770system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses 771system.l2c.ReadExReq_misses::cpu0.data 67309 # number of ReadExReq misses 772system.l2c.ReadExReq_misses::cpu1.data 72458 # number of ReadExReq misses 773system.l2c.ReadExReq_misses::total 139767 # number of ReadExReq misses | 452system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses 453system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses 454system.l2c.ReadExReq_misses::cpu0.data 63889 # number of ReadExReq misses 455system.l2c.ReadExReq_misses::cpu1.data 75455 # number of ReadExReq misses 456system.l2c.ReadExReq_misses::total 139344 # number of ReadExReq misses |
| 774system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 457system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses |
| 775system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 776system.l2c.demand_misses::cpu0.inst 5732 # number of demand (read+write) misses 777system.l2c.demand_misses::cpu0.data 75156 # number of demand (read+write) misses | 458system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 459system.l2c.demand_misses::cpu0.inst 5500 # number of demand (read+write) misses 460system.l2c.demand_misses::cpu0.data 71714 # number of demand (read+write) misses |
| 778system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses | 461system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses |
| 779system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 780system.l2c.demand_misses::cpu1.inst 5061 # number of demand (read+write) misses 781system.l2c.demand_misses::cpu1.data 76076 # number of demand (read+write) misses 782system.l2c.demand_misses::total 162033 # number of demand (read+write) misses | 462system.l2c.demand_misses::cpu1.inst 5275 # number of demand (read+write) misses 463system.l2c.demand_misses::cpu1.data 79107 # number of demand (read+write) misses 464system.l2c.demand_misses::total 161604 # number of demand (read+write) misses |
| 783system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 465system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses |
| 784system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 785system.l2c.overall_misses::cpu0.inst 5732 # number of overall misses 786system.l2c.overall_misses::cpu0.data 75156 # number of overall misses | 466system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 467system.l2c.overall_misses::cpu0.inst 5500 # number of overall misses 468system.l2c.overall_misses::cpu0.data 71714 # number of overall misses |
| 787system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses | 469system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses |
| 788system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 789system.l2c.overall_misses::cpu1.inst 5061 # number of overall misses 790system.l2c.overall_misses::cpu1.data 76076 # number of overall misses 791system.l2c.overall_misses::total 162033 # number of overall misses | 470system.l2c.overall_misses::cpu1.inst 5275 # number of overall misses 471system.l2c.overall_misses::cpu1.data 79107 # number of overall misses 472system.l2c.overall_misses::total 161604 # number of overall misses |
| 792system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles | 473system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles |
| 793system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 794system.l2c.ReadReq_miss_latency::cpu0.inst 403588750 # number of ReadReq miss cycles 795system.l2c.ReadReq_miss_latency::cpu0.data 587952999 # number of ReadReq miss cycles 796system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 347000 # number of ReadReq miss cycles 797system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 798system.l2c.ReadReq_miss_latency::cpu1.inst 364948250 # number of ReadReq miss cycles 799system.l2c.ReadReq_miss_latency::cpu1.data 284058750 # number of ReadReq miss cycles 800system.l2c.ReadReq_miss_latency::total 1641151749 # number of ReadReq miss cycles 801system.l2c.UpgradeReq_miss_latency::cpu0.data 13131433 # number of UpgradeReq miss cycles 802system.l2c.UpgradeReq_miss_latency::cpu1.data 12135478 # number of UpgradeReq miss cycles 803system.l2c.UpgradeReq_miss_latency::total 25266911 # number of UpgradeReq miss cycles 804system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1819924 # number of SCUpgradeReq miss cycles 805system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2531891 # number of SCUpgradeReq miss cycles 806system.l2c.SCUpgradeReq_miss_latency::total 4351815 # number of SCUpgradeReq miss cycles 807system.l2c.ReadExReq_miss_latency::cpu0.data 4527558160 # number of ReadExReq miss cycles 808system.l2c.ReadExReq_miss_latency::cpu1.data 5454938401 # number of ReadExReq miss cycles 809system.l2c.ReadExReq_miss_latency::total 9982496561 # number of ReadExReq miss cycles | 474system.l2c.ReadReq_miss_latency::cpu0.itb.walker 224500 # number of ReadReq miss cycles 475system.l2c.ReadReq_miss_latency::cpu0.inst 385138750 # number of ReadReq miss cycles 476system.l2c.ReadReq_miss_latency::cpu0.data 587705249 # number of ReadReq miss cycles 477system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 334500 # number of ReadReq miss cycles 478system.l2c.ReadReq_miss_latency::cpu1.inst 381420250 # number of ReadReq miss cycles 479system.l2c.ReadReq_miss_latency::cpu1.data 283658250 # number of ReadReq miss cycles 480system.l2c.ReadReq_miss_latency::total 1638513499 # number of ReadReq miss cycles 481system.l2c.UpgradeReq_miss_latency::cpu0.data 11041523 # number of UpgradeReq miss cycles 482system.l2c.UpgradeReq_miss_latency::cpu1.data 13954898 # number of UpgradeReq miss cycles 483system.l2c.UpgradeReq_miss_latency::total 24996421 # number of UpgradeReq miss cycles 484system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1841422 # number of SCUpgradeReq miss cycles 485system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2322900 # number of SCUpgradeReq miss cycles 486system.l2c.SCUpgradeReq_miss_latency::total 4164322 # number of SCUpgradeReq miss cycles 487system.l2c.ReadExReq_miss_latency::cpu0.data 4291032858 # number of ReadExReq miss cycles 488system.l2c.ReadExReq_miss_latency::cpu1.data 5578462720 # number of ReadExReq miss cycles 489system.l2c.ReadExReq_miss_latency::total 9869495578 # number of ReadExReq miss cycles |
| 810system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles | 490system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles |
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| 819system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles | 498system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles |
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| 842system.l2c.SCUpgradeReq_accesses::cpu0.data 791 # number of SCUpgradeReq accesses(hits+misses) | 520system.l2c.SCUpgradeReq_accesses::cpu0.data 791 # number of SCUpgradeReq accesses(hits+misses) |
| 843system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) 844system.l2c.SCUpgradeReq_accesses::total 1365 # number of SCUpgradeReq accesses(hits+misses) 845system.l2c.ReadExReq_accesses::cpu0.data 124002 # number of ReadExReq accesses(hits+misses) 846system.l2c.ReadExReq_accesses::cpu1.data 125183 # number of ReadExReq accesses(hits+misses) 847system.l2c.ReadExReq_accesses::total 249185 # number of ReadExReq accesses(hits+misses) 848system.l2c.demand_accesses::cpu0.dtb.walker 3811 # number of demand (read+write) accesses 849system.l2c.demand_accesses::cpu0.itb.walker 1733 # number of demand (read+write) accesses 850system.l2c.demand_accesses::cpu0.inst 425379 # number of demand (read+write) accesses 851system.l2c.demand_accesses::cpu0.data 337866 # number of demand (read+write) accesses 852system.l2c.demand_accesses::cpu1.dtb.walker 5554 # number of demand (read+write) accesses 853system.l2c.demand_accesses::cpu1.itb.walker 1932 # number of demand (read+write) accesses 854system.l2c.demand_accesses::cpu1.inst 469664 # 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number of overall (read+write) accesses 866system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for ReadReq accesses 867system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001154 # miss rate for ReadReq accesses 868system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses 869system.l2c.ReadReq_miss_rate::cpu0.data 0.036692 # miss rate for ReadReq accesses 870system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for ReadReq accesses 871system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000518 # miss rate for ReadReq accesses 872system.l2c.ReadReq_miss_rate::cpu1.inst 0.010776 # miss rate for ReadReq accesses 873system.l2c.ReadReq_miss_rate::cpu1.data 0.024637 # miss rate for ReadReq accesses 874system.l2c.ReadReq_miss_rate::total 0.017549 # miss rate for ReadReq accesses 875system.l2c.UpgradeReq_miss_rate::cpu0.data 0.809619 # miss rate for UpgradeReq accesses 876system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862029 # miss rate for UpgradeReq accesses 877system.l2c.UpgradeReq_miss_rate::total 0.831343 # miss rate for UpgradeReq accesses | 521system.l2c.SCUpgradeReq_accesses::cpu1.data 544 # number of SCUpgradeReq accesses(hits+misses) 522system.l2c.SCUpgradeReq_accesses::total 1335 # number of SCUpgradeReq accesses(hits+misses) 523system.l2c.ReadExReq_accesses::cpu0.data 111125 # number of ReadExReq accesses(hits+misses) 524system.l2c.ReadExReq_accesses::cpu1.data 137867 # number of ReadExReq accesses(hits+misses) 525system.l2c.ReadExReq_accesses::total 248992 # number of ReadExReq accesses(hits+misses) 526system.l2c.demand_accesses::cpu0.dtb.walker 2998 # number of demand (read+write) accesses 527system.l2c.demand_accesses::cpu0.itb.walker 1659 # number of demand (read+write) accesses 528system.l2c.demand_accesses::cpu0.inst 354952 # number of demand (read+write) accesses 529system.l2c.demand_accesses::cpu0.data 288875 # number of demand (read+write) accesses 530system.l2c.demand_accesses::cpu1.dtb.walker 6375 # number of demand (read+write) accesses 531system.l2c.demand_accesses::cpu1.itb.walker 1905 # number of demand (read+write) accesses 532system.l2c.demand_accesses::cpu1.inst 540562 # number of demand (read+write) accesses 533system.l2c.demand_accesses::cpu1.data 322356 # number of demand (read+write) accesses 534system.l2c.demand_accesses::total 1519682 # number of demand (read+write) accesses 535system.l2c.overall_accesses::cpu0.dtb.walker 2998 # number of overall (read+write) accesses 536system.l2c.overall_accesses::cpu0.itb.walker 1659 # number of overall (read+write) accesses 537system.l2c.overall_accesses::cpu0.inst 354952 # number of overall (read+write) accesses 538system.l2c.overall_accesses::cpu0.data 288875 # number of overall (read+write) accesses 539system.l2c.overall_accesses::cpu1.dtb.walker 6375 # number of overall (read+write) accesses 540system.l2c.overall_accesses::cpu1.itb.walker 1905 # number of overall (read+write) accesses 541system.l2c.overall_accesses::cpu1.inst 540562 # number of overall (read+write) accesses 542system.l2c.overall_accesses::cpu1.data 322356 # number of overall (read+write) accesses 543system.l2c.overall_accesses::total 1519682 # number of overall (read+write) accesses 544system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for ReadReq accesses 545system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001808 # miss rate for ReadReq accesses 546system.l2c.ReadReq_miss_rate::cpu0.inst 0.015495 # miss rate for ReadReq accesses 547system.l2c.ReadReq_miss_rate::cpu0.data 0.044023 # miss rate for ReadReq accesses 548system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for ReadReq accesses 549system.l2c.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses 550system.l2c.ReadReq_miss_rate::cpu1.data 0.019795 # miss rate for ReadReq accesses 551system.l2c.ReadReq_miss_rate::total 0.017518 # miss rate for ReadReq accesses 552system.l2c.UpgradeReq_miss_rate::cpu0.data 0.782527 # miss rate for UpgradeReq accesses 553system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890465 # miss rate for UpgradeReq accesses 554system.l2c.UpgradeReq_miss_rate::total 0.839488 # miss rate for UpgradeReq accesses |
| 878system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721871 # miss rate for SCUpgradeReq accesses | 555system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721871 # miss rate for SCUpgradeReq accesses |
| 879system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.825784 # miss rate for SCUpgradeReq accesses 880system.l2c.SCUpgradeReq_miss_rate::total 0.765568 # miss rate for SCUpgradeReq accesses 881system.l2c.ReadExReq_miss_rate::cpu0.data 0.542806 # miss rate for ReadExReq accesses 882system.l2c.ReadExReq_miss_rate::cpu1.data 0.578817 # miss rate for ReadExReq accesses 883system.l2c.ReadExReq_miss_rate::total 0.560897 # miss rate for ReadExReq accesses 884system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for demand accesses 885system.l2c.demand_miss_rate::cpu0.itb.walker 0.001154 # miss rate for demand accesses 886system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses 887system.l2c.demand_miss_rate::cpu0.data 0.222443 # miss rate for demand accesses 888system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for demand accesses 889system.l2c.demand_miss_rate::cpu1.itb.walker 0.000518 # miss rate for demand accesses 890system.l2c.demand_miss_rate::cpu1.inst 0.010776 # miss rate for demand accesses 891system.l2c.demand_miss_rate::cpu1.data 0.279652 # miss rate for demand accesses 892system.l2c.demand_miss_rate::total 0.106743 # miss rate for demand accesses 893system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for overall accesses 894system.l2c.overall_miss_rate::cpu0.itb.walker 0.001154 # miss rate for overall accesses 895system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses 896system.l2c.overall_miss_rate::cpu0.data 0.222443 # miss rate for overall accesses 897system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for overall accesses 898system.l2c.overall_miss_rate::cpu1.itb.walker 0.000518 # miss rate for overall accesses 899system.l2c.overall_miss_rate::cpu1.inst 0.010776 # miss rate for overall accesses 900system.l2c.overall_miss_rate::cpu1.data 0.279652 # miss rate for overall accesses 901system.l2c.overall_miss_rate::total 0.106743 # miss rate for overall accesses | 556system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.845588 # miss rate for SCUpgradeReq accesses 557system.l2c.SCUpgradeReq_miss_rate::total 0.772285 # miss rate for SCUpgradeReq accesses 558system.l2c.ReadExReq_miss_rate::cpu0.data 0.574929 # miss rate for ReadExReq accesses 559system.l2c.ReadExReq_miss_rate::cpu1.data 0.547303 # miss rate for ReadExReq accesses 560system.l2c.ReadExReq_miss_rate::total 0.559632 # miss rate for ReadExReq accesses 561system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for demand accesses 562system.l2c.demand_miss_rate::cpu0.itb.walker 0.001808 # miss rate for demand accesses 563system.l2c.demand_miss_rate::cpu0.inst 0.015495 # miss rate for demand accesses 564system.l2c.demand_miss_rate::cpu0.data 0.248253 # miss rate for demand accesses 565system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for demand accesses 566system.l2c.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses 567system.l2c.demand_miss_rate::cpu1.data 0.245403 # miss rate for demand accesses 568system.l2c.demand_miss_rate::total 0.106341 # miss rate for demand accesses 569system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for overall accesses 570system.l2c.overall_miss_rate::cpu0.itb.walker 0.001808 # miss rate for overall accesses 571system.l2c.overall_miss_rate::cpu0.inst 0.015495 # miss rate for overall accesses 572system.l2c.overall_miss_rate::cpu0.data 0.248253 # miss rate for overall accesses 573system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for overall accesses 574system.l2c.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses 575system.l2c.overall_miss_rate::cpu1.data 0.245403 # miss rate for overall accesses 576system.l2c.overall_miss_rate::total 0.106341 # miss rate for overall accesses |
| 902system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency | 577system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency |
| 903system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 904system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70409.760991 # average ReadReq miss latency 905system.l2c.ReadReq_avg_miss_latency::cpu0.data 74927.105773 # average ReadReq miss latency 906system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86750 # average ReadReq miss latency 907system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 908system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72109.909109 # average ReadReq miss latency 909system.l2c.ReadReq_avg_miss_latency::cpu1.data 78512.645108 # average ReadReq miss latency 910system.l2c.ReadReq_avg_miss_latency::total 73706.626650 # average ReadReq miss latency 911system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2689.765055 # average UpgradeReq miss latency 912system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3297.684239 # average UpgradeReq miss latency 913system.l2c.UpgradeReq_avg_miss_latency::total 2951.052441 # average UpgradeReq miss latency 914system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3187.257443 # average SCUpgradeReq miss latency 915system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5341.542194 # average SCUpgradeReq miss latency 916system.l2c.SCUpgradeReq_avg_miss_latency::total 4164.416268 # average SCUpgradeReq miss latency 917system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.271509 # average ReadExReq miss latency 918system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75284.142552 # average ReadExReq miss latency 919system.l2c.ReadExReq_avg_miss_latency::total 71422.414168 # average ReadExReq miss latency | 578system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74833.333333 # average ReadReq miss latency 579system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70025.227273 # average ReadReq miss latency 580system.l2c.ReadReq_avg_miss_latency::cpu0.data 75106.102109 # average ReadReq miss latency 581system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83625 # average ReadReq miss latency 582system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72307.156398 # average ReadReq miss latency 583system.l2c.ReadReq_avg_miss_latency::cpu1.data 77672.029025 # average ReadReq miss latency 584system.l2c.ReadReq_avg_miss_latency::total 73607.973899 # average ReadReq miss latency 585system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2942.052491 # average UpgradeReq miss latency 586system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2924.329003 # average UpgradeReq miss latency 587system.l2c.UpgradeReq_avg_miss_latency::total 2932.131496 # average UpgradeReq miss latency 588system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3224.907180 # average SCUpgradeReq miss latency 589system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5049.782609 # average SCUpgradeReq miss latency 590system.l2c.SCUpgradeReq_avg_miss_latency::total 4039.109602 # average SCUpgradeReq miss latency 591system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67163.875753 # average ReadExReq miss latency 592system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73930.988271 # average ReadExReq miss latency 593system.l2c.ReadExReq_avg_miss_latency::total 70828.278060 # average ReadExReq miss latency |
| 920system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency | 594system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency |
| 921system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 922system.l2c.demand_avg_miss_latency::cpu0.inst 70409.760991 # average overall miss latency 923system.l2c.demand_avg_miss_latency::cpu0.data 68065.239755 # average overall miss latency 924system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency 925system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 926system.l2c.demand_avg_miss_latency::cpu1.inst 72109.909109 # average overall miss latency 927system.l2c.demand_avg_miss_latency::cpu1.data 75437.682725 # average overall miss latency 928system.l2c.demand_avg_miss_latency::total 71736.302543 # average overall miss latency | 595system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency 596system.l2c.demand_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency 597system.l2c.demand_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency 598system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency 599system.l2c.demand_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency 600system.l2c.demand_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency 601system.l2c.demand_avg_miss_latency::total 71211.164804 # average overall miss latency |
| 929system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency | 602system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency |
| 930system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 931system.l2c.overall_avg_miss_latency::cpu0.inst 70409.760991 # average overall miss latency 932system.l2c.overall_avg_miss_latency::cpu0.data 68065.239755 # average overall miss latency 933system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency 934system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 935system.l2c.overall_avg_miss_latency::cpu1.inst 72109.909109 # average overall miss latency 936system.l2c.overall_avg_miss_latency::cpu1.data 75437.682725 # average overall miss latency 937system.l2c.overall_avg_miss_latency::total 71736.302543 # average overall miss latency | 603system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency 604system.l2c.overall_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency 605system.l2c.overall_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency 606system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency 607system.l2c.overall_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency 608system.l2c.overall_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency 609system.l2c.overall_avg_miss_latency::total 71211.164804 # average overall miss latency |
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number of ReadReq MSHR uncacheable cycles 693system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11221595994 # number of ReadReq MSHR uncacheable cycles 694system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5508250 # number of ReadReq MSHR uncacheable cycles 695system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155529668246 # number of ReadReq MSHR uncacheable cycles 696system.l2c.ReadReq_mshr_uncacheable_latency::total 167109098490 # number of ReadReq MSHR uncacheable cycles 697system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1041121994 # number of WriteReq MSHR uncacheable cycles 698system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15728911223 # number of WriteReq MSHR uncacheable cycles 699system.l2c.WriteReq_mshr_uncacheable_latency::total 16770033217 # number of WriteReq MSHR uncacheable cycles 700system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 352326000 # number of overall MSHR uncacheable cycles 701system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12262717988 # number of overall MSHR uncacheable cycles 702system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5508250 # number of overall MSHR uncacheable cycles 703system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171258579469 # number of overall MSHR uncacheable cycles 704system.l2c.overall_mshr_uncacheable_latency::total 183879131707 # number of overall MSHR uncacheable cycles 705system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for ReadReq accesses 706system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for ReadReq accesses 707system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for ReadReq accesses 708system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044023 # mshr miss rate for ReadReq accesses 709system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for ReadReq accesses 710system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for ReadReq accesses 711system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019795 # mshr miss rate for ReadReq accesses 712system.l2c.ReadReq_mshr_miss_rate::total 0.017517 # mshr miss rate for ReadReq accesses 713system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782527 # mshr miss rate for UpgradeReq accesses 714system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890465 # mshr miss rate for UpgradeReq accesses 715system.l2c.UpgradeReq_mshr_miss_rate::total 0.839488 # mshr miss rate for UpgradeReq accesses |
| 1051system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721871 # mshr miss rate for SCUpgradeReq accesses | 716system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721871 # mshr miss rate for SCUpgradeReq accesses |
| 1052system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825784 # mshr miss rate for SCUpgradeReq accesses 1053system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765568 # mshr miss rate for SCUpgradeReq accesses 1054system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542806 # mshr miss rate for ReadExReq accesses 1055system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578817 # mshr miss rate for ReadExReq accesses 1056system.l2c.ReadExReq_mshr_miss_rate::total 0.560897 # mshr miss rate for ReadExReq accesses 1057system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for demand accesses 1058system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for demand accesses 1059system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses 1060system.l2c.demand_mshr_miss_rate::cpu0.data 0.222443 # mshr miss rate for demand accesses 1061system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for demand accesses 1062system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for demand accesses 1063system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses 1064system.l2c.demand_mshr_miss_rate::cpu1.data 0.279652 # mshr miss rate for demand accesses 1065system.l2c.demand_mshr_miss_rate::total 0.106742 # mshr miss rate for demand accesses 1066system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for overall accesses 1067system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for overall accesses 1068system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses 1069system.l2c.overall_mshr_miss_rate::cpu0.data 0.222443 # mshr miss rate for overall accesses 1070system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for overall accesses 1071system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for overall accesses 1072system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses 1073system.l2c.overall_mshr_miss_rate::cpu1.data 0.279652 # mshr miss rate for overall accesses 1074system.l2c.overall_mshr_miss_rate::total 0.106742 # mshr miss rate for overall accesses | 717system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845588 # mshr miss rate for SCUpgradeReq accesses 718system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.772285 # mshr miss rate for SCUpgradeReq accesses 719system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.574929 # mshr miss rate for ReadExReq accesses 720system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.547303 # mshr miss rate for ReadExReq accesses 721system.l2c.ReadExReq_mshr_miss_rate::total 0.559632 # mshr miss rate for ReadExReq accesses 722system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for demand accesses 723system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for demand accesses 724system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for demand accesses 725system.l2c.demand_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for demand accesses 726system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for demand accesses 727system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for demand accesses 728system.l2c.demand_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for demand accesses 729system.l2c.demand_mshr_miss_rate::total 0.106340 # mshr miss rate for demand accesses 730system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for overall accesses 731system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for overall accesses 732system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for overall accesses 733system.l2c.overall_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for overall accesses 734system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for overall accesses 735system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for overall accesses 736system.l2c.overall_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for overall accesses 737system.l2c.overall_mshr_miss_rate::total 0.106340 # mshr miss rate for overall accesses |
| 1075system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency 1076system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency | 738system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency 739system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
| 1077system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average ReadReq mshr miss latency 1078system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62451.573722 # average ReadReq mshr miss latency 1079system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average ReadReq mshr miss latency 1080system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 1081system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average ReadReq mshr miss latency 1082system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66082.158651 # average ReadReq mshr miss latency 1083system.l2c.ReadReq_avg_mshr_miss_latency::total 61144.891040 # average ReadReq mshr miss latency 1084system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.632118 # average UpgradeReq mshr miss latency 1085system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.302446 # average UpgradeReq mshr miss latency 1086system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.218290 # average UpgradeReq mshr miss latency 1087system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10017.630473 # average SCUpgradeReq mshr miss latency 1088system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.364979 # average SCUpgradeReq mshr miss latency 1089system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.045933 # average SCUpgradeReq mshr miss latency 1090system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54359.154437 # average ReadExReq mshr miss latency 1091system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62553.446065 # average ReadExReq mshr miss latency 1092system.l2c.ReadExReq_avg_mshr_miss_latency::total 58607.238626 # average ReadExReq mshr miss latency | 740system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average ReadReq mshr miss latency 741system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898 # average ReadReq mshr miss latency 742system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency 743system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average ReadReq mshr miss latency 744system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117 # average ReadReq mshr miss latency 745system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425 # average ReadReq mshr miss latency 746system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270 # average UpgradeReq mshr miss latency 747system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207 # average UpgradeReq mshr miss latency 748system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255 # average UpgradeReq mshr miss latency 749system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284 # average SCUpgradeReq mshr miss latency 750system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261 # average SCUpgradeReq mshr miss latency 751system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403 # average SCUpgradeReq mshr miss latency 752system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803 # average ReadExReq mshr miss latency 753system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133 # average ReadExReq mshr miss latency 754system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616 # average ReadExReq mshr miss latency |
| 1093system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 1094system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 755system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 756system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 1095system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency 1096system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency 1097system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency 1098system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1099system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency 1100system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency 1101system.l2c.demand_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency | 757system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency 758system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency 759system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency 760system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency 761system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency 762system.l2c.demand_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency |
| 1102system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 1103system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency | 763system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 764system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
| 1104system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency 1105system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency 1106system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency 1107system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1108system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency 1109system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency 1110system.l2c.overall_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency | 765system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency 766system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency 767system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency 768system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency 769system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency 770system.l2c.overall_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency |
| 1111system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1112system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1113system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1114system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1115system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1116system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1117system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1118system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 1123system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1124system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1125system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1126system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1127system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1128system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1129system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1130system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 771system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 772system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 773system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 774system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 775system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 776system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 777system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 778system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency --- 4 unchanged lines hidden (view full) --- 783system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 784system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 785system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 786system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 787system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 788system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 789system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 790system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 1131system.toL2Bus.throughput 119544694 # Throughput (bytes/s) 1132system.toL2Bus.trans_dist::ReadReq 2535779 # Transaction distribution 1133system.toL2Bus.trans_dist::ReadResp 2535779 # Transaction distribution 1134system.toL2Bus.trans_dist::WriteReq 767577 # Transaction distribution 1135system.toL2Bus.trans_dist::WriteResp 767577 # Transaction distribution 1136system.toL2Bus.trans_dist::Writeback 570959 # Transaction distribution 1137system.toL2Bus.trans_dist::UpgradeReq 30837 # Transaction distribution 1138system.toL2Bus.trans_dist::SCUpgradeReq 17592 # Transaction distribution 1139system.toL2Bus.trans_dist::UpgradeResp 48429 # Transaction distribution 1140system.toL2Bus.trans_dist::ReadExReq 260947 # Transaction distribution 1141system.toL2Bus.trans_dist::ReadExResp 260947 # Transaction distribution 1142system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864602 # Packet count per connected master and slave (bytes) 1143system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1227966 # Packet count per connected master and slave (bytes) 1144system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6129 # Packet count per connected master and slave (bytes) 1145system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12680 # Packet count per connected master and slave (bytes) 1146system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940064 # Packet count per connected master and slave (bytes) 1147system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600791 # Packet count per connected master and slave (bytes) 1148system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6258 # Packet count per connected master and slave (bytes) 1149system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15477 # Packet count per connected master and slave (bytes) 1150system.toL2Bus.pkt_count::total 7673967 # Packet count per connected master and slave (bytes) 1151system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27250848 # Cumulative packet size per connected master and slave (bytes) 1152system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41432384 # Cumulative packet size per connected master and slave (bytes) 1153system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6932 # Cumulative packet size per connected master and slave (bytes) 1154system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) 1155system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30058932 # Cumulative packet size per connected master and slave (bytes) 1156system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39583066 # Cumulative packet size per connected master and slave (bytes) 1157system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7728 # Cumulative packet size per connected master and slave (bytes) 1158system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22216 # Cumulative packet size per connected master and slave (bytes) 1159system.toL2Bus.tot_pkt_size::total 138377350 # Cumulative packet size per connected master and slave (bytes) 1160system.toL2Bus.data_through_bus 138377350 # Total data (bytes) 1161system.toL2Bus.snoop_data_through_bus 4615184 # Total snoop data (bytes) 1162system.toL2Bus.reqLayer0.occupancy 4759626187 # Layer occupancy (ticks) | 791system.toL2Bus.throughput 119642613 # Throughput (bytes/s) 792system.toL2Bus.trans_dist::ReadReq 2536412 # Transaction distribution 793system.toL2Bus.trans_dist::ReadResp 2536412 # Transaction distribution 794system.toL2Bus.trans_dist::WriteReq 767585 # Transaction distribution 795system.toL2Bus.trans_dist::WriteResp 767585 # Transaction distribution 796system.toL2Bus.trans_dist::Writeback 572475 # Transaction distribution 797system.toL2Bus.trans_dist::UpgradeReq 30937 # Transaction distribution 798system.toL2Bus.trans_dist::SCUpgradeReq 17621 # Transaction distribution 799system.toL2Bus.trans_dist::UpgradeResp 48558 # Transaction distribution 800system.toL2Bus.trans_dist::ReadExReq 260776 # Transaction distribution 801system.toL2Bus.trans_dist::ReadExResp 260776 # Transaction distribution 802system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 723469 # Packet count per connected master and slave (bytes) 803system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1059051 # Packet count per connected master and slave (bytes) 804system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4339 # Packet count per connected master and slave (bytes) 805system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7907 # Packet count per connected master and slave (bytes) 806system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1082141 # Packet count per connected master and slave (bytes) 807system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4772543 # Packet count per connected master and slave (bytes) 808system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7929 # Packet count per connected master and slave (bytes) 809system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 20256 # Packet count per connected master and slave (bytes) 810system.toL2Bus.pkt_count::total 7677635 # Packet count per connected master and slave (bytes) 811system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 22743520 # Cumulative packet size per connected master and slave (bytes) 812system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35146882 # Cumulative packet size per connected master and slave (bytes) 813system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6636 # Cumulative packet size per connected master and slave (bytes) 814system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 11992 # Cumulative packet size per connected master and slave (bytes) 815system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34596404 # Cumulative packet size per connected master and slave (bytes) 816system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 46050592 # Cumulative packet size per connected master and slave (bytes) 817system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7620 # Cumulative packet size per connected master and slave (bytes) 818system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 25500 # Cumulative packet size per connected master and slave (bytes) 819system.toL2Bus.tot_pkt_size::total 138589146 # Cumulative packet size per connected master and slave (bytes) 820system.toL2Bus.data_through_bus 138589146 # Total data (bytes) 821system.toL2Bus.snoop_data_through_bus 4530356 # Total snoop data (bytes) 822system.toL2Bus.reqLayer0.occupancy 4766758175 # Layer occupancy (ticks) |
| 1163system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) | 823system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) |
| 1164system.toL2Bus.respLayer0.occupancy 1926082966 # Layer occupancy (ticks) 1165system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1166system.toL2Bus.respLayer1.occupancy 1756498781 # Layer occupancy (ticks) | 824system.toL2Bus.respLayer0.occupancy 1607753214 # Layer occupancy (ticks) 825system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 826system.toL2Bus.respLayer1.occupancy 1517597206 # Layer occupancy (ticks) |
| 1167system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 827system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1168system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) | 828system.toL2Bus.respLayer2.occupancy 2680000 # Layer occupancy (ticks) |
| 1169system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 829system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1170system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) | 830system.toL2Bus.respLayer3.occupancy 4909499 # Layer occupancy (ticks) |
| 1171system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 831system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1172system.toL2Bus.respLayer6.occupancy 2116921475 # Layer occupancy (ticks) | 832system.toL2Bus.respLayer6.occupancy 2437223968 # Layer occupancy (ticks) |
| 1173system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) | 833system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) |
| 1174system.toL2Bus.respLayer7.occupancy 2926499865 # Layer occupancy (ticks) 1175system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1176system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) | 834system.toL2Bus.respLayer7.occupancy 3163938724 # Layer occupancy (ticks) 835system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) 836system.toL2Bus.respLayer8.occupancy 6024000 # Layer occupancy (ticks) |
| 1177system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) | 837system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) |
| 1178system.toL2Bus.respLayer9.occupancy 9923499 # Layer occupancy (ticks) | 838system.toL2Bus.respLayer9.occupancy 13881500 # Layer occupancy (ticks) |
| 1179system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) | 839system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) |
| 1180system.iobus.throughput 45391348 # Throughput (bytes/s) 1181system.iobus.trans_dist::ReadReq 7671431 # Transaction distribution 1182system.iobus.trans_dist::ReadResp 7671431 # Transaction distribution 1183system.iobus.trans_dist::WriteReq 7963 # Transaction distribution 1184system.iobus.trans_dist::WriteResp 7963 # Transaction distribution 1185system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) 1186system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8056 # Packet count per connected master and slave (bytes) | 840system.iobus.throughput 45388263 # Throughput (bytes/s) 841system.iobus.trans_dist::ReadReq 7671442 # Transaction distribution 842system.iobus.trans_dist::ReadResp 7671442 # Transaction distribution 843system.iobus.trans_dist::WriteReq 7967 # Transaction distribution 844system.iobus.trans_dist::WriteResp 7967 # Transaction distribution 845system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) 846system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8070 # Packet count per connected master and slave (bytes) |
| 1187system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 1200system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1202system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1204system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1205system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1206system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 847system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 848system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) 849system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 850system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 851system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) 852system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 853system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 854system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 860system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 861system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 862system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 863system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 864system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 865system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 866system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 867system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 1208system.iobus.pkt_count_system.bridge.master::total 2382660 # Packet count per connected master and slave (bytes) | 868system.iobus.pkt_count_system.bridge.master::total 2382690 # Packet count per connected master and slave (bytes) |
| 1209system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) | 869system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 870system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) |
| 1211system.iobus.pkt_count::total 15358788 # Packet count per connected master and slave (bytes) 1212system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16112 # Cumulative packet size per connected master and slave (bytes) | 871system.iobus.pkt_count::total 15358818 # Packet count per connected master and slave (bytes) 872system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) 873system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16140 # Cumulative packet size per connected master and slave (bytes) |
| 1214system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 1227system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 874system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 875system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) 876system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 877system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 878system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) 879system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 880system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 881system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 887system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 888system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 889system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 890system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 891system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 892system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 893system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 894system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 1235system.iobus.tot_pkt_size_system.bridge.master::total 2390026 # Cumulative packet size per connected master and slave (bytes) | 895system.iobus.tot_pkt_size_system.bridge.master::total 2390070 # Cumulative packet size per connected master and slave (bytes) |
| 1236system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) | 896system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 897system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) |
| 1238system.iobus.tot_pkt_size::total 54294538 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.data_through_bus 54294538 # Total data (bytes) 1240system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) | 898system.iobus.tot_pkt_size::total 54294582 # Cumulative packet size per connected master and slave (bytes) 899system.iobus.data_through_bus 54294582 # Total data (bytes) 900system.iobus.reqLayer0.occupancy 21430000 # Layer occupancy (ticks) |
| 1241system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 901system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1242system.iobus.reqLayer1.occupancy 4034000 # Layer occupancy (ticks) | 902system.iobus.reqLayer1.occupancy 4041000 # Layer occupancy (ticks) |
| 1243system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1244system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1245system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1246system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) 1247system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1248system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1249system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1250system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) --- 29 unchanged lines hidden (view full) --- 1280system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1281system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1282system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1283system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1284system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1285system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1286system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1287system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) | 903system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 904system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 905system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 906system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) 907system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 908system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 909system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 910system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) --- 29 unchanged lines hidden (view full) --- 940system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 941system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 942system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 943system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 944system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 945system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 946system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 947system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) |
| 1288system.iobus.respLayer0.occupancy 2374697000 # Layer occupancy (ticks) | 948system.iobus.respLayer0.occupancy 2374723000 # Layer occupancy (ticks) |
| 1289system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) | 949system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1290system.iobus.respLayer1.occupancy 17777962501 # Layer occupancy (ticks) 1291system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) | 950system.iobus.respLayer1.occupancy 16195242500 # Layer occupancy (ticks) 951system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) |
| 1292system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1293system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1294system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1295system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1296system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1297system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1298system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1299system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 1307system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1308system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1309system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1310system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1311system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1312system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1313system.cpu0.dtb.inst_hits 0 # ITB inst hits 1314system.cpu0.dtb.inst_misses 0 # ITB inst misses | 952system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 953system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 954system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 955system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 956system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 957system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 958system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 959system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 967system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 968system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 969system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 970system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 971system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 972system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 973system.cpu0.dtb.inst_hits 0 # ITB inst hits 974system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 1315system.cpu0.dtb.read_hits 7070497 # DTB read hits 1316system.cpu0.dtb.read_misses 3747 # DTB read misses 1317system.cpu0.dtb.write_hits 5655659 # DTB write hits 1318system.cpu0.dtb.write_misses 806 # DTB write misses | 975system.cpu0.dtb.read_hits 5879584 # DTB read hits 976system.cpu0.dtb.read_misses 2138 # DTB read misses 977system.cpu0.dtb.write_hits 4838515 # DTB write hits 978system.cpu0.dtb.write_misses 406 # DTB write misses |
| 1319system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1320system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1321system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1322system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 979system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 980system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 981system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 982system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1323system.cpu0.dtb.flush_entries 1708 # Number of entries that have been flushed from TLB | 983system.cpu0.dtb.flush_entries 1387 # Number of entries that have been flushed from TLB |
| 1324system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 984system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1325system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch | 985system.cpu0.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch |
| 1326system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 986system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1327system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1328system.cpu0.dtb.read_accesses 7074244 # DTB read accesses 1329system.cpu0.dtb.write_accesses 5656465 # DTB write accesses | 987system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions 988system.cpu0.dtb.read_accesses 5881722 # DTB read accesses 989system.cpu0.dtb.write_accesses 4838921 # DTB write accesses |
| 1330system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 990system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 1331system.cpu0.dtb.hits 12726156 # DTB hits 1332system.cpu0.dtb.misses 4553 # DTB misses 1333system.cpu0.dtb.accesses 12730709 # DTB accesses | 991system.cpu0.dtb.hits 10718099 # DTB hits 992system.cpu0.dtb.misses 2544 # DTB misses 993system.cpu0.dtb.accesses 10720643 # DTB accesses |
| 1334system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1335system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1336system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1337system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1338system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1339system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1340system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1341system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1347system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1348system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1349system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1350system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1351system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1352system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1353system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1354system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 994system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 995system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 996system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 997system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 998system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 999system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1000system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1001system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1007system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1008system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1009system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1010system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1011system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1012system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1013system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1014system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1355system.cpu0.itb.inst_hits 29571351 # ITB inst hits 1356system.cpu0.itb.inst_misses 2205 # ITB inst misses | 1015system.cpu0.itb.inst_hits 24773464 # ITB inst hits 1016system.cpu0.itb.inst_misses 1350 # ITB inst misses |
| 1357system.cpu0.itb.read_hits 0 # DTB read hits 1358system.cpu0.itb.read_misses 0 # DTB read misses 1359system.cpu0.itb.write_hits 0 # DTB write hits 1360system.cpu0.itb.write_misses 0 # DTB write misses 1361system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1362system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1363system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1364system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1017system.cpu0.itb.read_hits 0 # DTB read hits 1018system.cpu0.itb.read_misses 0 # DTB read misses 1019system.cpu0.itb.write_hits 0 # DTB write hits 1020system.cpu0.itb.write_misses 0 # DTB write misses 1021system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1022system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1023system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1024system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1365system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB | 1025system.cpu0.itb.flush_entries 963 # Number of entries that have been flushed from TLB |
| 1366system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1367system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1368system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1369system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1370system.cpu0.itb.read_accesses 0 # DTB read accesses 1371system.cpu0.itb.write_accesses 0 # DTB write accesses | 1026system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1027system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1028system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1029system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1030system.cpu0.itb.read_accesses 0 # DTB read accesses 1031system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 1372system.cpu0.itb.inst_accesses 29573556 # ITB inst accesses 1373system.cpu0.itb.hits 29571351 # DTB hits 1374system.cpu0.itb.misses 2205 # DTB misses 1375system.cpu0.itb.accesses 29573556 # DTB accesses 1376system.cpu0.numCycles 2392285746 # number of cpu cycles simulated | 1032system.cpu0.itb.inst_accesses 24774814 # ITB inst accesses 1033system.cpu0.itb.hits 24773464 # DTB hits 1034system.cpu0.itb.misses 1350 # DTB misses 1035system.cpu0.itb.accesses 24774814 # DTB accesses 1036system.cpu0.numCycles 2391604989 # number of cpu cycles simulated |
| 1377system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1378system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 1037system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1038system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1379system.cpu0.committedInsts 28873226 # Number of instructions committed 1380system.cpu0.committedOps 37212709 # Number of ops (including micro ops) committed 1381system.cpu0.num_int_alu_accesses 33137047 # Number of integer alu accesses 1382system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 1383system.cpu0.num_func_calls 1242091 # number of times a function call or return occured 1384system.cpu0.num_conditional_control_insts 4373605 # number of instructions that are conditional controls 1385system.cpu0.num_int_insts 33137047 # number of integer instructions 1386system.cpu0.num_fp_insts 3860 # number of float instructions 1387system.cpu0.num_int_register_reads 192300691 # number of times the integer registers were read 1388system.cpu0.num_int_register_writes 36265278 # number of times the integer registers were written 1389system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1390system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1391system.cpu0.num_mem_refs 13394015 # number of memory refs 1392system.cpu0.num_load_insts 7407936 # Number of load instructions 1393system.cpu0.num_store_insts 5986079 # Number of store instructions 1394system.cpu0.num_idle_cycles 2246427166.466122 # Number of idle cycles 1395system.cpu0.num_busy_cycles 145858579.533878 # Number of busy cycles 1396system.cpu0.not_idle_fraction 0.060970 # Percentage of non-idle cycles 1397system.cpu0.idle_fraction 0.939030 # Percentage of idle cycles 1398system.cpu0.Branches 5601726 # Number of branches fetched | 1039system.cpu0.committedInsts 24375312 # Number of instructions committed 1040system.cpu0.committedOps 31460856 # Number of ops (including micro ops) committed 1041system.cpu0.num_int_alu_accesses 28085533 # Number of integer alu accesses 1042system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses 1043system.cpu0.num_func_calls 1070699 # number of times a function call or return occured 1044system.cpu0.num_conditional_control_insts 3751745 # number of instructions that are conditional controls 1045system.cpu0.num_int_insts 28085533 # number of integer instructions 1046system.cpu0.num_fp_insts 4364 # number of float instructions 1047system.cpu0.num_int_register_reads 162520351 # number of times the integer registers were read 1048system.cpu0.num_int_register_writes 30535592 # number of times the integer registers were written 1049system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read 1050system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written 1051system.cpu0.num_mem_refs 11309766 # number of memory refs 1052system.cpu0.num_load_insts 6158982 # Number of load instructions 1053system.cpu0.num_store_insts 5150784 # Number of store instructions 1054system.cpu0.num_idle_cycles 2265857607.135565 # Number of idle cycles 1055system.cpu0.num_busy_cycles 125747381.864435 # Number of busy cycles 1056system.cpu0.not_idle_fraction 0.052579 # Percentage of non-idle cycles 1057system.cpu0.idle_fraction 0.947421 # Percentage of idle cycles 1058system.cpu0.Branches 4778581 # Number of branches fetched |
| 1399system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 1059system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 1400system.cpu0.kern.inst.quiesce 46915 # number of quiesce instructions executed 1401system.cpu0.icache.tags.replacements 425414 # number of replacements 1402system.cpu0.icache.tags.tagsinuse 509.356883 # Cycle average of tags in use 1403system.cpu0.icache.tags.total_refs 29145407 # Total number of references to valid blocks. 1404system.cpu0.icache.tags.sampled_refs 425926 # Sample count of references to valid blocks. 1405system.cpu0.icache.tags.avg_refs 68.428335 # Average number of references to valid blocks. 1406system.cpu0.icache.tags.warmup_cycle 76234819000 # Cycle when the warmup percentage was hit. 1407system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.356883 # Average occupied blocks per requestor 1408system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994838 # Average percentage of cache occupancy 1409system.cpu0.icache.tags.occ_percent::total 0.994838 # Average percentage of cache occupancy | 1060system.cpu0.kern.inst.quiesce 39137 # number of quiesce instructions executed 1061system.cpu0.icache.tags.replacements 354708 # number of replacements 1062system.cpu0.icache.tags.tagsinuse 509.352361 # Cycle average of tags in use 1063system.cpu0.icache.tags.total_refs 24418226 # Total number of references to valid blocks. 1064system.cpu0.icache.tags.sampled_refs 355220 # Sample count of references to valid blocks. 1065system.cpu0.icache.tags.avg_refs 68.741135 # Average number of references to valid blocks. 1066system.cpu0.icache.tags.warmup_cycle 76254991000 # Cycle when the warmup percentage was hit. 1067system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352361 # Average occupied blocks per requestor 1068system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994829 # Average percentage of cache occupancy 1069system.cpu0.icache.tags.occ_percent::total 0.994829 # Average percentage of cache occupancy |
| 1410system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1070system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1411system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 1412system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 1413system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id 1414system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id | 1071system.cpu0.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id 1072system.cpu0.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 1073system.cpu0.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id |
| 1415system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1074system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1416system.cpu0.icache.tags.tag_accesses 29997261 # Number of tag accesses 1417system.cpu0.icache.tags.data_accesses 29997261 # Number of data accesses 1418system.cpu0.icache.ReadReq_hits::cpu0.inst 29145407 # number of ReadReq hits 1419system.cpu0.icache.ReadReq_hits::total 29145407 # number of ReadReq hits 1420system.cpu0.icache.demand_hits::cpu0.inst 29145407 # number of demand (read+write) hits 1421system.cpu0.icache.demand_hits::total 29145407 # number of demand (read+write) hits 1422system.cpu0.icache.overall_hits::cpu0.inst 29145407 # number of overall hits 1423system.cpu0.icache.overall_hits::total 29145407 # number of overall hits 1424system.cpu0.icache.ReadReq_misses::cpu0.inst 425927 # number of ReadReq misses 1425system.cpu0.icache.ReadReq_misses::total 425927 # number of ReadReq misses 1426system.cpu0.icache.demand_misses::cpu0.inst 425927 # number of demand (read+write) misses 1427system.cpu0.icache.demand_misses::total 425927 # number of demand (read+write) misses 1428system.cpu0.icache.overall_misses::cpu0.inst 425927 # number of overall misses 1429system.cpu0.icache.overall_misses::total 425927 # number of overall misses 1430system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899388216 # number of ReadReq miss cycles 1431system.cpu0.icache.ReadReq_miss_latency::total 5899388216 # number of ReadReq miss cycles 1432system.cpu0.icache.demand_miss_latency::cpu0.inst 5899388216 # number of demand (read+write) miss cycles 1433system.cpu0.icache.demand_miss_latency::total 5899388216 # number of demand (read+write) miss cycles 1434system.cpu0.icache.overall_miss_latency::cpu0.inst 5899388216 # number of overall miss cycles 1435system.cpu0.icache.overall_miss_latency::total 5899388216 # number of overall miss cycles 1436system.cpu0.icache.ReadReq_accesses::cpu0.inst 29571334 # number of ReadReq accesses(hits+misses) 1437system.cpu0.icache.ReadReq_accesses::total 29571334 # number of ReadReq accesses(hits+misses) 1438system.cpu0.icache.demand_accesses::cpu0.inst 29571334 # number of demand (read+write) accesses 1439system.cpu0.icache.demand_accesses::total 29571334 # number of demand (read+write) accesses 1440system.cpu0.icache.overall_accesses::cpu0.inst 29571334 # number of overall (read+write) accesses 1441system.cpu0.icache.overall_accesses::total 29571334 # number of overall (read+write) accesses 1442system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014403 # miss rate for ReadReq accesses 1443system.cpu0.icache.ReadReq_miss_rate::total 0.014403 # miss rate for ReadReq accesses 1444system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014403 # miss rate for demand accesses 1445system.cpu0.icache.demand_miss_rate::total 0.014403 # miss rate for demand accesses 1446system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014403 # miss rate for overall accesses 1447system.cpu0.icache.overall_miss_rate::total 0.014403 # miss rate for overall accesses 1448system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13850.702623 # average ReadReq miss latency 1449system.cpu0.icache.ReadReq_avg_miss_latency::total 13850.702623 # average ReadReq miss latency 1450system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency 1451system.cpu0.icache.demand_avg_miss_latency::total 13850.702623 # average overall miss latency 1452system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency 1453system.cpu0.icache.overall_avg_miss_latency::total 13850.702623 # average overall miss latency | 1075system.cpu0.icache.tags.tag_accesses 25128668 # Number of tag accesses 1076system.cpu0.icache.tags.data_accesses 25128668 # Number of data accesses 1077system.cpu0.icache.ReadReq_hits::cpu0.inst 24418226 # number of ReadReq hits 1078system.cpu0.icache.ReadReq_hits::total 24418226 # number of ReadReq hits 1079system.cpu0.icache.demand_hits::cpu0.inst 24418226 # number of demand (read+write) hits 1080system.cpu0.icache.demand_hits::total 24418226 # number of demand (read+write) hits 1081system.cpu0.icache.overall_hits::cpu0.inst 24418226 # number of overall hits 1082system.cpu0.icache.overall_hits::total 24418226 # number of overall hits 1083system.cpu0.icache.ReadReq_misses::cpu0.inst 355221 # number of ReadReq misses 1084system.cpu0.icache.ReadReq_misses::total 355221 # number of ReadReq misses 1085system.cpu0.icache.demand_misses::cpu0.inst 355221 # number of demand (read+write) misses 1086system.cpu0.icache.demand_misses::total 355221 # number of demand (read+write) misses 1087system.cpu0.icache.overall_misses::cpu0.inst 355221 # number of overall misses 1088system.cpu0.icache.overall_misses::total 355221 # number of overall misses 1089system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4963623214 # number of ReadReq miss cycles 1090system.cpu0.icache.ReadReq_miss_latency::total 4963623214 # number of ReadReq miss cycles 1091system.cpu0.icache.demand_miss_latency::cpu0.inst 4963623214 # number of demand (read+write) miss cycles 1092system.cpu0.icache.demand_miss_latency::total 4963623214 # number of demand (read+write) miss cycles 1093system.cpu0.icache.overall_miss_latency::cpu0.inst 4963623214 # number of overall miss cycles 1094system.cpu0.icache.overall_miss_latency::total 4963623214 # number of overall miss cycles 1095system.cpu0.icache.ReadReq_accesses::cpu0.inst 24773447 # number of ReadReq accesses(hits+misses) 1096system.cpu0.icache.ReadReq_accesses::total 24773447 # number of ReadReq accesses(hits+misses) 1097system.cpu0.icache.demand_accesses::cpu0.inst 24773447 # number of demand (read+write) accesses 1098system.cpu0.icache.demand_accesses::total 24773447 # number of demand (read+write) accesses 1099system.cpu0.icache.overall_accesses::cpu0.inst 24773447 # number of overall (read+write) accesses 1100system.cpu0.icache.overall_accesses::total 24773447 # number of overall (read+write) accesses 1101system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014339 # miss rate for ReadReq accesses 1102system.cpu0.icache.ReadReq_miss_rate::total 0.014339 # miss rate for ReadReq accesses 1103system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014339 # miss rate for demand accesses 1104system.cpu0.icache.demand_miss_rate::total 0.014339 # miss rate for demand accesses 1105system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014339 # miss rate for overall accesses 1106system.cpu0.icache.overall_miss_rate::total 0.014339 # miss rate for overall accesses 1107system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327 # average ReadReq miss latency 1108system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327 # average ReadReq miss latency 1109system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency 1110system.cpu0.icache.demand_avg_miss_latency::total 13973.338327 # average overall miss latency 1111system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency 1112system.cpu0.icache.overall_avg_miss_latency::total 13973.338327 # average overall miss latency |
| 1454system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1455system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1456system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1457system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1458system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1459system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1460system.cpu0.icache.fast_writes 0 # number of fast writes performed 1461system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1113system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1114system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1115system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1116system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1117system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1118system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1119system.cpu0.icache.fast_writes 0 # number of fast writes performed 1120system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1462system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425927 # number of ReadReq MSHR misses 1463system.cpu0.icache.ReadReq_mshr_misses::total 425927 # number of ReadReq MSHR misses 1464system.cpu0.icache.demand_mshr_misses::cpu0.inst 425927 # number of demand (read+write) MSHR misses 1465system.cpu0.icache.demand_mshr_misses::total 425927 # number of demand (read+write) MSHR misses 1466system.cpu0.icache.overall_mshr_misses::cpu0.inst 425927 # number of overall MSHR misses 1467system.cpu0.icache.overall_mshr_misses::total 425927 # number of overall MSHR misses 1468system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045293784 # number of ReadReq MSHR miss cycles 1469system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045293784 # number of ReadReq MSHR miss cycles 1470system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045293784 # number of demand (read+write) MSHR miss cycles 1471system.cpu0.icache.demand_mshr_miss_latency::total 5045293784 # number of demand (read+write) MSHR miss cycles 1472system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045293784 # number of overall MSHR miss cycles 1473system.cpu0.icache.overall_mshr_miss_latency::total 5045293784 # number of overall MSHR miss cycles 1474system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles 1475system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles 1477system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles 1478system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for ReadReq accesses 1479system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014403 # mshr miss rate for ReadReq accesses 1480system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for demand accesses 1481system.cpu0.icache.demand_mshr_miss_rate::total 0.014403 # mshr miss rate for demand accesses 1482system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for overall accesses 1483system.cpu0.icache.overall_mshr_miss_rate::total 0.014403 # mshr miss rate for overall accesses 1484system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average ReadReq mshr miss latency 1485system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11845.442491 # average ReadReq mshr miss latency 1486system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency 1487system.cpu0.icache.demand_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency 1488system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency 1489system.cpu0.icache.overall_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency | 1121system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355221 # number of ReadReq MSHR misses 1122system.cpu0.icache.ReadReq_mshr_misses::total 355221 # number of ReadReq MSHR misses 1123system.cpu0.icache.demand_mshr_misses::cpu0.inst 355221 # number of demand (read+write) MSHR misses 1124system.cpu0.icache.demand_mshr_misses::total 355221 # number of demand (read+write) MSHR misses 1125system.cpu0.icache.overall_mshr_misses::cpu0.inst 355221 # number of overall MSHR misses 1126system.cpu0.icache.overall_mshr_misses::total 355221 # number of overall MSHR misses 1127system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4251043786 # number of ReadReq MSHR miss cycles 1128system.cpu0.icache.ReadReq_mshr_miss_latency::total 4251043786 # number of ReadReq MSHR miss cycles 1129system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4251043786 # number of demand (read+write) MSHR miss cycles 1130system.cpu0.icache.demand_mshr_miss_latency::total 4251043786 # number of demand (read+write) MSHR miss cycles 1131system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4251043786 # number of overall MSHR miss cycles 1132system.cpu0.icache.overall_mshr_miss_latency::total 4251043786 # number of overall MSHR miss cycles 1133system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 443885000 # number of ReadReq MSHR uncacheable cycles 1134system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles 1135system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 443885000 # number of overall MSHR uncacheable cycles 1136system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles 1137system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for ReadReq accesses 1138system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014339 # mshr miss rate for ReadReq accesses 1139system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for demand accesses 1140system.cpu0.icache.demand_mshr_miss_rate::total 0.014339 # mshr miss rate for demand accesses 1141system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for overall accesses 1142system.cpu0.icache.overall_mshr_miss_rate::total 0.014339 # mshr miss rate for overall accesses 1143system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average ReadReq mshr miss latency 1144system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149 # average ReadReq mshr miss latency 1145system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency 1146system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency 1147system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency 1148system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency |
| 1490system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1491system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1492system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1493system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1494system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1149system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1150system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1151system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1152system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1153system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1495system.cpu0.dcache.tags.replacements 330503 # number of replacements 1496system.cpu0.dcache.tags.tagsinuse 455.093016 # Cycle average of tags in use 1497system.cpu0.dcache.tags.total_refs 12270625 # Total number of references to valid blocks. 1498system.cpu0.dcache.tags.sampled_refs 331015 # Sample count of references to valid blocks. 1499system.cpu0.dcache.tags.avg_refs 37.069695 # Average number of references to valid blocks. 1500system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. 1501system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.093016 # Average occupied blocks per requestor 1502system.cpu0.dcache.tags.occ_percent::cpu0.data 0.888854 # Average percentage of cache occupancy 1503system.cpu0.dcache.tags.occ_percent::total 0.888854 # Average percentage of cache occupancy 1504system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1505system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 1506system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id 1507system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 1508system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1509system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1510system.cpu0.dcache.tags.tag_accesses 50903218 # Number of tag accesses 1511system.cpu0.dcache.tags.data_accesses 50903218 # Number of data accesses 1512system.cpu0.dcache.ReadReq_hits::cpu0.data 6600273 # number of ReadReq hits 1513system.cpu0.dcache.ReadReq_hits::total 6600273 # number of ReadReq hits 1514system.cpu0.dcache.WriteReq_hits::cpu0.data 5350518 # number of WriteReq hits 1515system.cpu0.dcache.WriteReq_hits::total 5350518 # number of WriteReq hits 1516system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147975 # number of LoadLockedReq hits 1517system.cpu0.dcache.LoadLockedReq_hits::total 147975 # number of LoadLockedReq hits 1518system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149621 # number of StoreCondReq hits 1519system.cpu0.dcache.StoreCondReq_hits::total 149621 # number of StoreCondReq hits 1520system.cpu0.dcache.demand_hits::cpu0.data 11950791 # number of demand (read+write) hits 1521system.cpu0.dcache.demand_hits::total 11950791 # number of demand (read+write) hits 1522system.cpu0.dcache.overall_hits::cpu0.data 11950791 # number of overall hits 1523system.cpu0.dcache.overall_hits::total 11950791 # number of overall hits 1524system.cpu0.dcache.ReadReq_misses::cpu0.data 227769 # number of ReadReq misses 1525system.cpu0.dcache.ReadReq_misses::total 227769 # number of ReadReq misses 1526system.cpu0.dcache.WriteReq_misses::cpu0.data 141711 # number of WriteReq misses 1527system.cpu0.dcache.WriteReq_misses::total 141711 # number of WriteReq misses 1528system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9370 # number of LoadLockedReq misses 1529system.cpu0.dcache.LoadLockedReq_misses::total 9370 # number of LoadLockedReq misses 1530system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7532 # number of StoreCondReq misses 1531system.cpu0.dcache.StoreCondReq_misses::total 7532 # number of StoreCondReq misses 1532system.cpu0.dcache.demand_misses::cpu0.data 369480 # number of demand (read+write) misses 1533system.cpu0.dcache.demand_misses::total 369480 # number of demand (read+write) misses 1534system.cpu0.dcache.overall_misses::cpu0.data 369480 # number of overall misses 1535system.cpu0.dcache.overall_misses::total 369480 # number of overall misses 1536system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309712250 # number of ReadReq miss cycles 1537system.cpu0.dcache.ReadReq_miss_latency::total 3309712250 # number of ReadReq miss cycles 1538system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5686464712 # number of WriteReq miss cycles 1539system.cpu0.dcache.WriteReq_miss_latency::total 5686464712 # number of WriteReq miss cycles 1540system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92538750 # number of LoadLockedReq miss cycles 1541system.cpu0.dcache.LoadLockedReq_miss_latency::total 92538750 # number of LoadLockedReq miss cycles 1542system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44740069 # number of StoreCondReq miss cycles 1543system.cpu0.dcache.StoreCondReq_miss_latency::total 44740069 # number of StoreCondReq miss cycles 1544system.cpu0.dcache.demand_miss_latency::cpu0.data 8996176962 # number of demand (read+write) miss cycles 1545system.cpu0.dcache.demand_miss_latency::total 8996176962 # number of demand (read+write) miss cycles 1546system.cpu0.dcache.overall_miss_latency::cpu0.data 8996176962 # number of overall miss cycles 1547system.cpu0.dcache.overall_miss_latency::total 8996176962 # number of overall miss cycles 1548system.cpu0.dcache.ReadReq_accesses::cpu0.data 6828042 # number of ReadReq accesses(hits+misses) 1549system.cpu0.dcache.ReadReq_accesses::total 6828042 # number of ReadReq accesses(hits+misses) 1550system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492229 # number of WriteReq accesses(hits+misses) 1551system.cpu0.dcache.WriteReq_accesses::total 5492229 # number of WriteReq accesses(hits+misses) 1552system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157345 # number of LoadLockedReq accesses(hits+misses) 1553system.cpu0.dcache.LoadLockedReq_accesses::total 157345 # number of LoadLockedReq accesses(hits+misses) 1554system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses) 1555system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses) 1556system.cpu0.dcache.demand_accesses::cpu0.data 12320271 # number of demand (read+write) accesses 1557system.cpu0.dcache.demand_accesses::total 12320271 # number of demand (read+write) accesses 1558system.cpu0.dcache.overall_accesses::cpu0.data 12320271 # number of overall (read+write) accesses 1559system.cpu0.dcache.overall_accesses::total 12320271 # number of overall (read+write) accesses 1560system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033358 # miss rate for ReadReq accesses 1561system.cpu0.dcache.ReadReq_miss_rate::total 0.033358 # miss rate for ReadReq accesses 1562system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025802 # miss rate for WriteReq accesses 1563system.cpu0.dcache.WriteReq_miss_rate::total 0.025802 # miss rate for WriteReq accesses 1564system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059551 # miss rate for LoadLockedReq accesses 1565system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059551 # miss rate for LoadLockedReq accesses 1566system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047928 # miss rate for StoreCondReq accesses 1567system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047928 # miss rate for StoreCondReq accesses 1568system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029990 # miss rate for demand accesses 1569system.cpu0.dcache.demand_miss_rate::total 0.029990 # miss rate for demand accesses 1570system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029990 # miss rate for overall accesses 1571system.cpu0.dcache.overall_miss_rate::total 0.029990 # miss rate for overall accesses 1572system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.004000 # average ReadReq miss latency 1573system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.004000 # average ReadReq miss latency 1574system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40127.193457 # average WriteReq miss latency 1575system.cpu0.dcache.WriteReq_avg_miss_latency::total 40127.193457 # average WriteReq miss latency 1576system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9876.067236 # average LoadLockedReq miss latency 1577system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9876.067236 # average LoadLockedReq miss latency 1578system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5939.998540 # average StoreCondReq miss latency 1579system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5939.998540 # average StoreCondReq miss latency 1580system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency 1581system.cpu0.dcache.demand_avg_miss_latency::total 24348.210896 # average overall miss latency 1582system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency 1583system.cpu0.dcache.overall_avg_miss_latency::total 24348.210896 # average overall miss latency | 1154system.cpu0.dcache.tags.replacements 278858 # number of replacements 1155system.cpu0.dcache.tags.tagsinuse 453.142717 # Cycle average of tags in use 1156system.cpu0.dcache.tags.total_refs 10319958 # Total number of references to valid blocks. 1157system.cpu0.dcache.tags.sampled_refs 279247 # Sample count of references to valid blocks. 1158system.cpu0.dcache.tags.avg_refs 36.956379 # Average number of references to valid blocks. 1159system.cpu0.dcache.tags.warmup_cycle 673996250 # Cycle when the warmup percentage was hit. 1160system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.142717 # Average occupied blocks per requestor 1161system.cpu0.dcache.tags.occ_percent::cpu0.data 0.885044 # Average percentage of cache occupancy 1162system.cpu0.dcache.tags.occ_percent::total 0.885044 # Average percentage of cache occupancy 1163system.cpu0.dcache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id 1164system.cpu0.dcache.tags.age_task_id_blocks_1024::2 379 # Occupied blocks per task id 1165system.cpu0.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 1166system.cpu0.dcache.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id 1167system.cpu0.dcache.tags.tag_accesses 42855830 # Number of tag accesses 1168system.cpu0.dcache.tags.data_accesses 42855830 # Number of data accesses 1169system.cpu0.dcache.ReadReq_hits::cpu0.data 5473702 # number of ReadReq hits 1170system.cpu0.dcache.ReadReq_hits::total 5473702 # number of ReadReq hits 1171system.cpu0.dcache.WriteReq_hits::cpu0.data 4567964 # number of WriteReq hits 1172system.cpu0.dcache.WriteReq_hits::total 4567964 # number of WriteReq hits 1173system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129389 # number of LoadLockedReq hits 1174system.cpu0.dcache.LoadLockedReq_hits::total 129389 # number of LoadLockedReq hits 1175system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130155 # number of StoreCondReq hits 1176system.cpu0.dcache.StoreCondReq_hits::total 130155 # number of StoreCondReq hits 1177system.cpu0.dcache.demand_hits::cpu0.data 10041666 # number of demand (read+write) hits 1178system.cpu0.dcache.demand_hits::total 10041666 # number of demand (read+write) hits 1179system.cpu0.dcache.overall_hits::cpu0.data 10041666 # number of overall hits 1180system.cpu0.dcache.overall_hits::total 10041666 # number of overall hits 1181system.cpu0.dcache.ReadReq_misses::cpu0.data 191503 # number of ReadReq misses 1182system.cpu0.dcache.ReadReq_misses::total 191503 # number of ReadReq misses 1183system.cpu0.dcache.WriteReq_misses::cpu0.data 126416 # number of WriteReq misses 1184system.cpu0.dcache.WriteReq_misses::total 126416 # number of WriteReq misses 1185system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8708 # number of LoadLockedReq misses 1186system.cpu0.dcache.LoadLockedReq_misses::total 8708 # number of LoadLockedReq misses 1187system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7742 # number of StoreCondReq misses 1188system.cpu0.dcache.StoreCondReq_misses::total 7742 # number of StoreCondReq misses 1189system.cpu0.dcache.demand_misses::cpu0.data 317919 # number of demand (read+write) misses 1190system.cpu0.dcache.demand_misses::total 317919 # number of demand (read+write) misses 1191system.cpu0.dcache.overall_misses::cpu0.data 317919 # number of overall misses 1192system.cpu0.dcache.overall_misses::total 317919 # number of overall misses 1193system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2845005745 # number of ReadReq miss cycles 1194system.cpu0.dcache.ReadReq_miss_latency::total 2845005745 # number of ReadReq miss cycles 1195system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5278408391 # number of WriteReq miss cycles 1196system.cpu0.dcache.WriteReq_miss_latency::total 5278408391 # number of WriteReq miss cycles 1197system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82648500 # number of LoadLockedReq miss cycles 1198system.cpu0.dcache.LoadLockedReq_miss_latency::total 82648500 # number of LoadLockedReq miss cycles 1199system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45599070 # number of StoreCondReq miss cycles 1200system.cpu0.dcache.StoreCondReq_miss_latency::total 45599070 # number of StoreCondReq miss cycles 1201system.cpu0.dcache.demand_miss_latency::cpu0.data 8123414136 # number of demand (read+write) miss cycles 1202system.cpu0.dcache.demand_miss_latency::total 8123414136 # number of demand (read+write) miss cycles 1203system.cpu0.dcache.overall_miss_latency::cpu0.data 8123414136 # number of overall miss cycles 1204system.cpu0.dcache.overall_miss_latency::total 8123414136 # number of overall miss cycles 1205system.cpu0.dcache.ReadReq_accesses::cpu0.data 5665205 # number of ReadReq accesses(hits+misses) 1206system.cpu0.dcache.ReadReq_accesses::total 5665205 # number of ReadReq accesses(hits+misses) 1207system.cpu0.dcache.WriteReq_accesses::cpu0.data 4694380 # number of WriteReq accesses(hits+misses) 1208system.cpu0.dcache.WriteReq_accesses::total 4694380 # number of WriteReq accesses(hits+misses) 1209system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138097 # number of LoadLockedReq accesses(hits+misses) 1210system.cpu0.dcache.LoadLockedReq_accesses::total 138097 # number of LoadLockedReq accesses(hits+misses) 1211system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137897 # number of StoreCondReq accesses(hits+misses) 1212system.cpu0.dcache.StoreCondReq_accesses::total 137897 # number of StoreCondReq accesses(hits+misses) 1213system.cpu0.dcache.demand_accesses::cpu0.data 10359585 # number of demand (read+write) accesses 1214system.cpu0.dcache.demand_accesses::total 10359585 # number of demand (read+write) accesses 1215system.cpu0.dcache.overall_accesses::cpu0.data 10359585 # number of overall (read+write) accesses 1216system.cpu0.dcache.overall_accesses::total 10359585 # number of overall (read+write) accesses 1217system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033803 # miss rate for ReadReq accesses 1218system.cpu0.dcache.ReadReq_miss_rate::total 0.033803 # miss rate for ReadReq accesses 1219system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses 1220system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses 1221system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063057 # miss rate for LoadLockedReq accesses 1222system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063057 # miss rate for LoadLockedReq accesses 1223system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056143 # miss rate for StoreCondReq accesses 1224system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056143 # miss rate for StoreCondReq accesses 1225system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030688 # miss rate for demand accesses 1226system.cpu0.dcache.demand_miss_rate::total 0.030688 # miss rate for demand accesses 1227system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030688 # miss rate for overall accesses 1228system.cpu0.dcache.overall_miss_rate::total 0.030688 # miss rate for overall accesses 1229system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133 # average ReadReq miss latency 1230system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133 # average ReadReq miss latency 1231system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704 # average WriteReq miss latency 1232system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704 # average WriteReq miss latency 1233system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9491.100138 # average LoadLockedReq miss latency 1234system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9491.100138 # average LoadLockedReq miss latency 1235system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5889.830793 # average StoreCondReq miss latency 1236system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5889.830793 # average StoreCondReq miss latency 1237system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency 1238system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958 # average overall miss latency 1239system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency 1240system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958 # average overall miss latency |
| 1584system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1585system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1586system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1587system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1588system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1589system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1590system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1591system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1241system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1242system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1243system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1244system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1245system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1246system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1247system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1248system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1592system.cpu0.dcache.writebacks::writebacks 306085 # number of writebacks 1593system.cpu0.dcache.writebacks::total 306085 # number of writebacks 1594system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227769 # number of ReadReq MSHR misses 1595system.cpu0.dcache.ReadReq_mshr_misses::total 227769 # number of ReadReq MSHR misses 1596system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141711 # number of WriteReq MSHR misses 1597system.cpu0.dcache.WriteReq_mshr_misses::total 141711 # number of WriteReq MSHR misses 1598system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9370 # number of LoadLockedReq MSHR misses 1599system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9370 # number of LoadLockedReq MSHR misses 1600system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7530 # number of StoreCondReq MSHR misses 1601system.cpu0.dcache.StoreCondReq_mshr_misses::total 7530 # number of StoreCondReq MSHR misses 1602system.cpu0.dcache.demand_mshr_misses::cpu0.data 369480 # number of demand (read+write) MSHR misses 1603system.cpu0.dcache.demand_mshr_misses::total 369480 # number of demand (read+write) MSHR misses 1604system.cpu0.dcache.overall_mshr_misses::cpu0.data 369480 # number of overall MSHR misses 1605system.cpu0.dcache.overall_mshr_misses::total 369480 # number of overall MSHR misses 1606system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2852244750 # number of ReadReq MSHR miss cycles 1607system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2852244750 # number of ReadReq MSHR miss cycles 1608system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372105288 # number of WriteReq MSHR miss cycles 1609system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5372105288 # number of WriteReq MSHR miss cycles 1610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73750250 # number of LoadLockedReq MSHR miss cycles 1611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73750250 # number of LoadLockedReq MSHR miss cycles 1612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29678931 # number of StoreCondReq MSHR miss cycles 1613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29678931 # number of StoreCondReq MSHR miss cycles 1614system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8224350038 # number of demand (read+write) MSHR miss cycles 1615system.cpu0.dcache.demand_mshr_miss_latency::total 8224350038 # number of demand (read+write) MSHR miss cycles 1616system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8224350038 # number of overall MSHR miss cycles 1617system.cpu0.dcache.overall_mshr_miss_latency::total 8224350038 # number of overall MSHR miss cycles 1618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13565968500 # number of ReadReq MSHR uncacheable cycles 1619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13565968500 # number of ReadReq MSHR uncacheable cycles 1620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170779500 # number of WriteReq MSHR uncacheable cycles 1621system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170779500 # number of WriteReq MSHR uncacheable cycles 1622system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14736748000 # number of overall MSHR uncacheable cycles 1623system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14736748000 # number of overall MSHR uncacheable cycles 1624system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033358 # mshr miss rate for ReadReq accesses 1625system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033358 # mshr miss rate for ReadReq accesses 1626system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025802 # mshr miss rate for WriteReq accesses 1627system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025802 # mshr miss rate for WriteReq accesses 1628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059551 # mshr miss rate for LoadLockedReq accesses 1629system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059551 # mshr miss rate for LoadLockedReq accesses 1630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047915 # mshr miss rate for StoreCondReq accesses 1631system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047915 # mshr miss rate for StoreCondReq accesses 1632system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for demand accesses 1633system.cpu0.dcache.demand_mshr_miss_rate::total 0.029990 # mshr miss rate for demand accesses 1634system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for overall accesses 1635system.cpu0.dcache.overall_mshr_miss_rate::total 0.029990 # mshr miss rate for overall accesses 1636system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698 # average ReadReq mshr miss latency 1637system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698 # average ReadReq mshr miss latency 1638system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960 # average WriteReq mshr miss latency 1639system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960 # average WriteReq mshr miss latency 1640system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7870.891142 # average LoadLockedReq mshr miss latency 1641system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7870.891142 # average LoadLockedReq mshr miss latency 1642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3941.425100 # average StoreCondReq mshr miss latency 1643system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3941.425100 # average StoreCondReq mshr miss latency 1644system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency 1645system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency 1646system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency 1647system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency | 1249system.cpu0.dcache.writebacks::writebacks 257140 # number of writebacks 1250system.cpu0.dcache.writebacks::total 257140 # number of writebacks 1251system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191503 # number of ReadReq MSHR misses 1252system.cpu0.dcache.ReadReq_mshr_misses::total 191503 # number of ReadReq MSHR misses 1253system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126416 # number of WriteReq MSHR misses 1254system.cpu0.dcache.WriteReq_mshr_misses::total 126416 # number of WriteReq MSHR misses 1255system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8708 # number of LoadLockedReq MSHR misses 1256system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8708 # number of LoadLockedReq MSHR misses 1257system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7738 # number of StoreCondReq MSHR misses 1258system.cpu0.dcache.StoreCondReq_mshr_misses::total 7738 # number of StoreCondReq MSHR misses 1259system.cpu0.dcache.demand_mshr_misses::cpu0.data 317919 # number of demand (read+write) MSHR misses 1260system.cpu0.dcache.demand_mshr_misses::total 317919 # number of demand (read+write) MSHR misses 1261system.cpu0.dcache.overall_mshr_misses::cpu0.data 317919 # number of overall MSHR misses 1262system.cpu0.dcache.overall_mshr_misses::total 317919 # number of overall MSHR misses 1263system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2460118255 # number of ReadReq MSHR miss cycles 1264system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460118255 # number of ReadReq MSHR miss cycles 1265system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4997663609 # number of WriteReq MSHR miss cycles 1266system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4997663609 # number of WriteReq MSHR miss cycles 1267system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65185500 # number of LoadLockedReq MSHR miss cycles 1268system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65185500 # number of LoadLockedReq MSHR miss cycles 1269system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30121930 # number of StoreCondReq MSHR miss cycles 1270system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30121930 # number of StoreCondReq MSHR miss cycles 1271system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7457781864 # number of demand (read+write) MSHR miss cycles 1272system.cpu0.dcache.demand_mshr_miss_latency::total 7457781864 # number of demand (read+write) MSHR miss cycles 1273system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7457781864 # number of overall MSHR miss cycles 1274system.cpu0.dcache.overall_mshr_miss_latency::total 7457781864 # number of overall MSHR miss cycles 1275system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12214482000 # number of ReadReq MSHR uncacheable cycles 1276system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12214482000 # number of ReadReq MSHR uncacheable cycles 1277system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1164635000 # number of WriteReq MSHR uncacheable cycles 1278system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1164635000 # number of WriteReq MSHR uncacheable cycles 1279system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13379117000 # number of overall MSHR uncacheable cycles 1280system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13379117000 # number of overall MSHR uncacheable cycles 1281system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033803 # mshr miss rate for ReadReq accesses 1282system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033803 # mshr miss rate for ReadReq accesses 1283system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses 1284system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses 1285system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063057 # mshr miss rate for LoadLockedReq accesses 1286system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063057 # mshr miss rate for LoadLockedReq accesses 1287system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056114 # mshr miss rate for StoreCondReq accesses 1288system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056114 # mshr miss rate for StoreCondReq accesses 1289system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for demand accesses 1290system.cpu0.dcache.demand_mshr_miss_rate::total 0.030688 # mshr miss rate for demand accesses 1291system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for overall accesses 1292system.cpu0.dcache.overall_mshr_miss_rate::total 0.030688 # mshr miss rate for overall accesses 1293system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274 # average ReadReq mshr miss latency 1294system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274 # average ReadReq mshr miss latency 1295system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682 # average WriteReq mshr miss latency 1296system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682 # average WriteReq mshr miss latency 1297system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7485.702802 # average LoadLockedReq mshr miss latency 1298system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7485.702802 # average LoadLockedReq mshr miss latency 1299system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3892.728095 # average StoreCondReq mshr miss latency 1300system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3892.728095 # average StoreCondReq mshr miss latency 1301system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency 1302system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency 1303system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency 1304system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency |
| 1648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1649system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1651system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1654system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1655system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits --- 14 unchanged lines hidden (view full) --- 1670system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1671system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1672system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1673system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1674system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1675system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1676system.cpu1.dtb.inst_hits 0 # ITB inst hits 1677system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1305system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1306system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1307system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1308system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1309system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1310system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1311system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1312system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits --- 14 unchanged lines hidden (view full) --- 1327system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1328system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1329system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1330system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1331system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1332system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1333system.cpu1.dtb.inst_hits 0 # ITB inst hits 1334system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1678system.cpu1.dtb.read_hits 8312417 # DTB read hits 1679system.cpu1.dtb.read_misses 3644 # DTB read misses 1680system.cpu1.dtb.write_hits 5828126 # DTB write hits 1681system.cpu1.dtb.write_misses 1438 # DTB write misses | 1335system.cpu1.dtb.read_hits 9507781 # DTB read hits 1336system.cpu1.dtb.read_misses 5255 # DTB read misses 1337system.cpu1.dtb.write_hits 6647969 # DTB write hits 1338system.cpu1.dtb.write_misses 1834 # DTB write misses |
| 1682system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1683system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1684system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1685system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1339system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1340system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1341system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1342system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1686system.cpu1.dtb.flush_entries 1864 # Number of entries that have been flushed from TLB | 1343system.cpu1.dtb.flush_entries 2187 # Number of entries that have been flushed from TLB |
| 1687system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 1344system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1688system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch | 1345system.cpu1.dtb.prefetch_faults 188 # Number of TLB faults due to prefetch |
| 1689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1346system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1690system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1691system.cpu1.dtb.read_accesses 8316061 # DTB read accesses 1692system.cpu1.dtb.write_accesses 5829564 # DTB write accesses | 1347system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions 1348system.cpu1.dtb.read_accesses 9513036 # DTB read accesses 1349system.cpu1.dtb.write_accesses 6649803 # DTB write accesses |
| 1693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1350system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1694system.cpu1.dtb.hits 14140543 # DTB hits 1695system.cpu1.dtb.misses 5082 # DTB misses 1696system.cpu1.dtb.accesses 14145625 # DTB accesses | 1351system.cpu1.dtb.hits 16155750 # DTB hits 1352system.cpu1.dtb.misses 7089 # DTB misses 1353system.cpu1.dtb.accesses 16162839 # DTB accesses |
| 1697system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1698system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1699system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1700system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1701system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1702system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1703system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1704system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1710system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1711system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1712system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1713system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1714system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1715system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1716system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1717system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1354system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1355system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1356system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1357system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1358system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1359system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1360system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1361system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 1367system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1368system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1369system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1370system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1371system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1372system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1373system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1374system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1718system.cpu1.itb.inst_hits 33196912 # ITB inst hits 1719system.cpu1.itb.inst_misses 2171 # ITB inst misses | 1375system.cpu1.itb.inst_hits 38008437 # ITB inst hits 1376system.cpu1.itb.inst_misses 3017 # ITB inst misses |
| 1720system.cpu1.itb.read_hits 0 # DTB read hits 1721system.cpu1.itb.read_misses 0 # DTB read misses 1722system.cpu1.itb.write_hits 0 # DTB write hits 1723system.cpu1.itb.write_misses 0 # DTB write misses 1724system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1725system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1726system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1727system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 1377system.cpu1.itb.read_hits 0 # DTB read hits 1378system.cpu1.itb.read_misses 0 # DTB read misses 1379system.cpu1.itb.write_hits 0 # DTB write hits 1380system.cpu1.itb.write_misses 0 # DTB write misses 1381system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1382system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1383system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1384system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 1728system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB | 1385system.cpu1.itb.flush_entries 1485 # Number of entries that have been flushed from TLB |
| 1729system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1730system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1731system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1732system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1733system.cpu1.itb.read_accesses 0 # DTB read accesses 1734system.cpu1.itb.write_accesses 0 # DTB write accesses | 1386system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1387system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1388system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1389system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1390system.cpu1.itb.read_accesses 0 # DTB read accesses 1391system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1735system.cpu1.itb.inst_accesses 33199083 # ITB inst accesses 1736system.cpu1.itb.hits 33196912 # DTB hits 1737system.cpu1.itb.misses 2171 # DTB misses 1738system.cpu1.itb.accesses 33199083 # DTB accesses 1739system.cpu1.numCycles 2390815191 # number of cpu cycles simulated | 1392system.cpu1.itb.inst_accesses 38011454 # ITB inst accesses 1393system.cpu1.itb.hits 38008437 # DTB hits 1394system.cpu1.itb.misses 3017 # DTB misses 1395system.cpu1.itb.accesses 38011454 # DTB accesses 1396system.cpu1.numCycles 2392450295 # number of cpu cycles simulated |
| 1740system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1741system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1397system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1398system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1742system.cpu1.committedInsts 32585929 # Number of instructions committed 1743system.cpu1.committedOps 41097454 # Number of ops (including micro ops) committed 1744system.cpu1.num_int_alu_accesses 37620588 # Number of integer alu accesses 1745system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1746system.cpu1.num_func_calls 962436 # number of times a function call or return occured 1747system.cpu1.num_conditional_control_insts 3733629 # number of instructions that are conditional controls 1748system.cpu1.num_int_insts 37620588 # number of integer instructions 1749system.cpu1.num_fp_insts 6793 # number of float instructions 1750system.cpu1.num_int_register_reads 218203394 # number of times the integer registers were read 1751system.cpu1.num_int_register_writes 39762349 # number of times the integer registers were written 1752system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1753system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1754system.cpu1.num_mem_refs 14678716 # number of memory refs 1755system.cpu1.num_load_insts 8634369 # Number of load instructions 1756system.cpu1.num_store_insts 6044347 # Number of store instructions 1757system.cpu1.num_idle_cycles 1874341984.155535 # Number of idle cycles 1758system.cpu1.num_busy_cycles 516473206.844465 # Number of busy cycles 1759system.cpu1.not_idle_fraction 0.216024 # Percentage of non-idle cycles 1760system.cpu1.idle_fraction 0.783976 # Percentage of idle cycles 1761system.cpu1.Branches 4945874 # Number of branches fetched | 1399system.cpu1.committedInsts 37097446 # Number of instructions committed 1400system.cpu1.committedOps 46867102 # Number of ops (including micro ops) committed 1401system.cpu1.num_int_alu_accesses 42687988 # Number of integer alu accesses 1402system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses 1403system.cpu1.num_func_calls 1134316 # number of times a function call or return occured 1404system.cpu1.num_conditional_control_insts 4357000 # number of instructions that are conditional controls 1405system.cpu1.num_int_insts 42687988 # number of integer instructions 1406system.cpu1.num_fp_insts 5457 # number of float instructions 1407system.cpu1.num_int_register_reads 248074220 # number of times the integer registers were read 1408system.cpu1.num_int_register_writes 45509439 # number of times the integer registers were written 1409system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read 1410system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written 1411system.cpu1.num_mem_refs 16770062 # number of memory refs 1412system.cpu1.num_load_insts 9887948 # Number of load instructions 1413system.cpu1.num_store_insts 6882114 # Number of store instructions 1414system.cpu1.num_idle_cycles 1855714829.552449 # Number of idle cycles 1415system.cpu1.num_busy_cycles 536735465.447551 # Number of busy cycles 1416system.cpu1.not_idle_fraction 0.224346 # Percentage of non-idle cycles 1417system.cpu1.idle_fraction 0.775654 # Percentage of idle cycles 1418system.cpu1.Branches 5771094 # Number of branches fetched |
| 1762system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1419system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1763system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed 1764system.cpu1.icache.tags.replacements 469670 # number of replacements 1765system.cpu1.icache.tags.tagsinuse 478.560169 # Cycle average of tags in use 1766system.cpu1.icache.tags.total_refs 32726726 # Total number of references to valid blocks. 1767system.cpu1.icache.tags.sampled_refs 470182 # Sample count of references to valid blocks. 1768system.cpu1.icache.tags.avg_refs 69.604379 # Average number of references to valid blocks. 1769system.cpu1.icache.tags.warmup_cycle 94003216500 # Cycle when the warmup percentage was hit. 1770system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.560169 # Average occupied blocks per requestor 1771system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934688 # Average percentage of cache occupancy 1772system.cpu1.icache.tags.occ_percent::total 0.934688 # Average percentage of cache occupancy | 1420system.cpu1.kern.inst.quiesce 52097 # number of quiesce instructions executed 1421system.cpu1.icache.tags.replacements 540849 # number of replacements 1422system.cpu1.icache.tags.tagsinuse 478.554171 # Cycle average of tags in use 1423system.cpu1.icache.tags.total_refs 37467072 # Total number of references to valid blocks. 1424system.cpu1.icache.tags.sampled_refs 541361 # Sample count of references to valid blocks. 1425system.cpu1.icache.tags.avg_refs 69.209034 # Average number of references to valid blocks. 1426system.cpu1.icache.tags.warmup_cycle 94011084500 # Cycle when the warmup percentage was hit. 1427system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.554171 # Average occupied blocks per requestor 1428system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934676 # Average percentage of cache occupancy 1429system.cpu1.icache.tags.occ_percent::total 0.934676 # Average percentage of cache occupancy |
| 1773system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1430system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1774system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 1775system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1776system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id | 1431system.cpu1.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 1432system.cpu1.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id 1433system.cpu1.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id 1434system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id |
| 1777system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1435system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1778system.cpu1.icache.tags.tag_accesses 33667090 # Number of tag accesses 1779system.cpu1.icache.tags.data_accesses 33667090 # Number of data accesses 1780system.cpu1.icache.ReadReq_hits::cpu1.inst 32726726 # number of ReadReq hits 1781system.cpu1.icache.ReadReq_hits::total 32726726 # number of ReadReq hits 1782system.cpu1.icache.demand_hits::cpu1.inst 32726726 # number of demand (read+write) hits 1783system.cpu1.icache.demand_hits::total 32726726 # number of demand (read+write) hits 1784system.cpu1.icache.overall_hits::cpu1.inst 32726726 # number of overall hits 1785system.cpu1.icache.overall_hits::total 32726726 # number of overall hits 1786system.cpu1.icache.ReadReq_misses::cpu1.inst 470182 # number of ReadReq misses 1787system.cpu1.icache.ReadReq_misses::total 470182 # number of ReadReq misses 1788system.cpu1.icache.demand_misses::cpu1.inst 470182 # number of demand (read+write) misses 1789system.cpu1.icache.demand_misses::total 470182 # number of demand (read+write) misses 1790system.cpu1.icache.overall_misses::cpu1.inst 470182 # number of overall misses 1791system.cpu1.icache.overall_misses::total 470182 # number of overall misses 1792system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443403725 # number of ReadReq miss cycles 1793system.cpu1.icache.ReadReq_miss_latency::total 6443403725 # number of ReadReq miss cycles 1794system.cpu1.icache.demand_miss_latency::cpu1.inst 6443403725 # number of demand (read+write) miss cycles 1795system.cpu1.icache.demand_miss_latency::total 6443403725 # number of demand (read+write) miss cycles 1796system.cpu1.icache.overall_miss_latency::cpu1.inst 6443403725 # number of overall miss cycles 1797system.cpu1.icache.overall_miss_latency::total 6443403725 # number of overall miss cycles 1798system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196908 # number of ReadReq accesses(hits+misses) 1799system.cpu1.icache.ReadReq_accesses::total 33196908 # number of ReadReq accesses(hits+misses) 1800system.cpu1.icache.demand_accesses::cpu1.inst 33196908 # number of demand (read+write) accesses 1801system.cpu1.icache.demand_accesses::total 33196908 # number of demand (read+write) accesses 1802system.cpu1.icache.overall_accesses::cpu1.inst 33196908 # number of overall (read+write) accesses 1803system.cpu1.icache.overall_accesses::total 33196908 # number of overall (read+write) accesses 1804system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014163 # miss rate for ReadReq accesses 1805system.cpu1.icache.ReadReq_miss_rate::total 0.014163 # miss rate for ReadReq accesses 1806system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014163 # miss rate for demand accesses 1807system.cpu1.icache.demand_miss_rate::total 0.014163 # miss rate for demand accesses 1808system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014163 # miss rate for overall accesses 1809system.cpu1.icache.overall_miss_rate::total 0.014163 # miss rate for overall accesses 1810system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13704.062948 # average ReadReq miss latency 1811system.cpu1.icache.ReadReq_avg_miss_latency::total 13704.062948 # average ReadReq miss latency 1812system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency 1813system.cpu1.icache.demand_avg_miss_latency::total 13704.062948 # average overall miss latency 1814system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency 1815system.cpu1.icache.overall_avg_miss_latency::total 13704.062948 # average overall miss latency | 1436system.cpu1.icache.tags.tag_accesses 38549794 # Number of tag accesses 1437system.cpu1.icache.tags.data_accesses 38549794 # Number of data accesses 1438system.cpu1.icache.ReadReq_hits::cpu1.inst 37467072 # number of ReadReq hits 1439system.cpu1.icache.ReadReq_hits::total 37467072 # number of ReadReq hits 1440system.cpu1.icache.demand_hits::cpu1.inst 37467072 # number of demand (read+write) hits 1441system.cpu1.icache.demand_hits::total 37467072 # number of demand (read+write) hits 1442system.cpu1.icache.overall_hits::cpu1.inst 37467072 # number of overall hits 1443system.cpu1.icache.overall_hits::total 37467072 # number of overall hits 1444system.cpu1.icache.ReadReq_misses::cpu1.inst 541361 # number of ReadReq misses 1445system.cpu1.icache.ReadReq_misses::total 541361 # number of ReadReq misses 1446system.cpu1.icache.demand_misses::cpu1.inst 541361 # number of demand (read+write) misses 1447system.cpu1.icache.demand_misses::total 541361 # number of demand (read+write) misses 1448system.cpu1.icache.overall_misses::cpu1.inst 541361 # number of overall misses 1449system.cpu1.icache.overall_misses::total 541361 # number of overall misses 1450system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7383473218 # number of ReadReq miss cycles 1451system.cpu1.icache.ReadReq_miss_latency::total 7383473218 # number of ReadReq miss cycles 1452system.cpu1.icache.demand_miss_latency::cpu1.inst 7383473218 # number of demand (read+write) miss cycles 1453system.cpu1.icache.demand_miss_latency::total 7383473218 # number of demand (read+write) miss cycles 1454system.cpu1.icache.overall_miss_latency::cpu1.inst 7383473218 # number of overall miss cycles 1455system.cpu1.icache.overall_miss_latency::total 7383473218 # number of overall miss cycles 1456system.cpu1.icache.ReadReq_accesses::cpu1.inst 38008433 # number of ReadReq accesses(hits+misses) 1457system.cpu1.icache.ReadReq_accesses::total 38008433 # number of ReadReq accesses(hits+misses) 1458system.cpu1.icache.demand_accesses::cpu1.inst 38008433 # number of demand (read+write) accesses 1459system.cpu1.icache.demand_accesses::total 38008433 # number of demand (read+write) accesses 1460system.cpu1.icache.overall_accesses::cpu1.inst 38008433 # number of overall (read+write) accesses 1461system.cpu1.icache.overall_accesses::total 38008433 # number of overall (read+write) accesses 1462system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014243 # miss rate for ReadReq accesses 1463system.cpu1.icache.ReadReq_miss_rate::total 0.014243 # miss rate for ReadReq accesses 1464system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014243 # miss rate for demand accesses 1465system.cpu1.icache.demand_miss_rate::total 0.014243 # miss rate for demand accesses 1466system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014243 # miss rate for overall accesses 1467system.cpu1.icache.overall_miss_rate::total 0.014243 # miss rate for overall accesses 1468system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13638.723916 # average ReadReq miss latency 1469system.cpu1.icache.ReadReq_avg_miss_latency::total 13638.723916 # average ReadReq miss latency 1470system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency 1471system.cpu1.icache.demand_avg_miss_latency::total 13638.723916 # average overall miss latency 1472system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency 1473system.cpu1.icache.overall_avg_miss_latency::total 13638.723916 # average overall miss latency |
| 1816system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1817system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1818system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1819system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1820system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1821system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1822system.cpu1.icache.fast_writes 0 # number of fast writes performed 1823system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1474system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1475system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1476system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1477system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1478system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1479system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1480system.cpu1.icache.fast_writes 0 # number of fast writes performed 1481system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1824system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470182 # number of ReadReq MSHR misses 1825system.cpu1.icache.ReadReq_mshr_misses::total 470182 # number of ReadReq MSHR misses 1826system.cpu1.icache.demand_mshr_misses::cpu1.inst 470182 # number of demand (read+write) MSHR misses 1827system.cpu1.icache.demand_mshr_misses::total 470182 # number of demand (read+write) MSHR misses 1828system.cpu1.icache.overall_mshr_misses::cpu1.inst 470182 # number of overall MSHR misses 1829system.cpu1.icache.overall_mshr_misses::total 470182 # number of overall MSHR misses 1830system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5501099275 # number of ReadReq MSHR miss cycles 1831system.cpu1.icache.ReadReq_mshr_miss_latency::total 5501099275 # number of ReadReq MSHR miss cycles 1832system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5501099275 # number of demand (read+write) MSHR miss cycles 1833system.cpu1.icache.demand_mshr_miss_latency::total 5501099275 # number of demand (read+write) MSHR miss cycles 1834system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5501099275 # number of overall MSHR miss cycles 1835system.cpu1.icache.overall_mshr_miss_latency::total 5501099275 # number of overall MSHR miss cycles 1836system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6820250 # number of ReadReq MSHR uncacheable cycles 1837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6820250 # number of ReadReq MSHR uncacheable cycles 1838system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6820250 # number of overall MSHR uncacheable cycles 1839system.cpu1.icache.overall_mshr_uncacheable_latency::total 6820250 # number of overall MSHR uncacheable cycles 1840system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for ReadReq accesses 1841system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014163 # mshr miss rate for ReadReq accesses 1842system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for demand accesses 1843system.cpu1.icache.demand_mshr_miss_rate::total 0.014163 # mshr miss rate for demand accesses 1844system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for overall accesses 1845system.cpu1.icache.overall_mshr_miss_rate::total 0.014163 # mshr miss rate for overall accesses 1846system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average ReadReq mshr miss latency 1847system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11699.935929 # average ReadReq mshr miss latency 1848system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency 1849system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency 1850system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency 1851system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency | 1482system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 541361 # number of ReadReq MSHR misses 1483system.cpu1.icache.ReadReq_mshr_misses::total 541361 # number of ReadReq MSHR misses 1484system.cpu1.icache.demand_mshr_misses::cpu1.inst 541361 # number of demand (read+write) MSHR misses 1485system.cpu1.icache.demand_mshr_misses::total 541361 # number of demand (read+write) MSHR misses 1486system.cpu1.icache.overall_mshr_misses::cpu1.inst 541361 # number of overall MSHR misses 1487system.cpu1.icache.overall_mshr_misses::total 541361 # number of overall MSHR misses 1488system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6298814782 # number of ReadReq MSHR miss cycles 1489system.cpu1.icache.ReadReq_mshr_miss_latency::total 6298814782 # number of ReadReq MSHR miss cycles 1490system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6298814782 # number of demand (read+write) MSHR miss cycles 1491system.cpu1.icache.demand_mshr_miss_latency::total 6298814782 # number of demand (read+write) MSHR miss cycles 1492system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6298814782 # number of overall MSHR miss cycles 1493system.cpu1.icache.overall_mshr_miss_latency::total 6298814782 # number of overall MSHR miss cycles 1494system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6977250 # number of ReadReq MSHR uncacheable cycles 1495system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6977250 # number of ReadReq MSHR uncacheable cycles 1496system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6977250 # number of overall MSHR uncacheable cycles 1497system.cpu1.icache.overall_mshr_uncacheable_latency::total 6977250 # number of overall MSHR uncacheable cycles 1498system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for ReadReq accesses 1499system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014243 # mshr miss rate for ReadReq accesses 1500system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for demand accesses 1501system.cpu1.icache.demand_mshr_miss_rate::total 0.014243 # mshr miss rate for demand accesses 1502system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for overall accesses 1503system.cpu1.icache.overall_mshr_miss_rate::total 0.014243 # mshr miss rate for overall accesses 1504system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average ReadReq mshr miss latency 1505system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939 # average ReadReq mshr miss latency 1506system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency 1507system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency 1508system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency 1509system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency |
| 1852system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1853system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1854system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1855system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1856system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1510system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1511system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1512system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1513system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1514system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1857system.cpu1.dcache.tags.replacements 292321 # number of replacements 1858system.cpu1.dcache.tags.tagsinuse 471.500981 # Cycle average of tags in use 1859system.cpu1.dcache.tags.total_refs 11963226 # Total number of references to valid blocks. 1860system.cpu1.dcache.tags.sampled_refs 292696 # Sample count of references to valid blocks. 1861system.cpu1.dcache.tags.avg_refs 40.872530 # Average number of references to valid blocks. 1862system.cpu1.dcache.tags.warmup_cycle 85292295250 # Cycle when the warmup percentage was hit. 1863system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.500981 # Average occupied blocks per requestor 1864system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920900 # Average percentage of cache occupancy 1865system.cpu1.dcache.tags.occ_percent::total 0.920900 # Average percentage of cache occupancy 1866system.cpu1.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id 1867system.cpu1.dcache.tags.age_task_id_blocks_1024::2 361 # Occupied blocks per task id 1868system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 1869system.cpu1.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id 1870system.cpu1.dcache.tags.tag_accesses 49443351 # Number of tag accesses 1871system.cpu1.dcache.tags.data_accesses 49443351 # Number of data accesses 1872system.cpu1.dcache.ReadReq_hits::cpu1.data 6947316 # number of ReadReq hits 1873system.cpu1.dcache.ReadReq_hits::total 6947316 # number of ReadReq hits 1874system.cpu1.dcache.WriteReq_hits::cpu1.data 4827697 # number of WriteReq hits 1875system.cpu1.dcache.WriteReq_hits::total 4827697 # number of WriteReq hits 1876system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82016 # number of LoadLockedReq hits 1877system.cpu1.dcache.LoadLockedReq_hits::total 82016 # number of LoadLockedReq hits 1878system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82738 # number of StoreCondReq hits 1879system.cpu1.dcache.StoreCondReq_hits::total 82738 # number of StoreCondReq hits 1880system.cpu1.dcache.demand_hits::cpu1.data 11775013 # number of demand (read+write) hits 1881system.cpu1.dcache.demand_hits::total 11775013 # number of demand (read+write) hits 1882system.cpu1.dcache.overall_hits::cpu1.data 11775013 # number of overall hits 1883system.cpu1.dcache.overall_hits::total 11775013 # number of overall hits 1884system.cpu1.dcache.ReadReq_misses::cpu1.data 170735 # number of ReadReq misses 1885system.cpu1.dcache.ReadReq_misses::total 170735 # number of ReadReq misses 1886system.cpu1.dcache.WriteReq_misses::cpu1.data 150073 # number of WriteReq misses 1887system.cpu1.dcache.WriteReq_misses::total 150073 # number of WriteReq misses 1888system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11224 # number of LoadLockedReq misses 1889system.cpu1.dcache.LoadLockedReq_misses::total 11224 # number of LoadLockedReq misses 1890system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10063 # number of StoreCondReq misses 1891system.cpu1.dcache.StoreCondReq_misses::total 10063 # number of StoreCondReq misses 1892system.cpu1.dcache.demand_misses::cpu1.data 320808 # number of demand (read+write) misses 1893system.cpu1.dcache.demand_misses::total 320808 # number of demand (read+write) misses 1894system.cpu1.dcache.overall_misses::cpu1.data 320808 # number of overall misses 1895system.cpu1.dcache.overall_misses::total 320808 # number of overall misses 1896system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220021998 # number of ReadReq miss cycles 1897system.cpu1.dcache.ReadReq_miss_latency::total 2220021998 # number of ReadReq miss cycles 1898system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6568353267 # number of WriteReq miss cycles 1899system.cpu1.dcache.WriteReq_miss_latency::total 6568353267 # number of WriteReq miss cycles 1900system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96536250 # number of LoadLockedReq miss cycles 1901system.cpu1.dcache.LoadLockedReq_miss_latency::total 96536250 # number of LoadLockedReq miss cycles 1902system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52014971 # number of StoreCondReq miss cycles 1903system.cpu1.dcache.StoreCondReq_miss_latency::total 52014971 # number of StoreCondReq miss cycles 1904system.cpu1.dcache.demand_miss_latency::cpu1.data 8788375265 # number of demand (read+write) miss cycles 1905system.cpu1.dcache.demand_miss_latency::total 8788375265 # number of demand (read+write) miss cycles 1906system.cpu1.dcache.overall_miss_latency::cpu1.data 8788375265 # number of overall miss cycles 1907system.cpu1.dcache.overall_miss_latency::total 8788375265 # number of overall miss cycles 1908system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118051 # number of ReadReq accesses(hits+misses) 1909system.cpu1.dcache.ReadReq_accesses::total 7118051 # number of ReadReq accesses(hits+misses) 1910system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977770 # number of WriteReq accesses(hits+misses) 1911system.cpu1.dcache.WriteReq_accesses::total 4977770 # number of WriteReq accesses(hits+misses) 1912system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93240 # number of LoadLockedReq accesses(hits+misses) 1913system.cpu1.dcache.LoadLockedReq_accesses::total 93240 # number of LoadLockedReq accesses(hits+misses) 1914system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92801 # number of StoreCondReq accesses(hits+misses) 1915system.cpu1.dcache.StoreCondReq_accesses::total 92801 # number of StoreCondReq accesses(hits+misses) 1916system.cpu1.dcache.demand_accesses::cpu1.data 12095821 # number of demand (read+write) accesses 1917system.cpu1.dcache.demand_accesses::total 12095821 # number of demand (read+write) accesses 1918system.cpu1.dcache.overall_accesses::cpu1.data 12095821 # number of overall (read+write) accesses 1919system.cpu1.dcache.overall_accesses::total 12095821 # number of overall (read+write) accesses 1920system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023986 # miss rate for ReadReq accesses 1921system.cpu1.dcache.ReadReq_miss_rate::total 0.023986 # miss rate for ReadReq accesses 1922system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030149 # miss rate for WriteReq accesses 1923system.cpu1.dcache.WriteReq_miss_rate::total 0.030149 # miss rate for WriteReq accesses 1924system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120378 # miss rate for LoadLockedReq accesses 1925system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120378 # miss rate for LoadLockedReq accesses 1926system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108436 # miss rate for StoreCondReq accesses 1927system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108436 # miss rate for StoreCondReq accesses 1928system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026522 # miss rate for demand accesses 1929system.cpu1.dcache.demand_miss_rate::total 0.026522 # miss rate for demand accesses 1930system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026522 # miss rate for overall accesses 1931system.cpu1.dcache.overall_miss_rate::total 0.026522 # miss rate for overall accesses 1932system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221 # average ReadReq miss latency 1933system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221 # average ReadReq miss latency 1934system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489 # average WriteReq miss latency 1935system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489 # average WriteReq miss latency 1936system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8600.877584 # average LoadLockedReq miss latency 1937system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8600.877584 # average LoadLockedReq miss latency 1938system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5168.932823 # average StoreCondReq miss latency 1939system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5168.932823 # average StoreCondReq miss latency 1940system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency 1941system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587 # average overall miss latency 1942system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency 1943system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587 # average overall miss latency | 1515system.cpu1.dcache.tags.replacements 343803 # number of replacements 1516system.cpu1.dcache.tags.tagsinuse 472.607785 # Cycle average of tags in use 1517system.cpu1.dcache.tags.total_refs 13921652 # Total number of references to valid blocks. 1518system.cpu1.dcache.tags.sampled_refs 344315 # Sample count of references to valid blocks. 1519system.cpu1.dcache.tags.avg_refs 40.432894 # Average number of references to valid blocks. 1520system.cpu1.dcache.tags.warmup_cycle 85311468250 # Cycle when the warmup percentage was hit. 1521system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.607785 # Average occupied blocks per requestor 1522system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923062 # Average percentage of cache occupancy 1523system.cpu1.dcache.tags.occ_percent::total 0.923062 # Average percentage of cache occupancy 1524system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1525system.cpu1.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 1526system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 1527system.cpu1.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 1528system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1529system.cpu1.dcache.tags.tag_accesses 57519242 # Number of tag accesses 1530system.cpu1.dcache.tags.data_accesses 57519242 # Number of data accesses 1531system.cpu1.dcache.ReadReq_hits::cpu1.data 8078143 # number of ReadReq hits 1532system.cpu1.dcache.ReadReq_hits::total 8078143 # number of ReadReq hits 1533system.cpu1.dcache.WriteReq_hits::cpu1.data 5612875 # number of WriteReq hits 1534system.cpu1.dcache.WriteReq_hits::total 5612875 # number of WriteReq hits 1535system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100617 # number of LoadLockedReq hits 1536system.cpu1.dcache.LoadLockedReq_hits::total 100617 # number of LoadLockedReq hits 1537system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102310 # number of StoreCondReq hits 1538system.cpu1.dcache.StoreCondReq_hits::total 102310 # number of StoreCondReq hits 1539system.cpu1.dcache.demand_hits::cpu1.data 13691018 # number of demand (read+write) hits 1540system.cpu1.dcache.demand_hits::total 13691018 # number of demand (read+write) hits 1541system.cpu1.dcache.overall_hits::cpu1.data 13691018 # number of overall hits 1542system.cpu1.dcache.overall_hits::total 13691018 # number of overall hits 1543system.cpu1.dcache.ReadReq_misses::cpu1.data 207066 # number of ReadReq misses 1544system.cpu1.dcache.ReadReq_misses::total 207066 # number of ReadReq misses 1545system.cpu1.dcache.WriteReq_misses::cpu1.data 165297 # number of WriteReq misses 1546system.cpu1.dcache.WriteReq_misses::total 165297 # number of WriteReq misses 1547system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11987 # number of LoadLockedReq misses 1548system.cpu1.dcache.LoadLockedReq_misses::total 11987 # number of LoadLockedReq misses 1549system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9884 # number of StoreCondReq misses 1550system.cpu1.dcache.StoreCondReq_misses::total 9884 # number of StoreCondReq misses 1551system.cpu1.dcache.demand_misses::cpu1.data 372363 # number of demand (read+write) misses 1552system.cpu1.dcache.demand_misses::total 372363 # number of demand (read+write) misses 1553system.cpu1.dcache.overall_misses::cpu1.data 372363 # number of overall misses 1554system.cpu1.dcache.overall_misses::total 372363 # number of overall misses 1555system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2696827750 # number of ReadReq miss cycles 1556system.cpu1.dcache.ReadReq_miss_latency::total 2696827750 # number of ReadReq miss cycles 1557system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6860807042 # number of WriteReq miss cycles 1558system.cpu1.dcache.WriteReq_miss_latency::total 6860807042 # number of WriteReq miss cycles 1559system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 107474000 # number of LoadLockedReq miss cycles 1560system.cpu1.dcache.LoadLockedReq_miss_latency::total 107474000 # number of LoadLockedReq miss cycles 1561system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50841959 # number of StoreCondReq miss cycles 1562system.cpu1.dcache.StoreCondReq_miss_latency::total 50841959 # number of StoreCondReq miss cycles 1563system.cpu1.dcache.demand_miss_latency::cpu1.data 9557634792 # number of demand (read+write) miss cycles 1564system.cpu1.dcache.demand_miss_latency::total 9557634792 # number of demand (read+write) miss cycles 1565system.cpu1.dcache.overall_miss_latency::cpu1.data 9557634792 # number of overall miss cycles 1566system.cpu1.dcache.overall_miss_latency::total 9557634792 # number of overall miss cycles 1567system.cpu1.dcache.ReadReq_accesses::cpu1.data 8285209 # number of ReadReq accesses(hits+misses) 1568system.cpu1.dcache.ReadReq_accesses::total 8285209 # number of ReadReq accesses(hits+misses) 1569system.cpu1.dcache.WriteReq_accesses::cpu1.data 5778172 # number of WriteReq accesses(hits+misses) 1570system.cpu1.dcache.WriteReq_accesses::total 5778172 # number of WriteReq accesses(hits+misses) 1571system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112604 # number of LoadLockedReq accesses(hits+misses) 1572system.cpu1.dcache.LoadLockedReq_accesses::total 112604 # number of LoadLockedReq accesses(hits+misses) 1573system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112194 # number of StoreCondReq accesses(hits+misses) 1574system.cpu1.dcache.StoreCondReq_accesses::total 112194 # number of StoreCondReq accesses(hits+misses) 1575system.cpu1.dcache.demand_accesses::cpu1.data 14063381 # number of demand (read+write) accesses 1576system.cpu1.dcache.demand_accesses::total 14063381 # number of demand (read+write) accesses 1577system.cpu1.dcache.overall_accesses::cpu1.data 14063381 # number of overall (read+write) accesses 1578system.cpu1.dcache.overall_accesses::total 14063381 # number of overall (read+write) accesses 1579system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024992 # miss rate for ReadReq accesses 1580system.cpu1.dcache.ReadReq_miss_rate::total 0.024992 # miss rate for ReadReq accesses 1581system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses 1582system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses 1583system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106453 # miss rate for LoadLockedReq accesses 1584system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106453 # miss rate for LoadLockedReq accesses 1585system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088097 # miss rate for StoreCondReq accesses 1586system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088097 # miss rate for StoreCondReq accesses 1587system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026477 # miss rate for demand accesses 1588system.cpu1.dcache.demand_miss_rate::total 0.026477 # miss rate for demand accesses 1589system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026477 # miss rate for overall accesses 1590system.cpu1.dcache.overall_miss_rate::total 0.026477 # miss rate for overall accesses 1591system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802 # average ReadReq miss latency 1592system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802 # average ReadReq miss latency 1593system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051 # average WriteReq miss latency 1594system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051 # average WriteReq miss latency 1595system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8965.879703 # average LoadLockedReq miss latency 1596system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8965.879703 # average LoadLockedReq miss latency 1597system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5143.864731 # average StoreCondReq miss latency 1598system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5143.864731 # average StoreCondReq miss latency 1599system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency 1600system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113 # average overall miss latency 1601system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency 1602system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113 # average overall miss latency |
| 1944system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1945system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1946system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1947system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1948system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1949system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1950system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1951system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1603system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1604system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1605system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1606system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1607system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1608system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1609system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1610system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1952system.cpu1.dcache.writebacks::writebacks 264874 # number of writebacks 1953system.cpu1.dcache.writebacks::total 264874 # number of writebacks 1954system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170735 # number of ReadReq MSHR misses 1955system.cpu1.dcache.ReadReq_mshr_misses::total 170735 # number of ReadReq MSHR misses 1956system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150073 # number of WriteReq MSHR misses 1957system.cpu1.dcache.WriteReq_mshr_misses::total 150073 # number of WriteReq MSHR misses 1958system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11224 # number of LoadLockedReq MSHR misses 1959system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11224 # number of LoadLockedReq MSHR misses 1960system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses 1961system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses 1962system.cpu1.dcache.demand_mshr_misses::cpu1.data 320808 # number of demand (read+write) MSHR misses 1963system.cpu1.dcache.demand_mshr_misses::total 320808 # number of demand (read+write) MSHR misses 1964system.cpu1.dcache.overall_mshr_misses::cpu1.data 320808 # number of overall MSHR misses 1965system.cpu1.dcache.overall_mshr_misses::total 320808 # number of overall MSHR misses 1966system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877877002 # number of ReadReq MSHR miss cycles 1967system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877877002 # number of ReadReq MSHR miss cycles 1968system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6244849733 # number of WriteReq MSHR miss cycles 1969system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6244849733 # number of WriteReq MSHR miss cycles 1970system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74077750 # number of LoadLockedReq MSHR miss cycles 1971system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74077750 # number of LoadLockedReq MSHR miss cycles 1972system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31889029 # number of StoreCondReq MSHR miss cycles 1973system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31889029 # number of StoreCondReq MSHR miss cycles 1974system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8122726735 # number of demand (read+write) MSHR miss cycles 1975system.cpu1.dcache.demand_mshr_miss_latency::total 8122726735 # number of demand (read+write) MSHR miss cycles 1976system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8122726735 # number of overall MSHR miss cycles 1977system.cpu1.dcache.overall_mshr_miss_latency::total 8122726735 # number of overall MSHR miss cycles 1978system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250 # number of ReadReq MSHR uncacheable cycles 1979system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250 # number of ReadReq MSHR uncacheable cycles 1980system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182609871 # number of WriteReq MSHR uncacheable cycles 1981system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182609871 # number of WriteReq MSHR uncacheable cycles 1982system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121 # number of overall MSHR uncacheable cycles 1983system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121 # number of overall MSHR uncacheable cycles 1984system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023986 # mshr miss rate for ReadReq accesses 1985system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023986 # mshr miss rate for ReadReq accesses 1986system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030149 # mshr miss rate for WriteReq accesses 1987system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030149 # mshr miss rate for WriteReq accesses 1988system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120378 # mshr miss rate for LoadLockedReq accesses 1989system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120378 # mshr miss rate for LoadLockedReq accesses 1990system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108426 # mshr miss rate for StoreCondReq accesses 1991system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108426 # mshr miss rate for StoreCondReq accesses 1992system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for demand accesses 1993system.cpu1.dcache.demand_mshr_miss_rate::total 0.026522 # mshr miss rate for demand accesses 1994system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for overall accesses 1995system.cpu1.dcache.overall_mshr_miss_rate::total 0.026522 # mshr miss rate for overall accesses 1996system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749 # average ReadReq mshr miss latency 1997system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749 # average ReadReq mshr miss latency 1998system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341 # average WriteReq mshr miss latency 1999system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341 # average WriteReq mshr miss latency 2000system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6599.942088 # average LoadLockedReq mshr miss latency 2001system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6599.942088 # average LoadLockedReq mshr miss latency 2002system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3169.253528 # average StoreCondReq mshr miss latency 2003system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3169.253528 # average StoreCondReq mshr miss latency 2004system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency 2005system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency 2006system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency 2007system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency | 1611system.cpu1.dcache.writebacks::writebacks 315335 # number of writebacks 1612system.cpu1.dcache.writebacks::total 315335 # number of writebacks 1613system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207066 # number of ReadReq MSHR misses 1614system.cpu1.dcache.ReadReq_mshr_misses::total 207066 # number of ReadReq MSHR misses 1615system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165297 # number of WriteReq MSHR misses 1616system.cpu1.dcache.WriteReq_mshr_misses::total 165297 # number of WriteReq MSHR misses 1617system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11987 # number of LoadLockedReq MSHR misses 1618system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11987 # number of LoadLockedReq MSHR misses 1619system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9883 # number of StoreCondReq MSHR misses 1620system.cpu1.dcache.StoreCondReq_mshr_misses::total 9883 # number of StoreCondReq MSHR misses 1621system.cpu1.dcache.demand_mshr_misses::cpu1.data 372363 # number of demand (read+write) MSHR misses 1622system.cpu1.dcache.demand_mshr_misses::total 372363 # number of demand (read+write) MSHR misses 1623system.cpu1.dcache.overall_mshr_misses::cpu1.data 372363 # number of overall MSHR misses 1624system.cpu1.dcache.overall_mshr_misses::total 372363 # number of overall MSHR misses 1625system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2282040250 # number of ReadReq MSHR miss cycles 1626system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2282040250 # number of ReadReq MSHR miss cycles 1627system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6506824958 # number of WriteReq MSHR miss cycles 1628system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6506824958 # number of WriteReq MSHR miss cycles 1629system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83489000 # number of LoadLockedReq MSHR miss cycles 1630system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83489000 # number of LoadLockedReq MSHR miss cycles 1631system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31075041 # number of StoreCondReq MSHR miss cycles 1632system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31075041 # number of StoreCondReq MSHR miss cycles 1633system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8788865208 # number of demand (read+write) MSHR miss cycles 1634system.cpu1.dcache.demand_mshr_miss_latency::total 8788865208 # number of demand (read+write) MSHR miss cycles 1635system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8788865208 # number of overall MSHR miss cycles 1636system.cpu1.dcache.overall_mshr_miss_latency::total 8788865208 # number of overall MSHR miss cycles 1637system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250 # number of ReadReq MSHR uncacheable cycles 1638system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250 # number of ReadReq MSHR uncacheable cycles 1639system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25194386277 # number of WriteReq MSHR uncacheable cycles 1640system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25194386277 # number of WriteReq MSHR uncacheable cycles 1641system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527 # number of overall MSHR uncacheable cycles 1642system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527 # number of overall MSHR uncacheable cycles 1643system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024992 # mshr miss rate for ReadReq accesses 1644system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024992 # mshr miss rate for ReadReq accesses 1645system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses 1646system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses 1647system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106453 # mshr miss rate for LoadLockedReq accesses 1648system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106453 # mshr miss rate for LoadLockedReq accesses 1649system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088088 # mshr miss rate for StoreCondReq accesses 1650system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088088 # mshr miss rate for StoreCondReq accesses 1651system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for demand accesses 1652system.cpu1.dcache.demand_mshr_miss_rate::total 0.026477 # mshr miss rate for demand accesses 1653system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for overall accesses 1654system.cpu1.dcache.overall_mshr_miss_rate::total 0.026477 # mshr miss rate for overall accesses 1655system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144 # average ReadReq mshr miss latency 1656system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144 # average ReadReq mshr miss latency 1657system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772 # average WriteReq mshr miss latency 1658system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772 # average WriteReq mshr miss latency 1659system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6964.962042 # average LoadLockedReq mshr miss latency 1660system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6964.962042 # average LoadLockedReq mshr miss latency 1661system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3144.292320 # average StoreCondReq mshr miss latency 1662system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3144.292320 # average StoreCondReq mshr miss latency 1663system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency 1664system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency 1665system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency 1666system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency |
| 2008system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2009system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2010system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2011system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2012system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2013system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2014system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2015system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 2023system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2024system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2025system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2026system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2027system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2028system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2029system.iocache.fast_writes 0 # number of fast writes performed 2030system.iocache.cache_copies 0 # number of cache copies performed | 1667system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1668system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1669system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1670system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1671system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1672system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1673system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1674system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1682system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1683system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1684system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1685system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1686system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1687system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1688system.iocache.fast_writes 0 # number of fast writes performed 1689system.iocache.cache_copies 0 # number of cache copies performed |
| 2031system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501 # number of ReadReq MSHR uncacheable cycles 2032system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501 # number of ReadReq MSHR uncacheable cycles 2033system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501 # number of overall MSHR uncacheable cycles 2034system.iocache.overall_mshr_uncacheable_latency::total 651823594501 # number of overall MSHR uncacheable cycles | 1690system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500 # number of ReadReq MSHR uncacheable cycles 1691system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500 # number of ReadReq MSHR uncacheable cycles 1692system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500 # number of overall MSHR uncacheable cycles 1693system.iocache.overall_mshr_uncacheable_latency::total 746722879500 # number of overall MSHR uncacheable cycles |
| 2035system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2036system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2037system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2038system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2039system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2040 2041---------- End Simulation Statistics ---------- | 1694system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1695system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1696system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1697system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1698system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1699 1700---------- End Simulation Statistics ---------- |