Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

Deleted Added

sdiff udiff text old ( 9838:43d22d746e7a ) new ( 9978:81d7551dd3be )

full compact

3,5c3,5
< sim_seconds 1.194884 # Number of seconds simulated
< sim_ticks 1194883580500 # Number of ticks simulated
< final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.195756 # Number of seconds simulated
> sim_ticks 1195756323500 # Number of ticks simulated
> final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 298011 # Simulator instruction rate (inst/s)
< host_op_rate 379758 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 5802481089 # Simulator tick rate (ticks/s)
< host_mem_usage 399660 # Number of bytes of host memory used
< host_seconds 205.93 # Real time elapsed on the host
< sim_insts 61368273 # Number of instructions simulated
< sim_ops 78202205 # Number of ops (including micro ops) simulated
---
> host_inst_rate 469394 # Simulator instruction rate (inst/s)
> host_op_rate 598174 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9145402965 # Simulator tick rate (ticks/s)
> host_mem_usage 398732 # Number of bytes of host memory used
> host_seconds 130.75 # Real time elapsed on the host
> sim_insts 61373013 # Number of instructions simulated
> sim_ops 78210923 # Number of ops (including micro ops) simulated
17,18c17,18
< system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory
20,26c20,26
< system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory
< system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory
> system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory
29c29
< system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory
33,34c33,34
< system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory
36,39c36,39
< system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory
42,43c42,43
< system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s)
46,47c46,47
< system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s)
49,56c49,56
< system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s)
58,60c58,60
< system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s)
63,64c63,64
< system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s)
66,145c66,147
< system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 425896384 # Total number of bytes read from memory
< system.physmem.bytesWritten 52573888 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1194879167500 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 6825 # Categorize read packet sizes
< system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 159742 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 756836 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 64631 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see
---
> system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 6654771 # Number of read requests accepted
> system.physmem.writeReqs 821574 # Number of write requests accepted
> system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 415729 # Per bank write bursts
> system.physmem.perBankRdBursts::1 415559 # Per bank write bursts
> system.physmem.perBankRdBursts::2 414962 # Per bank write bursts
> system.physmem.perBankRdBursts::3 415336 # Per bank write bursts
> system.physmem.perBankRdBursts::4 422370 # Per bank write bursts
> system.physmem.perBankRdBursts::5 415375 # Per bank write bursts
> system.physmem.perBankRdBursts::6 415451 # Per bank write bursts
> system.physmem.perBankRdBursts::7 415289 # Per bank write bursts
> system.physmem.perBankRdBursts::8 415350 # Per bank write bursts
> system.physmem.perBankRdBursts::9 415631 # Per bank write bursts
> system.physmem.perBankRdBursts::10 415265 # Per bank write bursts
> system.physmem.perBankRdBursts::11 414898 # Per bank write bursts
> system.physmem.perBankRdBursts::12 415464 # Per bank write bursts
> system.physmem.perBankRdBursts::13 416088 # Per bank write bursts
> system.physmem.perBankRdBursts::14 415829 # Per bank write bursts
> system.physmem.perBankRdBursts::15 415792 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7314 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7200 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6696 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6864 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7395 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6961 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7170 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6990 # Per bank write bursts
> system.physmem.perBankWrBursts::8 6985 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7249 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6972 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6687 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7224 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7527 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7429 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7403 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 1195751937000 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 6825 # Read request sizes (log2)
> system.physmem.readPktSize::3 6488064 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 159882 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 756836 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 64738 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see
160,182c162,184
< system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see
184c186
< system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
192,467c194,610
< system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation
< system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests
< system.physmem.totBusLat 33270500000 # Total cycles spent in databus access
< system.physmem.totBankLat 8590725000 # Total cycles spent in bank access
< system.physmem.avgQLat 19013.79 # Average queueing delay per request
< system.physmem.avgBankLat 1291.04 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 25304.84 # Average memory access latency
< system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
< system.physmem.busUtil 3.13 # Data bus utilization in percentage
< system.physmem.avgRdQLen 0.14 # Average read queue length over time
< system.physmem.avgWrQLen 14.04 # Average write queue length over time
< system.physmem.readRowHits 6636405 # Number of row buffer hits during reads
< system.physmem.writeRowHits 97666 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes
< system.physmem.avgGap 159826.58 # Average gap between requests
---
> system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11968-11975 1 0.00% 84.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12032-12039 17 0.02% 84.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12288-12295 176 0.23% 84.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation
> system.physmem.totQLat 159590177750 # Total ticks spent queuing
> system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks
> system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
> system.physmem.busUtil 2.83 # Data bus utilization in percentage
> system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing
> system.physmem.readRowHits 6598517 # Number of row buffer hits during reads
> system.physmem.writeRowHits 94894 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes
> system.physmem.avgGap 159938.04 # Average gap between requests
> system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state
486,497c629,640
< system.membus.throughput 60029719 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 7703148 # Transaction distribution
< system.membus.trans_dist::ReadResp 7703148 # Transaction distribution
< system.membus.trans_dist::WriteReq 767203 # Transaction distribution
< system.membus.trans_dist::WriteResp 767203 # Transaction distribution
< system.membus.trans_dist::Writeback 64631 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution
< system.membus.trans_dist::ReadExReq 137763 # Transaction distribution
< system.membus.trans_dist::ReadExResp 137302 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes)
---
> system.membus.throughput 59999152 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 7703168 # Transaction distribution
> system.membus.trans_dist::ReadResp 7703168 # Transaction distribution
> system.membus.trans_dist::WriteReq 767205 # Transaction distribution
> system.membus.trans_dist::WriteResp 767205 # Transaction distribution
> system.membus.trans_dist::Writeback 64738 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution
> system.membus.trans_dist::ReadExReq 137900 # Transaction distribution
> system.membus.trans_dist::ReadExResp 137428 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes)
499c642
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes)
501,503c644,646
< system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes)
506,507c649,650
< system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes)
509c652
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes)
511,513c654,656
< system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes)
516,517c659,660
< system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 71728526 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 71744366 # Total data (bytes)
519c662
< system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks)
523c666
< system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks)
527c670
< system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks)
529c672
< system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks)
531c674
< system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks)
533c676
< system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks)
535,539c678,682
< system.l2c.tags.replacements 69624 # number of replacements
< system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use
< system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 69764 # number of replacements
> system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use
> system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks.
541,549c684,692
< system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy
552,553c695,696
< system.l2c.tags.occ_percent::cpu0.inst 0.070781 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.088346 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy
555,595c698,738
< system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.011548 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 1438 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 483013 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 241892 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 1869 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 372280 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 110462 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1219260 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 576006 # number of Writeback hits
< system.l2c.Writeback_hits::total 576006 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 1292 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 416 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1708 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 65542 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 45349 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 110891 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 1438 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 483013 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 307434 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 1869 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 372280 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 155811 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1330151 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 1438 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 483013 # number of overall hits
< system.l2c.overall_hits::cpu0.data 307434 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 1869 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 372280 # number of overall hits
< system.l2c.overall_hits::cpu1.data 155811 # number of overall hits
< system.l2c.overall_hits::total 1330151 # number of overall hits
---
> system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits
> system.l2c.Writeback_hits::total 576824 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits
> system.l2c.overall_hits::cpu0.data 307663 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits
> system.l2c.overall_hits::cpu1.data 156291 # number of overall hits
> system.l2c.overall_hits::total 1331260 # number of overall hits
598,599c741,742
< system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 9716 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.inst 6835 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 9720 # number of ReadReq misses
601,612c744,755
< system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 22441 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 3974 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 7345 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 385 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 476 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 44603 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139739 # number of ReadExReq misses
---
> system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1892 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 22455 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3383 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 7371 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 866 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 95249 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 44598 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 139847 # number of ReadExReq misses
615,616c758,759
< system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 104852 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 6835 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 104969 # number of demand (read+write) misses
618,620c761,763
< system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 46493 # number of demand (read+write) misses
< system.l2c.demand_misses::total 162180 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 46490 # number of demand (read+write) misses
> system.l2c.demand_misses::total 162302 # number of demand (read+write) misses
623,624c766,767
< system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses
< system.l2c.overall_misses::cpu0.data 104852 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 6835 # number of overall misses
> system.l2c.overall_misses::cpu0.data 104969 # number of overall misses
626,765c769,908
< system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses
< system.l2c.overall_misses::cpu1.data 46493 # number of overall misses
< system.l2c.overall_misses::total 162180 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 687750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 482771250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 688091749 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 282183750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 151111000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1605057249 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 11611000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 12427970 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 24038970 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1906918 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117452 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 3024370 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 6193599427 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 2824169884 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 9017769311 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 687750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 482771250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 6881691176 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 282183750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 2975280884 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 10622826560 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 687750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 482771250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 6881691176 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 282183750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 2975280884 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 10622826560 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 1440 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 489845 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 251608 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 1870 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 376276 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 112352 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1241701 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 576006 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 576006 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 5266 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 3787 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 9053 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 640 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1216 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 160678 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 89952 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 250630 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 1440 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 489845 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 1870 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 376276 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 202304 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1492331 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 1440 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 489845 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 1870 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 376276 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 202304 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1492331 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001389 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.013947 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.038616 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.010620 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.016822 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754652 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890151 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.811333 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601562 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826389 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.708059 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.592091 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.495853 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.557551 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.001389 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.013947 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.254319 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.010620 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.229818 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.108676 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.001389 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.013947 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.254319 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.010620 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.229818 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.108676 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 71523.428056 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2921.741319 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3686.730940 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 3272.834581 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4953.033766 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2347.588235 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3512.624855 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 64532.945785 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 65500.225429 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 65500.225429 # average overall miss latency
---
> system.l2c.overall_misses::cpu1.inst 4001 # number of overall misses
> system.l2c.overall_misses::cpu1.data 46490 # number of overall misses
> system.l2c.overall_misses::total 162302 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 302000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 491601250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 735185497 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 283983750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 151633750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1662931247 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 11383008 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 12410968 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 23793976 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1839921 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117953 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 2957874 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 6545912193 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 3449006386 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 9994918579 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 302000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 491601250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 7281097690 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 283983750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 3600640136 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 11657849826 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 302000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 491601250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 7281097690 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 283983750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 3600640136 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 11657849826 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 4690 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 1512 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 490005 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 251761 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 3562 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 1810 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 376570 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 112888 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1242798 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 576824 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 576824 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 5277 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 3835 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 9112 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 655 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1232 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 160871 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 89893 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 250764 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 4690 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 1512 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 490005 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 412632 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 3562 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 1810 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 376570 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 202781 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1493562 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 4690 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 1512 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 490005 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 412632 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 3562 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 1810 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 376570 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 202781 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1493562 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001323 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.013949 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.038608 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000552 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.010625 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.016760 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.018068 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.755732 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.882138 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.808933 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.590840 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830156 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.702922 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.592083 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.496123 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.557684 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.001323 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.013949 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.254389 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.000552 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.010625 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.229262 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.108668 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.001323 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.013949 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.254389 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.000552 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.010625 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.229262 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.108668 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71924.103877 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 75636.368004 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 75000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70978.192952 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 80144.688161 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 74056.167758 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2854.314945 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3668.627845 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 3228.052639 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4754.317829 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2333.931106 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3415.558891 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68724.209105 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77335.449706 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 71470.382482 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 71828.134133 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 71924.103877 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 75000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 71828.134133 # average overall miss latency
774,775c917,918
< system.l2c.writebacks::writebacks 64631 # number of writebacks
< system.l2c.writebacks::total 64631 # number of writebacks
---
> system.l2c.writebacks::writebacks 64738 # number of writebacks
> system.l2c.writebacks::total 64738 # number of writebacks
784,785c927,928
< system.l2c.ReadReq_mshr_misses::cpu0.inst 6831 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 9716 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 6834 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 9720 # number of ReadReq MSHR misses
787,798c930,941
< system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 22440 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 3974 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 7345 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 385 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 476 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 95136 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 44603 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139739 # number of ReadExReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu1.inst 4001 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 1892 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 22454 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 3988 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 3383 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 7371 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 387 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 866 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 95249 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 44598 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 139847 # number of ReadExReq MSHR misses
801,802c944,945
< system.l2c.demand_mshr_misses::cpu0.inst 6831 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 104852 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 6834 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 104969 # number of demand (read+write) MSHR misses
804,806c947,949
< system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 46493 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 162179 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 4001 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 46490 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 162301 # number of demand (read+write) MSHR misses
809,810c952,953
< system.l2c.overall_mshr_misses::cpu0.inst 6831 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 104852 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 6834 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 104969 # number of overall MSHR misses
812,926c955,1069
< system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 46493 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 162179 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 635750 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 396501000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 564859249 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles
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< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39771967 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33821856 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 73593823 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3851884 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768975 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 8620859 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5000986069 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2264195114 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 7265181183 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 635750 # number of demand (read+write) MSHR miss cycles
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< system.l2c.demand_mshr_miss_latency::total 8586175182 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 635750 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 396501000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 5565845318 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 231739250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 2391280114 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 8586175182 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 323836500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647640494 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272049535 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486218500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 16758268035 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 323836500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919690029 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 183805138029 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038616 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016822 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.018072 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754652 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890151 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.811333 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601562 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826389 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708059 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592091 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495853 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.557551 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.108675 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.108675 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency
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< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency
---
> system.l2c.overall_mshr_misses::cpu1.inst 4001 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 46490 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 162301 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 254000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 405760500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 614009497 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233748250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 128083750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 1382043497 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39929483 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33964367 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 73893850 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3876386 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4797478 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 8673864 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5351778297 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2889281614 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 8241059911 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 254000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 405760500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 5965787794 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 233748250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 3017365364 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 9623103408 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 254000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 405760500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 5965787794 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 233748250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 3017365364 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 9623103408 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648858491 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5098250 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154081373749 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272206162 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 16758418162 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5098250 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154567585749 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency
947,978c1090,1121
< system.toL2Bus.throughput 118384606 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 137140510 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks)
---
> system.toL2Bus.throughput 118413539 # Throughput (bytes/s)
> system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.data_through_bus 137274438 # Total data (bytes)
> system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes)
> system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks)
980c1123
< system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks)
982c1125
< system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks)
984c1127
< system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks)
986c1129
< system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks)
988c1131
< system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks)
990c1133
< system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks)
992c1135
< system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks)
994c1137
< system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks)
996,998c1139,1141
< system.iobus.throughput 45439063 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution
---
> system.iobus.throughput 45405912 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution
1002c1145
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes)
1004c1147
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes)
1024c1167
< system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes)
1027c1170
< system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes)
1029c1172
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes)
1031c1174
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes)
1051c1194
< system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes)
1054,1055c1197,1198
< system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 54294390 # Total data (bytes)
---
> system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 54294406 # Total data (bytes)
1058c1201
< system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks)
1062c1205
< system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks)
1104c1247
< system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks)
1106c1249
< system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks)
1110,1113c1253,1256
< system.cpu0.dtb.read_hits 9653247 # DTB read hits
< system.cpu0.dtb.read_misses 3738 # DTB read misses
< system.cpu0.dtb.write_hits 7597488 # DTB write hits
< system.cpu0.dtb.write_misses 1585 # DTB write misses
---
> system.cpu0.dtb.read_hits 9652613 # DTB read hits
> system.cpu0.dtb.read_misses 3746 # DTB read misses
> system.cpu0.dtb.write_hits 7596890 # DTB write hits
> system.cpu0.dtb.write_misses 1582 # DTB write misses
1120c1263
< system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
1123,1124c1266,1267
< system.cpu0.dtb.read_accesses 9656985 # DTB read accesses
< system.cpu0.dtb.write_accesses 7599073 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 9656359 # DTB read accesses
> system.cpu0.dtb.write_accesses 7598472 # DTB write accesses
1126,1129c1269,1272
< system.cpu0.dtb.hits 17250735 # DTB hits
< system.cpu0.dtb.misses 5323 # DTB misses
< system.cpu0.dtb.accesses 17256058 # DTB accesses
< system.cpu0.itb.inst_hits 43297764 # ITB inst hits
---
> system.cpu0.dtb.hits 17249503 # DTB hits
> system.cpu0.dtb.misses 5328 # DTB misses
> system.cpu0.dtb.accesses 17254831 # DTB accesses
> system.cpu0.itb.inst_hits 43298526 # ITB inst hits
1146,1147c1289,1290
< system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses
< system.cpu0.itb.hits 43297764 # DTB hits
---
> system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses
> system.cpu0.itb.hits 43298526 # DTB hits
1149,1150c1292,1293
< system.cpu0.itb.accesses 43299969 # DTB accesses
< system.cpu0.numCycles 2389767161 # number of cpu cycles simulated
---
> system.cpu0.itb.accesses 43300731 # DTB accesses
> system.cpu0.numCycles 2391512647 # number of cpu cycles simulated
1153,1155c1296,1298
< system.cpu0.committedInsts 42570861 # Number of instructions committed
< system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses
---
> system.cpu0.committedInsts 42571581 # Number of instructions committed
> system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses
1157,1159c1300,1302
< system.cpu0.num_func_calls 1403492 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 48060351 # number of integer instructions
---
> system.cpu0.num_func_calls 1403638 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 48058821 # number of integer instructions
1161,1162c1304,1305
< system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written
1165,1171c1308,1314
< system.cpu0.num_mem_refs 18020156 # number of memory refs
< system.cpu0.num_load_insts 10037111 # Number of load instructions
< system.cpu0.num_store_insts 7983045 # Number of store instructions
< system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles
< system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles
---
> system.cpu0.num_mem_refs 18019009 # number of memory refs
> system.cpu0.num_load_insts 10036459 # Number of load instructions
> system.cpu0.num_store_insts 7982550 # Number of store instructions
> system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles
> system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles
1173,1218c1316,1361
< system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed
< system.cpu0.icache.tags.replacements 490078 # number of replacements
< system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits
< system.cpu0.icache.overall_hits::total 42807156 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses
< system.cpu0.icache.overall_misses::total 490591 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency
---
> system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed
> system.cpu0.icache.tags.replacements 490259 # number of replacements
> system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits
> system.cpu0.icache.overall_hits::total 42807737 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses
> system.cpu0.icache.overall_misses::total 490772 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency
1227,1254c1370,1397
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency
1260,1340c1403,1483
< system.cpu0.dcache.tags.replacements 406634 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits
< system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 176685 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9910 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 9910 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7384 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7384 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 440354 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 440354 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 440354 # number of overall misses
< system.cpu0.dcache.overall_misses::total 440354 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3876875497 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 3876875497 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7541622539 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 7541622539 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98733750 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 98733750 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40506385 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 40506385 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 11418498036 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 11418498036 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 11418498036 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 11418498036 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401016 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 9401016 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671597 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.028047 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026483 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.026483 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059540 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059540 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044378 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044378 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency
---
> system.cpu0.dcache.tags.replacements 407019 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 470.951702 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 15966189 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 407531 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 39.177852 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.951702 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919828 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.919828 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 9136364 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 9136364 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 6494337 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 6494337 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156491 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 156491 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158920 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 158920 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 15630701 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 15630701 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 15630701 # number of overall hits
> system.cpu0.dcache.overall_hits::total 15630701 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 264039 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 264039 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 176698 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 176698 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9925 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 9925 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7429 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 7429 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 440737 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 440737 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 440737 # number of overall misses
> system.cpu0.dcache.overall_misses::total 440737 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3925412746 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 3925412746 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7893125788 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 7893125788 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98805250 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 98805250 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40843887 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 40843887 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11818538534 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11818538534 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11818538534 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11818538534 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400403 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 9400403 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671035 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 6671035 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166416 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 166416 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059640 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059640 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044659 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044659 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027424 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.027424 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency
1349,1370c1492,1513
< system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks
< system.cpu0.dcache.writebacks::total 376568 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles
---
> system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks
> system.cpu0.dcache.writebacks::total 376552 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles
1373,1402c1516,1545
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency
1405,1408c1548,1551
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency
1418,1421c1561,1564
< system.cpu1.dtb.read_hits 5705173 # DTB read hits
< system.cpu1.dtb.read_misses 3576 # DTB read misses
< system.cpu1.dtb.write_hits 3872049 # DTB write hits
< system.cpu1.dtb.write_misses 645 # DTB write misses
---
> system.cpu1.dtb.read_hits 5708064 # DTB read hits
> system.cpu1.dtb.read_misses 3582 # DTB read misses
> system.cpu1.dtb.write_hits 3874465 # DTB write hits
> system.cpu1.dtb.write_misses 647 # DTB write misses
1428c1571
< system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
1431,1432c1574,1575
< system.cpu1.dtb.read_accesses 5708749 # DTB read accesses
< system.cpu1.dtb.write_accesses 3872694 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 5711646 # DTB read accesses
> system.cpu1.dtb.write_accesses 3875112 # DTB write accesses
1434,1437c1577,1580
< system.cpu1.dtb.hits 9577222 # DTB hits
< system.cpu1.dtb.misses 4221 # DTB misses
< system.cpu1.dtb.accesses 9581443 # DTB accesses
< system.cpu1.itb.inst_hits 19377969 # ITB inst hits
---
> system.cpu1.dtb.hits 9582529 # DTB hits
> system.cpu1.dtb.misses 4229 # DTB misses
> system.cpu1.dtb.accesses 9586758 # DTB accesses
> system.cpu1.itb.inst_hits 19382020 # ITB inst hits
1454,1455c1597,1598
< system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses
< system.cpu1.itb.hits 19377969 # DTB hits
---
> system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses
> system.cpu1.itb.hits 19382020 # DTB hits
1457,1458c1600,1601
< system.cpu1.itb.accesses 19380140 # DTB accesses
< system.cpu1.numCycles 2388332817 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 19384191 # DTB accesses
> system.cpu1.numCycles 2390063941 # number of cpu cycles simulated
1461,1463c1604,1606
< system.cpu1.committedInsts 18797412 # Number of instructions committed
< system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses
---
> system.cpu1.committedInsts 18801432 # Number of instructions committed
> system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses
1465,1467c1608,1610
< system.cpu1.num_func_calls 796668 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 22263010 # number of integer instructions
---
> system.cpu1.num_func_calls 796781 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 22272671 # number of integer instructions
1469,1470c1612,1613
< system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written
1473,1479c1616,1622
< system.cpu1.num_mem_refs 10012651 # number of memory refs
< system.cpu1.num_load_insts 5981805 # Number of load instructions
< system.cpu1.num_store_insts 4030846 # Number of store instructions
< system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles
< system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles
---
> system.cpu1.num_mem_refs 10017952 # number of memory refs
> system.cpu1.num_load_insts 5984754 # Number of load instructions
> system.cpu1.num_store_insts 4033198 # Number of store instructions
> system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles
> system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles
1481,1526c1624,1669
< system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed
< system.cpu1.icache.tags.replacements 376539 # number of replacements
< system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits
< system.cpu1.icache.overall_hits::total 19000914 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses
< system.cpu1.icache.overall_misses::total 377051 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency
---
> system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed
> system.cpu1.icache.tags.replacements 376793 # number of replacements
> system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits
> system.cpu1.icache.overall_hits::total 19004711 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses
> system.cpu1.icache.overall_misses::total 377305 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency
1535,1562c1678,1705
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency
1568,1648c1711,1791
< system.cpu1.dcache.tags.replacements 220336 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 471.526784 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 8228665 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 220703 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 37.283884 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 106211109000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.526784 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920951 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.920951 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 4388185 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 4388185 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3672248 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3672248 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73451 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 73451 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73727 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 73727 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 8060433 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 8060433 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 8060433 # number of overall hits
< system.cpu1.dcache.overall_hits::total 8060433 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 133748 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 133748 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 112730 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 112730 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9735 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 9735 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9394 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 9394 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 246478 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 246478 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 246478 # number of overall misses
< system.cpu1.dcache.overall_misses::total 246478 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1649486235 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 1649486235 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3739097468 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 3739097468 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77937249 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 77937249 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49168975 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 49168975 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 5388583703 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 5388583703 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 5388583703 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 5388583703 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 4521933 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 4521933 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 3784978 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 3784978 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83186 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 83186 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83121 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 83121 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 8306911 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 8306911 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 8306911 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 8306911 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029578 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.029578 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029784 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.029784 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117027 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117027 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113016 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113016 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029671 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.029671 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029671 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8005.880740 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8005.880740 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5234.082925 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5234.082925 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336 # average overall miss latency
---
> system.cpu1.dcache.tags.replacements 220883 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73485 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 73485 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73732 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 73732 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 8065199 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 8065199 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 8065199 # number of overall hits
> system.cpu1.dcache.overall_hits::total 8065199 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 134090 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 134090 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 112827 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 112827 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9762 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 9762 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9429 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 9429 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 246917 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 246917 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 246917 # number of overall misses
> system.cpu1.dcache.overall_misses::total 246917 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1656976729 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 1656976729 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4353399476 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4353399476 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77544499 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 77544499 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49349978 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 49349978 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6010376205 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6010376205 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6010376205 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6010376205 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524762 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 4524762 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787354 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 3787354 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83247 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 83247 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83161 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 83161 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 8312116 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 8312116 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 8312116 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency
1657,1678c1800,1821
< system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks
< system.cpu1.dcache.writebacks::total 199438 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles
---
> system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks
> system.cpu1.dcache.writebacks::total 200272 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles
1681,1710c1824,1853
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency
1713,1716c1856,1859
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency
1738,1741c1881,1884
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles