3,5c3,5
< sim_seconds 1.183003 # Number of seconds simulated
< sim_ticks 1183003114000 # Number of ticks simulated
< final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.182958 # Number of seconds simulated
> sim_ticks 1182958259000 # Number of ticks simulated
> final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 673901 # Simulator instruction rate (inst/s)
< host_op_rate 858757 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 12970235901 # Simulator tick rate (ticks/s)
< host_mem_usage 408748 # Number of bytes of host memory used
< host_seconds 91.21 # Real time elapsed on the host
< sim_insts 61465824 # Number of instructions simulated
< sim_ops 78326377 # Number of ops (including micro ops) simulated
---
> host_inst_rate 332432 # Simulator instruction rate (inst/s)
> host_op_rate 423606 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 6399087906 # Simulator tick rate (ticks/s)
> host_mem_usage 408760 # Number of bytes of host memory used
> host_seconds 184.86 # Real time elapsed on the host
> sim_insts 61454647 # Number of instructions simulated
> sim_ops 78309315 # Number of ops (including micro ops) simulated
16,18c16,18
< system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory
20,26c20,26
< system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory
< system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory
> system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory
29c29
< system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory
32,34c32,34
< system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory
36,39c36,39
< system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory
42,43c42,43
< system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s)
45,47c45,47
< system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s)
49,60c49,60
< system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s)
62,64c62,64
< system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s)
66,75c66,75
< system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 6654023 # Total number of read requests seen
< system.physmem.writeReqs 820738 # Total number of write requests seen
< system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 425857472 # Total number of bytes read from memory
< system.physmem.bytesWritten 52527232 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 6654489 # Total number of read requests seen
> system.physmem.writeReqs 821150 # Total number of write requests seen
> system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 425887296 # Total number of bytes read from memory
> system.physmem.bytesWritten 52553600 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize()
77,109c77,109
< system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis
---
> system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis
112c112
< system.physmem.totGap 1182998675500 # Total gap between requests
---
> system.physmem.totGap 1182953705000 # Total gap between requests
119,156c119,143
< system.physmem.readPktSize::6 159134 # Categorize read packet sizes
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 756836 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 63902 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see
---
> system.physmem.readPktSize::6 159600 # Categorize read packet sizes
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 756836 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 64314 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see
172,200c159,186
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
202,211c188,196
< system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests
< system.physmem.totBusLat 33269555000 # Total cycles spent in databus access
< system.physmem.totBankLat 9041986250 # Total cycles spent in bank access
< system.physmem.avgQLat 22090.22 # Average queueing delay per request
< system.physmem.avgBankLat 1358.90 # Average bank access latency per request
---
> system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
> system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests
> system.physmem.totBusLat 33271885000 # Total cycles spent in databus access
> system.physmem.totBankLat 9050992500 # Total cycles spent in bank access
> system.physmem.avgQLat 22093.24 # Average queueing delay per request
> system.physmem.avgBankLat 1360.16 # Average bank access latency per request
213,217c198,202
< system.physmem.avgMemAccLat 28449.12 # Average memory access latency
< system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 28453.39 # Average memory access latency
> system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s
221,223c206,208
< system.physmem.avgWrQLen 12.54 # Average write queue length over time
< system.physmem.readRowHits 6611960 # Number of row buffer hits during reads
< system.physmem.writeRowHits 800133 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 12.52 # Average write queue length over time
> system.physmem.readRowHits 6612346 # Number of row buffer hits during reads
> system.physmem.writeRowHits 800481 # Number of row buffer hits during writes
225,226c210,211
< system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes
< system.physmem.avgGap 158265.75 # Average gap between requests
---
> system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes
> system.physmem.avgGap 158241.15 # Average gap between requests
245,249c230,234
< system.l2c.replacements 69015 # number of replacements
< system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use
< system.l2c.total_refs 1678594 # Total number of references to valid blocks.
< system.l2c.sampled_refs 134211 # Sample count of references to valid blocks.
< system.l2c.avg_refs 12.507127 # Average number of references to valid blocks.
---
> system.l2c.replacements 69480 # number of replacements
> system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use
> system.l2c.total_refs 1677464 # Total number of references to valid blocks.
> system.l2c.sampled_refs 134656 # Sample count of references to valid blocks.
> system.l2c.avg_refs 12.457403 # Average number of references to valid blocks.
251c236
< system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor
253,259c238,244
< system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy
262,263c247,248
< system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy
---
> system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy
265,305c250,290
< system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits
< system.l2c.Writeback_hits::total 573205 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 3013 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 1662 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 349398 # number of overall hits
< system.l2c.overall_hits::cpu0.data 217423 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 6389 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 534803 # number of overall hits
< system.l2c.overall_hits::cpu1.data 243393 # number of overall hits
< system.l2c.overall_hits::total 1358024 # number of overall hits
---
> system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.data 0.031453 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.809346 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.dtb.walker 3740 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 1661 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 419713 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 206323 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 5388 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 1856 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 464159 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 143887 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1246727 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 572264 # number of Writeback hits
> system.l2c.Writeback_hits::total 572264 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1120 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 606 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1726 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 57066 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 52392 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 109458 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 3740 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 1661 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 419713 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 263389 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5388 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 1856 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 464159 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 196279 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1356185 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 3740 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 1661 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 419713 # number of overall hits
> system.l2c.overall_hits::cpu0.data 263389 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5388 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 1856 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 464159 # number of overall hits
> system.l2c.overall_hits::cpu1.data 196279 # number of overall hits
> system.l2c.overall_hits::total 1356185 # number of overall hits
307,309c292,294
< system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.inst 5520 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 7838 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses
311,318c296,303
< system.l2c.ReadReq_misses::cpu1.inst 5255 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 3644 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 22265 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 3583 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4723 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 8306 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 461 # number of SCUpgradeReq misses
---
> system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 3624 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 4701 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3596 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 563 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses
320,322c305,307
< system.l2c.ReadExReq_misses::cpu0.data 63840 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 75452 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139292 # number of ReadExReq misses
---
> system.l2c.ReadExReq_misses::cpu0.data 67050 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 72720 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 139770 # number of ReadExReq misses
324,326c309,311
< system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 5520 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 71678 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 74913 # number of demand (read+write) misses
328,330c313,315
< system.l2c.demand_misses::cpu1.inst 5255 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 79096 # number of demand (read+write) misses
< system.l2c.demand_misses::total 161557 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 76344 # number of demand (read+write) misses
> system.l2c.demand_misses::total 162041 # number of demand (read+write) misses
332,334c317,319
< system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 5520 # number of overall misses
< system.l2c.overall_misses::cpu0.data 71678 # number of overall misses
---
> system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses
> system.l2c.overall_misses::cpu0.data 74913 # number of overall misses
336,338c321,323
< system.l2c.overall_misses::cpu1.inst 5255 # number of overall misses
< system.l2c.overall_misses::cpu1.data 79096 # number of overall misses
< system.l2c.overall_misses::total 161557 # number of overall misses
---
> system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses
> system.l2c.overall_misses::cpu1.data 76344 # number of overall misses
> system.l2c.overall_misses::total 162041 # number of overall misses
340,342c325,327
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 151500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 286631500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 416021500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 299840500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 416754500 # number of ReadReq miss cycles
344,355c329,340
< system.l2c.ReadReq_miss_latency::cpu1.inst 290826000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 222550500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1216497500 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 10882997 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 13761999 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 24644996 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1755500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2248500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 4004000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 2848043983 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 3574373499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6422417482 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 276698000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 223564500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1217256500 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 12757497 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 11938999 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 24696496 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1598500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 4007000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 3004157980 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 3438233497 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6442391477 # number of ReadExReq miss cycles
357,359c342,344
< system.l2c.demand_miss_latency::cpu0.itb.walker 151500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 286631500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 3264065483 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 299840500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 3420912480 # number of demand (read+write) miss cycles
361,363c346,348
< system.l2c.demand_miss_latency::cpu1.inst 290826000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 3796923999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 7638914982 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu1.inst 276698000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 3661797997 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 7659647977 # number of demand (read+write) miss cycles
365,367c350,352
< system.l2c.overall_miss_latency::cpu0.itb.walker 151500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 286631500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 3264065483 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 299840500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 3420912480 # number of overall miss cycles
369,442c354,427
< system.l2c.overall_miss_latency::cpu1.inst 290826000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 3796923999 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 7638914982 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 3014 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 1665 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 354918 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 177753 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 6393 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 540058 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 184457 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1270201 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 573205 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 573205 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 4704 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 10038 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 800 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 539 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1339 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 111348 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 138032 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 249380 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 3014 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 1665 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 354918 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 289101 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 6393 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 540058 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 322489 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1519581 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 3014 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 1665 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 354918 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 289101 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 6393 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 540058 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 322489 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1519581 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001802 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.015553 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.009730 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.019755 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.017529 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.761692 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.885452 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.827456 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.713750 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.855288 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.770724 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.573338 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.546627 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.558553 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.001802 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.015553 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.247934 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.009730 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.245267 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.106317 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000332 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.001802 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.015553 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.247934 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.009730 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.245267 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.106317 # miss rate for overall accesses
---
> system.l2c.overall_miss_latency::cpu1.inst 276698000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 3661797997 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 7659647977 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 3741 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 1663 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 425446 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 214186 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 5392 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 1856 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 469203 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 147511 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1268998 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 572264 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 572264 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 5821 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4202 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 10023 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1348 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 124116 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 125112 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 249228 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 3741 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 1663 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 425446 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 338302 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 5392 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 1856 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 469203 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 272623 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1518226 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 3741 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 1663 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 425446 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 338302 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 5392 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 1856 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 469203 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 272623 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1518226 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001203 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.036711 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.024568 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.017550 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807593 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855783 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.827796 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722721 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.824253 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.765579 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.540220 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.581239 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.560812 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.001203 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.221438 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.280035 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.106730 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000267 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.001203 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.221438 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000742 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.280035 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.106730 # miss rate for overall accesses
444,446c429,431
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 50500 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 51925.996377 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 53077.507017 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 41250 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52300.802372 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 53001.971258 # average ReadReq miss latency
448,459c433,444
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55342.721218 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 61073.133919 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 54637.210869 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3037.397991 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2913.825746 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2967.131712 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3074.430823 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4877.440347 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3879.844961 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44612.217779 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47372.813166 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 46107.583221 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54856.859635 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 61689.983444 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 54656.571326 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2713.783663 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3320.077586 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2976.557310 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2839.253996 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5135.394456 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3882.751938 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44804.742431 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47280.438628 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 46092.805874 # average ReadExReq miss latency
461,463c446,448
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency
465,467c450,452
< system.l2c.demand_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 47283.095019 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 47269.814288 # average overall miss latency
469,471c454,456
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 50500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 51925.996377 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 45537.898421 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 41250 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 52300.802372 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 45665.137960 # average overall miss latency
473,475c458,460
< system.l2c.overall_avg_miss_latency::cpu1.inst 55342.721218 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 48003.995132 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 47283.095019 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 54856.859635 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 47964.450343 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 47269.814288 # average overall miss latency
484,485c469,470
< system.l2c.writebacks::writebacks 63902 # number of writebacks
< system.l2c.writebacks::total 63902 # number of writebacks
---
> system.l2c.writebacks::writebacks 64314 # number of writebacks
> system.l2c.writebacks::total 64314 # number of writebacks
493,495c478,480
< system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.inst 5519 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 7838 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses
497,504c482,489
< system.l2c.ReadReq_mshr_misses::cpu1.inst 5255 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 3644 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 22264 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 3583 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 4723 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 8306 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 461 # number of SCUpgradeReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 3624 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 4701 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 3596 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 8297 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 563 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses
506,508c491,493
< system.l2c.ReadExReq_mshr_misses::cpu0.data 63840 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 75452 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139292 # number of ReadExReq MSHR misses
---
> system.l2c.ReadExReq_mshr_misses::cpu0.data 67050 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 72720 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 139770 # number of ReadExReq MSHR misses
510,512c495,497
< system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 5519 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 71678 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 74913 # number of demand (read+write) MSHR misses
514,516c499,501
< system.l2c.demand_mshr_misses::cpu1.inst 5255 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 79096 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 161556 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 76344 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 162040 # number of demand (read+write) MSHR misses
518,520c503,505
< system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 5519 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 71678 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 74913 # number of overall MSHR misses
522,636c507,621
< system.l2c.overall_mshr_misses::cpu1.inst 5255 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 79096 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 161556 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56252 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 113756 # number of ReadReq MSHR miss cycles
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< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 35910048 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47375165 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 83285213 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5731560 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4624957 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356517 # number of SCUpgradeReq MSHR miss cycles
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< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2629528179 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 4669285916 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
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< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56252 # number of overall MSHR miss cycles
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< system.l2c.overall_mshr_miss_latency::cpu0.inst 217401709 # number of overall MSHR miss cycles
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< system.l2c.overall_mshr_miss_latency::cpu1.inst 225003397 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 2806521612 # number of overall MSHR miss cycles
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< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209640082 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11218408858 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082174 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155565109792 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 166996240906 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 994820748 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 9209735788 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209640082 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12213229606 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082174 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 163780024832 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.384690 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31951.092372 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34850.344312 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 33521.565603 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency
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< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency
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< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency
---
> system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 76344 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 162040 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56251 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 57502 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 227938476 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 318715113 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 197504 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213513533 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 178263373 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 938741752 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47096148 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36051561 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 83147709 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5658050 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4702967 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 10361017 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2154770965 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2528315165 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 4683086130 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 57502 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 227938476 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2473486078 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197504 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 213513533 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 2706578538 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 5621827882 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56251 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 57502 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 227938476 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2473486078 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197504 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 213513533 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 2706578538 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 5621827882 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209633632 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12454649323 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082087 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154326885776 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 166994250818 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000448248 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209486413 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 9209934661 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455097571 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082087 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162536372189 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 176204185479 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036711 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024568 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.017549 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.807593 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855783 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.827796 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722721 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.824253 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765579 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540220 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581239 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.560812 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.106730 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000267 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001203 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.221438 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000742 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.280035 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.106730 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40533.525754 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49189.672461 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 42152.750427 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10018.325463 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.461902 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.418465 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10049.822380 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.648188 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.745155 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.778001 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34767.810300 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 33505.660228 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39765.958828 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33018.115387 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42330.200833 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35452.406712 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 34694.074809 # average overall mshr miss latency
659,662c644,647
< system.cpu0.dtb.read_hits 5883553 # DTB read hits
< system.cpu0.dtb.read_misses 2148 # DTB read misses
< system.cpu0.dtb.write_hits 4842455 # DTB write hits
< system.cpu0.dtb.write_misses 405 # DTB write misses
---
> system.cpu0.dtb.read_hits 7073604 # DTB read hits
> system.cpu0.dtb.read_misses 3763 # DTB read misses
> system.cpu0.dtb.write_hits 5658971 # DTB write hits
> system.cpu0.dtb.write_misses 806 # DTB write misses
667c652
< system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
669c654
< system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
671,673c656,658
< system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 5885701 # DTB read accesses
< system.cpu0.dtb.write_accesses 4842860 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 7077367 # DTB read accesses
> system.cpu0.dtb.write_accesses 5659777 # DTB write accesses
675,679c660,664
< system.cpu0.dtb.hits 10726008 # DTB hits
< system.cpu0.dtb.misses 2553 # DTB misses
< system.cpu0.dtb.accesses 10728561 # DTB accesses
< system.cpu0.itb.inst_hits 24779849 # ITB inst hits
< system.cpu0.itb.inst_misses 1350 # ITB inst misses
---
> system.cpu0.dtb.hits 12732575 # DTB hits
> system.cpu0.dtb.misses 4569 # DTB misses
> system.cpu0.dtb.accesses 12737144 # DTB accesses
> system.cpu0.itb.inst_hits 29573368 # ITB inst hits
> system.cpu0.itb.inst_misses 2205 # ITB inst misses
688c673
< system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
695,699c680,684
< system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses
< system.cpu0.itb.hits 24779849 # DTB hits
< system.cpu0.itb.misses 1350 # DTB misses
< system.cpu0.itb.accesses 24781199 # DTB accesses
< system.cpu0.numCycles 2364565551 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses
> system.cpu0.itb.hits 29573368 # DTB hits
> system.cpu0.itb.misses 2205 # DTB misses
> system.cpu0.itb.accesses 29575573 # DTB accesses
> system.cpu0.numCycles 2365916518 # number of cpu cycles simulated
702,720c687,705
< system.cpu0.committedInsts 24381823 # Number of instructions committed
< system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses
< system.cpu0.num_func_calls 1070639 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 28075203 # number of integer instructions
< system.cpu0.num_fp_insts 4364 # number of float instructions
< system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written
< system.cpu0.num_mem_refs 11318426 # number of memory refs
< system.cpu0.num_load_insts 6163151 # Number of load instructions
< system.cpu0.num_store_insts 5155275 # Number of store instructions
< system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles
< system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles
---
> system.cpu0.committedInsts 28875412 # Number of instructions committed
> system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
> system.cpu0.num_func_calls 1241807 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 33109279 # number of integer instructions
> system.cpu0.num_fp_insts 3860 # number of float instructions
> system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
> system.cpu0.num_mem_refs 13400902 # number of memory refs
> system.cpu0.num_load_insts 7411207 # Number of load instructions
> system.cpu0.num_store_insts 5989695 # Number of store instructions
> system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles
> system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles
722,727c707,712
< system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed
< system.cpu0.icache.replacements 354669 # number of replacements
< system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use
< system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks.
---
> system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed
> system.cpu0.icache.replacements 425482 # number of replacements
> system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use
> system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks.
729c714
< system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor
---
> system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor
732,767c717,752
< system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits
< system.cpu0.icache.overall_hits::total 24424650 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses
< system.cpu0.icache.overall_misses::total 355182 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency
---
> system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits
> system.cpu0.icache.overall_hits::total 29147356 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses
> system.cpu0.icache.overall_misses::total 425995 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency
776,787c761,772
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 425995 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 425995 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 425995 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4957951500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4957951500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4957951500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4957951500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4957951500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4957951500 # number of overall MSHR miss cycles
792,803c777,788
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency
809,813c794,798
< system.cpu0.dcache.replacements 279602 # number of replacements
< system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 331027 # number of replacements
> system.cpu0.dcache.tagsinuse 453.640914 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 12276777 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 331539 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 37.029662 # Average number of references to valid blocks.
815,889c800,874
< system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits
< system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses
< system.cpu0.dcache.overall_misses::total 318278 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency
---
> system.cpu0.dcache.occ_blocks::cpu0.data 453.640914 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.886017 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.886017 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6603200 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6603200 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 5353855 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 5353855 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147936 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 147936 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149699 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 149699 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 11957055 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 11957055 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 11957055 # number of overall hits
> system.cpu0.dcache.overall_hits::total 11957055 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 228068 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 228068 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 141674 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 141674 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9338 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 9338 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7490 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 7490 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 369742 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 369742 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 369742 # number of overall misses
> system.cpu0.dcache.overall_misses::total 369742 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3146768000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 3146768000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4132891500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 4132891500 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88585500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 88585500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44513500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 44513500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 7279659500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 7279659500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 7279659500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 7279659500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 6831268 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6831268 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495529 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5495529 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157274 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 157274 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157189 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 157189 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12326797 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12326797 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12326797 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12326797 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033386 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.033386 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025780 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.025780 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059374 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059374 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029995 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.029995 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029995 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.029995 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.498992 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.498992 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29171.841693 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 29171.841693 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9486.560291 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9486.560291 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5943.057410 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5943.057410 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19688.484132 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 19688.484132 # average overall miss latency
898,919c883,904
< system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks
< system.cpu0.dcache.writebacks::total 257540 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles
---
> system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks
> system.cpu0.dcache.writebacks::total 306714 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 369742 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 369742 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 369742 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2690632000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2690632000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3849543500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3849543500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69909500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69909500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29541500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29541500 # number of StoreCondReq MSHR miss cycles
922,951c907,936
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency
954,957c939,942
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency
967,970c952,955
< system.cpu1.dtb.read_hits 9504194 # DTB read hits
< system.cpu1.dtb.read_misses 5263 # DTB read misses
< system.cpu1.dtb.write_hits 6646220 # DTB write hits
< system.cpu1.dtb.write_misses 1833 # DTB write misses
---
> system.cpu1.dtb.read_hits 8309714 # DTB read hits
> system.cpu1.dtb.read_misses 3643 # DTB read misses
> system.cpu1.dtb.write_hits 5826503 # DTB write hits
> system.cpu1.dtb.write_misses 1435 # DTB write misses
975c960
< system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
977c962
< system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
979,981c964,966
< system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 9509457 # DTB read accesses
< system.cpu1.dtb.write_accesses 6648053 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 8313357 # DTB read accesses
> system.cpu1.dtb.write_accesses 5827938 # DTB write accesses
983,987c968,972
< system.cpu1.dtb.hits 16150414 # DTB hits
< system.cpu1.dtb.misses 7096 # DTB misses
< system.cpu1.dtb.accesses 16157510 # DTB accesses
< system.cpu1.itb.inst_hits 37994467 # ITB inst hits
< system.cpu1.itb.inst_misses 3017 # ITB inst misses
---
> system.cpu1.dtb.hits 14136217 # DTB hits
> system.cpu1.dtb.misses 5078 # DTB misses
> system.cpu1.dtb.accesses 14141295 # DTB accesses
> system.cpu1.itb.inst_hits 33189716 # ITB inst hits
> system.cpu1.itb.inst_misses 2171 # ITB inst misses
996c981
< system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
1003,1007c988,992
< system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses
< system.cpu1.itb.hits 37994467 # DTB hits
< system.cpu1.itb.misses 3017 # DTB misses
< system.cpu1.itb.accesses 37997484 # DTB accesses
< system.cpu1.numCycles 2366006228 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses
> system.cpu1.itb.hits 33189716 # DTB hits
> system.cpu1.itb.misses 2171 # DTB misses
> system.cpu1.itb.accesses 33191887 # DTB accesses
> system.cpu1.numCycles 2364475282 # number of cpu cycles simulated
1010,1028c995,1013
< system.cpu1.committedInsts 37084001 # Number of instructions committed
< system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses
< system.cpu1.num_func_calls 1133542 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 42360540 # number of integer instructions
< system.cpu1.num_fp_insts 5457 # number of float instructions
< system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written
< system.cpu1.num_mem_refs 16764021 # number of memory refs
< system.cpu1.num_load_insts 9884261 # Number of load instructions
< system.cpu1.num_store_insts 6879760 # Number of store instructions
< system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles
< system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles
---
> system.cpu1.committedInsts 32579235 # Number of instructions committed
> system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
> system.cpu1.num_func_calls 962009 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 37310899 # number of integer instructions
> system.cpu1.num_fp_insts 6793 # number of float instructions
> system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
> system.cpu1.num_mem_refs 14673985 # number of memory refs
> system.cpu1.num_load_insts 8631614 # Number of load instructions
> system.cpu1.num_store_insts 6042371 # Number of store instructions
> system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles
> system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles
1030,1035c1015,1020
< system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed
< system.cpu1.icache.replacements 540342 # number of replacements
< system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use
< system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks.
---
> system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed
> system.cpu1.icache.replacements 469209 # number of replacements
> system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use
> system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks.
1037,1075c1022,1060
< system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor
< system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy
< system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits
< system.cpu1.icache.overall_hits::total 37453609 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses
< system.cpu1.icache.overall_misses::total 540854 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency
---
> system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor
> system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy
> system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits
> system.cpu1.icache.overall_hits::total 32719991 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses
> system.cpu1.icache.overall_misses::total 469721 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency
1084,1095c1069,1080
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469721 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 469721 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 469721 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 469721 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 469721 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 469721 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5424313000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5424313000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5424313000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5424313000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5424313000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5424313000 # number of overall MSHR miss cycles
1100,1111c1085,1096
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11547.946547 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency
1117,1121c1102,1106
< system.cpu1.dcache.replacements 343957 # number of replacements
< system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks.
---
> system.cpu1.dcache.replacements 292184 # number of replacements
> system.cpu1.dcache.tagsinuse 472.133429 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 11959580 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 292554 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 40.879906 # Average number of references to valid blocks.
1123,1197c1108,1182
< system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits
< system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses
< system.cpu1.dcache.overall_misses::total 372427 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency
---
> system.cpu1.dcache.occ_blocks::cpu1.data 472.133429 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.922136 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.922136 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 6945060 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 6945060 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 4826351 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4826351 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81758 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 81758 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82709 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 82709 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 11771411 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 11771411 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 11771411 # number of overall hits
> system.cpu1.dcache.overall_hits::total 11771411 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 170725 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 170725 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 149867 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 149867 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11052 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 11052 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10028 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 10028 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 320592 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 320592 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 320592 # number of overall misses
> system.cpu1.dcache.overall_misses::total 320592 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2168241500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2168241500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4524943000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4524943000 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92270500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 92270500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51657000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 51657000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6693184500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6693184500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6693184500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6693184500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 7115785 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 7115785 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 4976218 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 4976218 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92810 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 92810 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92737 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 92737 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 12092003 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 12092003 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 12092003 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 12092003 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023992 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030117 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.030117 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119082 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119082 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108134 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108134 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency
1206,1227c1191,1212
< system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks
< system.cpu1.dcache.writebacks::total 315665 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles
---
> system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks
> system.cpu1.dcache.writebacks::total 265550 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles
1230,1259c1215,1244
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency
1262,1265c1247,1250
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency
1287,1290c1272,1275
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles