3,5c3,5
< sim_seconds 1.182883 # Number of seconds simulated
< sim_ticks 1182883275000 # Number of ticks simulated
< final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.182882 # Number of seconds simulated
> sim_ticks 1182882156500 # Number of ticks simulated
> final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,31
< host_inst_rate 656929 # Simulator instruction rate (inst/s)
< host_op_rate 837075 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 12645375755 # Simulator tick rate (ticks/s)
< host_mem_usage 400812 # Number of bytes of host memory used
< host_seconds 93.54 # Real time elapsed on the host
< sim_insts 61450949 # Number of instructions simulated
< sim_ops 78302298 # Number of ops (including micro ops) simulated
---
> host_inst_rate 184229 # Simulator instruction rate (inst/s)
> host_op_rate 234741 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3546252898 # Simulator tick rate (ticks/s)
> host_mem_usage 402168 # Number of bytes of host memory used
> host_seconds 333.56 # Real time elapsed on the host
> sim_insts 61450993 # Number of instructions simulated
> sim_ops 78299715 # Number of ops (including micro ops) simulated
> system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
17,18c35,36
< system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory
21,23c39,41
< system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory
< system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory
> system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory
25,26c43,44
< system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory
---
> system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory
29c47
< system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory
33,34c51,52
< system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory
37,39c55,57
< system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory
42,43c60,61
< system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s)
46,47c64,65
< system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s)
49,55c67,73
< system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s)
57,60c75,78
< system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s)
63,64c81,82
< system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s)
66,75c84,93
< system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 6653924 # Total number of read requests seen
< system.physmem.writeReqs 820678 # Total number of write requests seen
< system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 425851136 # Total number of bytes read from memory
< system.physmem.bytesWritten 52523392 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 6654451 # Total number of read requests seen
> system.physmem.writeReqs 821128 # Total number of write requests seen
> system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 425884864 # Total number of bytes read from memory
> system.physmem.bytesWritten 52552192 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize()
77,79c95,97
< system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis
---
> system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis
81,92c99,110
< system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis
94,95c112,113
< system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis
97,98c115,116
< system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis
100,108c118,126
< system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis
112c130
< system.physmem.totGap 1182878800500 # Total gap between requests
---
> system.physmem.totGap 1182877668000 # Total gap between requests
119c137
< system.physmem.readPktSize::6 159035 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 159562 # Categorize read packet sizes
128c146
< system.physmem.writePktSize::6 63842 # categorize write packet sizes
---
> system.physmem.writePktSize::6 64292 # categorize write packet sizes
137c155
< system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes
---
> system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes
140,156c158,174
< system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see
173,200c191,218
< system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
206,211c224,229
< system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests
< system.physmem.totBusLat 26615168000 # Total cycles spent in databus access
< system.physmem.totBankLat 92915214000 # Total cycles spent in bank access
< system.physmem.avgQLat 536.46 # Average queueing delay per request
< system.physmem.avgBankLat 13964.25 # Average bank access latency per request
---
> system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests
> system.physmem.totBusLat 26617276000 # Total cycles spent in databus access
> system.physmem.totBankLat 8784524000 # Total cycles spent in bank access
> system.physmem.avgQLat 18592.42 # Average queueing delay per request
> system.physmem.avgBankLat 1320.12 # Average bank access latency per request
213,217c231,235
< system.physmem.avgMemAccLat 18500.71 # Average memory access latency
< system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 23912.55 # Average memory access latency
> system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s
220,249c238,249
< system.physmem.avgRdQLen 0.10 # Average read queue length over time
< system.physmem.avgWrQLen 15.10 # Average write queue length over time
< system.physmem.readRowHits 6624970 # Number of row buffer hits during reads
< system.physmem.writeRowHits 788587 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes
< system.physmem.avgGap 158253.08 # Average gap between requests
< system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
< system.l2c.replacements 68922 # number of replacements
< system.l2c.tagsinuse 53038.398444 # Cycle average of tags in use
< system.l2c.total_refs 1676342 # Total number of references to valid blocks.
< system.l2c.sampled_refs 134082 # Sample count of references to valid blocks.
< system.l2c.avg_refs 12.502364 # Average number of references to valid blocks.
---
> system.physmem.avgRdQLen 0.13 # Average read queue length over time
> system.physmem.avgWrQLen 15.12 # Average write queue length over time
> system.physmem.readRowHits 6628163 # Number of row buffer hits during reads
> system.physmem.writeRowHits 789308 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes
> system.physmem.avgGap 158232.25 # Average gap between requests
> system.l2c.replacements 69442 # number of replacements
> system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use
> system.l2c.total_refs 1672967 # Total number of references to valid blocks.
> system.l2c.sampled_refs 134589 # Sample count of references to valid blocks.
> system.l2c.avg_refs 12.430191 # Average number of references to valid blocks.
251c251
< system.l2c.occ_blocks::writebacks 40183.482743 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 40188.045356 # Average occupied blocks per requestor
254,259c254,259
< system.l2c.occ_blocks::cpu0.inst 3728.899373 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 4237.689144 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 2823.942801 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 2061.640399 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.613151 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::cpu0.inst 3727.182104 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 4237.001170 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.dtb.walker 2.742163 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 2823.633866 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 2061.365608 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.613221 # Average percentage of cache occupancy
262,263c262,263
< system.l2c.occ_percent::cpu0.inst 0.056898 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.064662 # Average percentage of cache occupancy
---
> system.l2c.occ_percent::cpu0.inst 0.056872 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.064652 # Average percentage of cache occupancy
265,281c265,281
< system.l2c.occ_percent::cpu1.inst 0.043090 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.data 0.031458 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.809302 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.dtb.walker 4216 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 1874 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 419651 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 206094 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 5524 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 1914 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 464156 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 143505 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1246934 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 571634 # number of Writeback hits
< system.l2c.Writeback_hits::total 571634 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 1136 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1711 # number of UpgradeReq hits
---
> system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.data 0.031454 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.809326 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.dtb.walker 4055 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 1843 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 206158 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 5342 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 1844 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 464150 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 143311 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1246376 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 571308 # number of Writeback hits
> system.l2c.Writeback_hits::total 571308 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1277 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1841 # number of UpgradeReq hits
283,305c283,305
< system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 56997 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 52866 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 109863 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 4216 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 1874 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 419651 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 263091 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 5524 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 1914 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 464156 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 196371 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1356797 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 4216 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 1874 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 419651 # number of overall hits
< system.l2c.overall_hits::cpu0.data 263091 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 5524 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 1914 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 464156 # number of overall hits
< system.l2c.overall_hits::cpu1.data 196371 # number of overall hits
< system.l2c.overall_hits::total 1356797 # number of overall hits
---
> system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 56678 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 52482 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 109160 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 4055 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 1843 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 262836 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5342 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 1844 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 464150 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 195793 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1355536 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 4055 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 1843 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits
> system.l2c.overall_hits::cpu0.data 262836 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5342 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 1844 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 464150 # number of overall hits
> system.l2c.overall_hits::cpu1.data 195793 # number of overall hits
> system.l2c.overall_hits::total 1355536 # number of overall hits
308,309c308,309
< system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 7859 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.inst 5736 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses
313,322c313,322
< system.l2c.ReadReq_misses::total 22264 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 4681 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3591 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 8272 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 561 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 470 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 67060 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 72161 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139221 # number of ReadExReq misses
---
> system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 4685 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3595 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 8280 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1033 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 67153 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 72577 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 139730 # number of ReadExReq misses
325,326c325,326
< system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 74919 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 5736 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 75016 # number of demand (read+write) misses
329,330c329,330
< system.l2c.demand_misses::cpu1.data 75782 # number of demand (read+write) misses
< system.l2c.demand_misses::total 161485 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.data 76198 # number of demand (read+write) misses
> system.l2c.demand_misses::total 162001 # number of demand (read+write) misses
333,334c333,334
< system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses
< system.l2c.overall_misses::cpu0.data 74919 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 5736 # number of overall misses
> system.l2c.overall_misses::cpu0.data 75016 # number of overall misses
337,338c337,338
< system.l2c.overall_misses::cpu1.data 75782 # number of overall misses
< system.l2c.overall_misses::total 161485 # number of overall misses
---
> system.l2c.overall_misses::cpu1.data 76198 # number of overall misses
> system.l2c.overall_misses::total 162001 # number of overall misses
341,342c341,342
< system.l2c.ReadReq_miss_latency::cpu0.inst 285527000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 405599500 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 282793000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 402090500 # number of ReadReq miss cycles
344,355c344,355
< system.l2c.ReadReq_miss_latency::cpu1.inst 259776000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 211385500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1162672000 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 12888997 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 11730499 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 24619496 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1705500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2384500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 4090000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 2999097972 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 3428190491 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6427288463 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 256949000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 210391000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1152607500 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 12566496 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 11726999 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 24293495 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1712000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2362500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 4074500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 2978330461 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 3439869494 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6418199955 # number of ReadExReq miss cycles
358,359c358,359
< system.l2c.demand_miss_latency::cpu0.inst 285527000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 3404697472 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 282793000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 3380420961 # number of demand (read+write) miss cycles
361,363c361,363
< system.l2c.demand_miss_latency::cpu1.inst 259776000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 3639575991 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 7589960463 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu1.inst 256949000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 3650260494 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 7570807455 # number of demand (read+write) miss cycles
366,367c366,367
< system.l2c.overall_miss_latency::cpu0.inst 285527000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 3404697472 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.inst 282793000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 3380420961 # number of overall miss cycles
369,414c369,414
< system.l2c.overall_miss_latency::cpu1.inst 259776000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 3639575991 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 7589960463 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 4217 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 1876 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 425384 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 213953 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 5528 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 1914 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 469200 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 147126 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1269198 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 571634 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 571634 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 5817 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4166 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 9983 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1345 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 124057 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 125027 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 249084 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 4217 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 1876 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 425384 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 338010 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 5528 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 1914 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 469200 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 272153 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1518282 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 4217 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 1876 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 425384 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 338010 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 5528 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 1914 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 469200 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 272153 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1518282 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.036732 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses
---
> system.l2c.overall_miss_latency::cpu1.inst 256949000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 3650260494 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 7570807455 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 4056 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 1845 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 425409 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 214021 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 5346 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 1844 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 469194 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 146932 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1268647 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 571308 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 571308 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 5962 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4159 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 10121 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 573 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 123831 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 125059 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 248890 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 4056 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 1845 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 425409 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 337852 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 5346 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 1844 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 469194 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 271991 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1517537 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 4056 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 1845 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 425409 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 337852 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 5346 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 1844 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 469194 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 271991 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1517537 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001084 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.013483 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.036739 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for ReadReq accesses
416,431c416,431
< system.l2c.ReadReq_miss_rate::cpu1.data 0.024612 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.017542 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.804710 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861978 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.828609 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722938 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826011 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.766543 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.540558 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.577163 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.558932 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.221647 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses
---
> system.l2c.ReadReq_miss_rate::cpu1.data 0.024644 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785810 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.864390 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.818101 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.818499 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.764053 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.542296 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.580342 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.561413 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.001084 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.013483 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.222038 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for demand accesses
433,439c433,439
< system.l2c.demand_miss_rate::cpu1.data 0.278454 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.106360 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.221647 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses
---
> system.l2c.demand_miss_rate::cpu1.data 0.280149 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.106753 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000247 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.001084 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.013483 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.222038 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000748 # miss rate for overall accesses
441,442c441,442
< system.l2c.overall_miss_rate::cpu1.data 0.278454 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.106360 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.data 0.280149 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.106753 # miss rate for overall accesses
445,446c445,446
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49804.116518 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 51609.555923 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49301.429568 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 51137.034211 # average ReadReq miss latency
448,459c448,459
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51501.982554 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 58377.658105 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 52222.062522 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2753.470840 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3266.638541 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2976.244681 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3040.106952 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5073.404255 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3967.022308 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44722.606203 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47507.524716 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 46166.084592 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50941.514671 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 58103.010218 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 51753.738045 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2682.283031 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3262.030320 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2933.996981 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3035.460993 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5037.313433 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3944.336883 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44351.413355 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47396.137812 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 45932.870214 # average ReadExReq miss latency
462,463c462,463
< system.l2c.demand_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 49301.429568 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 45062.666111 # average overall miss latency
465,467c465,467
< system.l2c.demand_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 47001.024634 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 50941.514671 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 47904.938371 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 46733.090876 # average overall miss latency
470,471c470,471
< system.l2c.overall_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 49301.429568 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 45062.666111 # average overall miss latency
473,475c473,475
< system.l2c.overall_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 47001.024634 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 50941.514671 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 47904.938371 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 46733.090876 # average overall miss latency
484,485c484,485
< system.l2c.writebacks::writebacks 63842 # number of writebacks
< system.l2c.writebacks::total 63842 # number of writebacks
---
> system.l2c.writebacks::writebacks 64292 # number of writebacks
> system.l2c.writebacks::total 64292 # number of writebacks
494,495c494,495
< system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 7859 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 5735 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 7863 # number of ReadReq MSHR misses
499,508c499,508
< system.l2c.ReadReq_mshr_misses::total 22263 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 4681 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 3591 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 8272 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 561 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 470 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 67060 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 72161 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139221 # number of ReadExReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::total 22270 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 4685 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 3595 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 8280 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 469 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1033 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 67153 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 72577 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 139730 # number of ReadExReq MSHR misses
511,512c511,512
< system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 74919 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 5735 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 75016 # number of demand (read+write) MSHR misses
515,516c515,516
< system.l2c.demand_mshr_misses::cpu1.data 75782 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 161484 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.data 76198 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 162000 # number of demand (read+write) MSHR misses
519,520c519,520
< system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 74919 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 5735 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 75016 # number of overall MSHR misses
523,524c523,524
< system.l2c.overall_mshr_misses::cpu1.data 75782 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 161484 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu1.data 76198 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 162000 # number of overall MSHR misses
527,528c527,528
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212718377 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 304840627 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 209968387 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 301307132 # number of ReadReq MSHR miss cycles
530,541c530,541
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 195716490 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165149154 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 878718662 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46986078 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35996056 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 82982134 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5623056 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4727457 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 10350513 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2155048026 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2506935370 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 4661983396 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 192920490 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 164158147 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 868648170 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47014106 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36048563 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 83062669 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5661057 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4707461 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 10368518 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2133484234 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2513381312 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 4646865546 # number of ReadExReq MSHR miss cycles
544,545c544,545
< system.l2c.demand_mshr_miss_latency::cpu0.inst 212718377 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2459888653 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 209968387 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2434791366 # number of demand (read+write) MSHR miss cycles
547,549c547,549
< system.l2c.demand_mshr_miss_latency::cpu1.inst 195716490 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 2672084524 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 5540702058 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu1.inst 192920490 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 2677539459 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 5515513716 # number of demand (read+write) MSHR miss cycles
552,553c552,553
< system.l2c.overall_mshr_miss_latency::cpu0.inst 212718377 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2459888653 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 209968387 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2434791366 # number of overall MSHR miss cycles
555,557c555,557
< system.l2c.overall_mshr_miss_latency::cpu1.inst 195716490 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 2672084524 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 5540702058 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu1.inst 192920490 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 2677539459 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 5515513716 # number of overall MSHR miss cycles
559c559
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12452500109 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12453767609 # number of ReadReq MSHR uncacheable cycles
561,565c561,565
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154310795041 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 166964298407 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000517750 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209233939 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 9209751689 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154319820043 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 166974590909 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000478250 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214527645 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 9215005895 # number of WriteReq MSHR uncacheable cycles
567c567
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13453017859 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13454245859 # number of overall MSHR uncacheable cycles
569,575c569,575
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162520028980 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 176174050096 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162534347688 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 176189596804 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036739 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for ReadReq accesses
577,592c577,592
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024612 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.804710 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861978 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.828609 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722938 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826011 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766543 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540558 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577163 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.558932 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses
---
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024644 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785810 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.864390 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.818101 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.818499 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764053 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542296 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.580342 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.561413 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for demand accesses
594,600c594,600
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.106360 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses
---
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for overall accesses
602,603c602,603
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.106360 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses
606,607c606,607
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38788.729737 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38319.614905 # average ReadReq mshr miss latency
609,620c609,620
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45608.714167 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 39469.912501 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.615467 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.964355 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.689313 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10023.272727 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.419149 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.294859 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.117298 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34740.862377 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 33486.208230 # average ReadExReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45335.030931 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 39005.306242 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.027962 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.416690 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.723309 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.335106 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.230277 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10037.287512 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31770.497729 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34630.548411 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 33256.033393 # average ReadExReq mshr miss latency
623,624c623,624
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency
626,628c626,628
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency
631,632c631,632
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency
634,636c634,636
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency
659,662c659,662
< system.cpu0.dtb.read_hits 7072907 # DTB read hits
< system.cpu0.dtb.read_misses 3765 # DTB read misses
< system.cpu0.dtb.write_hits 5658426 # DTB write hits
< system.cpu0.dtb.write_misses 809 # DTB write misses
---
> system.cpu0.dtb.read_hits 7070111 # DTB read hits
> system.cpu0.dtb.read_misses 3764 # DTB read misses
> system.cpu0.dtb.write_hits 5656042 # DTB write hits
> system.cpu0.dtb.write_misses 804 # DTB write misses
669c669
< system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
672,673c672,673
< system.cpu0.dtb.read_accesses 7076672 # DTB read accesses
< system.cpu0.dtb.write_accesses 5659235 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 7073875 # DTB read accesses
> system.cpu0.dtb.write_accesses 5656846 # DTB write accesses
675,678c675,678
< system.cpu0.dtb.hits 12731333 # DTB hits
< system.cpu0.dtb.misses 4574 # DTB misses
< system.cpu0.dtb.accesses 12735907 # DTB accesses
< system.cpu0.itb.inst_hits 29570611 # ITB inst hits
---
> system.cpu0.dtb.hits 12726153 # DTB hits
> system.cpu0.dtb.misses 4568 # DTB misses
> system.cpu0.dtb.accesses 12730721 # DTB accesses
> system.cpu0.itb.inst_hits 29570310 # ITB inst hits
695,696c695,696
< system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses
< system.cpu0.itb.hits 29570611 # DTB hits
---
> system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses
> system.cpu0.itb.hits 29570310 # DTB hits
698,699c698,699
< system.cpu0.itb.accesses 29572816 # DTB accesses
< system.cpu0.numCycles 2365766550 # number of cpu cycles simulated
---
> system.cpu0.itb.accesses 29572515 # DTB accesses
> system.cpu0.numCycles 2365764313 # number of cpu cycles simulated
702,704c702,704
< system.cpu0.committedInsts 28872677 # Number of instructions committed
< system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses
---
> system.cpu0.committedInsts 28872367 # Number of instructions committed
> system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses
706,708c706,708
< system.cpu0.num_func_calls 1241693 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 33106294 # number of integer instructions
---
> system.cpu0.num_func_calls 1241715 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 33098187 # number of integer instructions
710,711c710,711
< system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written
714,720c714,720
< system.cpu0.num_mem_refs 13399479 # number of memory refs
< system.cpu0.num_load_insts 7410420 # Number of load instructions
< system.cpu0.num_store_insts 5989059 # Number of store instructions
< system.cpu0.num_idle_cycles 2224930438.354119 # Number of idle cycles
< system.cpu0.num_busy_cycles 140836111.645881 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
---
> system.cpu0.num_mem_refs 13394441 # number of memory refs
> system.cpu0.num_load_insts 7407672 # Number of load instructions
> system.cpu0.num_store_insts 5986769 # Number of store instructions
> system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles
> system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles
722,727c722,727
< system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed
< system.cpu0.icache.replacements 425420 # number of replacements
< system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use
< system.cpu0.icache.total_refs 29144662 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 425932 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 68.425622 # Average number of references to valid blocks.
---
> system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed
> system.cpu0.icache.replacements 425445 # number of replacements
> system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use
> system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks.
729,767c729,767
< system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor
< system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy
< system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 29144662 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 29144662 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 29144662 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 29144662 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 29144662 # number of overall hits
< system.cpu0.icache.overall_hits::total 29144662 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 425932 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 425932 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 425932 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 425932 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 425932 # number of overall misses
< system.cpu0.icache.overall_misses::total 425932 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794628000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 5794628000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 5794628000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 5794628000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 5794628000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 5794628000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570594 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 29570594 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 29570594 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 29570594 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 29570594 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 29570594 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.584769 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.584769 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency
---
> system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor
> system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy
> system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits
> system.cpu0.icache.overall_hits::total 29144335 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses
> system.cpu0.icache.overall_misses::total 425958 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency
776,787c776,787
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425932 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 425932 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 425932 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 425932 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 425932 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 425932 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942764000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942764000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942764000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 4942764000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942764000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 4942764000 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4940272000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4940272000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4940272000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4940272000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4940272000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4940272000 # number of overall MSHR miss cycles
792,803c792,803
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014404 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.584769 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency
809,813c809,813
< system.cpu0.dcache.replacements 330832 # number of replacements
< system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 330355 # number of replacements
> system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks.
815,835c815,835
< system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 5353299 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 5353299 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147927 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 147927 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149680 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 149680 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 11955959 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 11955959 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 11955959 # number of overall hits
< system.cpu0.dcache.overall_hits::total 11955959 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 227931 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 227931 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 141702 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 141702 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9328 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 9328 # number of LoadLockedReq misses
---
> system.cpu0.dcache.occ_blocks::cpu0.data 453.331528 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.885413 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.885413 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6599943 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6599943 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 5351121 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 5351121 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147941 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 147941 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149661 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 149661 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 11951064 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 11951064 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 11951064 # number of overall hits
> system.cpu0.dcache.overall_hits::total 11951064 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 227863 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 227863 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 141515 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 141515 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9301 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 9301 # number of LoadLockedReq misses
838,889c838,889
< system.cpu0.dcache.demand_misses::cpu0.data 369633 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 369633 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 369633 # number of overall misses
< system.cpu0.dcache.overall_misses::total 369633 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3133125500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 3133125500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4126730000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 4126730000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88286000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 88286000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44416500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 44416500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 7259855500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 7259855500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 7259855500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 7259855500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830591 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 6830591 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495001 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5495001 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157255 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 157255 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157172 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 157172 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 12325592 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 12325592 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 12325592 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 12325592 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033369 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.033369 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025787 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.025787 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059318 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059318 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047668 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047668 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029989 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.029989 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029989 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.029989 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13745.938464 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29122.595306 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency
---
> system.cpu0.dcache.demand_misses::cpu0.data 369378 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 369378 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 369378 # number of overall misses
> system.cpu0.dcache.overall_misses::total 369378 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3130112000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 3130112000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4103795500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 4103795500 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87984000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 87984000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44508500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 44508500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 7233907500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 7233907500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 7233907500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 7233907500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827806 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6827806 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492636 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5492636 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157242 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 157242 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12320442 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12320442 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12320442 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12320442 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033373 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.033373 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059151 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059151 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047673 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047673 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029981 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.029981 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029981 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.029981 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9459.627997 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9459.627997 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5940.803524 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5940.803524 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19584.023683 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 19584.023683 # average overall miss latency
898,905c898,905
< system.cpu0.dcache.writebacks::writebacks 306514 # number of writebacks
< system.cpu0.dcache.writebacks::total 306514 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227931 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 227931 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141702 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 141702 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9328 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses
---
> system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks
> system.cpu0.dcache.writebacks::total 306206 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses
908,951c908,951
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 369633 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 369633 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 369633 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 369633 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2677263500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2677263500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3843326000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3843326000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69630000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29442500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29442500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688598500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688598500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033369 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025787 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025787 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059318 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059318 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047648 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047648 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.029989 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.029989 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3931.432768 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency
954,957c954,957
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
967c967
< system.cpu1.dtb.read_hits 8308581 # DTB read hits
---
> system.cpu1.dtb.read_hits 8310545 # DTB read hits
969,970c969,970
< system.cpu1.dtb.write_hits 5825594 # DTB write hits
< system.cpu1.dtb.write_misses 1436 # DTB write misses
---
> system.cpu1.dtb.write_hits 5827351 # DTB write hits
> system.cpu1.dtb.write_misses 1434 # DTB write misses
977c977
< system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
980,981c980,981
< system.cpu1.dtb.read_accesses 8312224 # DTB read accesses
< system.cpu1.dtb.write_accesses 5827030 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 8314188 # DTB read accesses
> system.cpu1.dtb.write_accesses 5828785 # DTB write accesses
983,986c983,986
< system.cpu1.dtb.hits 14134175 # DTB hits
< system.cpu1.dtb.misses 5079 # DTB misses
< system.cpu1.dtb.accesses 14139254 # DTB accesses
< system.cpu1.itb.inst_hits 33188757 # ITB inst hits
---
> system.cpu1.dtb.hits 14137896 # DTB hits
> system.cpu1.dtb.misses 5077 # DTB misses
> system.cpu1.dtb.accesses 14142973 # DTB accesses
> system.cpu1.itb.inst_hits 33189113 # ITB inst hits
1003,1004c1003,1004
< system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses
< system.cpu1.itb.hits 33188757 # DTB hits
---
> system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses
> system.cpu1.itb.hits 33189113 # DTB hits
1006,1007c1006,1007
< system.cpu1.itb.accesses 33190928 # DTB accesses
< system.cpu1.numCycles 2364324282 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 33191284 # DTB accesses
> system.cpu1.numCycles 2364318212 # number of cpu cycles simulated
1010,1012c1010,1012
< system.cpu1.committedInsts 32578272 # Number of instructions committed
< system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses
---
> system.cpu1.committedInsts 32578626 # Number of instructions committed
> system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses
1014,1016c1014,1016
< system.cpu1.num_func_calls 961975 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 37307259 # number of integer instructions
---
> system.cpu1.num_func_calls 962009 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 37313171 # number of integer instructions
1018,1019c1018,1019
< system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written
1022,1028c1022,1028
< system.cpu1.num_mem_refs 14671912 # number of memory refs
< system.cpu1.num_load_insts 8630468 # Number of load instructions
< system.cpu1.num_store_insts 6041444 # Number of store instructions
< system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles
< system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles
---
> system.cpu1.num_mem_refs 14675641 # number of memory refs
> system.cpu1.num_load_insts 8632449 # Number of load instructions
> system.cpu1.num_store_insts 6043192 # Number of store instructions
> system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles
> system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles
1030,1037c1030,1037
< system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed
< system.cpu1.icache.replacements 469210 # number of replacements
< system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use
< system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks.
< system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor
---
> system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed
> system.cpu1.icache.replacements 469194 # number of replacements
> system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use
> system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks.
> system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor
1040,1075c1040,1075
< system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits
< system.cpu1.icache.overall_hits::total 32719031 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses
< system.cpu1.icache.overall_misses::total 469722 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency
---
> system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits
> system.cpu1.icache.overall_hits::total 32719403 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses
> system.cpu1.icache.overall_misses::total 469706 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency
1084,1095c1084,1095
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 469722 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 469722 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 469722 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5407172500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5407172500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5407172500 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles
1100,1111c1100,1111
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency
1117,1197c1117,1197
< system.cpu1.dcache.replacements 291698 # number of replacements
< system.cpu1.dcache.tagsinuse 472.096881 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 11957476 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 292067 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 40.940866 # Average number of references to valid blocks.
< system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.occ_blocks::cpu1.data 472.096881 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.922064 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.922064 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 6944335 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 6944335 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 4825513 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 4825513 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81763 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 81763 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82710 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 82710 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 11769848 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 11769848 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 11769848 # number of overall hits
< system.cpu1.dcache.overall_hits::total 11769848 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 170295 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 170295 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 149789 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 149789 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11069 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 11069 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10034 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 10034 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 320084 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 320084 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 320084 # number of overall misses
< system.cpu1.dcache.overall_misses::total 320084 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2151167000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2151167000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4518557500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 4518557500 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92001000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 92001000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51654000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 51654000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 6669724500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 6669724500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 6669724500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 6669724500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114630 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 7114630 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975302 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4975302 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92832 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 92832 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92744 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 92744 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 12089932 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 12089932 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 12089932 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 12089932 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023936 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.023936 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030107 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.030107 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119237 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119237 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108190 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108190 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026475 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.026475 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026475 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.026475 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12632.003288 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12632.003288 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30166.150385 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 30166.150385 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8311.590930 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8311.590930 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5147.897150 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5147.897150 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20837.419240 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20837.419240 # average overall miss latency
---
> system.cpu1.dcache.replacements 292054 # number of replacements
> system.cpu1.dcache.tagsinuse 471.972808 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 11961234 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 292426 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 40.903456 # Average number of references to valid blocks.
> system.cpu1.dcache.warmup_cycle 83625409000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.occ_blocks::cpu1.data 471.972808 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.921822 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.921822 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 6946091 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 6946091 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 4827134 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4827134 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81752 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 81752 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82714 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 82714 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 11773225 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 11773225 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 11773225 # number of overall hits
> system.cpu1.dcache.overall_hits::total 11773225 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 170515 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 170515 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 149924 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 149924 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11068 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 11068 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10031 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 10031 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 320439 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 320439 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 320439 # number of overall misses
> system.cpu1.dcache.overall_misses::total 320439 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2149232000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2149232000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4527081500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4527081500 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92245500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 92245500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51683000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 51683000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6676313500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6676313500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6676313500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6676313500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 7116606 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 7116606 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977058 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 4977058 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92820 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 92820 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92745 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 92745 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 12093664 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 12093664 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 12093664 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 12093664 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023960 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.023960 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119242 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119242 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108157 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108157 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026496 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.026496 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026496 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.026496 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 20834.896813 # average overall miss latency
1206,1227c1206,1227
< system.cpu1.dcache.writebacks::writebacks 265120 # number of writebacks
< system.cpu1.dcache.writebacks::total 265120 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170295 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 170295 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149789 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 149789 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11069 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11069 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10028 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 10028 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 320084 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 320084 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 320084 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 320084 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles
---
> system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks
> system.cpu1.dcache.writebacks::total 265102 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles
1230,1259c1230,1259
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency
1262,1265c1262,1265
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
1287,1290c1287,1290
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles