4,5c4,5
< sim_ticks 1182883077500 # Number of ticks simulated
< final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1182883275000 # Number of ticks simulated
> final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 330156 # Simulator instruction rate (inst/s)
< host_op_rate 420694 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6355289452 # Simulator tick rate (ticks/s)
< host_mem_usage 400808 # Number of bytes of host memory used
< host_seconds 186.13 # Real time elapsed on the host
< sim_insts 61450599 # Number of instructions simulated
< sim_ops 78301940 # Number of ops (including micro ops) simulated
---
> host_inst_rate 656929 # Simulator instruction rate (inst/s)
> host_op_rate 837075 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 12645375755 # Simulator tick rate (ticks/s)
> host_mem_usage 400812 # Number of bytes of host memory used
> host_seconds 93.54 # Real time elapsed on the host
> sim_insts 61450949 # Number of instructions simulated
> sim_ops 78302298 # Number of ops (including micro ops) simulated
18c18
< system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory
21,22c21,22
< system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory
< system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory
> system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory
26c26
< system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory
29c29
< system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory
34c34
< system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory
37,39c37,39
< system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory
42,43c42,43
< system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s)
47c47
< system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s)
55c55
< system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s)
58,60c58,60
< system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s)
64c64
< system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s)
67,75c67,75
< system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 6653925 # Total number of read requests seen
< system.physmem.writeReqs 820679 # Total number of write requests seen
< system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 425851200 # Total number of bytes read from memory
< system.physmem.bytesWritten 52523456 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize()
---
> system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 6653924 # Total number of read requests seen
> system.physmem.writeReqs 820678 # Total number of write requests seen
> system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 425851136 # Total number of bytes read from memory
> system.physmem.bytesWritten 52523392 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize()
77c77
< system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed
---
> system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed
81c81
< system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis
97c97
< system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis
112c112
< system.physmem.totGap 1182878628500 # Total gap between requests
---
> system.physmem.totGap 1182878800500 # Total gap between requests
119c119
< system.physmem.readPktSize::6 159036 # Categorize read packet sizes
---
> system.physmem.readPktSize::6 159035 # Categorize read packet sizes
128c128
< system.physmem.writePktSize::6 63843 # categorize write packet sizes
---
> system.physmem.writePktSize::6 63842 # categorize write packet sizes
137c137
< system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes
---
> system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes
140,152c140,152
< system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see
154,156c154,156
< system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see
188c188
< system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see
206,211c206,211
< system.physmem.totQLat 3516126974 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 123045854974 # Sum of mem lat for all requests
< system.physmem.totBusLat 26615172000 # Total cycles spent in databus access
< system.physmem.totBankLat 92914556000 # Total cycles spent in bank access
< system.physmem.avgQLat 528.44 # Average queueing delay per request
< system.physmem.avgBankLat 13964.15 # Average bank access latency per request
---
> system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests
> system.physmem.totBusLat 26615168000 # Total cycles spent in databus access
> system.physmem.totBankLat 92915214000 # Total cycles spent in bank access
> system.physmem.avgQLat 536.46 # Average queueing delay per request
> system.physmem.avgBankLat 13964.25 # Average bank access latency per request
213c213
< system.physmem.avgMemAccLat 18492.59 # Average memory access latency
---
> system.physmem.avgMemAccLat 18500.71 # Average memory access latency
221,223c221,223
< system.physmem.avgWrQLen 15.12 # Average write queue length over time
< system.physmem.readRowHits 6625021 # Number of row buffer hits during reads
< system.physmem.writeRowHits 788582 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 15.10 # Average write queue length over time
> system.physmem.readRowHits 6624970 # Number of row buffer hits during reads
> system.physmem.writeRowHits 788587 # Number of row buffer hits during writes
226c226
< system.physmem.avgGap 158253.02 # Average gap between requests
---
> system.physmem.avgGap 158253.08 # Average gap between requests
245,249c245,249
< system.l2c.replacements 68923 # number of replacements
< system.l2c.tagsinuse 53039.119781 # Cycle average of tags in use
< system.l2c.total_refs 1673706 # Total number of references to valid blocks.
< system.l2c.sampled_refs 134114 # Sample count of references to valid blocks.
< system.l2c.avg_refs 12.479726 # Average number of references to valid blocks.
---
> system.l2c.replacements 68922 # number of replacements
> system.l2c.tagsinuse 53038.398444 # Cycle average of tags in use
> system.l2c.total_refs 1676342 # Total number of references to valid blocks.
> system.l2c.sampled_refs 134082 # Sample count of references to valid blocks.
> system.l2c.avg_refs 12.502364 # Average number of references to valid blocks.
251c251
< system.l2c.occ_blocks::writebacks 40183.428696 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 40183.482743 # Average occupied blocks per requestor
254,255c254,255
< system.l2c.occ_blocks::cpu0.inst 3728.892697 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 4238.506487 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::cpu0.inst 3728.899373 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 4237.689144 # Average occupied blocks per requestor
257,259c257,259
< system.l2c.occ_blocks::cpu1.inst 2823.934351 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 2061.613566 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.613150 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::cpu1.inst 2823.942801 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 2061.640399 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.613151 # Average percentage of cache occupancy
263c263
< system.l2c.occ_percent::cpu0.data 0.064674 # Average percentage of cache occupancy
---
> system.l2c.occ_percent::cpu0.data 0.064662 # Average percentage of cache occupancy
267,281c267,281
< system.l2c.occ_percent::total 0.809313 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.dtb.walker 4148 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 1813 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 419656 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 206316 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 1906 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 464180 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 143508 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1247033 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 571732 # number of Writeback hits
< system.l2c.Writeback_hits::total 571732 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 640 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 1799 # number of UpgradeReq hits
---
> system.l2c.occ_percent::total 0.809302 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.dtb.walker 4216 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 1874 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 419651 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 206094 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 5524 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 1914 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 464156 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 143505 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1246934 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 571634 # number of Writeback hits
> system.l2c.Writeback_hits::total 571634 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 1136 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 1711 # number of UpgradeReq hits
283,305c283,305
< system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 56965 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 52844 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 109809 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 4148 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 1813 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 419656 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 263281 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 1906 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 464180 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 196352 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1356842 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 4148 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 1813 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 419656 # number of overall hits
< system.l2c.overall_hits::cpu0.data 263281 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 1906 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 464180 # number of overall hits
< system.l2c.overall_hits::cpu1.data 196352 # number of overall hits
< system.l2c.overall_hits::total 1356842 # number of overall hits
---
> system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 314 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 56997 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 52866 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 109863 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 4216 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 1874 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 419651 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 263091 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5524 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 1914 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 464156 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 196371 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1356797 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 4216 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 1874 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 419651 # number of overall hits
> system.l2c.overall_hits::cpu0.data 263091 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5524 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 1914 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 464156 # number of overall hits
> system.l2c.overall_hits::cpu1.data 196371 # number of overall hits
> system.l2c.overall_hits::total 1356797 # number of overall hits
314,322c314,322
< system.l2c.UpgradeReq_misses::cpu0.data 4676 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3594 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 8270 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1038 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 67114 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 72101 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139215 # number of ReadExReq misses
---
> system.l2c.UpgradeReq_misses::cpu0.data 4681 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3591 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 8272 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 561 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 470 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 67060 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 72161 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 139221 # number of ReadExReq misses
326c326
< system.l2c.demand_misses::cpu0.data 74973 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.data 74919 # number of demand (read+write) misses
329,330c329,330
< system.l2c.demand_misses::cpu1.data 75722 # number of demand (read+write) misses
< system.l2c.demand_misses::total 161479 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.data 75782 # number of demand (read+write) misses
> system.l2c.demand_misses::total 161485 # number of demand (read+write) misses
334c334
< system.l2c.overall_misses::cpu0.data 74973 # number of overall misses
---
> system.l2c.overall_misses::cpu0.data 74919 # number of overall misses
337,338c337,338
< system.l2c.overall_misses::cpu1.data 75722 # number of overall misses
< system.l2c.overall_misses::total 161479 # number of overall misses
---
> system.l2c.overall_misses::cpu1.data 75782 # number of overall misses
> system.l2c.overall_misses::total 161485 # number of overall misses
341,342c341,342
< system.l2c.ReadReq_miss_latency::cpu0.inst 285133000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 404030000 # number of ReadReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 285527000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 405599500 # number of ReadReq miss cycles
344,355c344,355
< system.l2c.ReadReq_miss_latency::cpu1.inst 261135000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 212169500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1162851500 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 12638997 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 11749999 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 24388996 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1751500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 4160000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 3003544975 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 3416776995 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 6420321970 # number of ReadExReq miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu1.inst 259776000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 211385500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 1162672000 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 12888997 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 11730499 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 24619496 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1705500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2384500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 4090000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 2999097972 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 3428190491 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 6427288463 # number of ReadExReq miss cycles
358,359c358,359
< system.l2c.demand_miss_latency::cpu0.inst 285133000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 3407574975 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 285527000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 3404697472 # number of demand (read+write) miss cycles
361,363c361,363
< system.l2c.demand_miss_latency::cpu1.inst 261135000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 3628946495 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 7583173470 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu1.inst 259776000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 3639575991 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 7589960463 # number of demand (read+write) miss cycles
366,367c366,367
< system.l2c.overall_miss_latency::cpu0.inst 285133000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 3407574975 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.inst 285527000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 3404697472 # number of overall miss cycles
369,411c369,411
< system.l2c.overall_miss_latency::cpu1.inst 261135000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 3628946495 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 7583173470 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 4149 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 1815 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 425389 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 214175 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 1906 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 469224 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 147129 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1269297 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 571732 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 571732 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 5835 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4234 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 10069 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 571 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1350 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 124079 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 124945 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 249024 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 4149 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 1815 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 425389 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 338254 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 1906 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 469224 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 272074 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1518321 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 4149 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 1815 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 425389 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 338254 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 1906 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 469224 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 272074 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1518321 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001102 # miss rate for ReadReq accesses
---
> system.l2c.overall_miss_latency::cpu1.inst 259776000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 3639575991 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 7589960463 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 4217 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 1876 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 425384 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 213953 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 5528 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 1914 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 469200 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 147126 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1269198 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 571634 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 571634 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 5817 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4166 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 9983 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1345 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 124057 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 125027 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 249084 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 4217 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 1876 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 425384 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 338010 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 5528 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 1914 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 469200 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 272153 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1518282 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 4217 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 1876 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 425384 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 338010 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 5528 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 1914 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 469200 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 272153 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1518282 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001066 # miss rate for ReadReq accesses
413,414c413,414
< system.l2c.ReadReq_miss_rate::cpu0.data 0.036694 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu0.data 0.036732 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses
416,428c416,428
< system.l2c.ReadReq_miss_rate::cpu1.data 0.024611 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.017540 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801371 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848843 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.821333 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830123 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.768889 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.540897 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.577062 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.559043 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.001102 # miss rate for demand accesses
---
> system.l2c.ReadReq_miss_rate::cpu1.data 0.024612 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.017542 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.804710 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.861978 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.828609 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.722938 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826011 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.766543 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.540558 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.577163 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.558932 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.001066 # miss rate for demand accesses
431c431
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses
433,436c433,436
< system.l2c.demand_miss_rate::cpu1.data 0.278314 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.106354 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.001102 # miss rate for overall accesses
---
> system.l2c.demand_miss_rate::cpu1.data 0.278454 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.106360 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000237 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.001066 # miss rate for overall accesses
439c439
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses
441,442c441,442
< system.l2c.overall_miss_rate::cpu1.data 0.278314 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.106354 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.data 0.278454 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.106360 # miss rate for overall accesses
445,446c445,446
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49735.391593 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 51409.848581 # average ReadReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49804.116518 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 51609.555923 # average ReadReq miss latency
448,459c448,459
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51771.411578 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 58594.172880 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 52230.124865 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2702.950599 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3269.337507 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2949.092624 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3105.496454 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5081.223629 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 4007.707129 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44752.882782 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47388.760142 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 46118.033042 # average ReadExReq miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51501.982554 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 58377.658105 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 52222.062522 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2753.470840 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3266.638541 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2976.244681 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3040.106952 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5073.404255 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3967.022308 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44722.606203 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47507.524716 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 46166.084592 # average ReadExReq miss latency
462,463c462,463
< system.l2c.demand_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
465,467c465,467
< system.l2c.demand_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 46960.740839 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 47001.024634 # average overall miss latency
470,471c470,471
< system.l2c.overall_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 49804.116518 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 45445.046944 # average overall miss latency
473,475c473,475
< system.l2c.overall_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 46960.740839 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu1.inst 51501.982554 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 48026.919202 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 47001.024634 # average overall miss latency
484,485c484,485
< system.l2c.writebacks::writebacks 63843 # number of writebacks
< system.l2c.writebacks::total 63843 # number of writebacks
---
> system.l2c.writebacks::writebacks 63842 # number of writebacks
> system.l2c.writebacks::total 63842 # number of writebacks
500,508c500,508
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 4676 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 3594 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 8270 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 474 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1038 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 67114 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 72101 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139215 # number of ReadExReq MSHR misses
---
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 4681 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 3591 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 8272 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 561 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 470 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 67060 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 72161 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 139221 # number of ReadExReq MSHR misses
512c512
< system.l2c.demand_mshr_misses::cpu0.data 74973 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.data 74919 # number of demand (read+write) MSHR misses
515,516c515,516
< system.l2c.demand_mshr_misses::cpu1.data 75722 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 161478 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.data 75782 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 161484 # number of demand (read+write) MSHR misses
520c520
< system.l2c.overall_mshr_misses::cpu0.data 74973 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.data 74919 # number of overall MSHR misses
523,524c523,524
< system.l2c.overall_mshr_misses::cpu1.data 75722 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 161478 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu1.data 75782 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 161484 # number of overall MSHR misses
527,528c527,528
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212317379 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 303283129 # number of ReadReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212718377 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 304840627 # number of ReadReq MSHR miss cycles
530,541c530,541
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 197074983 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165938649 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 878908154 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46908094 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36050560 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 82958654 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5654558 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4769959 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 10424517 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2158776151 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2496303754 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 4655079905 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 195716490 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165149154 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 878718662 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46986078 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35996056 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 82982134 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5623056 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4727457 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 10350513 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2155048026 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2506935370 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 4661983396 # number of ReadExReq MSHR miss cycles
544,545c544,545
< system.l2c.demand_mshr_miss_latency::cpu0.inst 212317379 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2462059280 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 212718377 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2459888653 # number of demand (read+write) MSHR miss cycles
547,549c547,549
< system.l2c.demand_mshr_miss_latency::cpu1.inst 197074983 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 2662242403 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 5533988059 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu1.inst 195716490 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 2672084524 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 5540702058 # number of demand (read+write) MSHR miss cycles
552,553c552,553
< system.l2c.overall_mshr_miss_latency::cpu0.inst 212317379 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2462059280 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 212718377 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2459888653 # number of overall MSHR miss cycles
555,557c555,557
< system.l2c.overall_mshr_miss_latency::cpu1.inst 197074983 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 2662242403 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 5533988059 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu1.inst 195716490 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 2672084524 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 5540702058 # number of overall MSHR miss cycles
559c559
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448379609 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12452500109 # number of ReadReq MSHR uncacheable cycles
561,565c561,565
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289730543 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 166939113409 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000300750 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8208718440 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 9209019190 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154310795041 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 166964298407 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000517750 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209233939 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 9209751689 # number of WriteReq MSHR uncacheable cycles
567c567
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13448680359 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13453017859 # number of overall MSHR uncacheable cycles
569,572c569,572
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162498448983 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 176148132599 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for ReadReq accesses
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162520028980 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 176174050096 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses
574,575c574,575
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036694 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses
---
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses
577,589c577,589
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024611 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.017540 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801371 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848843 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.821333 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830123 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses
---
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024612 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.804710 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861978 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.828609 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.722938 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826011 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766543 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540558 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577163 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.558932 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses
592c592
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses
---
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses
594,597c594,597
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses
---
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.106360 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000237 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses
600c600
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses
602,603c602,603
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses
---
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.278454 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.106360 # mshr miss rate for overall accesses
606,607c606,607
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38788.729737 # average ReadReq mshr miss latency
609,620c609,620
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45608.714167 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 39469.912501 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.615467 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.964355 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.689313 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10023.272727 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.419149 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.294859 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32136.117298 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34740.862377 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 33486.208230 # average ReadExReq mshr miss latency
623,624c623,624
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
626,628c626,628
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
631,632c631,632
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
634,636c634,636
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
659,661c659,661
< system.cpu0.dtb.read_hits 7072899 # DTB read hits
< system.cpu0.dtb.read_misses 3762 # DTB read misses
< system.cpu0.dtb.write_hits 5658444 # DTB write hits
---
> system.cpu0.dtb.read_hits 7072907 # DTB read hits
> system.cpu0.dtb.read_misses 3765 # DTB read misses
> system.cpu0.dtb.write_hits 5658426 # DTB write hits
669c669
< system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
672,673c672,673
< system.cpu0.dtb.read_accesses 7076661 # DTB read accesses
< system.cpu0.dtb.write_accesses 5659253 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 7076672 # DTB read accesses
> system.cpu0.dtb.write_accesses 5659235 # DTB write accesses
675,678c675,678
< system.cpu0.dtb.hits 12731343 # DTB hits
< system.cpu0.dtb.misses 4571 # DTB misses
< system.cpu0.dtb.accesses 12735914 # DTB accesses
< system.cpu0.itb.inst_hits 29570664 # ITB inst hits
---
> system.cpu0.dtb.hits 12731333 # DTB hits
> system.cpu0.dtb.misses 4574 # DTB misses
> system.cpu0.dtb.accesses 12735907 # DTB accesses
> system.cpu0.itb.inst_hits 29570611 # ITB inst hits
695,696c695,696
< system.cpu0.itb.inst_accesses 29572869 # ITB inst accesses
< system.cpu0.itb.hits 29570664 # DTB hits
---
> system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses
> system.cpu0.itb.hits 29570611 # DTB hits
698,699c698,699
< system.cpu0.itb.accesses 29572869 # DTB accesses
< system.cpu0.numCycles 2365766155 # number of cpu cycles simulated
---
> system.cpu0.itb.accesses 29572816 # DTB accesses
> system.cpu0.numCycles 2365766550 # number of cpu cycles simulated
702,704c702,704
< system.cpu0.committedInsts 28872728 # Number of instructions committed
< system.cpu0.committedOps 37219681 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 33106320 # Number of integer alu accesses
---
> system.cpu0.committedInsts 28872677 # Number of instructions committed
> system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses
706,708c706,708
< system.cpu0.num_func_calls 1241688 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 4373344 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 33106320 # number of integer instructions
---
> system.cpu0.num_func_calls 1241693 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 33106294 # number of integer instructions
710,711c710,711
< system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written
714,720c714,720
< system.cpu0.num_mem_refs 13399483 # number of memory refs
< system.cpu0.num_load_insts 7410404 # Number of load instructions
< system.cpu0.num_store_insts 5989079 # Number of store instructions
< system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles
< system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles
---
> system.cpu0.num_mem_refs 13399479 # number of memory refs
> system.cpu0.num_load_insts 7410420 # Number of load instructions
> system.cpu0.num_store_insts 5989059 # Number of store instructions
> system.cpu0.num_idle_cycles 2224930438.354119 # Number of idle cycles
> system.cpu0.num_busy_cycles 140836111.645881 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
722,723c722,723
< system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed
< system.cpu0.icache.replacements 425421 # number of replacements
---
> system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed
> system.cpu0.icache.replacements 425420 # number of replacements
725,727c725,727
< system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks.
---
> system.cpu0.icache.total_refs 29144662 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 425932 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 68.425622 # Average number of references to valid blocks.
732,755c732,755
< system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 29144714 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 29144714 # number of overall hits
< system.cpu0.icache.overall_hits::total 29144714 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 425933 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 425933 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 425933 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 425933 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 425933 # number of overall misses
< system.cpu0.icache.overall_misses::total 425933 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794506500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 5794506500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 5794506500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 5794506500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses
---
> system.cpu0.icache.ReadReq_hits::cpu0.inst 29144662 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 29144662 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 29144662 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 29144662 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 29144662 # number of overall hits
> system.cpu0.icache.overall_hits::total 29144662 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 425932 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 425932 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 425932 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 425932 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 425932 # number of overall misses
> system.cpu0.icache.overall_misses::total 425932 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794628000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 5794628000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 5794628000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 5794628000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 5794628000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 5794628000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570594 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 29570594 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 29570594 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 29570594 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 29570594 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 29570594 # number of overall (read+write) accesses
762,767c762,767
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.267573 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.267573 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 13604.267573 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 13604.267573 # average overall miss latency
---
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.584769 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.584769 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency
776,787c776,787
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425933 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 425933 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 425933 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 425933 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 425933 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 425933 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942640500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942640500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942640500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 4942640500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942640500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 4942640500 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425932 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 425932 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 425932 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 425932 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 425932 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 425932 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942764000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942764000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942764000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 4942764000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942764000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 4942764000 # number of overall MSHR miss cycles
798,803c798,803
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.267573 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.584769 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency
809,813c809,813
< system.cpu0.dcache.replacements 330958 # number of replacements
< system.cpu0.dcache.tagsinuse 453.838533 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 12275558 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 331470 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 37.033692 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 330832 # number of replacements
> system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks.
815,889c815,889
< system.cpu0.dcache.occ_blocks::cpu0.data 453.838533 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.886403 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.886403 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6602415 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6602415 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 5353315 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 5353315 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149687 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 149687 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 11955730 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 11955730 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 11955730 # number of overall hits
< system.cpu0.dcache.overall_hits::total 11955730 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 228156 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 228156 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 141693 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 141693 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9329 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 9329 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7496 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 7496 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 369849 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 369849 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 369849 # number of overall misses
< system.cpu0.dcache.overall_misses::total 369849 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3134416000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 3134416000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4131327000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 4131327000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88312000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 88312000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44497000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 44497000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 7265743000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 7265743000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 7265743000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 7265743000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830571 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 6830571 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495008 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 5495008 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157268 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 157268 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157183 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 157183 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 12325579 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 12325579 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 12325579 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 12325579 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033402 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.033402 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025786 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.025786 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059319 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059319 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047690 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047690 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030007 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.030007 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030007 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.030007 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13738.038886 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13738.038886 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29156.888484 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 29156.888484 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9466.395112 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency
---
> system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 5353299 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 5353299 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147927 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 147927 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149680 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 149680 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 11955959 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 11955959 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 11955959 # number of overall hits
> system.cpu0.dcache.overall_hits::total 11955959 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 227931 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 227931 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 141702 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 141702 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9328 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 9328 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 369633 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 369633 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 369633 # number of overall misses
> system.cpu0.dcache.overall_misses::total 369633 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3133125500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 3133125500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4126730000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 4126730000 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88286000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 88286000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44416500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 44416500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 7259855500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 7259855500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 7259855500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 7259855500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830591 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 6830591 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495001 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5495001 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157255 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 157255 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157172 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 157172 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12325592 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12325592 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12325592 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12325592 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033369 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.033369 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025787 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.025787 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059318 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059318 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047668 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047668 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029989 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.029989 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029989 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.029989 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13745.938464 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29122.595306 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency
898,951c898,951
< system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks
< system.cpu0.dcache.writebacks::total 306622 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 306514 # number of writebacks
> system.cpu0.dcache.writebacks::total 306514 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227931 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 227931 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141702 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 141702 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9328 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 369633 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 369633 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 369633 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 369633 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2677263500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2677263500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3843326000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3843326000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69630000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69630000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29442500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29442500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688598500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688598500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033369 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025787 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025787 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059318 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059318 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047648 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047648 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.029989 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029989 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.029989 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.938464 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.938464 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27122.595306 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27122.595306 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7464.622642 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7464.622642 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3931.432768 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3931.432768 # average StoreCondReq mshr miss latency
954,957c954,957
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
967,970c967,970
< system.cpu1.dtb.read_hits 8308478 # DTB read hits
< system.cpu1.dtb.read_misses 3644 # DTB read misses
< system.cpu1.dtb.write_hits 5825596 # DTB write hits
< system.cpu1.dtb.write_misses 1434 # DTB write misses
---
> system.cpu1.dtb.read_hits 8308581 # DTB read hits
> system.cpu1.dtb.read_misses 3643 # DTB read misses
> system.cpu1.dtb.write_hits 5825594 # DTB write hits
> system.cpu1.dtb.write_misses 1436 # DTB write misses
977c977
< system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
980c980
< system.cpu1.dtb.read_accesses 8312122 # DTB read accesses
---
> system.cpu1.dtb.read_accesses 8312224 # DTB read accesses
983,986c983,986
< system.cpu1.dtb.hits 14134074 # DTB hits
< system.cpu1.dtb.misses 5078 # DTB misses
< system.cpu1.dtb.accesses 14139152 # DTB accesses
< system.cpu1.itb.inst_hits 33188345 # ITB inst hits
---
> system.cpu1.dtb.hits 14134175 # DTB hits
> system.cpu1.dtb.misses 5079 # DTB misses
> system.cpu1.dtb.accesses 14139254 # DTB accesses
> system.cpu1.itb.inst_hits 33188757 # ITB inst hits
1003,1004c1003,1004
< system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses
< system.cpu1.itb.hits 33188345 # DTB hits
---
> system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses
> system.cpu1.itb.hits 33188757 # DTB hits
1006,1007c1006,1007
< system.cpu1.itb.accesses 33190516 # DTB accesses
< system.cpu1.numCycles 2364324255 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 33190928 # DTB accesses
> system.cpu1.numCycles 2364324282 # number of cpu cycles simulated
1010,1012c1010,1012
< system.cpu1.committedInsts 32577871 # Number of instructions committed
< system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses
---
> system.cpu1.committedInsts 32578272 # Number of instructions committed
> system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses
1015,1016c1015,1016
< system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 37307050 # number of integer instructions
---
> system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 37307259 # number of integer instructions
1018,1019c1018,1019
< system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written
1022,1028c1022,1028
< system.cpu1.num_mem_refs 14671800 # number of memory refs
< system.cpu1.num_load_insts 8630367 # Number of load instructions
< system.cpu1.num_store_insts 6041433 # Number of store instructions
< system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles
< system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles
---
> system.cpu1.num_mem_refs 14671912 # number of memory refs
> system.cpu1.num_load_insts 8630468 # Number of load instructions
> system.cpu1.num_store_insts 6041444 # Number of store instructions
> system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles
> system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles
1030,1035c1030,1035
< system.cpu1.kern.inst.quiesce 43884 # number of quiesce instructions executed
< system.cpu1.icache.replacements 469230 # number of replacements
< system.cpu1.icache.tagsinuse 478.783120 # Cycle average of tags in use
< system.cpu1.icache.total_refs 32718599 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 469742 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 69.652275 # Average number of references to valid blocks.
---
> system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed
> system.cpu1.icache.replacements 469210 # number of replacements
> system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use
> system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks.
1037c1037
< system.cpu1.icache.occ_blocks::cpu1.inst 478.783120 # Average occupied blocks per requestor
---
> system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor
1040,1075c1040,1075
< system.cpu1.icache.ReadReq_hits::cpu1.inst 32718599 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 32718599 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 32718599 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 32718599 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 32718599 # number of overall hits
< system.cpu1.icache.overall_hits::total 32718599 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 469742 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 469742 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 469742 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 469742 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 469742 # number of overall misses
< system.cpu1.icache.overall_misses::total 469742 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6348514000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 6348514000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 6348514000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 6348514000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 6348514000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 6348514000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188341 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 33188341 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 33188341 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 33188341 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 33188341 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 33188341 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014154 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.014154 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014154 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.014154 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014154 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.895411 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13514.895411 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13514.895411 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13514.895411 # average overall miss latency
---
> system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits
> system.cpu1.icache.overall_hits::total 32719031 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses
> system.cpu1.icache.overall_misses::total 469722 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency
1084,1095c1084,1095
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469742 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 469742 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 469742 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 469742 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 469742 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 469742 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5409030000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5409030000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5409030000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5409030000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5409030000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5409030000 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 469722 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 469722 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 469722 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 5407172500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 5407172500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 5407172500 # number of overall MSHR miss cycles
1100,1111c1100,1111
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014154 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.014154 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.014154 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11514.895411 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
1117,1121c1117,1121
< system.cpu1.dcache.replacements 291659 # number of replacements
< system.cpu1.dcache.tagsinuse 472.058793 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 11957529 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 292006 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 40.949600 # Average number of references to valid blocks.
---
> system.cpu1.dcache.replacements 291698 # number of replacements
> system.cpu1.dcache.tagsinuse 472.096881 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 11957476 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 292067 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 40.940866 # Average number of references to valid blocks.
1123,1197c1123,1197
< system.cpu1.dcache.occ_blocks::cpu1.data 472.058793 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.921990 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.921990 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 6944275 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 6944275 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 4825543 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 4825543 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81753 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 81753 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82700 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 82700 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 11769818 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 11769818 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 11769818 # number of overall hits
< system.cpu1.dcache.overall_hits::total 11769818 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 170271 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 170271 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 149767 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 149767 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11060 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 11060 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10038 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 10038 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 320038 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 320038 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 320038 # number of overall misses
< system.cpu1.dcache.overall_misses::total 320038 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2152137500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2152137500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4507881000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 4507881000 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91883000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 91883000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51759500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 51759500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 6660018500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 6660018500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 6660018500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 6660018500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114546 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 7114546 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975310 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4975310 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92813 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92738 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency
---
> system.cpu1.dcache.occ_blocks::cpu1.data 472.096881 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.922064 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.922064 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 6944335 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 6944335 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 4825513 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 4825513 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81763 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 81763 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82710 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 82710 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 11769848 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 11769848 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 11769848 # number of overall hits
> system.cpu1.dcache.overall_hits::total 11769848 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 170295 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 170295 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 149789 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 149789 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11069 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 11069 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10034 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 10034 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 320084 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 320084 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 320084 # number of overall misses
> system.cpu1.dcache.overall_misses::total 320084 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2151167000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2151167000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4518557500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 4518557500 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92001000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 92001000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51654000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 51654000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 6669724500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 6669724500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 6669724500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 6669724500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114630 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 7114630 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975302 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 4975302 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92832 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 92832 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92744 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 92744 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 12089932 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 12089932 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 12089932 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 12089932 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023936 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.023936 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030107 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.030107 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119237 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119237 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108190 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108190 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026475 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.026475 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026475 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.026475 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12632.003288 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12632.003288 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30166.150385 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 30166.150385 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8311.590930 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8311.590930 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5147.897150 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5147.897150 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20837.419240 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20837.419240 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 20837.419240 # average overall miss latency
1206,1227c1206,1227
< system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks
< system.cpu1.dcache.writebacks::total 265110 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles
---
> system.cpu1.dcache.writebacks::writebacks 265120 # number of writebacks
> system.cpu1.dcache.writebacks::total 265120 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170295 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 170295 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149789 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 149789 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11069 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11069 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10028 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 10028 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 320084 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 320084 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 320084 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 320084 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles
1230,1259c1230,1259
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency
1262,1265c1262,1265
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
1287,1290c1287,1290
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles