3,5c3,5
< sim_seconds 2.870989 # Number of seconds simulated
< sim_ticks 2870988926500 # Number of ticks simulated
< final_tick 2870988926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.870996 # Number of seconds simulated
> sim_ticks 2870995800500 # Number of ticks simulated
> final_tick 2870995800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 334502 # Simulator instruction rate (inst/s)
< host_op_rate 404603 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 7301303629 # Simulator tick rate (ticks/s)
< host_mem_usage 607968 # Number of bytes of host memory used
< host_seconds 393.22 # Real time elapsed on the host
< sim_insts 131531628 # Number of instructions simulated
< sim_ops 159096162 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1013503 # Simulator instruction rate (inst/s)
> host_op_rate 1225877 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 22160332076 # Simulator tick rate (ticks/s)
> host_mem_usage 622032 # Number of bytes of host memory used
> host_seconds 129.56 # Real time elapsed on the host
> sim_insts 131304972 # Number of instructions simulated
> sim_ops 158819278 # Number of ops (including micro ops) simulated
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
19,24c19,25
< system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1293924 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8559616 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 153620 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 569684 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 405184 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1181796 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1294372 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8555136 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 152212 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 573844 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 414464 # Number of bytes read from this memory
26,30c27,31
< system.physmem.bytes_read::total 12163760 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 153620 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1333816 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8766400 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12173424 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1181796 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 152212 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1334008 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8754752 # Number of bytes written to this memory
33c34
< system.physmem.bytes_written::total 8783964 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8772316 # Number of bytes written to this memory
36,41c37,43
< system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 20737 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 133744 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 2555 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 8922 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 6331 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 26919 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 20744 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 133674 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 2533 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8987 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 6476 # Number of read requests responded to by this memory
43,44c45,46
< system.physmem.num_reads::total 199207 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 136975 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 199358 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 136793 # Number of write requests responded to by this memory
47c49
< system.physmem.num_writes::total 141366 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 141184 # Number of write requests responded to by this memory
50,55c52,58
< system.physmem.bw_read::cpu0.inst 411076 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 450689 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2981417 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 53508 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 198428 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 141130 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 411633 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 450844 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2979850 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 53017 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 199876 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 144362 # Total read bandwidth from this memory (bytes/s)
57,61c60,64
< system.physmem.bw_read::total 4236784 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 411076 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 53508 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 464584 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3053443 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4240140 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 411633 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 53017 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 464650 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3049378 # Write bandwidth from this memory (bytes/s)
64,65c67,68
< system.physmem.bw_write::total 3059560 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3053443 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3055496 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3049378 # Total bandwidth to/from this memory (bytes/s)
68,73c71,77
< system.physmem.bw_total::cpu0.inst 411076 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 456793 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2981417 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 53508 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 198442 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 141130 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 411633 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 456948 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2979850 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 53017 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 199890 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 144362 # Total bandwidth to/from this memory (bytes/s)
75,85c79,89
< system.physmem.bw_total::total 7296344 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 199207 # Number of read requests accepted
< system.physmem.writeReqs 141366 # Number of write requests accepted
< system.physmem.readBursts 199207 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 141366 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12740608 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8796800 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12163760 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8783964 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 7295636 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 199358 # Number of read requests accepted
> system.physmem.writeReqs 141184 # Number of write requests accepted
> system.physmem.readBursts 199358 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 141184 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12748800 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 10112 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8785280 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12173424 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8772316 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by the write queue
88,119c92,123
< system.physmem.perBankRdBursts::0 11688 # Per bank write bursts
< system.physmem.perBankRdBursts::1 11970 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12095 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12159 # Per bank write bursts
< system.physmem.perBankRdBursts::4 20723 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12090 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12329 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12246 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12200 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12543 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11897 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11487 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11682 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11835 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11042 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11086 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8412 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8881 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9049 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8857 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8522 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8714 # Per bank write bursts
< system.physmem.perBankWrBursts::6 9020 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8690 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8720 # Per bank write bursts
< system.physmem.perBankWrBursts::9 9031 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8698 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8602 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8645 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8180 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7869 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7560 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 11937 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11961 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12063 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12015 # Per bank write bursts
> system.physmem.perBankRdBursts::4 20362 # Per bank write bursts
> system.physmem.perBankRdBursts::5 11984 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12067 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12160 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12406 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12763 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11654 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11199 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11763 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11689 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11766 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11411 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8587 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8807 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8988 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8742 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8269 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8555 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8883 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8651 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8881 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9204 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8442 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8330 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8611 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8076 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8388 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7856 # Per bank write bursts
121,122c125,126
< system.physmem.numWrRetry 78 # Number of times write queue was full causing retry
< system.physmem.totGap 2870987895000 # Total gap between requests
---
> system.physmem.numWrRetry 86 # Number of times write queue was full causing retry
> system.physmem.totGap 2870994769000 # Total gap between requests
129c133
< system.physmem.readPktSize::6 189447 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 189598 # Read request sizes (log2)
136,153c140,157
< system.physmem.writePktSize::6 136975 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 135724 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 17225 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 10602 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8875 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7477 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5952 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5078 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4199 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3667 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 121 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 77 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 48 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 136793 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 136138 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 17236 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 10604 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8747 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7299 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5883 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5032 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4260 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3698 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 128 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 51 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
184,250c188,254
< system.physmem.wrQLenPdf::15 2512 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3419 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4336 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5352 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6399 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6487 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7013 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7539 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8538 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8343 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9670 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10012 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8667 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9504 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7890 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7649 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 494 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 441 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 258 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 247 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 210 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 232 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 85540 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 251.780968 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 143.250026 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 307.334701 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 42821 50.06% 50.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18143 21.21% 71.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6218 7.27% 78.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3674 4.30% 82.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2664 3.11% 85.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1727 2.02% 87.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 953 1.11% 89.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 967 1.13% 90.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8373 9.79% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 85540 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6799 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 29.279453 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 564.517669 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6797 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2554 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3487 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4394 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5386 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6479 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6593 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8490 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9668 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9980 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8490 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8411 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9434 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7894 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7591 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 637 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 414 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 292 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 248 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 218 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 252 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 243 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 237 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 225 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 244 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 85519 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 251.803880 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 143.212865 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 307.683468 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 42851 50.11% 50.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18042 21.10% 71.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6336 7.41% 78.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3652 4.27% 82.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2667 3.12% 86.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1677 1.96% 87.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 875 1.02% 88.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 945 1.11% 90.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8474 9.91% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 85519 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 29.315232 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 564.685462 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes
253,299c257,304
< system.physmem.rdPerTurnAround::total 6799 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6799 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.216208 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.546976 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 13.866150 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5813 85.50% 85.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 291 4.28% 89.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 61 0.90% 90.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 49 0.72% 91.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 268 3.94% 95.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 20 0.29% 95.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 11 0.16% 95.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 22 0.32% 96.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 12 0.18% 96.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 7 0.10% 96.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 11 0.16% 96.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 154 2.27% 98.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 6 0.09% 99.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 3 0.04% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 7 0.10% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 4 0.06% 99.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.04% 99.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.01% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 4 0.06% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.01% 99.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 5 0.07% 99.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.01% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.03% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 4 0.06% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 9 0.13% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 4 0.06% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 4 0.06% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 1 0.01% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 4 0.06% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6799 # Writes before turning the bus around for reads
< system.physmem.totQLat 9415943788 # Total ticks spent queuing
< system.physmem.totMemAccLat 13148543788 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 995360000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 47299.19 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.201619 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.574221 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 13.473858 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5740 84.47% 84.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 356 5.24% 89.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 65 0.96% 90.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 46 0.68% 91.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 271 3.99% 95.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 21 0.31% 95.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 19 0.28% 95.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 18 0.26% 96.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 11 0.16% 96.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 7 0.10% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 2 0.03% 96.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 7 0.10% 96.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 153 2.25% 98.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 7 0.10% 98.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 9 0.13% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 5 0.07% 99.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 7 0.10% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.01% 99.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 3 0.04% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.04% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.01% 99.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 4 0.06% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.03% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 3 0.04% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 10 0.15% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.01% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 2 0.03% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.01% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 3 0.04% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 2 0.03% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 2 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads
> system.physmem.totQLat 9377591483 # Total ticks spent queuing
> system.physmem.totMemAccLat 13112591483 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 996000000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 47076.26 # Average queueing delay per DRAM burst
301c306
< system.physmem.avgMemAccLat 66049.19 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 65826.26 # Average memory access latency per DRAM burst
310,314c315,319
< system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing
< system.physmem.readRowHits 166164 # Number of row buffer hits during reads
< system.physmem.writeRowHits 84817 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
---
> system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
> system.physmem.readRowHits 166242 # Number of row buffer hits during reads
> system.physmem.writeRowHits 84708 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.45 # Row buffer hit rate for reads
316c321
< system.physmem.avgGap 8429875.22 # Average gap between requests
---
> system.physmem.avgGap 8430662.79 # Average gap between requests
318,356c323,361
< system.physmem_0.actEnergy 312774840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 166239975 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 751842000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 366156900 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 6214010400.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5556704280 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 357731520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 11629133730 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 9364882080 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 675113260110 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 709836228825 # Total energy per rank (pJ)
< system.physmem_0.averagePower 247.244502 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 2857863952057 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 659296177 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2641884000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 2807973624000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 24387714557 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 9823730266 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 25502677500 # Time in different power states
< system.physmem_1.actEnergy 297987900 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 158384325 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 669532080 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 351332100 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 6199259040.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 5628324780 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 351060000 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 11278473150 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 9521383680 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 675168861345 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 709627419000 # Total energy per rank (pJ)
< system.physmem_1.averagePower 247.171771 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 2857510482171 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 643430972 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2635632000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 2808196835750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 24795240087 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 9984355357 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 24733432334 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.physmem_0.actEnergy 309183420 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 164331090 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 746479860 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 362696040 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6139024320.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5630456580 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 369226560 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 11487380430 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 9121751040 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 675280298985 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 709613489745 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.166328 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2857680941179 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 688127950 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2609960000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2808734663750 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 23754548081 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 10016707371 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 25191793348 # Time in different power states
> system.physmem_1.actEnergy 301429380 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 160213515 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 675808140 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 353853360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 6242283840.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5675698050 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 365488800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 11403357870 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 9537644640 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 675067441050 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 709786212765 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.226489 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2857340478310 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 678311229 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2653946000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2807745675250 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 24837614861 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 10072973461 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 25007279699 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
375,377c380,382
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
385c390
< system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
415,432c420,437
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.dtb.walker.walks 7799 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 7799 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1450 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6349 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 7799 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 7799 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 7799 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 6405 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 12453.161593 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 11389.819011 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 6523.003169 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 5861 91.51% 91.51% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 469 7.32% 98.83% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 66 1.03% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.dtb.walker.walks 7823 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 7823 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1468 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6355 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 7823 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 7823 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 6429 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 12550.163322 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 11491.858959 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 6296.322703 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 5867 91.26% 91.26% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 463 7.20% 98.46% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 86 1.34% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.12% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% # Table walker service (enqueue to completion) latency
434c439
< system.cpu0.dtb.walker.walkCompletionTime::total 6405 # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walkCompletionTime::total 6429 # Table walker service (enqueue to completion) latency
438,441c443,446
< system.cpu0.dtb.walker.walkPageSizes::4K 4994 77.97% 77.97% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1411 22.03% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6405 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7799 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkPageSizes::4K 5000 77.77% 77.77% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1429 22.23% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6429 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 # Table walker requests started/completed, data/inst
443,444c448,449
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7799 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6405 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 # Table walker requests started/completed, data/inst
446,447c451,452
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6405 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 14204 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 14252 # Table walker requests started/completed, data/inst
450,453c455,458
< system.cpu0.dtb.read_hits 25116933 # DTB read hits
< system.cpu0.dtb.read_misses 6669 # DTB read misses
< system.cpu0.dtb.write_hits 18718433 # DTB write hits
< system.cpu0.dtb.write_misses 1130 # DTB write misses
---
> system.cpu0.dtb.read_hits 25081905 # DTB read hits
> system.cpu0.dtb.read_misses 6707 # DTB read misses
> system.cpu0.dtb.write_hits 18693539 # DTB write hits
> system.cpu0.dtb.write_misses 1116 # DTB write misses
458c463
< system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB
460c465
< system.cpu0.dtb.prefetch_faults 1753 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch
463,464c468,469
< system.cpu0.dtb.read_accesses 25123602 # DTB read accesses
< system.cpu0.dtb.write_accesses 18719563 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 25088612 # DTB read accesses
> system.cpu0.dtb.write_accesses 18694655 # DTB write accesses
466,469c471,474
< system.cpu0.dtb.hits 43835366 # DTB hits
< system.cpu0.dtb.misses 7799 # DTB misses
< system.cpu0.dtb.accesses 43843165 # DTB accesses
< system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.hits 43775444 # DTB hits
> system.cpu0.dtb.misses 7823 # DTB misses
> system.cpu0.dtb.accesses 43783267 # DTB accesses
> system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
499,501c504,506
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.itb.walker.walks 3348 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors
---
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.itb.walker.walks 3349 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
503,518c508,521
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3049 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 12654.159520 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 11787.335553 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 5848.484815 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-8191 389 16.68% 16.68% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::8192-16383 1671 71.66% 88.34% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-24575 217 9.31% 97.64% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.16% 98.80% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-40959 21 0.90% 99.70% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.13% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 12879.339906 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 12002.998619 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 5903.446394 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-8191 363 15.56% 15.56% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::8192-16383 1682 72.10% 87.66% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-24575 212 9.09% 96.74% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.59% 98.33% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.54% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
521c524
< system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
525c528
< system.cpu0.itb.walker.walkPageSizes::4K 2033 87.18% 87.18% # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
527c530
< system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
529,530c532,533
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
532,536c535,539
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 118797664 # ITB inst hits
< system.cpu0.itb.inst_misses 3348 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 118659015 # ITB inst hits
> system.cpu0.itb.inst_misses 3349 # ITB inst misses
545c548
< system.cpu0.itb.flush_entries 2086 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
552,563c555,566
< system.cpu0.itb.inst_accesses 118801012 # ITB inst accesses
< system.cpu0.itb.hits 118797664 # DTB hits
< system.cpu0.itb.misses 3348 # DTB misses
< system.cpu0.itb.accesses 118801012 # DTB accesses
< system.cpu0.numPwrStateTransitions 3664 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 1832 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 1490824715.864083 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 23921725256.931263 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::underflows 1059 57.81% 57.81% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.92% 99.73% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
---
> system.cpu0.itb.inst_accesses 118662364 # ITB inst accesses
> system.cpu0.itb.hits 118659015 # DTB hits
> system.cpu0.itb.misses 3349 # DTB misses
> system.cpu0.itb.accesses 118662364 # DTB accesses
> system.cpu0.numPwrStateTransitions 3724 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 1862 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 1466902343.272825 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 23730658455.603134 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
565,569c568,572
< system.cpu0.pwrStateClkGateDist::max_value 499964287288 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::total 1832 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 139798047037 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731190879463 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 5741977853 # number of cpu cycles simulated
---
> system.cpu0.pwrStateClkGateDist::max_value 499963373360 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::total 1862 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 139623637326 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731372163174 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 5741991601 # number of cpu cycles simulated
573,576c576,579
< system.cpu0.kern.inst.quiesce 1832 # number of quiesce instructions executed
< system.cpu0.committedInsts 115134358 # Number of instructions committed
< system.cpu0.committedOps 139131175 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 123155389 # Number of integer alu accesses
---
> system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed
> system.cpu0.committedInsts 114996919 # Number of instructions committed
> system.cpu0.committedOps 138962993 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 122999157 # Number of integer alu accesses
578,580c581,583
< system.cpu0.num_func_calls 12669084 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 15658471 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 123155389 # number of integer instructions
---
> system.cpu0.num_func_calls 12659267 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 15643522 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 122999157 # number of integer instructions
582,583c585,586
< system.cpu0.num_int_register_reads 226724524 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 85578914 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 226444380 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 85465434 # number of times the integer registers were written
586,595c589,598
< system.cpu0.num_cc_register_reads 504070716 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 52161373 # number of times the CC registers were written
< system.cpu0.num_mem_refs 44970744 # number of memory refs
< system.cpu0.num_load_insts 25368600 # Number of load instructions
< system.cpu0.num_store_insts 19602144 # Number of store instructions
< system.cpu0.num_idle_cycles 5462381758.924097 # Number of idle cycles
< system.cpu0.num_busy_cycles 279596094.075903 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.048693 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.951307 # Percentage of idle cycles
< system.cpu0.Branches 29063879 # Number of branches fetched
---
> system.cpu0.num_cc_register_reads 503448381 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 52091583 # number of times the CC registers were written
> system.cpu0.num_mem_refs 44908198 # number of memory refs
> system.cpu0.num_load_insts 25331105 # Number of load instructions
> system.cpu0.num_store_insts 19577093 # Number of store instructions
> system.cpu0.num_idle_cycles 5462744326.346097 # Number of idle cycles
> system.cpu0.num_busy_cycles 279247274.653903 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.048632 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.951368 # Percentage of idle cycles
> system.cpu0.Branches 29039529 # Number of branches fetched
597,624c600,627
< system.cpu0.op_class::IntAlu 97803517 68.44% 68.45% # Class of executed instruction
< system.cpu0.op_class::IntMult 109759 0.08% 68.52% # Class of executed instruction
< system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 8141 0.01% 68.53% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 97695313 68.45% 68.45% # Class of executed instruction
> system.cpu0.op_class::IntMult 108459 0.08% 68.53% # Class of executed instruction
> system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% # Class of executed instruction
628,629c631,632
< system.cpu0.op_class::MemRead 25366344 17.75% 86.28% # Class of executed instruction
< system.cpu0.op_class::MemWrite 19594649 13.71% 99.99% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 25328849 17.75% 86.28% # Class of executed instruction
> system.cpu0.op_class::MemWrite 19569598 13.71% 99.99% # Class of executed instruction
634,640c637,643
< system.cpu0.op_class::total 142894434 # Class of executed instruction
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 691910 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 491.841324 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 42965158 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 692422 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 62.050539 # Average number of references to valid blocks.
---
> system.cpu0.op_class::total 142722234 # Class of executed instruction
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 690121 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 498.373175 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 42907120 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 690633 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 62.127237 # Average number of references to valid blocks.
642,644c645,647
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.841324 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.960628 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.960628 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.373175 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973385 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.973385 # Average percentage of cache occupancy
646,648c649,651
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
650,730c653,733
< system.cpu0.dcache.tags.tag_accesses 88306903 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 88306903 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23857214 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23857214 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 17987587 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 17987587 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319351 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 319351 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364951 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 364951 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361858 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 361858 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 41844801 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 41844801 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 42164152 # number of overall hits
< system.cpu0.dcache.overall_hits::total 42164152 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 395864 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 395864 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 325028 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 325028 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126936 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 126936 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21386 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21386 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19587 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 19587 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 720892 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 720892 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 847828 # number of overall misses
< system.cpu0.dcache.overall_misses::total 847828 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519668500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5519668500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6305983500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 6305983500 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336140000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 336140000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459598500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 459598500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1175500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1175500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 11825652000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 11825652000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 11825652000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 11825652000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 24253078 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 24253078 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 18312615 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 18312615 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446287 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 446287 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386337 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 386337 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381445 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 381445 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 42565693 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 42565693 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 43011980 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 43011980 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016322 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.016322 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017749 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.017749 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284427 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284427 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055356 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055356 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051349 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051349 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016936 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.016936 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13943.345442 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13943.345442 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19401.354653 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 19401.354653 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15717.759282 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15717.759282 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23464.466228 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23464.466228 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 88185256 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 88185256 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23824030 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23824030 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 17964029 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 17964029 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318863 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 318863 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364525 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 364525 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361510 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 361510 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 41788059 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 41788059 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 42106922 # number of overall hits
> system.cpu0.dcache.overall_hits::total 42106922 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 394827 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 394827 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 324085 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 324085 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127008 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 127008 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21435 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21435 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19554 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 19554 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 718912 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 718912 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 845920 # number of overall misses
> system.cpu0.dcache.overall_misses::total 845920 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5517390500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5517390500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6298218500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 6298218500 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337010500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 337010500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 458737500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 458737500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1113000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1113000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11815609000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11815609000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11815609000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11815609000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 24218857 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 24218857 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 18288114 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 18288114 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445871 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 445871 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385960 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 385960 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381064 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 381064 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 42506971 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 42506971 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 42952842 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 42952842 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016302 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.016302 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017721 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.017721 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284854 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284854 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055537 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055537 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051314 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051314 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016913 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.016913 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019694 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.019694 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13974.197560 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13974.197560 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19433.847602 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 19433.847602 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15722.439935 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15722.439935 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23460.033753 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23460.033753 # average StoreCondReq miss latency
733,736c736,739
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16404.193693 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 16404.193693 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13948.173450 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13948.173450 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16435.403777 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 16435.403777 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13967.761727 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13967.761727 # average overall miss latency
743,818c746,819
< system.cpu0.dcache.writebacks::writebacks 691910 # number of writebacks
< system.cpu0.dcache.writebacks::total 691910 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25218 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 25218 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15019 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15019 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 25219 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 25219 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 25219 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 25219 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370646 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 370646 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325027 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 325027 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99914 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 99914 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6367 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6367 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19587 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 19587 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 695673 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 695673 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 795587 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 795587 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60236 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4741194000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741194000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5980473000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5980473000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1654728000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1654728000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97962000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97962000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440045500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440045500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1141500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1141500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10721667000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 10721667000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376395000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 12376395000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631909500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631909500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631909500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631909500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015282 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015282 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017749 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017749 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223878 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223878 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016480 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016480 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051349 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051349 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016344 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.016344 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12791.704214 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12791.704214 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18399.926775 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18399.926775 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16561.522910 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16561.522910 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15385.896026 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15385.896026 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22466.202073 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22466.202073 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 690121 # number of writebacks
> system.cpu0.dcache.writebacks::total 690121 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25200 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 25200 # number of ReadReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15056 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15056 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 25200 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 25200 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 25200 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 25200 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369627 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 369627 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324085 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 324085 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100010 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 100010 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6379 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6379 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19554 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 19554 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 693712 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 693712 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 793722 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 793722 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31768 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60214 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4739955500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739955500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5974133500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5974133500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1650418500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1650418500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101003000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101003000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439215500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439215500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1081000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1081000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10714089000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10714089000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12364507500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 12364507500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631169500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631169500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631169500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631169500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015262 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015262 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017721 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017721 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224303 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224303 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016528 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016528 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051314 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051314 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016320 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.016320 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018479 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.018479 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12823.618134 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12823.618134 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18433.847602 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18433.847602 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16502.534747 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16502.534747 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15833.672989 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15833.672989 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22461.670246 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22461.670246 # average StoreCondReq mshr miss latency
821,834c822,835
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15411.934918 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15411.934918 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15556.306224 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15556.306224 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208668.727582 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208668.727582 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110098.769839 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110098.769839 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 1101405 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.436911 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 117695738 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1101917 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 106.809985 # Average number of references to valid blocks.
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15444.577865 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15444.577865 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15577.881802 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15577.881802 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208737.392974 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208737.392974 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110126.706414 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110126.706414 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 1095423 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.436912 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 117563071 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1095935 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 107.271938 # Average number of references to valid blocks.
836c837
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436911 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436912 # Average occupied blocks per requestor
841,842c842,843
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
844,882c845,883
< system.cpu0.icache.tags.tag_accesses 238697254 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 238697254 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 117695738 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 117695738 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 117695738 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 117695738 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 117695738 # number of overall hits
< system.cpu0.icache.overall_hits::total 117695738 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1101926 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1101926 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1101926 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1101926 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1101926 # number of overall misses
< system.cpu0.icache.overall_misses::total 1101926 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11884591500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 11884591500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 11884591500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 11884591500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 11884591500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 11884591500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 118797664 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 118797664 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 118797664 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 118797664 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 118797664 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 118797664 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10785.290029 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10785.290029 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10785.290029 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10785.290029 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 238413974 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 238413974 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 117563071 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 117563071 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 117563071 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 117563071 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 117563071 # number of overall hits
> system.cpu0.icache.overall_hits::total 117563071 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1095944 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1095944 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1095944 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1095944 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1095944 # number of overall misses
> system.cpu0.icache.overall_misses::total 1095944 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11846969000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 11846969000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 11846969000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 11846969000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 11846969000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 11846969000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 118659015 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 118659015 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 118659015 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 118659015 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 118659015 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 118659015 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009236 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.009236 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009236 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.009236 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009236 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.009236 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10809.830612 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10809.830612 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10809.830612 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10809.830612 # average overall miss latency
889,896c890,897
< system.cpu0.icache.writebacks::writebacks 1101405 # number of writebacks
< system.cpu0.icache.writebacks::total 1101405 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101926 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1101926 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101926 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1101926 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101926 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1101926 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 1095423 # number of writebacks
> system.cpu0.icache.writebacks::total 1095423 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1095944 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1095944 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1095944 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1095944 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1095944 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1095944 # number of overall MSHR misses
901,906c902,907
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11333628500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11333628500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11333628500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11333628500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11333628500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11333628500 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11298997000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11298997000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11298997000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11298997000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11298997000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11298997000 # number of overall MSHR miss cycles
911,922c912,923
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10285.290029 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009236 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.009236 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.009236 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10309.830612 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency
927,930c928,931
< system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842335 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1842343 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843455 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1843489 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 30 # number of redundant prefetches already in prefetch queue
933,939c934,940
< system.cpu0.l2cache.prefetcher.pfSpanPage 236049 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.tags.replacements 259510 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 15639.759609 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1683263 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 275158 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.117442 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 237167 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.tags.replacements 260392 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15616.554479 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1673878 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 276011 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.064534 # Average number of references to valid blocks.
941,956c942,957
< system.cpu0.l2cache.tags.occ_blocks::writebacks 14465.018905 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.607944 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.119153 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1173.013607 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.882875 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000098 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071595 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.954575 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 297 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15346 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 119 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 14458.510897 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.380966 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135465 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1156.527151 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.882477 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070589 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.953159 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15300 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 129 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 150 # Occupied blocks per task id
958,1075c959,1075
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 812 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6453 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1818 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018127 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936646 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 61207036 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 61207036 # Number of data accesses
< system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9838 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4464 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 14302 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 475527 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 475527 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 1289984 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 1289984 # number of WritebackClean hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227136 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 227136 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1039867 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1039867 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376033 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 376033 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9838 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4464 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1039867 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 603169 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1657338 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9838 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4464 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1039867 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 603169 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1657338 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 303 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 441 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54610 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 54610 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19582 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19582 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43281 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 43281 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62059 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 62059 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100894 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 100894 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 303 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 62059 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144175 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 206675 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 303 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 62059 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144175 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 206675 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8179000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3277000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 11456000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32137500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 32137500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8911500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8911500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1089999 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1089999 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2751603000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2751603000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3417541500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3417541500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3327393000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3327393000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8179000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3277000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3417541500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 6078996000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 9507993500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8179000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3277000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3417541500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 6078996000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 9507993500 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10141 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4602 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 14743 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475527 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 475527 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289984 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 1289984 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54610 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 54610 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19582 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 19582 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270417 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 270417 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1101926 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1101926 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476927 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 476927 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10141 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4602 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1101926 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 747344 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1864013 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10141 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4602 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1101926 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 747344 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1864013 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029987 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6046 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6216 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2035 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933838 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 60952812 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 60952812 # Number of data accesses
> system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9949 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4513 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 14462 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 474087 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 474087 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 1283679 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 1283679 # number of WritebackClean hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226501 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 226501 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1033387 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1033387 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 374984 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 374984 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9949 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4513 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1033387 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 601485 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1649334 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9949 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4513 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1033387 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 601485 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1649334 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 333 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 154 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 487 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54609 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 54609 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19552 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19552 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42975 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 42975 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62557 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 62557 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101032 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 101032 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 333 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 154 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 62557 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 144007 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 207051 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 333 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 154 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 62557 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 144007 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 207051 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8868000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 12486500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 29801000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 29801000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8716000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8716000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1032499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1032499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2749345500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2749345500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3431495000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3431495000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3333037000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3333037000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8868000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3431495000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 6082382500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 9526364000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8868000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3431495000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 6082382500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 9526364000 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10282 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4667 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 14949 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 474087 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 474087 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 1283679 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 1283679 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54609 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 54609 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19552 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 19552 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269476 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 269476 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1095944 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1095944 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476016 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 476016 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10282 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4667 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1095944 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 745492 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1856385 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10282 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4667 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1095944 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 745492 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1856385 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032998 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.032577 # miss rate for ReadReq accesses
1082,1122c1082,1122
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.160053 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.160053 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056319 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056319 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211550 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211550 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029987 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056319 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.192917 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.110876 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029987 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056319 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.192917 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.110876 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23746.376812 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25977.324263 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 588.491119 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 588.491119 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 455.086304 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 455.086304 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 217999.800000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 217999.800000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63575.310182 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63575.310182 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55069.232505 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55069.232505 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32979.096874 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32979.096874 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 46004.565139 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 46004.565139 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159476 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159476 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.057080 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.057080 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212245 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212245 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032998 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057080 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193170 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.111535 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032998 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057080 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193170 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.111535 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23496.753247 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25639.630390 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 545.715908 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 545.715908 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 445.785597 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 445.785597 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 516249.500000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 516249.500000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63975.462478 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63975.462478 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54853.893249 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54853.893249 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32989.914087 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32989.914087 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 46009.746391 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 46009.746391 # average overall miss latency
1129,1133c1129,1133
< system.cpu0.l2cache.unused_prefetches 10584 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 226675 # number of writebacks
< system.cpu0.l2cache.writebacks::total 226675 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1590 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 1590 # number of ReadExReq MSHR hits
---
> system.cpu0.l2cache.unused_prefetches 10486 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 227470 # number of writebacks
> system.cpu0.l2cache.writebacks::total 227470 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1575 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 1575 # number of ReadExReq MSHR hits
1136,1167c1136,1167
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1620 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 1620 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1620 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 1620 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 303 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 262593 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54610 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54610 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19582 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19582 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41691 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 41691 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62059 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62059 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100864 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100864 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 303 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62059 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142555 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 205055 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 303 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62059 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142555 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 467648 # number of overall MSHR misses
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1605 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 1605 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1605 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 1605 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 333 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 154 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 487 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 261736 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54609 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54609 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19552 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19552 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41400 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41400 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62557 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62557 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 333 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 154 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62557 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142402 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 205446 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 333 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 154 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62557 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142402 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 467182 # number of overall MSHR misses
1169,1172c1169,1172
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40804 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40790 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable
1174,1203c1174,1203
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69258 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2449000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 8810000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16813897141 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 934853500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 934853500 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293341500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293341500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 885999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 885999 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2209696500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2209696500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3045187500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3045187500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2716829000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2716829000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2449000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3045187500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4926525500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 7980523000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2449000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3045187500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4926525500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 24794420141 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69236 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2694500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9564500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16748653122 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 936375500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 936375500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292739000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292739000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 840499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 840499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2221757000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2221757000 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3056153000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3056153000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2721461500 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2721461500 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2694500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3056153000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4943218500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 8008936000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2694500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3056153000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4943218500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 24757589122 # number of overall MSHR miss cycles
1205,1206c1205,1206
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377241500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172882000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6376615000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172255500 # number of ReadReq MSHR uncacheable cycles
1208,1212c1208,1212
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377241500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172882000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029913 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6376615000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172255500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032577 # mshr miss rate for ReadReq accesses
1221,1235c1221,1235
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154173 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154173 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056319 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211487 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211487 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110007 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153631 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153631 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.057080 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212182 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212182 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110670 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for overall accesses
1237,1265c1237,1265
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.250882 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19977.324263 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64030.256484 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17118.723677 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17118.723677 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14980.160351 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14980.160351 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 177199.800000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 177199.800000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53001.762970 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53001.762970 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49069.232505 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26935.566704 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26935.566704 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38918.938821 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53019.408061 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251662 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19639.630390 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63990.636068 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17146.908019 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17146.908019 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14972.330196 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.330196 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 420249.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 420249.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53665.628019 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53665.628019 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48853.893249 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26944.629809 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26944.629809 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38983.168326 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52993.456773 # average overall mshr miss latency
1267,1268c1267,1268
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200655.764269 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175788.697187 # average ReadReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200724.471166 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175833.672469 # average ReadReq mshr uncacheable latency
1270,1311c1270,1313
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105870.932665 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103567.558982 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 3728751 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879521 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27804 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 211480 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209803 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1677 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu0.toL2Bus.trans_dist::ReadReq 61377 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1688185 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28454 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28454 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 702444 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 1317788 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 79827 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 309039 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 86996 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41768 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 111544 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 289661 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 286091 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1101926 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562800 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 3273 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3323301 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2556545 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10999 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24289 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 5915134 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141049272 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96382808 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18408 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40564 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 237491052 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 885699 # Total snoops (count)
< system.cpu0.toL2Bus.snoopTraffic 18622452 # Total snoop traffic (bytes)
< system.cpu0.toL2Bus.snoop_fanout::samples 2792086 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.090598 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.289121 # Request fanout histogram
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105899.209486 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.419204 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 3713043 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871637 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27791 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 210694 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209047 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1647 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu0.toL2Bus.trans_dist::ReadReq 61395 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1681090 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28446 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28446 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 701864 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 1311457 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 80209 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 307976 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 86960 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41708 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 111633 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 288540 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 285048 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095944 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562349 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3305355 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550756 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11066 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24460 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 5891637 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140283576 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96129280 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18668 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41128 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 236472652 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 885693 # Total snoops (count)
> system.cpu0.toL2Bus.snoopTraffic 18656572 # Total snoop traffic (bytes)
> system.cpu0.toL2Bus.snoop_fanout::samples 2784580 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.090516 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.288973 # Request fanout histogram
1313,1315c1315,1317
< system.cpu0.toL2Bus.snoop_fanout::0 2540806 91.00% 91.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 249603 8.94% 99.94% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 1677 0.06% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 2534179 91.01% 91.01% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 248754 8.93% 99.94% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 1647 0.06% 100.00% # Request fanout histogram
1319,1320c1321,1322
< system.cpu0.toL2Bus.snoop_fanout::total 2792086 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 3710834999 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 2784580 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 3695245998 # Layer occupancy (ticks)
1322c1324
< system.cpu0.toL2Bus.snoopLayer0.occupancy 114296030 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 113887546 # Layer occupancy (ticks)
1324c1326
< system.cpu0.toL2Bus.respLayer0.occupancy 1661911000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1652938000 # Layer occupancy (ticks)
1326c1328
< system.cpu0.toL2Bus.respLayer1.occupancy 1204165985 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1201348488 # Layer occupancy (ticks)
1328c1330
< system.cpu0.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
1330c1332
< system.cpu0.toL2Bus.respLayer3.occupancy 14154986 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 14180994 # Layer occupancy (ticks)
1332c1334
< system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
1362,1364c1364,1366
< system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
---
> system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.dtb.walker.walks 3368 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 3368 # Table walker walks initiated with short descriptors
1366,1387c1368,1385
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 2589 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 12693.897258 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 11812.728196 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 5453.033399 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-4095 2 0.08% 0.08% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::4096-8191 579 22.36% 22.44% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1101 42.53% 64.97% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::12288-16383 577 22.29% 87.25% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-20479 84 3.24% 90.50% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::20480-24575 148 5.72% 96.21% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-28671 49 1.89% 98.11% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::28672-32767 18 0.70% 98.80% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-36863 23 0.89% 99.69% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.08% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-45055 4 0.15% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 2589 # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 3368 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 3368 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 3368 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 2598 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 12496.920708 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 11544.208502 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 5669.313441 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-8191 611 23.52% 23.52% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 64.32% 87.84% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 8.85% 96.69% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::24576-32767 69 2.66% 99.35% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-40959 10 0.38% 99.73% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 2598 # Table walker service (enqueue to completion) latency
1391,1394c1389,1392
< system.cpu1.dtb.walker.walkPageSizes::4K 1928 74.47% 74.47% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 661 25.53% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.56% 74.56% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 661 25.44% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3368 # Table walker requests started/completed, data/inst
1396,1397c1394,1395
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3368 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst
1399,1400c1397,1398
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 5966 # Table walker requests started/completed, data/inst
1403,1406c1401,1404
< system.cpu1.dtb.read_hits 3975776 # DTB read hits
< system.cpu1.dtb.read_misses 2856 # DTB read misses
< system.cpu1.dtb.write_hits 3446428 # DTB write hits
< system.cpu1.dtb.write_misses 503 # DTB write misses
---
> system.cpu1.dtb.read_hits 3952331 # DTB read hits
> system.cpu1.dtb.read_misses 2852 # DTB read misses
> system.cpu1.dtb.write_hits 3427850 # DTB write hits
> system.cpu1.dtb.write_misses 516 # DTB write misses
1411c1409
< system.cpu1.dtb.flush_entries 1973 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_entries 1975 # Number of entries that have been flushed from TLB
1413c1411
< system.cpu1.dtb.prefetch_faults 329 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 341 # Number of TLB faults due to prefetch
1416,1417c1414,1415
< system.cpu1.dtb.read_accesses 3978632 # DTB read accesses
< system.cpu1.dtb.write_accesses 3446931 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 3955183 # DTB read accesses
> system.cpu1.dtb.write_accesses 3428366 # DTB write accesses
1419,1422c1417,1420
< system.cpu1.dtb.hits 7422204 # DTB hits
< system.cpu1.dtb.misses 3359 # DTB misses
< system.cpu1.dtb.accesses 7425563 # DTB accesses
< system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dtb.hits 7380181 # DTB hits
> system.cpu1.dtb.misses 3368 # DTB misses
> system.cpu1.dtb.accesses 7383549 # DTB accesses
> system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
1452c1450
< system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
1461,1474c1459,1473
< system.cpu1.itb.walker.walkCompletionTime::mean 13066.847335 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 12198.452511 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5775.216215 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::4096-8191 143 12.92% 12.92% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 70.55% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 85.64% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-20479 51 4.61% 90.24% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::20480-24575 51 4.61% 94.85% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.53% 97.38% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 98.92% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 99.01% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.45% 99.46% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.73% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.27% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkCompletionTime::mean 12746.160795 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 11849.716682 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5651.710937 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.36% 15.36% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 628 56.73% 72.09% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 162 14.63% 86.72% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.43% 91.15% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 38 3.43% 94.58% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 32 2.89% 97.47% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.01% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-36863 4 0.36% 99.37% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1489c1488
< system.cpu1.itb.inst_hits 16753470 # ITB inst hits
---
> system.cpu1.itb.inst_hits 16663369 # ITB inst hits
1506,1507c1505,1506
< system.cpu1.itb.inst_accesses 16755216 # ITB inst accesses
< system.cpu1.itb.hits 16753470 # DTB hits
---
> system.cpu1.itb.inst_accesses 16665115 # ITB inst accesses
> system.cpu1.itb.hits 16663369 # DTB hits
1509,1515c1508,1514
< system.cpu1.itb.accesses 16755216 # DTB accesses
< system.cpu1.numPwrStateTransitions 5461 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 2731 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 1041523757.275357 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 25854556705.104488 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::underflows 1955 71.59% 71.59% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 770 28.19% 99.78% # Distribution of time spent in the clock gated state
---
> system.cpu1.itb.accesses 16665115 # DTB accesses
> system.cpu1.numPwrStateTransitions 5435 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 2718 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 1046549937.704562 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 25917662670.452511 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::underflows 1945 71.56% 71.56% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 767 28.22% 99.78% # Distribution of time spent in the clock gated state
1523,1526c1522,1525
< system.cpu1.pwrStateClkGateDist::total 2731 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 26587545381 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844401381119 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 5741033861 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::total 2718 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 26473069819 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844522730681 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 5741059879 # number of cpu cycles simulated
1530,1533c1529,1532
< system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed
< system.cpu1.committedInsts 16397270 # Number of instructions committed
< system.cpu1.committedOps 19964987 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 17986629 # Number of integer alu accesses
---
> system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed
> system.cpu1.committedInsts 16308053 # Number of instructions committed
> system.cpu1.committedOps 19856285 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 17888019 # Number of integer alu accesses
1535,1537c1534,1536
< system.cpu1.num_func_calls 1033857 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 1854028 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 17986629 # number of integer instructions
---
> system.cpu1.num_func_calls 1028859 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 1844250 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 17888019 # number of integer instructions
1539,1540c1538,1539
< system.cpu1.num_int_register_reads 32622652 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 12608250 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 32444258 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 12537466 # number of times the integer registers were written
1543,1552c1542,1551
< system.cpu1.num_cc_register_reads 72946565 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 6544066 # number of times the CC registers were written
< system.cpu1.num_mem_refs 7656991 # number of memory refs
< system.cpu1.num_load_insts 4087327 # Number of load instructions
< system.cpu1.num_store_insts 3569664 # Number of store instructions
< system.cpu1.num_idle_cycles 5687867512.323336 # Number of idle cycles
< system.cpu1.num_busy_cycles 53166348.676665 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.009261 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.990739 # Percentage of idle cycles
< system.cpu1.Branches 2968001 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 72543530 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 6508973 # number of times the CC registers were written
> system.cpu1.num_mem_refs 7613771 # number of memory refs
> system.cpu1.num_load_insts 4063495 # Number of load instructions
> system.cpu1.num_store_insts 3550276 # Number of store instructions
> system.cpu1.num_idle_cycles 5688122330.646462 # Number of idle cycles
> system.cpu1.num_busy_cycles 52937548.353538 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.009221 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.990779 # Percentage of idle cycles
> system.cpu1.Branches 2952894 # Number of branches fetched
1554,1555c1553,1554
< system.cpu1.op_class::IntAlu 12630695 62.17% 62.17% # Class of executed instruction
< system.cpu1.op_class::IntMult 26529 0.13% 62.30% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 12563541 62.17% 62.17% # Class of executed instruction
> system.cpu1.op_class::IntMult 26310 0.13% 62.30% # Class of executed instruction
1581,1586c1580,1585
< system.cpu1.op_class::SimdFloatMisc 3311 0.02% 62.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% # Class of executed instruction
< system.cpu1.op_class::MemRead 4086811 20.11% 82.43% # Class of executed instruction
< system.cpu1.op_class::MemWrite 3568388 17.56% 99.99% # Class of executed instruction
---
> system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.32% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction
> system.cpu1.op_class::MemRead 4062979 20.11% 82.43% # Class of executed instruction
> system.cpu1.op_class::MemWrite 3549000 17.56% 99.99% # Class of executed instruction
1591,1676c1590,1675
< system.cpu1.op_class::total 20317592 # Class of executed instruction
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 188214 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 469.650282 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 7155880 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 188578 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 37.946526 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 105561245500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.650282 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917286 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.917286 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 15064679 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 15064679 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 3662279 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3662279 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3257080 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3257080 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49206 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 49206 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79332 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 79332 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71298 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 71298 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 6919359 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 6919359 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 6968565 # number of overall hits
< system.cpu1.dcache.overall_hits::total 6968565 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 134376 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 134376 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 92202 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 92202 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30516 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 30516 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17009 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17009 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23197 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23197 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 226578 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 226578 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 257094 # number of overall misses
< system.cpu1.dcache.overall_misses::total 257094 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2053970000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2053970000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2521876000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2521876000 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321694000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 321694000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544347500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 544347500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1836500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1836500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4575846000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4575846000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4575846000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4575846000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3796655 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3796655 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 3349282 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 3349282 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79722 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 79722 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96341 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 96341 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94495 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 94495 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 7145937 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 7145937 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 7225659 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 7225659 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035393 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.035393 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027529 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.027529 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382780 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382780 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176550 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176550 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.245484 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.245484 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031707 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.031707 # miss rate for demand accesses
---
> system.cpu1.op_class::total 20206967 # Class of executed instruction
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 187241 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 470.165247 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 7113602 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 187604 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 37.918179 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 128171950500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.165247 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918291 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.918291 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 14979376 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 14979376 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3640649 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3640649 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 3239316 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 3239316 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49005 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 49005 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78940 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 78940 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70837 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 70837 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 6879965 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 6879965 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 6928970 # number of overall hits
> system.cpu1.dcache.overall_hits::total 6928970 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 133578 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 133578 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 91863 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 91863 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30193 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 30193 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16916 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 16916 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23207 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23207 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 225441 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 225441 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 255634 # number of overall misses
> system.cpu1.dcache.overall_misses::total 255634 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2045952000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2045952000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2531885000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 2531885000 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322352500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 322352500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544400500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 544400500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2036500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2036500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4577837000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4577837000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4577837000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4577837000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3774227 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3774227 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 3331179 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 3331179 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79198 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 79198 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95856 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 95856 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94044 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 94044 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 7105406 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 7105406 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 7184604 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 7184604 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035392 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035392 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027577 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.027577 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381234 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381234 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176473 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176473 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246767 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246767 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031728 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031728 # miss rate for demand accesses
1679,1686c1678,1685
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15285.244389 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15285.244389 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27351.640962 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 27351.640962 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18913.163619 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18913.163619 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23466.288744 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23466.288744 # average StoreCondReq miss latency
---
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15316.534160 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15316.534160 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27561.531846 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 27561.531846 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19056.071175 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19056.071175 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23458.460809 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23458.460809 # average StoreCondReq miss latency
1689,1692c1688,1691
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20195.455870 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20195.455870 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17798.338351 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17798.338351 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20306.142184 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20306.142184 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17907.778308 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17907.778308 # average overall miss latency
1699,1772c1698,1771
< system.cpu1.dcache.writebacks::writebacks 188214 # number of writebacks
< system.cpu1.dcache.writebacks::total 188214 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 253 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 253 # number of ReadReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12043 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12043 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 253 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 253 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 253 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134123 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 134123 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92202 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 92202 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29799 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 29799 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4966 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4966 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23197 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23197 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 226325 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 226325 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 256124 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 256124 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5526 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1909849500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1909849500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2429674000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2429674000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508192000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508192000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89547000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89547000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521193500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521193500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1793500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4339523500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4339523500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4847715500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4847715500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443097000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443097000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443097000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443097000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035327 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035327 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027529 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027529 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373786 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373786 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051546 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051546 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.245484 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.245484 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031672 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.031672 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035446 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.035446 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14239.537589 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14239.537589 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26351.640962 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26351.640962 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17053.995101 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17053.995101 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18032.017720 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18032.017720 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22468.142432 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22468.142432 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 187241 # number of writebacks
> system.cpu1.dcache.writebacks::total 187241 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 248 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11947 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11947 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 248 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 248 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133330 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 133330 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91863 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 91863 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29503 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 29503 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4969 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4969 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23207 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23207 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 225193 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 225193 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 254696 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 254696 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3077 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5509 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901282500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901282500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2440022000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2440022000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 505317500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 505317500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91175500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91175500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521240500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521240500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1989500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1989500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4341304500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4341304500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846622000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4846622000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442663500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442663500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442663500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442663500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035326 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035326 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027577 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027577 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372522 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372522 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051838 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051838 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246767 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246767 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031693 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031693 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035450 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035450 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14259.975249 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14259.975249 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26561.531846 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26561.531846 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17127.664983 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17127.664983 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18348.862950 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18348.862950 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22460.486060 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22460.486060 # average StoreCondReq mshr miss latency
1775,1792c1774,1791
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19173.858389 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19173.858389 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18927.220799 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18927.220799 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143629.497569 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143629.497569 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80184.039088 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80184.039088 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 506865 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.456606 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 16246088 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 507377 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 32.019757 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 85409397000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.456606 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973548 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973548 # Average percentage of cache occupancy
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19278.150298 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19278.150298 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19029.046393 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19029.046393 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143862.040949 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143862.040949 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80352.786350 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80352.786350 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 503470 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.455555 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 16159382 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 503982 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 32.063411 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 85409649000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455555 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.973546 # Average percentage of cache occupancy
1794,1795c1793,1794
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 389 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id
1798,1836c1797,1835
< system.cpu1.icache.tags.tag_accesses 34014307 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 34014307 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 16246088 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 16246088 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 16246088 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 16246088 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 16246088 # number of overall hits
< system.cpu1.icache.overall_hits::total 16246088 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 507377 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 507377 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 507377 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 507377 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 507377 # number of overall misses
< system.cpu1.icache.overall_misses::total 507377 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4790701000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4790701000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4790701000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4790701000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4790701000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4790701000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 16753465 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 16753465 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 16753465 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 16753465 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 16753465 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 16753465 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030285 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.030285 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030285 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.030285 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030285 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.030285 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9442.093355 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9442.093355 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9442.093355 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9442.093355 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 33830710 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 33830710 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 16159382 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 16159382 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 16159382 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 16159382 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 16159382 # number of overall hits
> system.cpu1.icache.overall_hits::total 16159382 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 503982 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 503982 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 503982 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 503982 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 503982 # number of overall misses
> system.cpu1.icache.overall_misses::total 503982 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4760681000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4760681000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4760681000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4760681000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4760681000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4760681000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 16663364 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 16663364 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 16663364 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 16663364 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 16663364 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 16663364 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030245 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.030245 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030245 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.030245 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030245 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.030245 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9446.132997 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9446.132997 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9446.132997 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9446.132997 # average overall miss latency
1843,1850c1842,1849
< system.cpu1.icache.writebacks::writebacks 506865 # number of writebacks
< system.cpu1.icache.writebacks::total 506865 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 507377 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 507377 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 507377 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 507377 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 507377 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 507377 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 503470 # number of writebacks
> system.cpu1.icache.writebacks::total 503470 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503982 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 503982 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 503982 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 503982 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 503982 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 503982 # number of overall MSHR misses
1855,1860c1854,1859
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4537012500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4537012500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4537012500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4537012500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4537012500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4537012500 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4508690000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4508690000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4508690000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4508690000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4508690000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4508690000 # number of overall MSHR miss cycles
1865,1876c1864,1875
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030285 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.030285 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.030285 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8942.093355 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030245 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.030245 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.030245 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8946.132997 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency
1881,1883c1880,1882
< system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 202159 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 202159 # number of prefetch candidates identified
---
> system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 202393 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 202393 # number of prefetch candidates identified
1887,1893c1886,1892
< system.cpu1.l2cache.prefetcher.pfSpanPage 59833 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.tags.replacements 43683 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 14553.446834 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 604546 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 57834 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 10.453124 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 60767 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.tags.replacements 44084 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 14674.344516 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 603056 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 58488 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 10.310765 # Average number of references to valid blocks.
1895,2025c1894,2024
< system.cpu1.l2cache.tags.occ_blocks::writebacks 14136.855711 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.245443 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.035798 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 412.309882 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.862845 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000137 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025165 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.888272 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13825 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 293 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1016 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2429 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10380 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.843811 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 24413579 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 24413579 # Number of data accesses
< system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3816 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 5831 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 114934 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 114934 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 568988 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 568988 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27893 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 27893 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485948 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 485948 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99069 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 99069 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3816 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 485948 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 126962 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 618741 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3816 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2015 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 485948 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 126962 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 618741 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 325 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 766 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29445 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29445 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23189 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 23189 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34864 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 34864 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21429 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 21429 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69819 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 69819 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 325 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 21429 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 104683 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 126878 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 325 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 21429 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 104683 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 126878 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9097000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6572000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 15669000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14547500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 14547500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17306000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17306000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1729000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1729000 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1479795000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1479795000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845906500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845906500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606277000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606277000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9097000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6572000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845906500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3086072000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 3947647500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9097000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6572000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845906500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3086072000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 3947647500 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4257 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2340 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 6597 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114934 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 114934 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 568988 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 568988 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29445 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 29445 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23189 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23189 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62757 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 62757 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 507377 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 507377 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168888 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 168888 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4257 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2340 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 507377 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 231645 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 745619 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4257 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2340 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 507377 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 231645 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 745619 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138889 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.116113 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 14288.601821 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.272921 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.058859 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.410915 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.872107 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023279 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.895651 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14077 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 292 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 892 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2699 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10486 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.859192 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 24261935 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 24261935 # Number of data accesses
> system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3748 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1963 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 5711 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 114339 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 114339 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 565289 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 565289 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27869 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 27869 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 482614 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 482614 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98302 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 98302 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3748 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1963 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 482614 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 126171 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 614496 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3748 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1963 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 482614 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 126171 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 614496 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 433 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 316 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29344 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29344 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23201 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 23201 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34650 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 34650 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21368 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 21368 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69500 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 69500 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 433 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 316 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 21368 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 104150 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 126267 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 433 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 316 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 21368 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 104150 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 126267 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8916500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6346000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 15262500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14232000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 14232000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17729000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17729000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1919000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1919000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1493005000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1493005000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 842821500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 842821500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1603059500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1603059500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8916500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6346000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 842821500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3096064500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3954148500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8916500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6346000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 842821500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3096064500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3954148500 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4181 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2279 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 6460 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114339 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 114339 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 565289 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 565289 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29344 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 29344 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23201 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23201 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62519 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 62519 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 503982 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 503982 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167802 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 167802 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4181 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2279 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 503982 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 230321 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 740763 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4181 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2279 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 503982 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 230321 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 740763 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138657 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.115944 # miss rate for ReadReq accesses
2032,2072c2031,2071
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555540 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555540 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042235 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042235 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.413404 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.413404 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138889 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042235 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.451911 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.170165 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138889 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042235 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.451911 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.170165 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20221.538462 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20455.613577 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 494.056716 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 494.056716 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 746.302126 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 746.302126 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 216125 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 216125 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42444.785452 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42444.785452 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39474.847170 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39474.847170 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23006.302009 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23006.302009 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 31113.727360 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 31113.727360 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554232 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554232 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042398 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042398 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414179 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414179 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138657 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042398 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452195 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.170455 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138657 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042398 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452195 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.170455 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20082.278481 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20377.169559 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 485.005453 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 485.005453 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 764.148097 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 764.148097 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 319833.333333 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 319833.333333 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43088.167388 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43088.167388 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39443.162673 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39443.162673 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23065.604317 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23065.604317 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 31315.771342 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 31315.771342 # average overall miss latency
2079,2115c2078,2114
< system.cpu1.l2cache.unused_prefetches 815 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 32960 # number of writebacks
< system.cpu1.l2cache.writebacks::total 32960 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 325 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 25865 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29445 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29445 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23189 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23189 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34780 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 34780 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21429 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21429 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69819 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69819 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 325 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21429 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104599 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 126794 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 325 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21429 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104599 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 152659 # number of overall MSHR misses
---
> system.cpu1.l2cache.unused_prefetches 850 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 33278 # number of writebacks
> system.cpu1.l2cache.writebacks::total 33278 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 91 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 91 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 91 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 433 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 316 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 26693 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29344 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29344 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23201 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23201 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34559 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 34559 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21368 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21368 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69500 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69500 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 433 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 316 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21368 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104059 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 126176 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 433 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 316 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21368 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104059 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 152869 # number of overall MSHR misses
2117,2120c2116,2119
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3262 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3254 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable
2122,2151c2121,2150
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5703 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4622000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11073000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 943203517 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 450885000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 450885000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347198000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347198000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1471000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1471000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1260374500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1260374500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 717332500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 717332500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1187363000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1187363000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4622000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 717332500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2447737500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3176143000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4622000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 717332500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2447737500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4119346517 # number of overall MSHR miss cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5686 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4450000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10768500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 957745966 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 449306000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 449306000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347204000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347204000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1637000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1637000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1274798000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1274798000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 714613500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 714613500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1186059500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1186059500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4450000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 714613500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2460857500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3186239500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4450000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 714613500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2460857500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4143985466 # number of overall MSHR miss cycles
2153,2154c2152,2153
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418070500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433811500 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417705000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433446000 # number of ReadReq MSHR uncacheable cycles
2156,2160c2155,2159
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418070500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433811500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.116113 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417705000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433446000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115944 # mshr miss rate for ReadReq accesses
2169,2183c2168,2182
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554201 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554201 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042235 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.413404 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.413404 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170052 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552776 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552776 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042398 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414179 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414179 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170332 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for overall accesses
2185,2213c2184,2212
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.204741 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14455.613577 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36466.403132 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.786551 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15312.786551 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14972.530079 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.530079 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183875 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183875 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36238.484761 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36238.484761 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33474.847170 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17006.302009 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17006.302009 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25049.631686 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26983.974197 # average overall mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206367 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14377.169559 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35880.042183 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15311.682116 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15311.682116 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.044610 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.044610 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 272833.333333 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 272833.333333 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36887.583553 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36887.583553 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33443.162673 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17065.604317 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17065.604317 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25252.341967 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27108.082515 # average overall mshr miss latency
2215,2216c2214,2215
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135517.179903 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132989.423666 # average ReadReq mshr uncacheable latency
---
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135750.731232 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133204.056546 # average ReadReq mshr uncacheable latency
2218,2259c2217,2258
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75655.175534 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76067.245309 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 1493074 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 754096 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11157 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 112771 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104472 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.cpu1.toL2Bus.trans_dist::ReadReq 12635 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 726264 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2441 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2441 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 148991 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 580145 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 27848 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 30881 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 70910 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40918 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 85257 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 69946 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 67407 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 507377 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 264100 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 245 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1521973 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 842546 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5664 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10306 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2380489 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64912196 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29583168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17028 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 94521752 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 332142 # Total snoops (count)
< system.cpu1.toL2Bus.snoopTraffic 4881760 # Total snoop traffic (bytes)
< system.cpu1.toL2Bus.snoop_fanout::samples 1061400 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.130546 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.359362 # Request fanout histogram
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75822.290797 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76230.390433 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 1483973 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749706 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 112750 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104482 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.cpu1.toL2Bus.trans_dist::ReadReq 12645 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 721727 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2432 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2432 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 148874 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 576372 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 28336 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 31823 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 70615 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40952 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 85036 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 69693 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 67178 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 503982 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263487 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 292 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511788 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838524 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5603 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10248 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2366163 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64477636 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29432570 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9116 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16724 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 93936046 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 334351 # Total snoops (count)
> system.cpu1.toL2Bus.snoopTraffic 4909260 # Total snoop traffic (bytes)
> system.cpu1.toL2Bus.snoop_fanout::samples 1058830 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.130816 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.359612 # Request fanout histogram
2261,2263c2260,2262
< system.cpu1.toL2Bus.snoop_fanout::0 931138 87.73% 87.73% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 121963 11.49% 99.22% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 8299 0.78% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 928586 87.70% 87.70% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 121976 11.52% 99.22% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 8268 0.78% 100.00% # Request fanout histogram
2267,2268c2266,2267
< system.cpu1.toL2Bus.snoop_fanout::total 1061400 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1447209000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1058830 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1438248000 # Layer occupancy (ticks)
2270c2269
< system.cpu1.toL2Bus.snoopLayer0.occupancy 79433455 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 79282585 # Layer occupancy (ticks)
2272c2271
< system.cpu1.toL2Bus.respLayer0.occupancy 761242500 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 756150000 # Layer occupancy (ticks)
2274c2273
< system.cpu1.toL2Bus.respLayer1.occupancy 378138998 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 376097000 # Layer occupancy (ticks)
2278c2277
< system.cpu1.toL2Bus.respLayer3.occupancy 6050996 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 6067998 # Layer occupancy (ticks)
2280c2279
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
2283,2285c2282,2284
< system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 59423 # Transaction distribution
> system.iobus.trans_dist::WriteResp 59423 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes)
2304c2303
< system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
2307,2308c2306,2307
< system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes)
2327c2326
< system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes)
2330,2331c2329,2330
< system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 48592000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 48604000 # Layer occupancy (ticks)
2335c2334
< system.iobus.reqLayer2.occupancy 318500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks)
2337c2336
< system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
2341c2340
< system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks)
2343c2342
< system.iobus.reqLayer8.occupancy 615500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks)
2365c2364
< system.iobus.reqLayer23.occupancy 6203500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6201500 # Layer occupancy (ticks)
2367c2366
< system.iobus.reqLayer24.occupancy 32039500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 32041500 # Layer occupancy (ticks)
2369c2368
< system.iobus.reqLayer25.occupancy 187757841 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187869528 # Layer occupancy (ticks)
2371c2370
< system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks)
2375c2374
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
2377c2376
< system.iocache.tags.tagsinuse 14.377097 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.382505 # Cycle average of tags in use
2381,2384c2380,2383
< system.iocache.tags.warmup_cycle 290025611000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.377097 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.898569 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.898569 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 290037968000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.382505 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.898907 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.898907 # Average percentage of cache occupancy
2390c2389
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
2399,2406c2398,2405
< system.iocache.ReadReq_miss_latency::realview.ide 40988875 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 40988875 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4375977966 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4375977966 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4416966841 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4416966841 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4416966841 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4416966841 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 41042377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 41042377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4379492151 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4379492151 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4420534528 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4420534528 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4420534528 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4420534528 # number of overall miss cycles
2423,2431c2422,2430
< system.iocache.ReadReq_avg_miss_latency::realview.ide 160740.686275 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 160740.686275 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120803.278655 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 120803.278655 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 121082.454042 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 121082.454042 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 160950.498039 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 160950.498039 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120900.291271 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 120900.291271 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 121180.255161 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 121180.255161 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked
2433c2432
< system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked
2435c2434
< system.iocache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 33.111111 # average number of cycles each access was blocked
2447,2454c2446,2453
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 28238875 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 28238875 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562446714 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2562446714 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2590685589 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2590685589 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2590685589 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2590685589 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 28292377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 28292377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2566405842 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2566405842 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2594698219 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2594698219 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2594698219 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2594698219 # number of overall MSHR miss cycles
2463,2488c2462,2488
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110740.686275 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 110740.686275 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70738.922096 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70738.922096 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 137086 # number of replacements
< system.l2c.tags.tagsinuse 65074.643000 # Cycle average of tags in use
< system.l2c.tags.total_refs 524868 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 202455 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.592517 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 103102985000 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 6607.466111 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.944223 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038978 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 7194.422354 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6927.905114 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37164.228779 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1475.884148 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 3147.084233 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2554.669060 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.100822 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110950.498039 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 110950.498039 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70848.217811 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70848.217811 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 137345 # number of replacements
> system.l2c.tags.tagsinuse 65074.392349 # Cycle average of tags in use
> system.l2c.tags.total_refs 526935 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 202695 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.599645 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 103119965000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 6537.248776 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009779 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050987 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 7065.227850 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6920.254188 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.581661 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1513.426266 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 3159.258777 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2388.379223 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.099751 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy
2490,2503c2490,2505
< system.l2c.tags.occ_percent::cpu0.inst 0.109778 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.105711 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567081 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.022520 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.048021 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038981 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.992960 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 34101 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 31263 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 29155 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu0.inst 0.107807 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.105595 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571985 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.023093 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.048206 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036444 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 34308 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 31034 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 4715 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 29456 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
2505,2567c2507,2569
< system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 30056 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.520340 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.477036 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6098343 # Number of tag accesses
< system.l2c.tags.data_accesses 6098343 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 259635 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 259635 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 39907 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 4995 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 44902 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 2353 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 2177 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 4530 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1485 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5463 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 146 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 44179 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 52512 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45683 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 56 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 30 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 19035 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 10985 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5208 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 177905 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 44179 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 56490 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 45683 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 56 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 30 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 19035 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 12470 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 5208 # number of demand (read+write) hits
< system.l2c.demand_hits::total 183368 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 44179 # number of overall hits
< system.l2c.overall_hits::cpu0.data 56490 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 45683 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 56 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 30 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 19035 # number of overall hits
< system.l2c.overall_hits::cpu1.data 12470 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 5208 # number of overall hits
< system.l2c.overall_hits::total 183368 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 508 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 339 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 847 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 113 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 106 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 219 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11276 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 7954 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 19230 # number of ReadExReq misses
---
> system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 1168 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 29797 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.523499 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.473541 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6118121 # Number of tag accesses
> system.l2c.tags.data_accesses 6118121 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 260748 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 260748 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 39886 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 4893 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 44779 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2390 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 2219 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 4609 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 3995 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1504 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5499 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 159 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 44649 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 52745 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45897 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 18994 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 11024 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5470 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 179087 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 159 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 44649 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 56740 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 45897 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 28 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 18994 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 12528 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 5470 # number of demand (read+write) hits
> system.l2c.demand_hits::total 184586 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 159 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 44649 # number of overall hits
> system.l2c.overall_hits::cpu0.data 56740 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 45897 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 28 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 18994 # number of overall hits
> system.l2c.overall_hits::cpu1.data 12528 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 5470 # number of overall hits
> system.l2c.overall_hits::total 184586 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 631 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 289 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 920 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 83 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 96 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 179 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11301 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 8030 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 19331 # number of ReadExReq misses
2570,2576c2572,2579
< system.l2c.ReadSharedReq_misses::cpu0.inst 17880 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 9100 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 952 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 170581 # number of ReadSharedReq misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 17908 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9085 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 2374 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 170639 # number of ReadSharedReq misses
2579,2585c2582,2589
< system.l2c.demand_misses::cpu0.inst 17880 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 20376 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 8906 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) misses
< system.l2c.demand_misses::total 189811 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 17908 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20386 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 2374 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8972 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) misses
> system.l2c.demand_misses::total 189970 # number of demand (read+write) misses
2588,2746c2592,2760
< system.l2c.overall_misses::cpu0.inst 17880 # number of overall misses
< system.l2c.overall_misses::cpu0.data 20376 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 133915 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses
< system.l2c.overall_misses::cpu1.data 8906 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 6331 # number of overall misses
< system.l2c.overall_misses::total 189811 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 9776500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1123500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 10900000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 603500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 259000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 862500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1642507500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 809344500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 2451852000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1270000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 179500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949692500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106153000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 265577500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 121124000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 20274349932 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 1270000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 179500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1949692500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 2748660500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 265577500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 930468500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 22726201932 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 1270000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 179500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1949692500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 2748660500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 265577500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 930468500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 22726201932 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 259635 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 259635 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 40415 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 45749 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 2466 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 2283 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 4749 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15254 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 9439 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 24693 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 153 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 62059 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 61612 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179598 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 56 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 21429 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 11937 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11539 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 348486 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 153 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 62059 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 76866 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179598 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 21429 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 21376 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11539 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 373179 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 153 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 62059 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 76866 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179598 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 21429 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 21376 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11539 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 373179 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012570 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.063555 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.018514 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045823 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.046430 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.046115 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.739216 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.842674 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.778763 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.288113 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.147699 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111718 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.079752 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.489492 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.288113 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.265085 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.111718 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.416635 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.508633 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.288113 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.265085 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.111718 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.416635 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.508633 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19245.078740 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3314.159292 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 12868.949233 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5340.707965 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2443.396226 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3938.356164 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145664.020929 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101753.143073 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 127501.404056 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89750 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109043.204698 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121555.274725 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110934.628237 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 127231.092437 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 118854.678610 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 119730.689644 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 119730.689644 # average overall miss latency
---
> system.l2c.overall_misses::cpu0.inst 17908 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20386 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 133844 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 2374 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8972 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 6476 # number of overall misses
> system.l2c.overall_misses::total 189970 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 10365500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 935500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 11301000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 563000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 725500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1654925500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 828235000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 2483160500 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1167000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 185500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949681500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106313500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 90000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261013000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 123092000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 20215818501 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 1167000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 185500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1949681500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2761239000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 90000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 261013000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 951327000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 22698979001 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 1167000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 185500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1949681500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2761239000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 90000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 261013000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 951327000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 22698979001 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 260748 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 260748 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 40517 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5182 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 45699 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 2473 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 2315 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 4788 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15296 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9534 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24830 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 166 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 77 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 62557 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 61830 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179741 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 47 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 28 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 21368 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 11966 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11946 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 349726 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 166 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 62557 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 77126 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179741 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 47 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 21368 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 21500 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11946 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 374556 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 166 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 62557 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 77126 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179741 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 47 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 21368 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 21500 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11946 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 374556 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.015574 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055770 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.020132 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033562 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.041469 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.037385 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.738821 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.842249 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.778534 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.286267 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146935 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111101 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078723 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.487922 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.286267 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.264321 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.111101 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.417302 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.507187 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.286267 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.264321 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.111101 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.417302 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.507187 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16427.099842 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3237.024221 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 12283.695652 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6783.132530 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1692.708333 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 4053.072626 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146440.624723 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103142.590286 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 128454.839377 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92750 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 108872.096270 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121773.637865 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90000 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109946.503791 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130670.912951 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 118471.266832 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 119487.176928 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 119487.176928 # average overall miss latency
2753,2774c2767,2788
< system.l2c.writebacks::writebacks 100785 # number of writebacks
< system.l2c.writebacks::total 100785 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3664 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3664 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 508 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 339 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 847 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 113 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 106 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 219 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11276 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 7954 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 19230 # number of ReadExReq MSHR misses
---
> system.l2c.writebacks::writebacks 100603 # number of writebacks
> system.l2c.writebacks::total 100603 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 10 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3738 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3738 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 631 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 289 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 920 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 83 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 96 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 179 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11301 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 8030 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 19331 # number of ReadExReq MSHR misses
2777,2783c2791,2798
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17879 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9100 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2390 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 952 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 170576 # number of ReadSharedReq MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17904 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9085 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2368 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 170629 # number of ReadSharedReq MSHR misses
2786,2792c2801,2808
< system.l2c.demand_mshr_misses::cpu0.inst 17879 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 20376 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 2390 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 8906 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 189806 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 17904 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 20386 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 2368 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8972 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 189960 # number of demand (read+write) MSHR misses
2795,2801c2811,2818
< system.l2c.overall_mshr_misses::cpu0.inst 17879 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 20376 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 2390 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 8906 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 189806 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 17904 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 20386 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 2368 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8972 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 189960 # number of overall MSHR misses
2803c2820
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable
2805,2809c2822,2826
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 44063 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 30895 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3074 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 44041 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30878 # number of WriteReq MSHR uncacheable
2811c2828
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses
2813,2850c2830,2870
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5523 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 74958 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11966500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7400000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 19366500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2957500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2539000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 5496500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1529747500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729804500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 2259552000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 159500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770876500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015153000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 241454001 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111604000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 18568333447 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 159500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1770876500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2544900500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 241454001 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 841408500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 20827885447 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 159500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1770876500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2544900500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 241454001 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 841408500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 20827885447 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5506 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 74919 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14735500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6305500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 21041000 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2194500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2340500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 4535000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1541915500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 747935000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 2289850500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 165500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770529000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015463500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 80000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 236880000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 113671002 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 18508956015 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1770529000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2557379000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 80000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 236880000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 861606002 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 20798806515 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1770529000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2557379000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 80000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 236880000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 861606002 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 20798806515 # number of overall MSHR miss cycles
2852c2872
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805153000 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5804773000 # number of ReadReq MSHR uncacheable cycles
2854,2855c2874,2875
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362546500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6813498500 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362314500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6812886500 # number of ReadReq MSHR uncacheable cycles
2857c2877
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805153000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5804773000 # number of overall MSHR uncacheable cycles
2859,2860c2879,2880
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362546500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 6813498500 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362314500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6812886500 # number of overall MSHR uncacheable cycles
2863,2934c2883,2960
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012570 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.063555 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.018514 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.045823 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.046430 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.046115 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739216 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842674 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.778763 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.147699 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.079752 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489477 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.508619 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.508619 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23556.102362 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21828.908555 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22864.817001 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26172.566372 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23952.830189 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25098.173516 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135664.020929 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91753.143073 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 117501.404056 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111555.274725 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 117231.092437 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108856.658891 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015574 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055770 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.020132 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033562 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.041469 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037385 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.738821 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842249 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.778534 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146935 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078723 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487893 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.507160 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.507160 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23352.614897 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21818.339100 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22870.652174 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26439.759036 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24380.208333 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25335.195531 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136440.624723 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93142.590286 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 118454.839377 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111773.637865 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120669.853503 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108474.854890 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency
2936c2962
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182655.370965 # average ReadReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182723.904558 # average ReadReq mshr uncacheable latency
2938,2939c2964,2965
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117633.517197 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154630.835395 # average ReadReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117864.183474 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154694.182693 # average ReadReq mshr uncacheable latency
2941c2967
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96373.480975 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96402.381506 # average overall mshr uncacheable latency
2943,2947c2969,2973
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65643.038204 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 90897.549294 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 503139 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 282937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 589 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65803.577915 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 90936.698301 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 502698 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 282285 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 634 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2951,2960c2977,2986
< system.membus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 44063 # Transaction distribution
< system.membus.trans_dist::ReadResp 214894 # Transaction distribution
< system.membus.trans_dist::WriteReq 30895 # Transaction distribution
< system.membus.trans_dist::WriteResp 30895 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 136975 # Transaction distribution
< system.membus.trans_dist::CleanEvict 16276 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 64763 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 38177 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 17 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 44041 # Transaction distribution
> system.membus.trans_dist::ReadResp 214925 # Transaction distribution
> system.membus.trans_dist::WriteReq 30878 # Transaction distribution
> system.membus.trans_dist::WriteResp 30878 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 136793 # Transaction distribution
> system.membus.trans_dist::CleanEvict 16421 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 64440 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 38073 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
2962,2964c2988,2990
< system.membus.trans_dist::ReadExReq 39789 # Transaction distribution
< system.membus.trans_dist::ReadExResp 19204 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 170831 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 39751 # Transaction distribution
> system.membus.trans_dist::ReadExResp 19302 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 170884 # Transaction distribution
2966c2992,2993
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::InvalidateResp 4530 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
2968,2970c2995,2997
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13664 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647846 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 769460 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13584 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647548 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 769084 # Packet count per connected master and slave (bytes)
2973,2974c3000,3001
< system.membus.pkt_count::total 842399 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 842023 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes)
2976,2978c3003,3005
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27328 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18630604 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18820796 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27168 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18628620 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18818654 # Cumulative packet size per connected master and slave (bytes)
2981,2982c3008,3009
< system.membus.pkt_size::total 21137916 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 123039 # Total snoops (count)
---
> system.membus.pkt_size::total 21135774 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 126969 # Total snoops (count)
2984,2986c3011,3013
< system.membus.snoop_fanout::samples 424743 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.012198 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.109769 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 424292 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.012213 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.109837 # Request fanout histogram
2988,2989c3015,3016
< system.membus.snoop_fanout::0 419562 98.78% 98.78% # Request fanout histogram
< system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 419110 98.78% 98.78% # Request fanout histogram
> system.membus.snoop_fanout::1 5182 1.22% 100.00% # Request fanout histogram
2994,2995c3021,3022
< system.membus.snoop_fanout::total 424743 # Request fanout histogram
< system.membus.reqLayer0.occupancy 88158500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 424292 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88179000 # Layer occupancy (ticks)
2999c3026
< system.membus.reqLayer2.occupancy 11394500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11330000 # Layer occupancy (ticks)
3001c3028
< system.membus.reqLayer5.occupancy 971210962 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 970733801 # Layer occupancy (ticks)
3003c3030
< system.membus.respLayer2.occupancy 1112716909 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1113560532 # Layer occupancy (ticks)
3005c3032
< system.membus.respLayer3.occupancy 1441377 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 7243389 # Layer occupancy (ticks)
3007,3013c3034,3040
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
3020,3021c3047,3048
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
3053,3059c3080,3086
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
3064,3096c3091,3123
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 1012483 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 538775 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 174846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 29019 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 27944 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 1075 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
< system.toL2Bus.trans_dist::ReadReq 44066 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 511105 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30895 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30895 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 360420 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 118997 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 109639 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 42707 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 152346 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50919 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50919 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 467041 # Transaction distribution
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 1013922 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 527446 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 187526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 29573 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 28355 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 1218 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.trans_dist::ReadReq 44044 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 511645 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30878 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30878 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 361351 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 119836 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 109190 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 42682 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 151872 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 50757 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 50757 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 467605 # Transaction distribution
3098,3108c3125,3136
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1269868 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316423 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1586291 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35149508 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5612856 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 40762364 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 388626 # Total snoops (count)
< system.toL2Bus.snoopTraffic 15721036 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 887021 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.395992 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.491535 # Request fanout histogram
---
> system.toL2Bus.trans_dist::InvalidateResp 3427 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1275330 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317115 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1592445 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35259052 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5662514 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 40921566 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 390876 # Total snoops (count)
> system.toL2Bus.snoopTraffic 15646988 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 887171 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.397282 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.492133 # Request fanout histogram
3110,3112c3138,3140
< system.toL2Bus.snoop_fanout::0 536843 60.52% 60.52% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 349103 39.36% 99.88% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 1075 0.12% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 535932 60.41% 60.41% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 350021 39.45% 99.86% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 1218 0.14% 100.00% # Request fanout histogram
3116,3117c3144,3145
< system.toL2Bus.snoop_fanout::total 887021 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 892902016 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 887171 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 894860010 # Layer occupancy (ticks)
3119c3147
< system.toL2Bus.snoopLayer0.occupancy 360623 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2155585 # Layer occupancy (ticks)
3121c3149
< system.toL2Bus.respLayer0.occupancy 675868420 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 676392933 # Layer occupancy (ticks)
3123c3151
< system.toL2Bus.respLayer1.occupancy 239041660 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 238880542 # Layer occupancy (ticks)