3,5c3,5
< sim_seconds 2.870823 # Number of seconds simulated
< sim_ticks 2870822663000 # Number of ticks simulated
< final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.870989 # Number of seconds simulated
> sim_ticks 2870988926500 # Number of ticks simulated
> final_tick 2870988926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1048966 # Simulator instruction rate (inst/s)
< host_op_rate 1268757 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 22889064818 # Simulator tick rate (ticks/s)
< host_mem_usage 618276 # Number of bytes of host memory used
< host_seconds 125.42 # Real time elapsed on the host
< sim_insts 131564747 # Number of instructions simulated
< sim_ops 159131669 # Number of ops (including micro ops) simulated
---
> host_inst_rate 334502 # Simulator instruction rate (inst/s)
> host_op_rate 404603 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 7301303629 # Simulator tick rate (ticks/s)
> host_mem_usage 607968 # Number of bytes of host memory used
> host_seconds 393.22 # Real time elapsed on the host
> sim_insts 131531628 # Number of instructions simulated
> sim_ops 159096162 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
20,24c20,24
< system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.data 1293924 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8559616 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 153620 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 569684 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 405184 # Number of bytes read from this memory
26c26
< system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 12163760 # Number of bytes read from this memory
28,30c28,30
< system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory
---
> system.physmem.bytes_inst_read::cpu1.inst 153620 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1333816 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8766400 # Number of bytes written to this memory
33,34c33,34
< system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8783964 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
37,41c37,41
< system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.data 20737 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 133744 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 2555 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8922 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 6331 # Number of read requests responded to by this memory
43,44c43,44
< system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 199207 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 136975 # Number of write requests responded to by this memory
47,48c47,48
< system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 141366 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
50,55c50,55
< system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 411076 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 450689 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2981417 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 53508 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 198428 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 141130 # Total read bandwidth from this memory (bytes/s)
57,61c57,61
< system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4236784 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 411076 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 53508 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 464584 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3053443 # Write bandwidth from this memory (bytes/s)
64,66c64,66
< system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3059560 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3053443 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
68,73c68,73
< system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 411076 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 456793 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2981417 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 53508 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 198442 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 141130 # Total bandwidth to/from this memory (bytes/s)
75,85c75,85
< system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 198466 # Number of read requests accepted
< system.physmem.writeReqs 140553 # Number of write requests accepted
< system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 7296344 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 199207 # Number of read requests accepted
> system.physmem.writeReqs 141366 # Number of write requests accepted
> system.physmem.readBursts 199207 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 141366 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12740608 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8796800 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12163760 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8783964 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue
88,119c88,119
< system.physmem.perBankRdBursts::0 11821 # Per bank write bursts
< system.physmem.perBankRdBursts::1 11810 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12062 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12027 # Per bank write bursts
< system.physmem.perBankRdBursts::4 20473 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12098 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12277 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12432 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12179 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12459 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11810 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11367 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11535 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11583 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11073 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11307 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8516 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8730 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8955 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8735 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8248 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8655 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8964 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8852 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8742 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8980 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8644 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8478 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8438 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8004 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7925 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7759 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 11688 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11970 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12095 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12159 # Per bank write bursts
> system.physmem.perBankRdBursts::4 20723 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12090 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12329 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12246 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12200 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12543 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11897 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11487 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11682 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11835 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11042 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11086 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8412 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8881 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9049 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8857 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8522 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8714 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9020 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8690 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8720 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9031 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8698 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8602 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8645 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8180 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7869 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7560 # Per bank write bursts
121,122c121,122
< system.physmem.numWrRetry 91 # Number of times write queue was full causing retry
< system.physmem.totGap 2870821632000 # Total gap between requests
---
> system.physmem.numWrRetry 78 # Number of times write queue was full causing retry
> system.physmem.totGap 2870987895000 # Total gap between requests
129c129
< system.physmem.readPktSize::6 188706 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 189447 # Read request sizes (log2)
136,156c136,156
< system.physmem.writePktSize::6 136162 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 136975 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 135724 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 17225 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 10602 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8875 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7477 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5952 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5078 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4199 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3667 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 121 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 77 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 48 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
184,197c184,197
< system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2512 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3419 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4336 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5352 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6399 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6487 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7013 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7539 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8538 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9670 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 10012 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8667 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8175 # What write queue length does an incoming req see
199,250c199,250
< system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::30 9504 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7890 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7649 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 684 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 494 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 441 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 314 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 258 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 232 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 85540 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 251.780968 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 143.250026 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 307.334701 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 42821 50.06% 50.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18143 21.21% 71.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6218 7.27% 78.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3674 4.30% 82.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2664 3.11% 85.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1727 2.02% 87.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 953 1.11% 89.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 967 1.13% 90.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8373 9.79% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 85540 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6799 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 29.279453 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 564.517669 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6797 99.97% 99.97% # Reads before turning the bus around for writes
253,298c253,299
< system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads
< system.physmem.totQLat 9353740299 # Total ticks spent queuing
< system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6799 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6799 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.216208 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.546976 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 13.866150 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5813 85.50% 85.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 291 4.28% 89.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 61 0.90% 90.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 49 0.72% 91.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 268 3.94% 95.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 20 0.29% 95.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 11 0.16% 95.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 22 0.32% 96.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 12 0.18% 96.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 7 0.10% 96.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 11 0.16% 96.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 154 2.27% 98.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 6 0.09% 99.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 3 0.04% 99.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 7 0.10% 99.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 4 0.06% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 3 0.04% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.01% 99.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 4 0.06% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.01% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 5 0.07% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.01% 99.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 4 0.06% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 9 0.13% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 4 0.06% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.01% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 4 0.06% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 1 0.01% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 1 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 4 0.06% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6799 # Writes before turning the bus around for reads
> system.physmem.totQLat 9415943788 # Total ticks spent queuing
> system.physmem.totMemAccLat 13148543788 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 995360000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 47299.19 # Average queueing delay per DRAM burst
300,304c301,305
< system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 66049.19 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.06 # Average system write bandwidth in MiByte/s
309,355c310,356
< system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing
< system.physmem.readRowHits 165583 # Number of row buffer hits during reads
< system.physmem.writeRowHits 84490 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes
< system.physmem.avgGap 8468025.78 # Average gap between requests
< system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ)
< system.physmem_0.averagePower 247.210424 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states
< system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states
< system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ)
< system.physmem_1.averagePower 247.137601 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states
< system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing
> system.physmem.readRowHits 166164 # Number of row buffer hits during reads
> system.physmem.writeRowHits 84817 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes
> system.physmem.avgGap 8429875.22 # Average gap between requests
> system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 312774840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 166239975 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 751842000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 366156900 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6214010400.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5556704280 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 357731520 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 11629133730 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 9364882080 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 675113260110 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 709836228825 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.244502 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2857863952057 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 659296177 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2641884000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2807973624000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 24387714557 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 9823730266 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 25502677500 # Time in different power states
> system.physmem_1.actEnergy 297987900 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 158384325 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 669532080 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 351332100 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 6199259040.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5628324780 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 351060000 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 11278473150 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 9521383680 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 675168861345 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 709627419000 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.171771 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2857510482171 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 643430972 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2635632000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2808196835750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 24795240087 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 9984355357 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 24733432334 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
374,376c375,377
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
384c385
< system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
414,438c415,441
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.dtb.walker.walks 7793 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.dtb.walker.walks 7799 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 7799 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1450 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6349 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 7799 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 7799 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 7799 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 6405 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 12453.161593 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 11389.819011 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 6523.003169 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 5861 91.51% 91.51% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 469 7.32% 98.83% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 66 1.03% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 6405 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 4994 77.97% 77.97% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1411 22.03% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6405 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7799 # Table walker requests started/completed, data/inst
440,441c443,444
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7799 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6405 # Table walker requests started/completed, data/inst
443,444c446,447
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6405 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 14204 # Table walker requests started/completed, data/inst
447c450
< system.cpu0.dtb.read_hits 25156364 # DTB read hits
---
> system.cpu0.dtb.read_hits 25116933 # DTB read hits
449,450c452,453
< system.cpu0.dtb.write_hits 18748845 # DTB write hits
< system.cpu0.dtb.write_misses 1124 # DTB write misses
---
> system.cpu0.dtb.write_hits 18718433 # DTB write hits
> system.cpu0.dtb.write_misses 1130 # DTB write misses
455c458
< system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 3389 # Number of entries that have been flushed from TLB
457c460
< system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 1753 # Number of TLB faults due to prefetch
460,461c463,464
< system.cpu0.dtb.read_accesses 25163033 # DTB read accesses
< system.cpu0.dtb.write_accesses 18749969 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 25123602 # DTB read accesses
> system.cpu0.dtb.write_accesses 18719563 # DTB write accesses
463,466c466,469
< system.cpu0.dtb.hits 43905209 # DTB hits
< system.cpu0.dtb.misses 7793 # DTB misses
< system.cpu0.dtb.accesses 43913002 # DTB accesses
< system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.hits 43835366 # DTB hits
> system.cpu0.dtb.misses 7799 # DTB misses
> system.cpu0.dtb.accesses 43843165 # DTB accesses
> system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
496,498c499,501
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.itb.walker.walks 3349 # Table walker walks requested
< system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
---
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.itb.walker.walks 3348 # Table walker walks requested
> system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors
500,514c503,517
< system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3049 # Level at which table walker walks with short descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 12654.159520 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 11787.335553 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 5848.484815 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-8191 389 16.68% 16.68% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::8192-16383 1671 71.66% 88.34% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-24575 217 9.31% 97.64% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.16% 98.80% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-40959 21 0.90% 99.70% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.13% 99.87% # Table walker service (enqueue to completion) latency
518c521
< system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency
522c525
< system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 2033 87.18% 87.18% # Table walker page sizes translated
524c527
< system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated
526,527c529,530
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst
529,533c532,536
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 119019454 # ITB inst hits
< system.cpu0.itb.inst_misses 3349 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 118797664 # ITB inst hits
> system.cpu0.itb.inst_misses 3348 # ITB inst misses
542c545
< system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2086 # Number of entries that have been flushed from TLB
549,560c552,563
< system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses
< system.cpu0.itb.hits 119019454 # DTB hits
< system.cpu0.itb.misses 3349 # DTB misses
< system.cpu0.itb.accesses 119022803 # DTB accesses
< system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
---
> system.cpu0.itb.inst_accesses 118801012 # ITB inst accesses
> system.cpu0.itb.hits 118797664 # DTB hits
> system.cpu0.itb.misses 3348 # DTB misses
> system.cpu0.itb.accesses 118801012 # DTB accesses
> system.cpu0.numPwrStateTransitions 3664 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 1832 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 1490824715.864083 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 23921725256.931263 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 1059 57.81% 57.81% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.92% 99.73% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
562,566c565,569
< system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 5741645326 # number of cpu cycles simulated
---
> system.cpu0.pwrStateClkGateDist::max_value 499964287288 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::total 1832 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 139798047037 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731190879463 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 5741977853 # number of cpu cycles simulated
570,581c573,584
< system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed
< system.cpu0.committedInsts 115354991 # Number of instructions committed
< system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses
< system.cpu0.num_func_calls 12675511 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 123361088 # number of integer instructions
< system.cpu0.num_fp_insts 9690 # number of float instructions
< system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read
---
> system.cpu0.kern.inst.quiesce 1832 # number of quiesce instructions executed
> system.cpu0.committedInsts 115134358 # Number of instructions committed
> system.cpu0.committedOps 139131175 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 123155389 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
> system.cpu0.num_func_calls 12669084 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 15658471 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 123155389 # number of integer instructions
> system.cpu0.num_fp_insts 9755 # number of float instructions
> system.cpu0.num_int_register_reads 226724524 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 85578914 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
583,592c586,595
< system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written
< system.cpu0.num_mem_refs 45041487 # number of memory refs
< system.cpu0.num_load_insts 25408167 # Number of load instructions
< system.cpu0.num_store_insts 19633320 # Number of store instructions
< system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles
< system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles
< system.cpu0.Branches 29114863 # Number of branches fetched
---
> system.cpu0.num_cc_register_reads 504070716 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 52161373 # number of times the CC registers were written
> system.cpu0.num_mem_refs 44970744 # number of memory refs
> system.cpu0.num_load_insts 25368600 # Number of load instructions
> system.cpu0.num_store_insts 19602144 # Number of store instructions
> system.cpu0.num_idle_cycles 5462381758.924097 # Number of idle cycles
> system.cpu0.num_busy_cycles 279596094.075903 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.048693 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.951307 # Percentage of idle cycles
> system.cpu0.Branches 29063879 # Number of branches fetched
594,621c597,624
< system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction
< system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction
< system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 97803517 68.44% 68.45% # Class of executed instruction
> system.cpu0.op_class::IntMult 109759 0.08% 68.52% # Class of executed instruction
> system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 8141 0.01% 68.53% # Class of executed instruction
625,626c628,629
< system.cpu0.op_class::MemRead 25405911 17.75% 86.28% # Class of executed instruction
< system.cpu0.op_class::MemWrite 19625890 13.71% 99.99% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 25366344 17.75% 86.28% # Class of executed instruction
> system.cpu0.op_class::MemWrite 19594649 13.71% 99.99% # Class of executed instruction
628c631
< system.cpu0.op_class::FloatMemWrite 7430 0.01% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction
631,641c634,644
< system.cpu0.op_class::total 143146475 # Class of executed instruction
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 692883 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy
---
> system.cpu0.op_class::total 142894434 # Class of executed instruction
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 691910 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 491.841324 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 42965158 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 692422 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 62.050539 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.841324 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.960628 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.960628 # Average percentage of cache occupancy
643,645c646,648
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
647,727c650,730
< system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits
< system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses
< system.cpu0.dcache.overall_misses::total 849725 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 88306903 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 88306903 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23857214 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23857214 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 17987587 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 17987587 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319351 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 319351 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364951 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 364951 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361858 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 361858 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 41844801 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 41844801 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 42164152 # number of overall hits
> system.cpu0.dcache.overall_hits::total 42164152 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 395864 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 395864 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 325028 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 325028 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126936 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 126936 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21386 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21386 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19587 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 19587 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 720892 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 720892 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 847828 # number of overall misses
> system.cpu0.dcache.overall_misses::total 847828 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519668500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5519668500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6305983500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 6305983500 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336140000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 336140000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459598500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 459598500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1175500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1175500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11825652000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11825652000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11825652000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11825652000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 24253078 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 24253078 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 18312615 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 18312615 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446287 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 446287 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386337 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 386337 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381445 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 381445 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 42565693 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 42565693 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 43011980 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 43011980 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016322 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.016322 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017749 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.017749 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284427 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284427 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055356 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055356 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051349 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051349 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016936 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.016936 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13943.345442 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13943.345442 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19401.354653 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 19401.354653 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15717.759282 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15717.759282 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23464.466228 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23464.466228 # average StoreCondReq miss latency
730,733c733,736
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16404.193693 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 16404.193693 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13948.173450 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13948.173450 # average overall miss latency
740,743c743,746
< system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks
< system.cpu0.dcache.writebacks::total 692883 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits
---
> system.cpu0.dcache.writebacks::writebacks 691910 # number of writebacks
> system.cpu0.dcache.writebacks::total 691910 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25218 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 25218 # number of ReadReq MSHR hits
746,815c749,818
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15019 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15019 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 25219 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 25219 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 25219 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 25219 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370646 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 370646 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325027 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 325027 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99914 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 99914 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6367 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6367 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19587 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 19587 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 695673 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 695673 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 795587 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 795587 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60236 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4741194000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4741194000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5980473000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5980473000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1654728000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1654728000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97962000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97962000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440045500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440045500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1141500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1141500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10721667000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10721667000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376395000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 12376395000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631909500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631909500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631909500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631909500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015282 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015282 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017749 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017749 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223878 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223878 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016480 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016480 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051349 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051349 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016344 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.016344 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12791.704214 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12791.704214 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18399.926775 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18399.926775 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16561.522910 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16561.522910 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15385.896026 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15385.896026 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22466.202073 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22466.202073 # average StoreCondReq mshr miss latency
818,833c821,836
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 1103683 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15411.934918 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15411.934918 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15556.306224 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15556.306224 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208668.727582 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208668.727582 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110098.769839 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110098.769839 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 1101405 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.436911 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 117695738 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1101917 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 106.809985 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436911 # Average occupied blocks per requestor
838,839c841,842
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
841,879c844,882
< system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits
< system.cpu0.icache.overall_hits::total 117915250 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1104204 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1104204 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1104204 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1104204 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1104204 # number of overall misses
< system.cpu0.icache.overall_misses::total 1104204 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11911095000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 11911095000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 11911095000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 11911095000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 11911095000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 11911095000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 119019454 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 119019454 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 119019454 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 119019454 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 119019454 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 119019454 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009278 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.009278 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009278 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.009278 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009278 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.009278 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10787.042068 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10787.042068 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 238697254 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 238697254 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 117695738 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 117695738 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 117695738 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 117695738 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 117695738 # number of overall hits
> system.cpu0.icache.overall_hits::total 117695738 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1101926 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1101926 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1101926 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1101926 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1101926 # number of overall misses
> system.cpu0.icache.overall_misses::total 1101926 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11884591500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 11884591500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 11884591500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 11884591500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 11884591500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 11884591500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 118797664 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 118797664 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 118797664 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 118797664 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 118797664 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 118797664 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10785.290029 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10785.290029 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10785.290029 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10785.290029 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10785.290029 # average overall miss latency
886,893c889,896
< system.cpu0.icache.writebacks::writebacks 1103683 # number of writebacks
< system.cpu0.icache.writebacks::total 1103683 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104204 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1104204 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104204 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1104204 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104204 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1104204 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 1101405 # number of writebacks
> system.cpu0.icache.writebacks::total 1101405 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101926 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1101926 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101926 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1101926 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101926 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1101926 # number of overall MSHR misses
898,903c901,906
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11333628500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11333628500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11333628500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11333628500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11333628500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11333628500 # number of overall MSHR miss cycles
908,919c911,922
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.009278 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.009278 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10285.290029 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10285.290029 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10285.290029 # average overall mshr miss latency
924,927c927,930
< system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842335 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1842343 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
930,936c933,939
< system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.tags.replacements 259898 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 236049 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.tags.replacements 259510 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15639.759609 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1683263 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 275158 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.117442 # Average number of references to valid blocks.
938,1072c941,1075
< system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6084 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1977 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020752 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933411 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 61320295 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 61320295 # Number of data accesses
< system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9508 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4316 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 13824 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 476285 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 476285 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 1292383 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 1292383 # number of WritebackClean hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227392 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 227392 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1042059 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1042059 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376265 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 376265 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9508 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4316 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1042059 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 603657 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1659540 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9508 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4316 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1042059 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 603657 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1659540 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 306 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 159 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 465 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55222 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 55222 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19651 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19651 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43215 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 43215 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62145 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 62145 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101544 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 101544 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 306 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 159 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 62145 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144759 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 207369 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 306 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 159 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 62145 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144759 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 207369 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8941000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3729500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 12670500 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32046500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 32046500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9591500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9591500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1480500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1480500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2734835500 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2734835500 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3426232500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3426232500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3359763500 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3359763500 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8941000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3729500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3426232500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094599000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 9533502000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8941000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3729500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3426232500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094599000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 9533502000 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9814 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4475 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 14289 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476285 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 476285 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 1292383 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 1292383 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55222 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55222 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19651 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 19651 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270607 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 270607 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104204 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1104204 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477809 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 477809 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9814 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4475 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1104204 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 748416 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1866909 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9814 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4475 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1104204 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 748416 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1866909 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035531 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.032543 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 14465.018905 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.607944 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.119153 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1173.013607 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.882875 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000098 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071595 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.954575 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 297 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15346 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 119 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 812 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6453 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1818 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018127 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936646 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 61207036 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 61207036 # Number of data accesses
> system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9838 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4464 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 14302 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 475527 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 475527 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 1289984 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 1289984 # number of WritebackClean hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227136 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 227136 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1039867 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1039867 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376033 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 376033 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9838 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4464 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1039867 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 603169 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1657338 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9838 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4464 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1039867 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 603169 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1657338 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 303 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 441 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54610 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 54610 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19582 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19582 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43281 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 43281 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62059 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 62059 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100894 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 100894 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 303 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 62059 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 144175 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 206675 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 303 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 62059 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 144175 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 206675 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8179000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3277000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 11456000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32137500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 32137500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8911500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8911500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1089999 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1089999 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2751603000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2751603000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3417541500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3417541500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3327393000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3327393000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8179000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3277000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3417541500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 6078996000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 9507993500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8179000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3277000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3417541500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 6078996000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 9507993500 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10141 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4602 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 14743 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475527 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 475527 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289984 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 1289984 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54610 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 54610 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19582 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 19582 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270417 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 270417 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1101926 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1101926 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476927 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 476927 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10141 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4602 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1101926 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 747344 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1864013 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10141 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4602 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1101926 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 747344 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1864013 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029987 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses
1079,1119c1082,1122
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159697 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159697 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056280 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056280 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212520 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212520 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035531 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056280 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193421 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.111076 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035531 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056280 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193421 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.111076 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 580.321249 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 580.321249 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 488.092209 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 488.092209 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 493500 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 493500 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.160053 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.160053 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056319 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056319 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211550 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211550 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029987 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056319 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.192917 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.110876 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.029879 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029987 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056319 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.192917 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.110876 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23746.376812 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25977.324263 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 588.491119 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 588.491119 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 455.086304 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 455.086304 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 217999.800000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 217999.800000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63575.310182 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63575.310182 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55069.232505 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55069.232505 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32979.096874 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32979.096874 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 46004.565139 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26993.399340 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23746.376812 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55069.232505 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42164.009017 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 46004.565139 # average overall miss latency
1126,1164c1129,1167
< system.cpu0.l2cache.unused_prefetches 10606 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 227429 # number of writebacks
< system.cpu0.l2cache.writebacks::total 227429 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1561 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 1561 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1594 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 1594 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1594 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 1594 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 306 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 264666 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55222 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55222 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19651 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19651 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41654 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 41654 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62145 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62145 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101511 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101511 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 306 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62145 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143165 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 205775 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 306 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62145 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143165 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 470441 # number of overall MSHR misses
---
> system.cpu0.l2cache.unused_prefetches 10584 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 226675 # number of writebacks
> system.cpu0.l2cache.writebacks::total 226675 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1590 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 1590 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1620 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 1620 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1620 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 1620 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 303 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 138 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 441 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 262593 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54610 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54610 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19582 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19582 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41691 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41691 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62059 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62059 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100864 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100864 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 303 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 138 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62059 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142555 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 205055 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 303 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 138 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62059 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142555 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262593 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 467648 # number of overall MSHR misses
1166,1169c1169,1172
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40812 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40804 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28454 # number of WriteReq MSHR uncacheable
1171,1200c1174,1203
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69276 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9880500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16752910842 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 946229000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 946229000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294413000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294413000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1198500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1198500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2205065500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69258 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2449000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 8810000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16813897141 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 934853500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 934853500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293341500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293341500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 885999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 885999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2209696500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2209696500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3045187500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3045187500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2716829000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2716829000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2449000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3045187500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4926525500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 7980523000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6361000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2449000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3045187500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4926525500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16813897141 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 24794420141 # number of overall MSHR miss cycles
1202,1203c1205,1206
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377241500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172882000 # number of ReadReq MSHR uncacheable cycles
1205,1209c1208,1212
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377241500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172882000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029913 # mshr miss rate for ReadReq accesses
1218,1232c1221,1235
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154173 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154173 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056319 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211487 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211487 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110007 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029879 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029987 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056319 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.190749 # mshr miss rate for overall accesses
1234,1262c1237,1265
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.250882 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19977.324263 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64030.256484 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17118.723677 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17118.723677 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14980.160351 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14980.160351 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 177199.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 177199.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53001.762970 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53001.762970 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49069.232505 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26935.566704 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26935.566704 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38918.938821 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49069.232505 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34558.770299 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53019.408061 # average overall mshr miss latency
1264,1265c1267,1268
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200655.764269 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175788.697187 # average ReadReq mshr uncacheable latency
1267,1308c1270,1311
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 888922 # Total snoops (count)
< system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes)
< system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105870.932665 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103567.558982 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 3728751 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879521 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27804 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 211480 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209803 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1677 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu0.toL2Bus.trans_dist::ReadReq 61377 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1688185 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28454 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28454 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 702444 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 1317788 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 79827 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 309039 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 86996 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41768 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 111544 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 289661 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 286091 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1101926 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562800 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3273 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3323301 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2556545 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10999 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24289 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 5915134 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141049272 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96382808 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18408 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40564 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 237491052 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 885699 # Total snoops (count)
> system.cpu0.toL2Bus.snoopTraffic 18622452 # Total snoop traffic (bytes)
> system.cpu0.toL2Bus.snoop_fanout::samples 2792086 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.090598 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.289121 # Request fanout histogram
1310,1312c1313,1315
< system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 2540806 91.00% 91.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 249603 8.94% 99.94% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 1677 0.06% 100.00% # Request fanout histogram
1316,1317c1319,1320
< system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 2792086 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 3710834999 # Layer occupancy (ticks)
1319c1322
< system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 114296030 # Layer occupancy (ticks)
1321c1324
< system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1661911000 # Layer occupancy (ticks)
1323c1326
< system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1204165985 # Layer occupancy (ticks)
1325c1328
< system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks)
1327c1330
< system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 14154986 # Layer occupancy (ticks)
1329c1332
< system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
1359,1391c1362,1394
< system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.dtb.walker.walks 3333 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 2589 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 12693.897258 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 11812.728196 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 5453.033399 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-4095 2 0.08% 0.08% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::4096-8191 579 22.36% 22.44% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1101 42.53% 64.97% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::12288-16383 577 22.29% 87.25% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-20479 84 3.24% 90.50% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::20480-24575 148 5.72% 96.21% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::24576-28671 49 1.89% 98.11% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::28672-32767 18 0.70% 98.80% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-36863 23 0.89% 99.69% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.08% 99.77% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::40960-45055 4 0.15% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 2589 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1928 74.47% 74.47% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 661 25.53% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst
1393,1394c1396,1397
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst
1396,1397c1399,1400
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst
1400,1403c1403,1406
< system.cpu1.dtb.read_hits 3943012 # DTB read hits
< system.cpu1.dtb.read_misses 2827 # DTB read misses
< system.cpu1.dtb.write_hits 3420749 # DTB write hits
< system.cpu1.dtb.write_misses 506 # DTB write misses
---
> system.cpu1.dtb.read_hits 3975776 # DTB read hits
> system.cpu1.dtb.read_misses 2856 # DTB read misses
> system.cpu1.dtb.write_hits 3446428 # DTB write hits
> system.cpu1.dtb.write_misses 503 # DTB write misses
1408c1411
< system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_entries 1973 # Number of entries that have been flushed from TLB
1410c1413
< system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 329 # Number of TLB faults due to prefetch
1413,1414c1416,1417
< system.cpu1.dtb.read_accesses 3945839 # DTB read accesses
< system.cpu1.dtb.write_accesses 3421255 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 3978632 # DTB read accesses
> system.cpu1.dtb.write_accesses 3446931 # DTB write accesses
1416,1419c1419,1422
< system.cpu1.dtb.hits 7363761 # DTB hits
< system.cpu1.dtb.misses 3333 # DTB misses
< system.cpu1.dtb.accesses 7367094 # DTB accesses
< system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dtb.hits 7422204 # DTB hits
> system.cpu1.dtb.misses 3359 # DTB misses
> system.cpu1.dtb.accesses 7425563 # DTB accesses
> system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
1449c1452
< system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
1458,1471c1461,1474
< system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkCompletionTime::mean 13066.847335 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 12198.452511 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5775.216215 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 143 12.92% 12.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 70.55% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 85.64% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-20479 51 4.61% 90.24% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 51 4.61% 94.85% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.53% 97.38% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 98.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 99.01% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.45% 99.46% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.73% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.27% 100.00% # Table walker service (enqueue to completion) latency
1473,1475c1476,1478
< system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution
---
> system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total -1938367828 # Table walker pending requests distribution
1486c1489
< system.cpu1.itb.inst_hits 16565425 # ITB inst hits
---
> system.cpu1.itb.inst_hits 16753470 # ITB inst hits
1503,1504c1506,1507
< system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses
< system.cpu1.itb.hits 16565425 # DTB hits
---
> system.cpu1.itb.inst_accesses 16755216 # ITB inst accesses
> system.cpu1.itb.hits 16753470 # DTB hits
1506,1512c1509,1515
< system.cpu1.itb.accesses 16567171 # DTB accesses
< system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state
---
> system.cpu1.itb.accesses 16755216 # DTB accesses
> system.cpu1.numPwrStateTransitions 5461 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 2731 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 1041523757.275357 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 25854556705.104488 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::underflows 1955 71.59% 71.59% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 770 28.19% 99.78% # Distribution of time spent in the clock gated state
1519,1523c1522,1526
< system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 5740713090 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::total 2731 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 26587545381 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844401381119 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 5741033861 # number of cpu cycles simulated
1527,1530c1530,1533
< system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed
< system.cpu1.committedInsts 16209756 # Number of instructions committed
< system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses
---
> system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed
> system.cpu1.committedInsts 16397270 # Number of instructions committed
> system.cpu1.committedOps 19964987 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 17986629 # Number of integer alu accesses
1532,1534c1535,1537
< system.cpu1.num_func_calls 1029227 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 17811459 # number of integer instructions
---
> system.cpu1.num_func_calls 1033857 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 1854028 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 17986629 # number of integer instructions
1536,1537c1539,1540
< system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 32622652 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 12608250 # number of times the integer registers were written
1540,1549c1543,1552
< system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written
< system.cpu1.num_mem_refs 7597281 # number of memory refs
< system.cpu1.num_load_insts 4054552 # Number of load instructions
< system.cpu1.num_store_insts 3542729 # Number of store instructions
< system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles
< system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles
< system.cpu1.Branches 2922489 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 72946565 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 6544066 # number of times the CC registers were written
> system.cpu1.num_mem_refs 7656991 # number of memory refs
> system.cpu1.num_load_insts 4087327 # Number of load instructions
> system.cpu1.num_store_insts 3569664 # Number of store instructions
> system.cpu1.num_idle_cycles 5687867512.323336 # Number of idle cycles
> system.cpu1.num_busy_cycles 53166348.676665 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.009261 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.990739 # Percentage of idle cycles
> system.cpu1.Branches 2968001 # Number of branches fetched
1551,1583c1554,1586
< system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction
< system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction
< system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatMultAcc 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatMisc 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction
< system.cpu1.op_class::MemRead 4054036 20.17% 82.37% # Class of executed instruction
< system.cpu1.op_class::MemWrite 3541453 17.62% 99.99% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 12630695 62.17% 62.17% # Class of executed instruction
> system.cpu1.op_class::IntMult 26529 0.13% 62.30% # Class of executed instruction
> system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatMisc 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 3311 0.02% 62.31% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% # Class of executed instruction
> system.cpu1.op_class::MemRead 4086811 20.11% 82.43% # Class of executed instruction
> system.cpu1.op_class::MemWrite 3568388 17.56% 99.99% # Class of executed instruction
1588,1598c1591,1601
< system.cpu1.op_class::total 20100990 # Class of executed instruction
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 186832 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy
---
> system.cpu1.op_class::total 20317592 # Class of executed instruction
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 188214 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 469.650282 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 7155880 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 188578 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 37.946526 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 105561245500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.650282 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917286 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.917286 # Average percentage of cache occupancy
1600,1601c1603,1604
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
1603,1683c1606,1686
< system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits
< system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses
< system.cpu1.dcache.overall_misses::total 255886 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.tag_accesses 15064679 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 15064679 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3662279 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3662279 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 3257080 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 3257080 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49206 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 49206 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79332 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 79332 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71298 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 71298 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 6919359 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 6919359 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 6968565 # number of overall hits
> system.cpu1.dcache.overall_hits::total 6968565 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 134376 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 134376 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 92202 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 92202 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30516 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 30516 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17009 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 17009 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23197 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23197 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 226578 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 226578 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 257094 # number of overall misses
> system.cpu1.dcache.overall_misses::total 257094 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2053970000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2053970000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2521876000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 2521876000 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321694000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 321694000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544347500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 544347500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1836500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1836500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4575846000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4575846000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4575846000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4575846000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3796655 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3796655 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 3349282 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 3349282 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79722 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 79722 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96341 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 96341 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94495 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 94495 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 7145937 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 7145937 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 7225659 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 7225659 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035393 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035393 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027529 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.027529 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382780 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382780 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176550 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176550 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.245484 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.245484 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031707 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031707 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15285.244389 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15285.244389 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27351.640962 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 27351.640962 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18913.163619 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18913.163619 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23466.288744 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23466.288744 # average StoreCondReq miss latency
1686,1689c1689,1692
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20195.455870 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20195.455870 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17798.338351 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17798.338351 # average overall miss latency
1696,1769c1699,1772
< system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks
< system.cpu1.dcache.writebacks::total 186832 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 188214 # number of writebacks
> system.cpu1.dcache.writebacks::total 188214 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 253 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 253 # number of ReadReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12043 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12043 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 253 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 253 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 253 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 253 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134123 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 134123 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92202 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 92202 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29799 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 29799 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4966 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4966 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23197 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23197 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 226325 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 226325 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 256124 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 256124 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3085 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5526 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1909849500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1909849500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2429674000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2429674000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508192000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508192000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89547000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89547000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521193500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521193500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1793500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4339523500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4339523500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4847715500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4847715500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443097000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443097000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443097000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443097000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035327 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035327 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027529 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027529 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373786 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373786 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051546 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051546 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.245484 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.245484 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031672 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031672 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035446 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035446 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14239.537589 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14239.537589 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26351.640962 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26351.640962 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17053.995101 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17053.995101 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18032.017720 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18032.017720 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22468.142432 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22468.142432 # average StoreCondReq mshr miss latency
1772,1789c1775,1792
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 505764 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.454577 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 16059144 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 506276 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 31.720137 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 85411536000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.454577 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973544 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973544 # Average percentage of cache occupancy
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19173.858389 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19173.858389 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18927.220799 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18927.220799 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143629.497569 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143629.497569 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80184.039088 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80184.039088 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 506865 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.456606 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 16246088 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 507377 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 32.019757 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 85409397000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.456606 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973548 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.973548 # Average percentage of cache occupancy
1791,1793c1794,1796
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 389 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id
1795,1833c1798,1836
< system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits
< system.cpu1.icache.overall_hits::total 16059144 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses
< system.cpu1.icache.overall_misses::total 506276 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 16565420 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 16565420 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030562 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.030562 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030562 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.030562 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030562 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.030562 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9427.881235 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9427.881235 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 34014307 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 34014307 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 16246088 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 16246088 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 16246088 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 16246088 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 16246088 # number of overall hits
> system.cpu1.icache.overall_hits::total 16246088 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 507377 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 507377 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 507377 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 507377 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 507377 # number of overall misses
> system.cpu1.icache.overall_misses::total 507377 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4790701000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4790701000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4790701000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4790701000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4790701000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4790701000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 16753465 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 16753465 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 16753465 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 16753465 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 16753465 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 16753465 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030285 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.030285 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030285 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.030285 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030285 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.030285 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9442.093355 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9442.093355 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9442.093355 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9442.093355 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9442.093355 # average overall miss latency
1840,1847c1843,1850
< system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks
< system.cpu1.icache.writebacks::total 505764 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 506865 # number of writebacks
> system.cpu1.icache.writebacks::total 506865 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 507377 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 507377 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 507377 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 507377 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 507377 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 507377 # number of overall MSHR misses
1852,1880c1855,1883
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency
< system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4537012500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4537012500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4537012500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4537012500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4537012500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4537012500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030285 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.030285 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030285 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.030285 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8942.093355 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8942.093355 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8942.093355 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency
> system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 202159 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 202159 # number of prefetch candidates identified
1884,1890c1887,1893
< system.cpu1.l2cache.prefetcher.pfSpanPage 59073 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.tags.replacements 42341 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 14550.545082 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 605184 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 56718 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 10.670052 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 59833 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.tags.replacements 43683 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 14553.446834 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 604546 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 57834 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 10.453124 # Average number of references to valid blocks.
1892,2022c1895,2025
< system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.888095 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 333 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2799 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10333 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020325 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 24327160 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 24327160 # Number of data accesses
< system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3447 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1877 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 5324 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 114448 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 114448 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 567034 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 567034 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27676 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 27676 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485156 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 485156 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98414 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 98414 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3447 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1877 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 485156 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 126090 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 616570 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3447 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1877 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 485156 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 126090 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 616570 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 422 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 327 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29541 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29541 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23233 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 23233 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34651 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 34651 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21120 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 21120 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69614 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 69614 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 422 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 327 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 21120 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 104265 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 126134 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 422 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 327 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 21120 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 104265 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 126134 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8582000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6568500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 15150500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13749500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 13749500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16999500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16999500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1709500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1709500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1487134000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1487134000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 835278500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 835278500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1591067500 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1591067500 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8582000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6568500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 835278500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3078201500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 3928630500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8582000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6568500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 835278500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3078201500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 3928630500 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3869 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2204 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 6073 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114448 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 114448 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 567034 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 567034 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29541 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 29541 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23233 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23233 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62327 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 62327 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506276 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 506276 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168028 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 168028 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3869 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2204 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 506276 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 230355 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 742704 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3869 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2204 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 506276 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 230355 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 742704 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.148367 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.123333 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 14136.855711 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.245443 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.035798 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 412.309882 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.862845 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000137 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025165 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.888272 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13825 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 293 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1016 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2429 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10380 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.843811 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 24413579 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 24413579 # Number of data accesses
> system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3816 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 5831 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 114934 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 114934 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 568988 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 568988 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27893 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 27893 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485948 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 485948 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99069 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 99069 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3816 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 485948 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 126962 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 618741 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3816 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2015 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 485948 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 126962 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 618741 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 325 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 766 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29445 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29445 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23189 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 23189 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34864 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 34864 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21429 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 21429 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69819 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 69819 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 325 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 21429 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 104683 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 126878 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 325 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 21429 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 104683 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 126878 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9097000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6572000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 15669000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14547500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 14547500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17306000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17306000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1729000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1729000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1479795000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1479795000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845906500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845906500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606277000 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606277000 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9097000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6572000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845906500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3086072000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3947647500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9097000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6572000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845906500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3086072000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3947647500 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4257 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2340 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 6597 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114934 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 114934 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 568988 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 568988 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29445 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 29445 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23189 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23189 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62757 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 62757 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 507377 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 507377 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168888 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 168888 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4257 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2340 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 507377 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 231645 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 745619 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4257 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2340 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 507377 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 231645 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 745619 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138889 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.116113 # miss rate for ReadReq accesses
2029,2069c2032,2072
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555955 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555955 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041716 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041716 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414300 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414300 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.148367 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041716 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452627 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.169831 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.148367 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041716 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452627 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.169831 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 465.437866 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 465.437866 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 731.696294 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 731.696294 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 854750 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 854750 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555540 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555540 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042235 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042235 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.413404 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.413404 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138889 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042235 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.451911 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.170165 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103594 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138889 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042235 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.451911 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.170165 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20221.538462 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20455.613577 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 494.056716 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 494.056716 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 746.302126 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 746.302126 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 216125 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 216125 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42444.785452 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42444.785452 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39474.847170 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39474.847170 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23006.302009 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23006.302009 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 31113.727360 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20628.117914 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20221.538462 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39474.847170 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29480.163923 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 31113.727360 # average overall miss latency
2076,2112c2079,2115
< system.cpu1.l2cache.unused_prefetches 833 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 32020 # number of writebacks
< system.cpu1.l2cache.writebacks::total 32020 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 87 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 87 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 422 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 327 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 25249 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29541 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29541 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23233 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23233 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34564 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 34564 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21120 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21120 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69614 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69614 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 422 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 327 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21120 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104178 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 126047 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 422 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 327 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21120 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104178 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 151296 # number of overall MSHR misses
---
> system.cpu1.l2cache.unused_prefetches 815 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 32960 # number of writebacks
> system.cpu1.l2cache.writebacks::total 32960 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 325 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 25865 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29445 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29445 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23189 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23189 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34780 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 34780 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21429 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21429 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69819 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69819 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 325 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21429 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104599 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 126794 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 325 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21429 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104599 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25865 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 152659 # number of overall MSHR misses
2114,2117c2117,2120
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3273 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3085 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3262 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2441 # number of WriteReq MSHR uncacheable
2119,2157c2122,2160
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5526 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5703 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4622000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11073000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 943203517 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 450885000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 450885000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347198000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347198000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1471000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1471000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1260374500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1260374500 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 717332500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 717332500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1187363000 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1187363000 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4622000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 717332500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2447737500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3176143000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6451000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4622000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 717332500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2447737500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 943203517 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4119346517 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418070500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433811500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418070500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433811500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.116113 # mshr miss rate for ReadReq accesses
2166,2180c2169,2183
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554201 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554201 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042235 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.413404 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.413404 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170052 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103594 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138889 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042235 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451549 # mshr miss rate for overall accesses
2182,2256c2185,2259
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 331491 # Total snoops (count)
< system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes)
< system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.204741 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14455.613577 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36466.403132 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.786551 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15312.786551 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14972.530079 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.530079 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183875 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183875 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36238.484761 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36238.484761 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33474.847170 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17006.302009 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17006.302009 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25049.631686 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33474.847170 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23401.155843 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26983.974197 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135517.179903 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132989.423666 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75655.175534 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76067.245309 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 1493074 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 754096 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11157 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 112771 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104472 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.cpu1.toL2Bus.trans_dist::ReadReq 12635 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 726264 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2441 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2441 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 148991 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 580145 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 27848 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 30881 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 70910 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40918 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 85257 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 69946 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 67407 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 507377 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 264100 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 245 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1521973 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 842546 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5664 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10306 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2380489 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64912196 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29583168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17028 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 94521752 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 332142 # Total snoops (count)
> system.cpu1.toL2Bus.snoopTraffic 4881760 # Total snoop traffic (bytes)
> system.cpu1.toL2Bus.snoop_fanout::samples 1061400 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.130546 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.359362 # Request fanout histogram
2258,2260c2261,2263
< system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 931138 87.73% 87.73% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 121963 11.49% 99.22% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 8299 0.78% 100.00% # Request fanout histogram
2264,2265c2267,2268
< system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1061400 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1447209000 # Layer occupancy (ticks)
2267c2270
< system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 79433455 # Layer occupancy (ticks)
2269c2272
< system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 761242500 # Layer occupancy (ticks)
2271c2274
< system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 378138998 # Layer occupancy (ticks)
2275c2278
< system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 6050996 # Layer occupancy (ticks)
2277c2280
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
2328c2331
< system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 48592000 # Layer occupancy (ticks)
2330c2333
< system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks)
2332c2335
< system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 318500 # Layer occupancy (ticks)
2334c2337
< system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
2336c2339
< system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks)
2338c2341
< system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
2340c2343
< system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 615500 # Layer occupancy (ticks)
2342c2345
< system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2344c2347
< system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
2346c2349
< system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
2348c2351
< system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
2350c2353
< system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 46500 # Layer occupancy (ticks)
2352c2355
< system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
2354c2357
< system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks)
2360c2363
< system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks)
2362c2365
< system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6203500 # Layer occupancy (ticks)
2364c2367
< system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 32039500 # Layer occupancy (ticks)
2366c2369
< system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187757841 # Layer occupancy (ticks)
2372c2375
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
2374c2377
< system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.377097 # Cycle average of tags in use
2378,2381c2381,2384
< system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 290025611000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.377097 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.898569 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.898569 # Average percentage of cache occupancy
2387c2390
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
2396,2403c2399,2406
< system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 40988875 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 40988875 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4375977966 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4375977966 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4416966841 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4416966841 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4416966841 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4416966841 # number of overall miss cycles
2420,2428c2423,2431
< system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 160740.686275 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 160740.686275 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120803.278655 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 120803.278655 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 121082.454042 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 121082.454042 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 121082.454042 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked
2430c2433
< system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
2432c2435
< system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked
2444,2451c2447,2454
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 28238875 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 28238875 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562446714 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2562446714 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2590685589 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2590685589 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2590685589 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2590685589 # number of overall MSHR miss cycles
2460,2485c2463,2488
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 136024 # number of replacements
< system.l2c.tags.tagsinuse 65074.400284 # Cycle average of tags in use
< system.l2c.tags.total_refs 524979 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 201414 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.606467 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 103030494000 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 6378.541377 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.901261 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045973 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 7223.294710 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6923.893951 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110740.686275 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 110740.686275 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70738.922096 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70738.922096 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 71018.547356 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 71018.547356 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 137086 # number of replacements
> system.l2c.tags.tagsinuse 65074.643000 # Cycle average of tags in use
> system.l2c.tags.total_refs 524868 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 202455 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.592517 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 103102985000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 6607.466111 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.944223 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038978 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 7194.422354 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6927.905114 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37164.228779 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1475.884148 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 3147.084233 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2554.669060 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.100822 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
2487,2494c2490,2497
< system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu0.inst 0.109778 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.105711 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567081 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.022520 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.048021 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038981 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.992960 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 34101 # Occupied blocks per task id
2496,2500c2499,2502
< system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id
---
> system.l2c.tags.occ_task_id_blocks::1024 31263 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 29155 # Occupied blocks per task id
2504,2507c2506,2509
< system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 1178 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 29816 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.523697 # Percentage of cache occupancy per task id
---
> system.l2c.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 30056 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.520340 # Percentage of cache occupancy per task id
2509,2566c2511,2568
< system.l2c.tags.occ_task_id_percent::1024 0.473999 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6089608 # Number of tag accesses
< system.l2c.tags.data_accesses 6089608 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5419 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 142 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 44259 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 52827 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45774 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 18793 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 10825 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5311 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 178070 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 142 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 44259 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 56833 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 45774 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 18793 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 12238 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 5311 # number of demand (read+write) hits
< system.l2c.demand_hits::total 183489 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 142 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 44259 # number of overall hits
< system.l2c.overall_hits::cpu0.data 56833 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 45774 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits
< system.l2c.overall_hits::cpu1.data 12238 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits
< system.l2c.overall_hits::total 183489 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 19232 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 9 # number of ReadSharedReq misses
---
> system.l2c.tags.occ_task_id_percent::1024 0.477036 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6098343 # Number of tag accesses
> system.l2c.tags.data_accesses 6098343 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 259635 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 259635 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 39907 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 4995 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 44902 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2353 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 2177 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 4530 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1485 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5463 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 146 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 44179 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 52512 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45683 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 56 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 30 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 19035 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 10985 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5208 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 177905 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 44179 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 56490 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 45683 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 56 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 30 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 19035 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 12470 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 5208 # number of demand (read+write) hits
> system.l2c.demand_hits::total 183368 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 44179 # number of overall hits
> system.l2c.overall_hits::cpu0.data 56490 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 45683 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 56 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 30 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 19035 # number of overall hits
> system.l2c.overall_hits::cpu1.data 12470 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 5208 # number of overall hits
> system.l2c.overall_hits::total 183368 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 508 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 339 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 847 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 113 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 106 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 219 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11276 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7954 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 19230 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
2568,2575c2570,2577
< system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 17880 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9100 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 952 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 170581 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
2577,2584c2579,2586
< system.l2c.demand_misses::cpu0.inst 17886 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 20308 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 2327 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 8890 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) misses
< system.l2c.demand_misses::total 189076 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 17880 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20376 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8906 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) misses
> system.l2c.demand_misses::total 189811 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
2586,2745c2588,2747
< system.l2c.overall_misses::cpu0.inst 17886 # number of overall misses
< system.l2c.overall_misses::cpu0.data 20308 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 133589 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 2327 # number of overall misses
< system.l2c.overall_misses::cpu1.data 8890 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 6065 # number of overall misses
< system.l2c.overall_misses::total 189076 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 9921500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 813500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 10735000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 361000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 975000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1635531500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 824298500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 2459830000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1956500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1955907500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 1124374000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261946000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 108772000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 20157534022 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 1956500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 180000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1955907500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 2759905500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 261946000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 933070500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 22617364022 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 1956500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 180000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1955907500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 2759905500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 261946000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 933070500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 22617364022 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 259449 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 259449 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 40695 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5158 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 45853 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 2504 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 2310 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 4814 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15223 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 9428 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 24651 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 151 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 62145 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 61918 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179363 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 21120 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 11700 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11376 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 347914 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 151 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 62145 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 77141 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179363 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 21120 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 21128 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11376 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 372565 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 151 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 62145 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 77141 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179363 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 21120 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 21128 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11376 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 372565 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014547 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.048856 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.018407 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.047125 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.039827 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.043623 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.736846 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.850127 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.780171 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.024096 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287811 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146823 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110180 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.074786 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.488178 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.024096 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.287811 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.263258 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.110180 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.420769 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.507498 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.024096 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.287811 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.263258 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.110180 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.420769 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.507498 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3228.174603 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5203.389831 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3923.913043 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 4642.857143 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 127902.974210 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 119620.491347 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 119620.491347 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 873 # number of cycles access was blocked
---
> system.l2c.overall_misses::cpu0.inst 17880 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20376 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 133915 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8906 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 6331 # number of overall misses
> system.l2c.overall_misses::total 189811 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 9776500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 1123500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 10900000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 603500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 259000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 862500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1642507500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 809344500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 2451852000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1270000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 179500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949692500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106153000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 265577500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 121124000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 20274349932 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 1270000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 179500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1949692500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2748660500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 265577500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 930468500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 22726201932 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 1270000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 179500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1949692500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2748660500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16003328825 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 265577500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 930468500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 827024607 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 22726201932 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 259635 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 259635 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 40415 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5334 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 45749 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 2466 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 2283 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 4749 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15254 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9439 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24693 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 153 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 62059 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 61612 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179598 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 56 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 21429 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 11937 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11539 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 348486 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 153 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 62059 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 76866 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179598 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 21429 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 21376 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11539 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 373179 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 153 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 62059 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 76866 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179598 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 21429 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 21376 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11539 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 373179 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012570 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.063555 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.018514 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045823 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.046430 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.046115 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.739216 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.842674 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.778763 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.288113 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.147699 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111718 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.079752 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.489492 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.288113 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.265085 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.111718 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.416635 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.508633 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.045752 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.288113 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.265085 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.745637 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.111718 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.416635 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.548661 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.508633 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19245.078740 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3314.159292 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 12868.949233 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5340.707965 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2443.396226 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3938.356164 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145664.020929 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101753.143073 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 127501.404056 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89750 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109043.204698 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121555.274725 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110934.628237 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 127231.092437 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 118854.678610 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 119730.689644 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 181428.571429 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89750 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 109043.204698 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 134896.962112 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 110934.628237 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 104476.588817 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 119730.689644 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2747c2749
< system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2749c2751
< system.l2c.avg_blocked_cycles::no_mshrs 109.125000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2751,2773c2753,2775
< system.l2c.writebacks::writebacks 99972 # number of writebacks
< system.l2c.writebacks::total 99972 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3644 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3644 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 592 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 252 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 844 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 118 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 92 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 210 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11217 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 8015 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 19232 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadSharedReq MSHR misses
---
> system.l2c.writebacks::writebacks 100785 # number of writebacks
> system.l2c.writebacks::total 100785 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 5 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3664 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3664 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 508 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 339 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 847 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 113 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 106 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 219 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11276 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7954 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 19230 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses
2776,2782c2778,2784
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9091 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2318 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 875 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 169828 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9100 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2390 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 952 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 170576 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses
2785,2791c2787,2793
< system.l2c.demand_mshr_misses::cpu0.data 20308 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 2318 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 8890 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 189060 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.data 20376 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 2390 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8906 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 189806 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses
2794,2799c2796,2801
< system.l2c.overall_mshr_misses::cpu0.data 20308 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 2318 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 8890 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 189060 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.data 20376 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133915 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 2390 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8906 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6331 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 189806 # number of overall MSHR misses
2801c2803
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
2803,2807c2805,2809
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3093 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 44082 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 30915 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 44063 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28454 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2441 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30895 # number of WriteReq MSHR uncacheable
2809c2811
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60236 # number of overall MSHR uncacheable misses
2811,2848c2813,2850
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5544 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 74997 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13698000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5474500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 19172500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3092000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2171500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 5263500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1523361500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 744148500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 2267510000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1775966000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1033464000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 238288500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 100021501 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 18457620033 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1775966000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2556825500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 238288500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 844170001 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 20725130033 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1775966000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2556825500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 238288500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 844170001 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 20725130033 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5523 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 74958 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11966500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7400000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 19366500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2957500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2539000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 5496500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1529747500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729804500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 2259552000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 159500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770876500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015153000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 241454001 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111604000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 18568333447 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 159500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1770876500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2544900500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 241454001 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 841408500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 20827885447 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1200000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 159500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1770876500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2544900500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14664172837 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 241454001 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 841408500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 763713609 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 20827885447 # number of overall MSHR miss cycles
2850,2853c2852,2855
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805450500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12497000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362875500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6814067000 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805153000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362546500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6813498500 # number of ReadReq MSHR uncacheable cycles
2855,2858c2857,2860
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805450500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12497000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362875500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 6814067000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805153000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362546500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6813498500 # number of overall MSHR uncacheable cycles
2861,2932c2863,2934
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012570 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.063555 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.018514 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.045823 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.046430 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.046115 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739216 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842674 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.778763 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.147699 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.079752 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489477 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.508619 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.045752 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.288097 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.265085 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745637 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.111531 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.416635 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.548661 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.508619 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23556.102362 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21828.908555 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22864.817001 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26172.566372 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23952.830189 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25098.173516 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135664.020929 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91753.143073 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 117501.404056 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111555.274725 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 117231.092437 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108856.658891 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79750 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99047.849432 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124896.962112 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101026.778661 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94476.588817 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 109732.492371 # average overall mshr miss latency
2934,2937c2936,2939
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182655.370965 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117633.517197 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154630.835395 # average ReadReq mshr uncacheable latency
2939,2945c2941,2947
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96373.480975 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65643.038204 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 90897.549294 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 503139 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 282937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 589 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2949,2961c2951,2964
< system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 44082 # Transaction distribution
< system.membus.trans_dist::ReadResp 214165 # Transaction distribution
< system.membus.trans_dist::WriteReq 30915 # Transaction distribution
< system.membus.trans_dist::WriteResp 30915 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution
< system.membus.trans_dist::CleanEvict 16178 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
< system.membus.trans_dist::ReadExReq 39788 # Transaction distribution
< system.membus.trans_dist::ReadExResp 19211 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 44063 # Transaction distribution
> system.membus.trans_dist::ReadResp 214894 # Transaction distribution
> system.membus.trans_dist::WriteReq 30895 # Transaction distribution
> system.membus.trans_dist::WriteResp 30895 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 136975 # Transaction distribution
> system.membus.trans_dist::CleanEvict 16276 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 64763 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 38177 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 17 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
> system.membus.trans_dist::ReadExReq 39789 # Transaction distribution
> system.membus.trans_dist::ReadExResp 19204 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 170831 # Transaction distribution
2965,2967c2968,2970
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13664 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647846 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 769460 # Packet count per connected master and slave (bytes)
2970c2973
< system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 842399 # Packet count per connected master and slave (bytes)
2973,2975c2976,2978
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27328 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18630604 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18820796 # Cumulative packet size per connected master and slave (bytes)
2978,2979c2981,2982
< system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 123440 # Total snoops (count)
---
> system.membus.pkt_size::total 21137916 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 123039 # Total snoops (count)
2981,2983c2984,2986
< system.membus.snoop_fanout::samples 424426 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 424743 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.012198 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.109769 # Request fanout histogram
2985c2988
< system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram
---
> system.membus.snoop_fanout::0 419562 98.78% 98.78% # Request fanout histogram
2991,2992c2994,2995
< system.membus.snoop_fanout::total 424426 # Request fanout histogram
< system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 424743 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88158500 # Layer occupancy (ticks)
2996c2999
< system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11394500 # Layer occupancy (ticks)
2998c3001
< system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 971210962 # Layer occupancy (ticks)
3000c3003
< system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1112716909 # Layer occupancy (ticks)
3002c3005
< system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1441377 # Layer occupancy (ticks)
3004,3010c3007,3013
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
3017,3018c3020,3021
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
3050,3056c3053,3059
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
3061,3105c3064,3108
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 388372 # Total snoops (count)
< system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 1012483 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 538775 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 174846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 29019 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 27944 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 1075 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500 # Cumulative time (in ticks) in various power states
> system.toL2Bus.trans_dist::ReadReq 44066 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 511105 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30895 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30895 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 360420 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 118997 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 109639 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 42707 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 152346 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 50919 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 50919 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 467041 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1269868 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316423 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1586291 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35149508 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5612856 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 40762364 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 388626 # Total snoops (count)
> system.toL2Bus.snoopTraffic 15721036 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 887021 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.395992 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.491535 # Request fanout histogram
3107,3109c3110,3112
< system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 536843 60.52% 60.52% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 349103 39.36% 99.88% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 1075 0.12% 100.00% # Request fanout histogram
3113,3114c3116,3117
< system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 887021 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 892902016 # Layer occupancy (ticks)
3116c3119
< system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 360623 # Layer occupancy (ticks)
3118c3121
< system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 675868420 # Layer occupancy (ticks)
3120c3123
< system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 239041660 # Layer occupancy (ticks)