3,5c3,5
< sim_seconds 2.870001 # Number of seconds simulated
< sim_ticks 2870000710000 # Number of ticks simulated
< final_tick 2870000710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.870823 # Number of seconds simulated
> sim_ticks 2870822663000 # Number of ticks simulated
> final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 371570 # Simulator instruction rate (inst/s)
< host_op_rate 449436 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 8101953096 # Simulator tick rate (ticks/s)
< host_mem_usage 621024 # Number of bytes of host memory used
< host_seconds 354.24 # Real time elapsed on the host
< sim_insts 131623434 # Number of instructions simulated
< sim_ops 159206188 # Number of ops (including micro ops) simulated
---
> host_inst_rate 442891 # Simulator instruction rate (inst/s)
> host_op_rate 535691 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9664154143 # Simulator tick rate (ticks/s)
> host_mem_usage 616988 # Number of bytes of host memory used
> host_seconds 297.06 # Real time elapsed on the host
> sim_insts 131564747 # Number of instructions simulated
> sim_ops 159131669 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory
19,25c19,24
< system.physmem.bytes_read::cpu0.inst 1182180 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1312420 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8596224 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 150484 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 578772 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 396096 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory
27,31c26,30
< system.physmem.bytes_read::total 12217776 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1182180 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 150484 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1332664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8789056 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory
34,35c33,34
< system.physmem.bytes_written::total 8806620 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory
37,43c36,41
< system.physmem.num_reads::cpu0.inst 26925 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 21026 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 134316 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 2506 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 9064 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 6189 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory
45,46c43,44
< system.physmem.num_reads::total 200051 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 137329 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory
49,50c47,48
< system.physmem.num_writes::total 141720 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s)
52,58c50,55
< system.physmem.bw_read::cpu0.inst 411909 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 457289 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2995199 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 52433 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 201663 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 138013 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s)
60,65c57,62
< system.physmem.bw_read::total 4257064 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 411909 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 52433 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 464343 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3062388 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s)
67,69c64,66
< system.physmem.bw_write::total 3068508 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3062388 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s)
71,77c68,73
< system.physmem.bw_total::cpu0.inst 411909 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 463395 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2995199 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 52433 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 201677 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 138013 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s)
79,90c75,86
< system.physmem.bw_total::total 7325572 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 200051 # Number of read requests accepted
< system.physmem.writeReqs 141720 # Number of write requests accepted
< system.physmem.readBursts 200051 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 141720 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12793920 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8819520 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12217776 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8806620 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 198466 # Number of read requests accepted
> system.physmem.writeReqs 140553 # Number of write requests accepted
> system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
92,123c88,119
< system.physmem.perBankRdBursts::0 11709 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12160 # Per bank write bursts
< system.physmem.perBankRdBursts::2 12038 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12178 # Per bank write bursts
< system.physmem.perBankRdBursts::4 20671 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12806 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12086 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12477 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12638 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12504 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11795 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11324 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11594 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11843 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11003 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11079 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8559 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9022 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9017 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8844 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8437 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9230 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8825 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8866 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9056 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8974 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8482 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8329 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8472 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8225 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7833 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7634 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 11821 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11810 # Per bank write bursts
> system.physmem.perBankRdBursts::2 12062 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12027 # Per bank write bursts
> system.physmem.perBankRdBursts::4 20473 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12098 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12277 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12432 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12179 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12459 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11810 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11367 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11535 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11583 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11073 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11307 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8516 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8730 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8955 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8735 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8248 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8655 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8964 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8852 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8742 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8980 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8644 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8478 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8438 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8004 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7925 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7759 # Per bank write bursts
125,126c121,122
< system.physmem.numWrRetry 37 # Number of times write queue was full causing retry
< system.physmem.totGap 2870000192000 # Total gap between requests
---
> system.physmem.numWrRetry 91 # Number of times write queue was full causing retry
> system.physmem.totGap 2870821632000 # Total gap between requests
133c129
< system.physmem.readPktSize::6 190291 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 188706 # Read request sizes (log2)
140,154c136,150
< system.physmem.writePktSize::6 137329 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 139673 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 16007 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 10455 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8865 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7050 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5558 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 4708 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 3913 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3442 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 43 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 136162 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see
156,160c152,156
< system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
188,254c184,251
< system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4613 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5803 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6737 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6707 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7866 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8644 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9954 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10413 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 10166 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7446 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 368 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 134 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 78 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 75 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 85925 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 251.537690 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 143.363316 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 306.826134 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 42893 49.92% 49.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 18336 21.34% 71.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6281 7.31% 78.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3896 4.53% 83.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2533 2.95% 86.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1590 1.85% 87.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1050 1.22% 89.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 985 1.15% 90.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8361 9.73% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 85925 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6834 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 29.251244 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 562.918265 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6833 99.99% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
256,298c253,298
< system.physmem.rdPerTurnAround::total 6834 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6834 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.164618 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.651361 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.320527 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5790 84.72% 84.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 323 4.73% 89.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 59 0.86% 90.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 46 0.67% 90.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 267 3.91% 94.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 35 0.51% 95.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 21 0.31% 95.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 28 0.41% 96.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 23 0.34% 96.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 7 0.10% 96.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 12 0.18% 96.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 155 2.27% 99.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.04% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 5 0.07% 99.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 6 0.09% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 12 0.18% 99.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 2 0.03% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.01% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.01% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 2 0.03% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6834 # Writes before turning the bus around for reads
< system.physmem.totQLat 4674239132 # Total ticks spent queuing
< system.physmem.totMemAccLat 8422457882 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 999525000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 23382.30 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads
> system.physmem.totQLat 9353740299 # Total ticks spent queuing
> system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst
300,304c300,304
< system.physmem.avgMemAccLat 42132.30 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.07 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
309,345c309,355
< system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing
< system.physmem.readRowHits 166683 # Number of row buffer hits during reads
< system.physmem.writeRowHits 85101 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 61.75 # Row buffer hit rate for writes
< system.physmem.avgGap 8397436.27 # Average gap between requests
< system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 335240640 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 182919000 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 827767200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 458784000 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 84698340030 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1647701064750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1921658314500 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.568191 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2740964082488 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95835480000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 33201034512 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 314352360 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 171521625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 731484000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 434192400 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 83981561895 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1648329817500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1921417128660 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.484154 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2742009812705 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95835480000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 32151144795 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing
> system.physmem.readRowHits 165583 # Number of row buffer hits during reads
> system.physmem.writeRowHits 84490 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes
> system.physmem.avgGap 8468025.78 # Average gap between requests
> system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ)
> system.physmem_0.averagePower 247.210424 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states
> system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ)
> system.physmem_1.averagePower 247.137601 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
364,366c374,376
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
374c384
< system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
404,430c414,438
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.dtb.walker.walks 7878 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 7878 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1506 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6372 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 7878 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 7878 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 7878 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 6484 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 5676.180841 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-16383 5980 92.23% 92.23% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::16384-32767 464 7.16% 99.38% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 6484 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 5017 77.38% 77.38% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1467 22.62% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 6484 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7878 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.dtb.walker.walks 7793 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst
432,433c440,441
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7878 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6484 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst
435,436c443,444
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6484 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 14362 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst
439,442c447,450
< system.cpu0.dtb.read_hits 25174501 # DTB read hits
< system.cpu0.dtb.read_misses 6776 # DTB read misses
< system.cpu0.dtb.write_hits 18763964 # DTB write hits
< system.cpu0.dtb.write_misses 1102 # DTB write misses
---
> system.cpu0.dtb.read_hits 25156364 # DTB read hits
> system.cpu0.dtb.read_misses 6669 # DTB read misses
> system.cpu0.dtb.write_hits 18748845 # DTB write hits
> system.cpu0.dtb.write_misses 1124 # DTB write misses
447c455
< system.cpu0.dtb.flush_entries 3391 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB
449c457
< system.cpu0.dtb.prefetch_faults 1765 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch
452,453c460,461
< system.cpu0.dtb.read_accesses 25181277 # DTB read accesses
< system.cpu0.dtb.write_accesses 18765066 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 25163033 # DTB read accesses
> system.cpu0.dtb.write_accesses 18749969 # DTB write accesses
455,458c463,466
< system.cpu0.dtb.hits 43938465 # DTB hits
< system.cpu0.dtb.misses 7878 # DTB misses
< system.cpu0.dtb.accesses 43946343 # DTB accesses
< system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.hits 43905209 # DTB hits
> system.cpu0.dtb.misses 7793 # DTB misses
> system.cpu0.dtb.accesses 43913002 # DTB accesses
> system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
488c496
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
497,504c505,513
< system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 5637.639193 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-8191 386 16.55% 16.55% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::8192-16383 1666 71.41% 87.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-24575 225 9.64% 97.60% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 98.71% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.11% 99.83% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency
507c516
< system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
510,512c519,521
< system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution
---
> system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution
523c532
< system.cpu0.itb.inst_hits 119077538 # ITB inst hits
---
> system.cpu0.itb.inst_hits 119019454 # ITB inst hits
540,541c549,550
< system.cpu0.itb.inst_accesses 119080887 # ITB inst accesses
< system.cpu0.itb.hits 119077538 # DTB hits
---
> system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses
> system.cpu0.itb.hits 119019454 # DTB hits
543,549c552,558
< system.cpu0.itb.accesses 119080887 # DTB accesses
< system.cpu0.numPwrStateTransitions 3762 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 1881 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 1452265205.015417 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 23608911235.366570 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::underflows 1082 57.52% 57.52% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 794 42.21% 99.73% # Distribution of time spent in the clock gated state
---
> system.cpu0.itb.accesses 119022803 # DTB accesses
> system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state
553,557c562,566
< system.cpu0.pwrStateClkGateDist::max_value 499963656512 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::total 1881 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 138289859366 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 5740001420 # number of cpu cycles simulated
---
> system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 5741645326 # number of cpu cycles simulated
561,572c570,581
< system.cpu0.kern.inst.quiesce 1881 # number of quiesce instructions executed
< system.cpu0.committedInsts 115412619 # Number of instructions committed
< system.cpu0.committedOps 139453859 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 123427491 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
< system.cpu0.num_func_calls 12678366 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 15706258 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 123427491 # number of integer instructions
< system.cpu0.num_fp_insts 9820 # number of float instructions
< system.cpu0.num_int_register_reads 227200136 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 85767213 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
---
> system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed
> system.cpu0.committedInsts 115354991 # Number of instructions committed
> system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses
> system.cpu0.num_func_calls 12675511 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 123361088 # number of integer instructions
> system.cpu0.num_fp_insts 9690 # number of float instructions
> system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read
574,583c583,592
< system.cpu0.num_cc_register_reads 505219370 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 52317118 # number of times the CC registers were written
< system.cpu0.num_mem_refs 45075192 # number of memory refs
< system.cpu0.num_load_insts 25426401 # Number of load instructions
< system.cpu0.num_store_insts 19648791 # Number of store instructions
< system.cpu0.num_idle_cycles 5463421701.266096 # Number of idle cycles
< system.cpu0.num_busy_cycles 276579718.733904 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.048185 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.951815 # Percentage of idle cycles
< system.cpu0.Branches 29123439 # Number of branches fetched
---
> system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written
> system.cpu0.num_mem_refs 45041487 # number of memory refs
> system.cpu0.num_load_insts 25408167 # Number of load instructions
> system.cpu0.num_store_insts 19633320 # Number of store instructions
> system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles
> system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles
> system.cpu0.Branches 29114863 # Number of branches fetched
585,610c594,619
< system.cpu0.op_class::IntAlu 98023875 68.44% 68.44% # Class of executed instruction
< system.cpu0.op_class::IntMult 109907 0.08% 68.52% # Class of executed instruction
< system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.53% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction
> system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction
> system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction
614,615c623,624
< system.cpu0.op_class::MemRead 25426401 17.75% 86.28% # Class of executed instruction
< system.cpu0.op_class::MemWrite 19648791 13.72% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 25408167 17.75% 86.28% # Class of executed instruction
> system.cpu0.op_class::MemWrite 19633320 13.72% 100.00% # Class of executed instruction
618,628c627,637
< system.cpu0.op_class::total 143219456 # Class of executed instruction
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 693439 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 491.449824 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 43066582 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 693951 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 62.059975 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.449824 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959863 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.959863 # Average percentage of cache occupancy
---
> system.cpu0.op_class::total 143146475 # Class of executed instruction
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 692883 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy
630,632c639,641
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
634,714c643,723
< system.cpu0.dcache.tags.tag_accesses 88514427 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 88514427 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23911425 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23911425 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 18032865 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 18032865 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319065 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 319065 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365782 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 365782 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362736 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 362736 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 41944290 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 41944290 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 42263355 # number of overall hits
< system.cpu0.dcache.overall_hits::total 42263355 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 397667 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 397667 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 324388 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 324388 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127754 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 127754 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21573 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21573 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19602 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 19602 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 722055 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 722055 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 849809 # number of overall misses
< system.cpu0.dcache.overall_misses::total 849809 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5269907000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5269907000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5597938000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 5597938000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327322000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 327322000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 460475500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 460475500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1158000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1158000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 10867845000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 10867845000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 10867845000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 10867845000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 24309092 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 24309092 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 18357253 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 18357253 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446819 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 446819 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387355 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 387355 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382338 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 382338 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 42666345 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 42666345 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 43113164 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 43113164 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017671 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.017671 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285919 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285919 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055693 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055693 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051269 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051269 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016923 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.016923 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits
> system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses
> system.cpu0.dcache.overall_misses::total 849725 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency
717,720c726,729
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency
727,800c736,811
< system.cpu0.dcache.writebacks::writebacks 693439 # number of writebacks
< system.cpu0.dcache.writebacks::total 693439 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25271 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 25271 # number of ReadReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15260 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15260 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 25271 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 25271 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 25271 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 25271 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372396 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 372396 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324388 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 324388 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100689 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 100689 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6313 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6313 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19602 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 19602 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 696784 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 696784 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 797473 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 797473 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31786 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60249 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4503432000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4503432000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5273550000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5273550000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615902000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615902000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94571500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94571500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440907500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440907500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1124000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1124000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9776982000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9776982000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11392884000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 11392884000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628627500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628627500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628627500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628627500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015319 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015319 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017671 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017671 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225346 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225346 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016298 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016298 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051269 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051269 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016331 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.016331 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks
> system.cpu0.dcache.writebacks::total 692883 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency
803,820c814,831
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 1105141 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.449200 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 117971876 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1105653 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 106.698825 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 14058125000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449200 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 1103683 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy
826,864c837,875
< system.cpu0.icache.tags.tag_accesses 239260738 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 239260738 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 117971876 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 117971876 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 117971876 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 117971876 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 117971876 # number of overall hits
< system.cpu0.icache.overall_hits::total 117971876 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1105662 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1105662 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1105662 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1105662 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1105662 # number of overall misses
< system.cpu0.icache.overall_misses::total 1105662 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11445416000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 11445416000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 11445416000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 11445416000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 11445416000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 11445416000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 119077538 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 119077538 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 119077538 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 119077538 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 119077538 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 119077538 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009285 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.009285 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009285 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.009285 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009285 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.009285 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.640917 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.640917 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10351.640917 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10351.640917 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits
> system.cpu0.icache.overall_hits::total 117915250 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1104204 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1104204 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1104204 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1104204 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1104204 # number of overall misses
> system.cpu0.icache.overall_misses::total 1104204 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11911095000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 11911095000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 11911095000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 11911095000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 11911095000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 11911095000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 119019454 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 119019454 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 119019454 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 119019454 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 119019454 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 119019454 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009278 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.009278 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009278 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.009278 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009278 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.009278 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10787.042068 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10787.042068 # average overall miss latency
871,878c882,889
< system.cpu0.icache.writebacks::writebacks 1105141 # number of writebacks
< system.cpu0.icache.writebacks::total 1105141 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1105662 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1105662 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1105662 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1105662 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1105662 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1105662 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 1103683 # number of writebacks
> system.cpu0.icache.writebacks::total 1103683 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104204 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1104204 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104204 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1104204 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104204 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1104204 # number of overall MSHR misses
883,912c894,923
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10892585000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 10892585000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10892585000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 10892585000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10892585000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 10892585000 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009285 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.009285 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009285 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.009285 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.640917 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.640917 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.640917 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency
< system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836809 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1836835 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.009278 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.009278 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency
> system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue
915,921c926,932
< system.cpu0.l2cache.prefetcher.pfSpanPage 235109 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.tags.replacements 260353 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 15640.705301 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1686155 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 275976 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.109789 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.tags.replacements 259898 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks.
923,928c934,939
< system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.272651 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.132938 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1167.807630 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.883270 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000078 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy
930,934c941,945
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071277 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.954633 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15308 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id
936,938c947,950
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 29 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 144 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
940,1056c952,1068
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 815 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6065 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6346 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1905 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934326 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 61385527 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 61385527 # Number of data accesses
< system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9987 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4390 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 14377 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 478787 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 478787 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 1291925 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 1291925 # number of WritebackClean hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226376 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 226376 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1043295 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1043295 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 377938 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 377938 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9987 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4390 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1043295 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 604314 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1661986 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9987 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4390 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1043295 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 604314 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1661986 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 261 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 402 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55107 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 55107 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19598 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19598 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42905 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 42905 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62367 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 62367 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101460 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 101460 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 261 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 62367 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 144365 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 207134 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 261 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 141 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 62367 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 144365 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 207134 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6301500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3315500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 9617000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 31218000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 31218000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9500500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9500500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1071498 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1071498 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2039769000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2039769000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2950382000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2950382000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3031048000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3031048000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6301500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3315500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2950382000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 5070817000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 8030816000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6301500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3315500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2950382000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 5070817000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 8030816000 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10248 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4531 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 14779 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 478787 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 478787 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291925 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 1291925 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55107 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55107 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19598 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 19598 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269281 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 269281 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1105662 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1105662 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 479398 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 479398 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10248 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4531 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1105662 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 748679 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1869120 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10248 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4531 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1105662 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 748679 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1869120 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.025468 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031119 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.027201 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6084 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1977 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020752 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933411 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 61320295 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 61320295 # Number of data accesses
> system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9508 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4316 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 13824 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 476285 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 476285 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 1292383 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 1292383 # number of WritebackClean hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227392 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 227392 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1042059 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1042059 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376265 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 376265 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9508 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4316 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1042059 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 603657 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1659540 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9508 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4316 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1042059 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 603657 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1659540 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 306 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 159 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 465 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55222 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 55222 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19651 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19651 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43215 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 43215 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62145 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 62145 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101544 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 101544 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 306 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 159 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 62145 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 144759 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 207369 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 306 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 159 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 62145 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 144759 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 207369 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8941000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3729500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 12670500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32046500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 32046500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9591500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9591500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1480500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1480500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2734835500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2734835500 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3426232500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3426232500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3359763500 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3359763500 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8941000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3729500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3426232500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094599000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 9533502000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8941000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3729500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3426232500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094599000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 9533502000 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9814 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4475 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 14289 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476285 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 476285 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 1292383 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 1292383 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55222 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 55222 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19651 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 19651 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270607 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 270607 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104204 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1104204 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477809 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 477809 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9814 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4475 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1104204 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 748416 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1866909 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9814 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4475 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1104204 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 748416 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1866909 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035531 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.032543 # miss rate for ReadReq accesses
1063,1103c1075,1115
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159332 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159332 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056407 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056407 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.211640 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.211640 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.025468 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031119 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056407 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.192826 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.110819 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.025468 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031119 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056407 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.192826 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.110819 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23514.184397 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23922.885572 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 566.497904 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 566.497904 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 484.768854 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 484.768854 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 267874.500000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 267874.500000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47541.521967 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47541.521967 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47306.780830 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47306.780830 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29874.315001 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29874.315001 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23514.184397 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47306.780830 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35124.974890 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 38771.114351 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24143.678161 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23514.184397 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47306.780830 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35124.974890 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 38771.114351 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159697 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159697 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056280 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056280 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212520 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212520 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035531 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056280 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193421 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.111076 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035531 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056280 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193421 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.111076 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 580.321249 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 580.321249 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 488.092209 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 488.092209 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 493500 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 493500 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256 # average overall miss latency
1110,1148c1122,1160
< system.cpu0.l2cache.unused_prefetches 10615 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 227687 # number of writebacks
< system.cpu0.l2cache.writebacks::total 227687 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1191 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 1191 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1221 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 1221 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1221 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 1221 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 261 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 141 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 402 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259983 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 259983 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55107 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55107 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19598 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19598 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41714 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 41714 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62367 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62367 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101430 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101430 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 261 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 141 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62367 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143144 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 205913 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 261 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 141 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62367 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143144 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259983 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 465896 # number of overall MSHR misses
---
> system.cpu0.l2cache.unused_prefetches 10606 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 227429 # number of writebacks
> system.cpu0.l2cache.writebacks::total 227429 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1561 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 1561 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1594 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 1594 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1594 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 1594 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 306 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 264666 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55222 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55222 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19651 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19651 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41654 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41654 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62145 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62145 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101511 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101511 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 306 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62145 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143165 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 205775 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 306 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62145 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143165 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 470441 # number of overall MSHR misses
1150,1153c1162,1165
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40808 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40812 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable
1155,1193c1167,1205
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69271 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2469500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 7205000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13869294782 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13869294782 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 942789000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 942789000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294087500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294087500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 867498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 867498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1672104500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1672104500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2576180000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2576180000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2417355500 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2417355500 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2469500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2576180000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4089460000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 6672845000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4735500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2469500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2576180000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4089460000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13869294782 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 20542139782 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373927500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117679000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373927500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117679000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69276 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9880500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16752910842 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 946229000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 946229000 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294413000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294413000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1198500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1198500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2205065500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses
1202,1216c1214,1228
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154909 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154909 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056407 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211578 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211578 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110166 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses
1218,1292c1230,1304
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.249260 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 3740310 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1886004 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27868 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 209163 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 207471 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1692 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu0.toL2Bus.trans_dist::ReadReq 61471 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1694410 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 706729 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 1319793 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 79890 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 307615 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 87684 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41751 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 111919 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 288494 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 284839 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1105662 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 565382 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 3277 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3334509 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561453 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10930 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24498 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 5931390 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141527480 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96553100 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18124 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 238139696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 885320 # Total snoops (count)
< system.cpu0.toL2Bus.snoopTraffic 18675332 # Total snoop traffic (bytes)
< system.cpu0.toL2Bus.snoop_fanout::samples 2797680 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.089870 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.288103 # Request fanout histogram
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 888922 # Total snoops (count)
> system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes)
> system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram
1294,1296c1306,1308
< system.cpu0.toL2Bus.snoop_fanout::0 2547944 91.07% 91.07% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 248044 8.87% 99.94% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 1692 0.06% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram
1300,1301c1312,1313
< system.cpu0.toL2Bus.snoop_fanout::total 2797680 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 3721587498 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks)
1303c1315
< system.cpu0.toL2Bus.snoopLayer0.occupancy 113922479 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks)
1305c1317
< system.cpu0.toL2Bus.respLayer0.occupancy 1667515000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks)
1307c1319
< system.cpu0.toL2Bus.respLayer1.occupancy 1206437474 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks)
1311c1323
< system.cpu0.toL2Bus.respLayer3.occupancy 14255489 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks)
1313c1325
< system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
1343,1370c1355,1387
< system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.dtb.walker.walks 3379 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 3379 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 3379 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 3379 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 3379 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 2609 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 5547.212388 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-8191 616 23.61% 23.61% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1660 63.63% 87.24% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-24575 255 9.77% 97.01% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::24576-32767 67 2.57% 99.58% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-40959 5 0.19% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 2609 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples -2073200828 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 -2073200828 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total -2073200828 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.13% 74.13% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 675 25.87% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 2609 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3379 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.dtb.walker.walks 3333 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst
1372,1373c1389,1390
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3379 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2609 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst
1375,1376c1392,1393
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2609 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 5988 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst
1379,1382c1396,1399
< system.cpu1.dtb.read_hits 3943912 # DTB read hits
< system.cpu1.dtb.read_misses 2863 # DTB read misses
< system.cpu1.dtb.write_hits 3421052 # DTB write hits
< system.cpu1.dtb.write_misses 516 # DTB write misses
---
> system.cpu1.dtb.read_hits 3943012 # DTB read hits
> system.cpu1.dtb.read_misses 2827 # DTB read misses
> system.cpu1.dtb.write_hits 3420749 # DTB write hits
> system.cpu1.dtb.write_misses 506 # DTB write misses
1387c1404
< system.cpu1.dtb.flush_entries 1981 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB
1389c1406
< system.cpu1.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch
1392,1393c1409,1410
< system.cpu1.dtb.read_accesses 3946775 # DTB read accesses
< system.cpu1.dtb.write_accesses 3421568 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 3945839 # DTB read accesses
> system.cpu1.dtb.write_accesses 3421255 # DTB write accesses
1395,1398c1412,1415
< system.cpu1.dtb.hits 7364964 # DTB hits
< system.cpu1.dtb.misses 3379 # DTB misses
< system.cpu1.dtb.accesses 7368343 # DTB accesses
< system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dtb.hits 7363761 # DTB hits
> system.cpu1.dtb.misses 3333 # DTB misses
> system.cpu1.dtb.accesses 7367094 # DTB accesses
> system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
1428c1445
< system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
1437,1448c1454,1465
< system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5740.258970 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::4096-8191 165 14.91% 14.91% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-12287 593 53.57% 68.47% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 84.82% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.52% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::20480-24575 63 5.69% 95.21% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.56% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.10% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.37% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency
1452,1454c1469,1471
< system.cpu1.itb.walker.walksPending::samples -2073744828 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 -2073744828 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total -2073744828 # Table walker pending requests distribution
---
> system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution
1465c1482
< system.cpu1.itb.inst_hits 16566340 # ITB inst hits
---
> system.cpu1.itb.inst_hits 16565425 # ITB inst hits
1482,1483c1499,1500
< system.cpu1.itb.inst_accesses 16568086 # ITB inst accesses
< system.cpu1.itb.hits 16566340 # DTB hits
---
> system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses
> system.cpu1.itb.hits 16565425 # DTB hits
1485,1491c1502,1508
< system.cpu1.itb.accesses 16568086 # DTB accesses
< system.cpu1.numPwrStateTransitions 5497 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 2749 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 1034540641.602037 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 25769735768.471432 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::underflows 1960 71.30% 71.30% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 783 28.48% 99.78% # Distribution of time spent in the clock gated state
---
> system.cpu1.itb.accesses 16567171 # DTB accesses
> system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state
1498,1502c1515,1519
< system.cpu1.pwrStateClkGateDist::max_value 929980464320 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::total 2749 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 26048486236 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 5739069639 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 5740713090 # number of cpu cycles simulated
1506,1517c1523,1534
< system.cpu1.kern.inst.quiesce 2749 # number of quiesce instructions executed
< system.cpu1.committedInsts 16210815 # Number of instructions committed
< system.cpu1.committedOps 19752329 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 17813732 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
< system.cpu1.num_func_calls 1029438 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 1815045 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 17813732 # number of integer instructions
< system.cpu1.num_fp_insts 1857 # number of float instructions
< system.cpu1.num_int_register_reads 32326512 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 12493939 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
---
> system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed
> system.cpu1.committedInsts 16209756 # Number of instructions committed
> system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
> system.cpu1.num_func_calls 1029227 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 17811459 # number of integer instructions
> system.cpu1.num_fp_insts 1792 # number of float instructions
> system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
1519,1528c1536,1545
< system.cpu1.num_cc_register_reads 72207765 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 6423893 # number of times the CC registers were written
< system.cpu1.num_mem_refs 7598514 # number of memory refs
< system.cpu1.num_load_insts 4055507 # Number of load instructions
< system.cpu1.num_store_insts 3543007 # Number of store instructions
< system.cpu1.num_idle_cycles 5686981123.489185 # Number of idle cycles
< system.cpu1.num_busy_cycles 52088515.510815 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.009076 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.990924 # Percentage of idle cycles
< system.cpu1.Branches 2922923 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written
> system.cpu1.num_mem_refs 7597281 # number of memory refs
> system.cpu1.num_load_insts 4054552 # Number of load instructions
> system.cpu1.num_store_insts 3542729 # Number of store instructions
> system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles
> system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles
> system.cpu1.Branches 2922489 # Number of branches fetched
1530,1531c1547,1548
< system.cpu1.op_class::IntAlu 12474914 62.05% 62.05% # Class of executed instruction
< system.cpu1.op_class::IntMult 26468 0.13% 62.19% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction
> system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction
1555c1572
< system.cpu1.op_class::SimdFloatMisc 3329 0.02% 62.20% # Class of executed instruction
---
> system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction
1559,1560c1576,1577
< system.cpu1.op_class::MemRead 4055507 20.17% 82.38% # Class of executed instruction
< system.cpu1.op_class::MemWrite 3543007 17.62% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 4054552 20.17% 82.38% # Class of executed instruction
> system.cpu1.op_class::MemWrite 3542729 17.62% 100.00% # Class of executed instruction
1563,1658c1580,1675
< system.cpu1.op_class::total 20103291 # Class of executed instruction
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 186972 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 469.131643 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 7097155 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 187306 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 37.890698 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 127531940000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.131643 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916273 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.916273 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 14948788 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 14948788 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 3631994 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3631994 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3232351 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3232351 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48894 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 48894 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78959 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 78959 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70892 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 70892 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 6864345 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 6864345 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 6913239 # number of overall hits
< system.cpu1.dcache.overall_hits::total 6913239 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 133677 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 133677 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 91948 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 91948 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30343 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 30343 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16973 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 16973 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23209 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23209 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 225625 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 225625 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 255968 # number of overall misses
< system.cpu1.dcache.overall_misses::total 255968 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2021367000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2021367000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2373794500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2373794500 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317489000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 317489000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544203500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 544203500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1998500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4395161500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4395161500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4395161500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4395161500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3765671 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3765671 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 3324299 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 3324299 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79237 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 79237 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95932 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 95932 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94101 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 94101 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 7089970 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 7089970 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 7169207 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 7169207 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035499 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027659 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.027659 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382940 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382940 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176927 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176927 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246639 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246639 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031823 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.031823 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035704 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.035704 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226 # average StoreCondReq miss latency
---
> system.cpu1.op_class::total 20100990 # Class of executed instruction
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 186832 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits
> system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses
> system.cpu1.dcache.overall_misses::total 255886 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency
1661,1664c1678,1681
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency
1671,1730c1688,1747
< system.cpu1.dcache.writebacks::writebacks 186972 # number of writebacks
< system.cpu1.dcache.writebacks::total 186972 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12048 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12048 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133394 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 133394 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91948 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 91948 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29641 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 29641 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23209 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23209 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 225342 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 225342 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 254983 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 254983 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3099 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5549 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1881488500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1881488500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2281846500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2281846500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 500338500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 500338500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85063000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85063000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521039500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521039500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1953500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1953500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4163335000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4163335000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4663673500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4663673500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443787500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443787500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443787500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443787500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035424 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035424 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027659 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027659 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374080 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374080 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051338 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051338 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246639 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246639 # mshr miss rate for StoreCondReq accesses
---
> system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks
> system.cpu1.dcache.writebacks::total 186832 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses
1733,1744c1750,1761
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.035566 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14104.746091 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14104.746091 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24816.706182 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24816.706182 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16879.946695 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16879.946695 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17271.675127 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17271.675127 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22449.890129 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency
1747,1764c1764,1781
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18475.628156 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18475.628156 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18290.135029 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18290.135029 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143203.452727 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143203.452727 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79976.121824 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79976.121824 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 505656 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.477037 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 16060167 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 506168 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 31.728926 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 85274966000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.477037 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973588 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973588 # Average percentage of cache occupancy
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 505764 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.454577 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 16059144 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 506276 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 31.720137 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 85411536000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.454577 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973544 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.973544 # Average percentage of cache occupancy
1770,1808c1787,1825
< system.cpu1.icache.tags.tag_accesses 33638838 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 33638838 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 16060167 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 16060167 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 16060167 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 16060167 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 16060167 # number of overall hits
< system.cpu1.icache.overall_hits::total 16060167 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 506168 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 506168 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 506168 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 506168 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 506168 # number of overall misses
< system.cpu1.icache.overall_misses::total 506168 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4710776500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4710776500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4710776500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4710776500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4710776500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4710776500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 16566335 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 16566335 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 16566335 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 16566335 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 16566335 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 16566335 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030554 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.030554 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030554 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.030554 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030554 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.030554 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9306.744994 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9306.744994 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9306.744994 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9306.744994 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits
> system.cpu1.icache.overall_hits::total 16059144 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses
> system.cpu1.icache.overall_misses::total 506276 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 16565420 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 16565420 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030562 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.030562 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030562 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.030562 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030562 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.030562 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9427.881235 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9427.881235 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency
1815,1822c1832,1839
< system.cpu1.icache.writebacks::writebacks 505656 # number of writebacks
< system.cpu1.icache.writebacks::total 505656 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506168 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 506168 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 506168 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 506168 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 506168 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 506168 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks
> system.cpu1.icache.writebacks::total 505764 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses
1827,1855c1844,1872
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4457692500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 4457692500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4457692500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 4457692500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4457692500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 4457692500 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15627500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15627500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15627500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 15627500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030554 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.030554 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.030554 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8806.744994 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452 # average overall mshr uncacheable latency
< system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 198543 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 198543 # number of prefetch candidates identified
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency
> system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified
1859,1865c1876,1882
< system.cpu1.l2cache.prefetcher.pfSpanPage 58537 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.tags.replacements 43670 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 14604.323800 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 603874 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 58010 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 10.409826 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 59073 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.tags.replacements 42341 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 14550.545082 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 605184 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 56718 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 10.670052 # Average number of references to valid blocks.
1867,1880c1884,1898
< system.cpu1.l2cache.tags.occ_blocks::writebacks 14211.070638 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.100990 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.057181 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 388.094990 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.867375 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023687 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.891377 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 327 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14000 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 304 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.888095 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 333 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id
1882c1900
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
1884,1921c1902,1939
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2815 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10290 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019958 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 24332814 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 24332814 # Number of data accesses
< system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3764 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1983 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 5747 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 114262 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 114262 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 567214 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 567214 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27479 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 27479 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 484841 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 484841 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98007 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 98007 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3764 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1983 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 484841 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 125486 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 616074 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3764 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1983 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 484841 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 125486 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 616074 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 441 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 340 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 781 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29645 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29645 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23207 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 23207 # number of SCUpgradeReq misses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2799 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10333 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020325 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 24327160 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 24327160 # Number of data accesses
> system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3447 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1877 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 5324 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 114448 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 114448 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 567034 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 567034 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27676 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 27676 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485156 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 485156 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98414 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 98414 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3447 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1877 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 485156 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 126090 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 616570 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3447 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1877 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 485156 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 126090 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 616570 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 422 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 327 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29541 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29541 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23233 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 23233 # number of SCUpgradeReq misses
1924,1975c1942,1993
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34824 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 34824 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21327 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 21327 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69953 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 69953 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 441 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 340 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 21327 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 104777 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 126885 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 441 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 340 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 21327 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 104777 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 126885 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9030000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6837500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 15867500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14606500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 14606500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16450500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16450500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1885500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1885500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1331294000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1331294000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 775115000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 775115000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1573819000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1573819000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9030000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6837500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 775115000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 2905113000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 3696095500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9030000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6837500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 775115000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 2905113000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 3696095500 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4205 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2323 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 6528 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114262 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 114262 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 567214 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 567214 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29645 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 29645 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23207 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23207 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34651 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 34651 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21120 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 21120 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69614 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 69614 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 422 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 327 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 21120 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 104265 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 126134 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 422 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 327 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 21120 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 104265 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 126134 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8582000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6568500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 15150500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13749500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 13749500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16999500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16999500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1709500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1709500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1487134000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1487134000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 835278500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 835278500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1591067500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1591067500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8582000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6568500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 835278500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3078201500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3928630500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8582000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6568500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 835278500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3078201500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3928630500 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3869 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2204 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 6073 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114448 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 114448 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 567034 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 567034 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29541 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 29541 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23233 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23233 # number of SCUpgradeReq accesses(hits+misses)
1978,1996c1996,2014
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62303 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 62303 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506168 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 506168 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167960 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 167960 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4205 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2323 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 506168 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 230263 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 742959 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4205 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2323 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 506168 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 230263 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 742959 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.146362 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.119638 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62327 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 62327 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506276 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 506276 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168028 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 168028 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3869 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2204 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 506276 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 230355 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 742704 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3869 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2204 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 506276 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 230355 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 742704 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.148367 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.123333 # miss rate for ReadReq accesses
2003,2043c2021,2061
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.558946 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.558946 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042134 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042134 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.416486 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.416486 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.146362 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042134 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.455032 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.170783 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.104875 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.146362 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042134 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.455032 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.170783 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20110.294118 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20316.901408 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 492.713780 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 492.713780 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 708.859396 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 708.859396 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 942750 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 942750 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38229.209740 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38229.209740 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36344.305341 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36344.305341 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22498.234529 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22498.234529 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20110.294118 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36344.305341 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27726.628936 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 29129.491272 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20476.190476 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20110.294118 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36344.305341 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27726.628936 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 29129.491272 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555955 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555955 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041716 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041716 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414300 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414300 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.148367 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041716 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452627 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.169831 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.148367 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041716 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452627 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.169831 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 465.437866 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 465.437866 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 731.696294 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 731.696294 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 854750 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 854750 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105 # average overall miss latency
2050,2067c2068,2085
< system.cpu1.l2cache.unused_prefetches 787 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 33133 # number of writebacks
< system.cpu1.l2cache.writebacks::total 33133 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 84 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 84 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 84 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 84 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 84 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 441 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 340 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25691 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 25691 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29645 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29645 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23207 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23207 # number of SCUpgradeReq MSHR misses
---
> system.cpu1.l2cache.unused_prefetches 833 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 32020 # number of writebacks
> system.cpu1.l2cache.writebacks::total 32020 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 87 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 87 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 422 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 327 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 25249 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29541 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29541 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23233 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23233 # number of SCUpgradeReq MSHR misses
2070,2086c2088,2104
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34740 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 34740 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21327 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21327 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69953 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69953 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 441 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 340 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21327 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104693 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 126801 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 441 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 340 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21327 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104693 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25691 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 152492 # number of overall MSHR misses
---
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34564 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 34564 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21120 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21120 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69614 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69614 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 422 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 327 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21120 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104178 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 126047 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 422 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 327 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21120 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104178 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 151296 # number of overall MSHR misses
2088,2091c2106,2109
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3276 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3273 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable
2093,2131c2111,2149
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5726 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4797500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11181500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 812147618 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 812147618 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453420500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453420500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 346968500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 346968500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1615500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1615500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1114497500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1114497500 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 647153000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 647153000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1154101000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1154101000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4797500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 647153000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2268598500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 2926933000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6384000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4797500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 647153000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2268598500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 812147618 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 3739080618 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14300000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418649000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432949000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14300000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418649000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432949000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119638 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses
2140,2154c2158,2172
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557598 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557598 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.416486 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.416486 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170670 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses
2156,2230c2174,2248
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.205250 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 807750 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 807750 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 1488311 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751924 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 112911 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104591 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.cpu1.toL2Bus.trans_dist::ReadReq 12675 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 724258 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 148574 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 578366 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 28228 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 30717 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 71065 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40939 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 85439 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 36 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 69452 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 66978 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506168 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 262948 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518346 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839098 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5647 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10280 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2373371 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64757444 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29422876 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9292 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16820 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 94206432 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 332481 # Total snoops (count)
< system.cpu1.toL2Bus.snoopTraffic 4905948 # Total snoop traffic (bytes)
< system.cpu1.toL2Bus.snoop_fanout::samples 1059226 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.359953 # Request fanout histogram
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 331491 # Total snoops (count)
> system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes)
> system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram
2232,2234c2250,2252
< system.cpu1.toL2Bus.snoop_fanout::0 928762 87.68% 87.68% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 122144 11.53% 99.21% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 8320 0.79% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram
2238,2239c2256,2257
< system.cpu1.toL2Bus.snoop_fanout::total 1059226 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1442372000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks)
2241c2259
< system.cpu1.toL2Bus.snoopLayer0.occupancy 79594348 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks)
2243c2261
< system.cpu1.toL2Bus.respLayer0.occupancy 759429000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks)
2245c2263
< system.cpu1.toL2Bus.respLayer1.occupancy 376190500 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks)
2249c2267
< system.cpu1.toL2Bus.respLayer3.occupancy 6075998 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks)
2251c2269
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
2302c2320
< system.iobus.reqLayer0.occupancy 48721500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks)
2306c2324
< system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
2312c2330
< system.iobus.reqLayer7.occupancy 94000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
2314c2332
< system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks)
2318c2336
< system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2322c2340
< system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2336c2354
< system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks)
2338c2356
< system.iobus.reqLayer24.occupancy 32045000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks)
2340c2358
< system.iobus.reqLayer25.occupancy 187728827 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks)
2346c2364
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
2348c2366
< system.iocache.tags.tagsinuse 14.386151 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use
2352,2355c2370,2373
< system.iocache.tags.warmup_cycle 289285136000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.386151 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.899134 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.899134 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy
2361c2379
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
2370,2377c2388,2395
< system.iocache.ReadReq_miss_latency::realview.ide 34821377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 34821377 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4306604450 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4306604450 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 4341425827 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4341425827 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 4341425827 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4341425827 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles
2394,2402c2412,2420
< system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 136554.419608 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 119011.645796 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 119011.645796 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
2404c2422
< system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked
2406c2424
< system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
2418,2425c2436,2443
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 22071377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 22071377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493082245 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2493082245 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 2515153622 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2515153622 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 2515153622 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2515153622 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles
2434,2460c2452,2477
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 137913 # number of replacements
< system.l2c.tags.tagsinuse 65077.078827 # Cycle average of tags in use
< system.l2c.tags.total_refs 526584 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 203352 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.589520 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 102405123000 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 6467.156176 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.052663 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040623 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 7119.410088 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6998.473757 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.004586 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1431.375532 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 3211.021288 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2361.112045 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.098681 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 136024 # number of replacements
> system.l2c.tags.tagsinuse 65074.400284 # Cycle average of tags in use
> system.l2c.tags.total_refs 524979 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 201414 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.606467 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 103030494000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 6378.541377 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.901261 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045973 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 7223.294710 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6923.893951 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
2462,2476c2479,2493
< system.l2c.tags.occ_percent::cpu0.inst 0.108634 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.106788 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571982 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.021841 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.048996 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036028 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.992997 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 34227 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 31208 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 194 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 4904 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 29129 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
2479,2503c2496,2520
< system.l2c.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 1170 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 29939 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.522263 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.476196 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6120881 # Number of tag accesses
< system.l2c.tags.data_accesses 6120881 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 260820 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 260820 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 40104 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 5060 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 45164 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 2347 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 2252 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 4599 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4026 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1389 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 108 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 44456 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 52767 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45168 # number of ReadSharedReq hits
---
> system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 1178 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 29816 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.523697 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.473999 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6089608 # Number of tag accesses
> system.l2c.tags.data_accesses 6089608 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5419 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 142 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 44259 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 52827 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45774 # number of ReadSharedReq hits
2505,2514c2522,2531
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 18981 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 11141 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5391 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 178148 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 108 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 44456 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 56793 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 45168 # number of demand (read+write) hits
---
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 18793 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 10825 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5311 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 178070 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 142 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 44259 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 56833 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 45774 # number of demand (read+write) hits
2516,2525c2533,2542
< system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 18981 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 12530 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 5391 # number of demand (read+write) hits
< system.l2c.demand_hits::total 183563 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 108 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 44456 # number of overall hits
< system.l2c.overall_hits::cpu0.data 56793 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 45168 # number of overall hits
---
> system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 18793 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 12238 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 5311 # number of demand (read+write) hits
> system.l2c.demand_hits::total 183489 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 142 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 44259 # number of overall hits
> system.l2c.overall_hits::cpu0.data 56833 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 45774 # number of overall hits
2527,2541c2544,2558
< system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 18981 # number of overall hits
< system.l2c.overall_hits::cpu1.data 12530 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 5391 # number of overall hits
< system.l2c.overall_hits::total 183563 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 439 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 262 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 701 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 134 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 214 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11600 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 8098 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 19698 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
---
> system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits
> system.l2c.overall_hits::cpu1.data 12238 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits
> system.l2c.overall_hits::total 183489 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 19232 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 9 # number of ReadSharedReq misses
2543,2551c2560,2567
< system.l2c.ReadSharedReq_misses::cpu0.inst 17911 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 9058 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134486 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 2346 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 949 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6189 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 170949 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses
2553,2561c2569,2576
< system.l2c.demand_misses::cpu0.inst 17911 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 20658 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 134486 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 2346 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 9047 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 6189 # number of demand (read+write) misses
< system.l2c.demand_misses::total 190647 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
---
> system.l2c.demand_misses::cpu0.inst 17886 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 20308 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 2327 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8890 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) misses
> system.l2c.demand_misses::total 189076 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses
2563,2732c2578,2737
< system.l2c.overall_misses::cpu0.inst 17911 # number of overall misses
< system.l2c.overall_misses::cpu0.data 20658 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 134486 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 2346 # number of overall misses
< system.l2c.overall_misses::cpu1.data 9047 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 6189 # number of overall misses
< system.l2c.overall_misses::total 190647 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 8533000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 947500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 9480500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 549000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 243000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 792000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1114115000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 666355000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 1780470000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 613500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1475165500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 798074000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13067739073 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 89500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 196303000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 84484000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 694399123 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 16317041696 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 613500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 1475165500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1912189000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13067739073 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 89500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 196303000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 750839000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 694399123 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 18097511696 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 613500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 1475165500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1912189000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13067739073 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 89500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 196303000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 750839000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 694399123 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 18097511696 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 260820 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 260820 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 40543 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5322 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 45865 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 2481 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 2332 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 4813 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15626 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 9487 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 25113 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 115 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 62367 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 61825 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179654 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 39 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 21327 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 12090 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11580 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 349097 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 115 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 62367 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 77451 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179654 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 39 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 21327 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 21577 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11580 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 374210 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 115 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 62367 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 77451 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179654 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 39 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 21327 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 21577 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11580 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 374210 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010828 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.049230 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.015284 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.054010 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034305 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.044463 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.742352 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.853589 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.784375 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.060870 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287187 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146510 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.748583 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.025641 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110001 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078495 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.534456 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.489689 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.060870 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.287187 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.266723 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748583 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.025641 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.110001 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.419289 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.534456 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.509465 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.060870 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.287187 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.266723 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748583 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.025641 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.110001 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.419289 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.534456 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.509465 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19437.357631 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3616.412214 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 13524.251070 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4097.014925 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3037.500000 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3700.934579 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96044.396552 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82286.367004 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 90388.364301 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 87642.857143 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82360.867623 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88107.087657 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83675.618073 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89024.236038 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 95449.763941 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87642.857143 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 82360.867623 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 92564.091393 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 83675.618073 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 82993.146900 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 94926.810786 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87642.857143 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 82360.867623 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 92564.091393 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97168.025467 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 83675.618073 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 82993.146900 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112198.921150 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 94926.810786 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 12 # number of cycles access was blocked
---
> system.l2c.overall_misses::cpu0.inst 17886 # number of overall misses
> system.l2c.overall_misses::cpu0.data 20308 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 133589 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 2327 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8890 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 6065 # number of overall misses
> system.l2c.overall_misses::total 189076 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 9921500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 813500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 10735000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 361000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 975000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1635531500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 824298500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 2459830000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1956500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1955907500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 1124374000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261946000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 108772000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 20157534022 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 1956500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 180000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 1955907500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2759905500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 261946000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 933070500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 22617364022 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 1956500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 180000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 1955907500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2759905500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 261946000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 933070500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 22617364022 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 259449 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 259449 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 40695 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5158 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 45853 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 2504 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 2310 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 4814 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15223 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9428 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24651 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 151 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 62145 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 61918 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179363 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 21120 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 11700 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11376 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 347914 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 151 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 62145 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 77141 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179363 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 21120 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 21128 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11376 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 372565 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 151 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 62145 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 77141 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179363 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 21120 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 21128 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11376 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 372565 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014547 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.048856 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.018407 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.047125 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.039827 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.043623 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.736846 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.850127 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.780171 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.024096 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287811 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146823 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110180 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.074786 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.488178 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.024096 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.287811 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.263258 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.110180 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.420769 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.507498 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.024096 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.287811 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.263258 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.110180 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.420769 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.507498 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3228.174603 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5203.389831 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3923.913043 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 4642.857143 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 127902.974210 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 119620.491347 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 119620.491347 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 873 # number of cycles access was blocked
2734c2739
< system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
2736c2741
< system.l2c.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 109.125000 # average number of cycles each access was blocked
2738,2760c2743,2765
< system.l2c.writebacks::writebacks 101139 # number of writebacks
< system.l2c.writebacks::total 101139 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 5 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 3904 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 3904 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 439 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 262 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 701 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 134 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 214 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11600 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 8098 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 19698 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses
---
> system.l2c.writebacks::writebacks 99972 # number of writebacks
> system.l2c.writebacks::total 99972 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 3644 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 3644 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 592 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 252 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 844 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 118 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 92 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 210 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11217 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 8015 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 19232 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadSharedReq MSHR misses
2762,2770c2767,2774
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17910 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9058 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2341 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 949 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 170943 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17879 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9091 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2318 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 875 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 169828 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses
2772,2780c2776,2783
< system.l2c.demand_mshr_misses::cpu0.inst 17910 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 20658 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 2341 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 9047 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 190641 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 17879 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 20308 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 2318 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8890 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 189060 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses
2782,2789c2785,2791
< system.l2c.overall_mshr_misses::cpu0.inst 17910 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 20658 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134486 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 2341 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 9047 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6189 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 190641 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 17879 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 20308 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 2318 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8890 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 189060 # number of overall MSHR misses
2791c2793
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable
2793,2797c2795,2799
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 44081 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3093 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 44082 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30915 # number of WriteReq MSHR uncacheable
2799c2801
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses
2801,2851c2803,2850
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5546 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 74994 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10668500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5960000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 16628500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3486500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1878000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 5364500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 998115000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585374501 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 1583489501 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 543500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1296016500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 707494000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 79500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 172535500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 74994000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 14607202702 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 543500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 1296016500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 1705609000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 79500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 172535500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 660368501 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 16190692203 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 543500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 1296016500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 1705609000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11722877577 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 79500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 172535500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 660368501 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 632508125 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 16190692203 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801764501 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11113500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362869500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6757102501 # number of ReadReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801764501 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11113500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362869500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 6757102501 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5544 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 74997 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13698000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5474500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 19172500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3092000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2171500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 5263500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1523361500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 744148500 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 2267510000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1775966000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1033464000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 238288500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 100021501 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 18457620033 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 1775966000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2556825500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 238288500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 844170001 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 20725130033 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 1775966000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2556825500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 238288500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 844170001 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 20725130033 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805450500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12497000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362875500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6814067000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805450500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12497000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362875500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6814067000 # number of overall MSHR uncacheable cycles
2854,2943c2853,2936
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010828 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.049230 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.015284 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.054010 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034305 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.044463 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742352 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853589 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.784375 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146510 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078495 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.489672 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.509449 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.060870 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287171 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.266723 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748583 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.025641 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109767 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.419289 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.534456 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.509449 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 24301.822323 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22748.091603 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23721.112696 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26018.656716 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23475 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25067.757009 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86044.396552 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72286.305384 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 80388.338968 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78107.087657 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79024.236038 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85450.721597 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77642.857143 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72362.730318 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82564.091393 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87168.014344 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73701.623238 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72993.091743 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102198.759897 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 84927.650416 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182525.781822 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117205.910853 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522 # average ReadReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 504508 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 283356 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2948,2956c2941,2949
< system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 44081 # Transaction distribution
< system.membus.trans_dist::ReadResp 215279 # Transaction distribution
< system.membus.trans_dist::WriteReq 30913 # Transaction distribution
< system.membus.trans_dist::WriteResp 30913 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 137329 # Transaction distribution
< system.membus.trans_dist::CleanEvict 16651 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 64792 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 38133 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 44082 # Transaction distribution
> system.membus.trans_dist::ReadResp 214165 # Transaction distribution
> system.membus.trans_dist::WriteReq 30915 # Transaction distribution
> system.membus.trans_dist::WriteResp 30915 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution
> system.membus.trans_dist::CleanEvict 16178 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution
2958,2961c2951,2953
< system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
< system.membus.trans_dist::ReadExReq 40131 # Transaction distribution
< system.membus.trans_dist::ReadExResp 19681 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 171198 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 39788 # Transaction distribution
> system.membus.trans_dist::ReadExResp 19211 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution
2965,2967c2957,2959
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13736 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650114 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 771800 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes)
2970c2962
< system.membus.pkt_count::total 844739 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes)
2973,2975c2965,2967
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27472 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18707276 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18897612 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes)
2978,2979c2970,2971
< system.membus.pkt_size::total 21214732 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 123049 # Total snoops (count)
---
> system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 123440 # Total snoops (count)
2981,2983c2973,2975
< system.membus.snoop_fanout::samples 425474 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.012172 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.109655 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 424426 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram
2985,2986c2977,2978
< system.membus.snoop_fanout::0 420295 98.78% 98.78% # Request fanout histogram
< system.membus.snoop_fanout::1 5179 1.22% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram
> system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram
2991,2992c2983,2984
< system.membus.snoop_fanout::total 425474 # Request fanout histogram
< system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 424426 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks)
2996c2988
< system.membus.reqLayer2.occupancy 11470000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks)
2998c2990
< system.membus.reqLayer5.occupancy 976922430 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks)
3000c2992
< system.membus.respLayer2.occupancy 1118158241 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks)
3002c2994
< system.membus.respLayer3.occupancy 1366131 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks)
3004,3010c2996,3002
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
3017,3018c3009,3010
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
3050,3056c3042,3048
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
3061,3105c3053,3097
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 1015113 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 540228 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 174806 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 29447 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 28379 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 1068 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.trans_dist::ReadReq 44084 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 511780 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 361959 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 119582 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 109939 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 42732 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 152671 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 51282 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 51282 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 467698 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 4573 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1273273 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316945 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1590218 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35272632 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5631700 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 40904332 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 389588 # Total snoops (count)
< system.toL2Bus.snoopTraffic 15743116 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 889230 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.395392 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.491385 # Request fanout histogram
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states
> system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 388372 # Total snoops (count)
> system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram
3107,3109c3099,3101
< system.toL2Bus.snoop_fanout::0 538704 60.58% 60.58% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 349458 39.30% 99.88% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 1068 0.12% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram
3113,3114c3105,3106
< system.toL2Bus.snoop_fanout::total 889230 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 894701567 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks)
3116c3108
< system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks)
3118c3110
< system.toL2Bus.respLayer0.occupancy 677372101 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks)
3120c3112
< system.toL2Bus.respLayer1.occupancy 239236747 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks)