7,13c7,13
< host_inst_rate 543935 # Simulator instruction rate (inst/s)
< host_op_rate 657921 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11865725522 # Simulator tick rate (ticks/s)
< host_mem_usage 611884 # Number of bytes of host memory used
< host_seconds 241.86 # Real time elapsed on the host
< sim_insts 131553572 # Number of instructions simulated
< sim_ops 159121620 # Number of ops (including micro ops) simulated
---
> host_inst_rate 480288 # Simulator instruction rate (inst/s)
> host_op_rate 580935 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10477281069 # Simulator tick rate (ticks/s)
> host_mem_usage 611892 # Number of bytes of host memory used
> host_seconds 273.91 # Real time elapsed on the host
> sim_insts 131553574 # Number of instructions simulated
> sim_ops 159121622 # Number of ops (including micro ops) simulated
289,290c289,290
< system.physmem.totQLat 4572923146 # Total ticks spent queuing
< system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 4572903146 # Total ticks spent queuing
> system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM
292c292
< system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst
294c294
< system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst
316,318c316,318
< system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ)
320c320
< system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states
323c323
< system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states
330,332c330,332
< system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ)
334c334
< system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states
337c337
< system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states
428c428
< system.cpu0.dtb.read_hits 25156507 # DTB read hits
---
> system.cpu0.dtb.read_hits 25156508 # DTB read hits
430c430
< system.cpu0.dtb.write_hits 18749940 # DTB write hits
---
> system.cpu0.dtb.write_hits 18749941 # DTB write hits
441,442c441,442
< system.cpu0.dtb.read_accesses 25163336 # DTB read accesses
< system.cpu0.dtb.write_accesses 18751054 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 25163337 # DTB read accesses
> system.cpu0.dtb.write_accesses 18751055 # DTB write accesses
444c444
< system.cpu0.dtb.hits 43906447 # DTB hits
---
> system.cpu0.dtb.hits 43906449 # DTB hits
446c446
< system.cpu0.dtb.accesses 43914390 # DTB accesses
---
> system.cpu0.dtb.accesses 43914392 # DTB accesses
536,537c536,537
< system.cpu0.committedInsts 115352403 # Number of instructions committed
< system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed
---
> system.cpu0.committedInsts 115352405 # Number of instructions committed
> system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed
544,545c544,545
< system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written
548c548
< system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read
---
> system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read
595c595
< system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks.
597c597
< system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks.
607,612c607,612
< system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits
619,622c619,622
< system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits
< system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits
---
> system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits
> system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits
637,638c637,638
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles
---
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles
647,654c647,654
< system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses)
661,664c661,664
< system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses
679,680c679,680
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency
---
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency
689,692c689,692
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency
729,730c729,730
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles
---
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles
741,744c741,744
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles
763,764c763,764
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency
---
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency
775,778c775,778
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency
980,981c980,981
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles
---
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles
985,986c985,986
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles
---
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles
990,991c990,991
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles
---
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles
1059,1060c1059,1060
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency
---
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency
1064,1065c1064,1065
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency
---
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency
1069,1070c1069,1070
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency
---
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency
1127,1128c1127,1128
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles
---
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles
1139,1140c1139,1140
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles
1144,1145c1144,1145
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles
1149,1151c1149,1151
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles
1189,1190c1189,1190
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency
---
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency
1201,1202c1201,1202
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency
---
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency
1206,1207c1206,1207
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency
---
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency
1211,1213c1211,1213
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency
2515,2516c2515,2516
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles
2520c2520
< system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles
2524,2525c2524,2525
< system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles
2529c2529
< system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles
2533,2534c2533,2534
< system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles
2538c2538
< system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles
2631,2632c2631,2632
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency
2636c2636
< system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency
2640,2641c2640,2641
< system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
2645c2645
< system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency
2649,2650c2649,2650
< system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
2654c2654
< system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency
2735,2736c2735,2736
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles
2740c2740
< system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles
2744,2745c2744,2745
< system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles
2749c2749
< system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles
2753,2754c2753,2754
< system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles
2758c2758
< system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles
2819,2820c2819,2820
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency
2824c2824
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency
2828,2829c2828,2829
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
2833c2833
< system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
2837,2838c2837,2838
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
2842c2842
< system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
< host_inst_rate 543935 # Simulator instruction rate (inst/s)
< host_op_rate 657921 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11865725522 # Simulator tick rate (ticks/s)
< host_mem_usage 611884 # Number of bytes of host memory used
< host_seconds 241.86 # Real time elapsed on the host
< sim_insts 131553572 # Number of instructions simulated
< sim_ops 159121620 # Number of ops (including micro ops) simulated
---
> host_inst_rate 480288 # Simulator instruction rate (inst/s)
> host_op_rate 580935 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10477281069 # Simulator tick rate (ticks/s)
> host_mem_usage 611892 # Number of bytes of host memory used
> host_seconds 273.91 # Real time elapsed on the host
> sim_insts 131553574 # Number of instructions simulated
> sim_ops 159121622 # Number of ops (including micro ops) simulated
289,290c289,290
< system.physmem.totQLat 4572923146 # Total ticks spent queuing
< system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 4572903146 # Total ticks spent queuing
> system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM
292c292
< system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst
294c294
< system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst
316,318c316,318
< system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ)
320c320
< system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states
323c323
< system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states
330,332c330,332
< system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ)
334c334
< system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states
337c337
< system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states
428c428
< system.cpu0.dtb.read_hits 25156507 # DTB read hits
---
> system.cpu0.dtb.read_hits 25156508 # DTB read hits
430c430
< system.cpu0.dtb.write_hits 18749940 # DTB write hits
---
> system.cpu0.dtb.write_hits 18749941 # DTB write hits
441,442c441,442
< system.cpu0.dtb.read_accesses 25163336 # DTB read accesses
< system.cpu0.dtb.write_accesses 18751054 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 25163337 # DTB read accesses
> system.cpu0.dtb.write_accesses 18751055 # DTB write accesses
444c444
< system.cpu0.dtb.hits 43906447 # DTB hits
---
> system.cpu0.dtb.hits 43906449 # DTB hits
446c446
< system.cpu0.dtb.accesses 43914390 # DTB accesses
---
> system.cpu0.dtb.accesses 43914392 # DTB accesses
536,537c536,537
< system.cpu0.committedInsts 115352403 # Number of instructions committed
< system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed
---
> system.cpu0.committedInsts 115352405 # Number of instructions committed
> system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed
544,545c544,545
< system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written
548c548
< system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read
---
> system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read
595c595
< system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks.
---
> system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks.
597c597
< system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks.
607,612c607,612
< system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits
619,622c619,622
< system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits
< system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits
---
> system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits
> system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits
637,638c637,638
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles
---
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles
647,654c647,654
< system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses)
661,664c661,664
< system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses
679,680c679,680
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency
---
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency
689,692c689,692
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency
729,730c729,730
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles
---
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles
741,744c741,744
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles
763,764c763,764
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency
---
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency
775,778c775,778
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency
980,981c980,981
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles
---
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles
985,986c985,986
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles
---
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles
990,991c990,991
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles
---
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles
1059,1060c1059,1060
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency
---
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency
1064,1065c1064,1065
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency
---
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency
1069,1070c1069,1070
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency
---
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency
1127,1128c1127,1128
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles
---
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles
1139,1140c1139,1140
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles
1144,1145c1144,1145
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles
1149,1151c1149,1151
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles
1189,1190c1189,1190
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency
---
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency
1201,1202c1201,1202
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency
---
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency
1206,1207c1206,1207
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency
---
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency
1211,1213c1211,1213
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency
2515,2516c2515,2516
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles
2520c2520
< system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles
---
> system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles
2524,2525c2524,2525
< system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles
2529c2529
< system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles
2533,2534c2533,2534
< system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles
2538c2538
< system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles
2631,2632c2631,2632
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency
2636c2636
< system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency
---
> system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency
2640,2641c2640,2641
< system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
2645c2645
< system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency
2649,2650c2649,2650
< system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
2654c2654
< system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency
2735,2736c2735,2736
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles
2740c2740
< system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles
---
> system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles
2744,2745c2744,2745
< system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles
2749c2749
< system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles
2753,2754c2753,2754
< system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles
2758c2758
< system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles
2819,2820c2819,2820
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency
2824c2824
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency
---
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency
2828,2829c2828,2829
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
2833c2833
< system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
2837,2838c2837,2838
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
2842c2842
< system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency