7,11c7,11
< host_inst_rate 937604 # Simulator instruction rate (inst/s)
< host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
< host_mem_usage 614632 # Number of bytes of host memory used
< host_seconds 140.24 # Real time elapsed on the host
---
> host_inst_rate 717242 # Simulator instruction rate (inst/s)
> host_op_rate 867543 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15665668571 # Simulator tick rate (ticks/s)
> host_mem_usage 616200 # Number of bytes of host memory used
> host_seconds 183.32 # Real time elapsed on the host
690,691d689
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
742,745c740,741
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles
778,782c774,775
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency
841,842d833
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
881d871
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1083,1084d1072
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1163,1164d1150
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles
1166,1167c1152,1153
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles
1227,1228d1212
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency
1230,1232c1214,1215
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency
1632,1633d1614
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1682,1685c1663,1664
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles
1718,1722c1697,1698
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency
1781,1782d1756
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1821d1794
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2018,2019d1990
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2096,2097d2066
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles
2099,2100c2068,2069
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles
2160,2161d2128
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency
2163,2165c2130,2131
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency
2336,2339c2302,2305
< system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
< system.iocache.demand_misses::total 255 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 255 # number of overall misses
< system.iocache.overall_misses::total 255 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36479 # number of overall misses
> system.iocache.overall_misses::total 36479 # number of overall misses
2344,2347c2310,2313
< system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles
2352,2355c2318,2321
< system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2368,2371c2334,2337
< system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency
2378,2379d2343
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2386,2389c2350,2353
< system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2394,2397c2358,2361
< system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles
2410,2414c2374,2377
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
2696,2697d2658
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
2801,2803d2761
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles
2805c2763
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles
2807,2808c2765,2766
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles
2888,2890d2845
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency
2892c2847
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency
2894,2896c2849,2850
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency
< host_inst_rate 937604 # Simulator instruction rate (inst/s)
< host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
< host_mem_usage 614632 # Number of bytes of host memory used
< host_seconds 140.24 # Real time elapsed on the host
---
> host_inst_rate 717242 # Simulator instruction rate (inst/s)
> host_op_rate 867543 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15665668571 # Simulator tick rate (ticks/s)
> host_mem_usage 616200 # Number of bytes of host memory used
> host_seconds 183.32 # Real time elapsed on the host
690,691d689
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
742,745c740,741
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles
778,782c774,775
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency
841,842d833
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
881d871
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1083,1084d1072
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1163,1164d1150
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles
1166,1167c1152,1153
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles
1227,1228d1212
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency
1230,1232c1214,1215
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency
1632,1633d1614
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1682,1685c1663,1664
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles
1718,1722c1697,1698
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency
1781,1782d1756
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1821d1794
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2018,2019d1990
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2096,2097d2066
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles
2099,2100c2068,2069
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles
2160,2161d2128
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency
2163,2165c2130,2131
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency
2336,2339c2302,2305
< system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
< system.iocache.demand_misses::total 255 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 255 # number of overall misses
< system.iocache.overall_misses::total 255 # number of overall misses
---
> system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
> system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 36479 # number of overall misses
> system.iocache.overall_misses::total 36479 # number of overall misses
2344,2347c2310,2313
< system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles
2352,2355c2318,2321
< system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2368,2371c2334,2337
< system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency
2378,2379d2343
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2386,2389c2350,2353
< system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2394,2397c2358,2361
< system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles
2410,2414c2374,2377
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
2696,2697d2658
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
2801,2803d2761
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles
2805c2763
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles
2807,2808c2765,2766
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles
2888,2890d2845
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency
2892c2847
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency
2894,2896c2849,2850
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency