3,5c3,5
< sim_seconds 2.871850 # Number of seconds simulated
< sim_ticks 2871850306000 # Number of ticks simulated
< final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.871782 # Number of seconds simulated
> sim_ticks 2871782342000 # Number of ticks simulated
> final_tick 2871782342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 312956 # Simulator instruction rate (inst/s)
< host_op_rate 378531 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6832247646 # Simulator tick rate (ticks/s)
< host_mem_usage 599868 # Number of bytes of host memory used
< host_seconds 420.34 # Real time elapsed on the host
< sim_insts 131546959 # Number of instructions simulated
< sim_ops 159110973 # Number of ops (including micro ops) simulated
---
> host_inst_rate 937604 # Simulator instruction rate (inst/s)
> host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
> host_mem_usage 614632 # Number of bytes of host memory used
> host_seconds 140.24 # Real time elapsed on the host
> sim_insts 131486349 # Number of instructions simulated
> sim_ops 159039994 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
18,20c18,20
< system.physmem.bytes_read::cpu0.inst 1178404 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 1267556 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 8608576 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1156004 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 1264932 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602496 # Number of bytes read from this memory
22,24c22,24
< system.physmem.bytes_read::cpu1.inst 129300 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 549908 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 341632 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.inst 151508 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 548500 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 349120 # Number of bytes read from this memory
26,30c26,30
< system.physmem.bytes_read::total 12076912 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1178404 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 129300 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1307704 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8530240 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 12074032 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1156004 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 151508 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1307512 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8524352 # Number of bytes written to this memory
33,34c33,34
< system.physmem.bytes_written::total 8547804 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8541916 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
36,38c36,38
< system.physmem.num_reads::cpu0.inst 26866 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 20325 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 134509 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 26516 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 20284 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 134414 # Number of read requests responded to by this memory
40,42c40,42
< system.physmem.num_reads::cpu1.inst 2175 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 5338 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 2522 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 8591 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 5455 # Number of read requests responded to by this memory
44,45c44,45
< system.physmem.num_reads::total 197850 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 133285 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 197805 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 133193 # Number of write requests responded to by this memory
48,49c48,49
< system.physmem.num_writes::total 137676 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 137584 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 111 # Total read bandwidth from this memory (bytes/s)
51,53c51,53
< system.physmem.bw_read::cpu0.inst 410329 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 441373 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 2997571 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 402539 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 440469 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 2995525 # Total read bandwidth from this memory (bytes/s)
55,57c55,57
< system.physmem.bw_read::cpu1.inst 45023 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 191482 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 118959 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 52757 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 190996 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 121569 # Total read bandwidth from this memory (bytes/s)
59,63c59,63
< system.physmem.bw_read::total 4205272 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 410329 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 45023 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 455352 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2970294 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4204369 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 402539 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 52757 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 455296 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2968314 # Write bandwidth from this memory (bytes/s)
66,68c66,68
< system.physmem.bw_write::total 2976410 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2970294 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2974430 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2968314 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 111 # Total bandwidth to/from this memory (bytes/s)
70,72c70,72
< system.physmem.bw_total::cpu0.inst 410329 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 447475 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 2997571 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 402539 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 446571 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 2995525 # Total bandwidth to/from this memory (bytes/s)
74,76c74,76
< system.physmem.bw_total::cpu1.inst 45023 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 191496 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 118959 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu1.inst 52757 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 191010 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 121569 # Total bandwidth to/from this memory (bytes/s)
78,88c78,88
< system.physmem.bw_total::total 7181682 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 197850 # Number of read requests accepted
< system.physmem.writeReqs 137676 # Number of write requests accepted
< system.physmem.readBursts 197850 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 137676 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12652352 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8560960 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12076912 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8547804 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 7178799 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 197805 # Number of read requests accepted
> system.physmem.writeReqs 137584 # Number of write requests accepted
> system.physmem.readBursts 197805 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 137584 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 12650304 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8554240 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12074032 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8541916 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
90,122c90,122
< system.physmem.neitherReadNorWriteReqs 64578 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 11583 # Per bank write bursts
< system.physmem.perBankRdBursts::1 11800 # Per bank write bursts
< system.physmem.perBankRdBursts::2 11971 # Per bank write bursts
< system.physmem.perBankRdBursts::3 11847 # Per bank write bursts
< system.physmem.perBankRdBursts::4 20098 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11961 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12460 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12487 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11821 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12495 # Per bank write bursts
< system.physmem.perBankRdBursts::10 11828 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11338 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11476 # Per bank write bursts
< system.physmem.perBankRdBursts::13 11922 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11270 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11336 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8288 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8566 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8821 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8522 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7854 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8398 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8910 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8793 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8333 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8912 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8495 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8357 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8083 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7998 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7822 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7613 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11699 # Per bank write bursts
> system.physmem.perBankRdBursts::1 11843 # Per bank write bursts
> system.physmem.perBankRdBursts::2 11790 # Per bank write bursts
> system.physmem.perBankRdBursts::3 11735 # Per bank write bursts
> system.physmem.perBankRdBursts::4 20524 # Per bank write bursts
> system.physmem.perBankRdBursts::5 11797 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12442 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12572 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12187 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12631 # Per bank write bursts
> system.physmem.perBankRdBursts::10 11774 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11306 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11587 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11723 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11020 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11031 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8350 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8610 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8670 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8312 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8160 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8304 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8940 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8786 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8636 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9040 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8341 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8261 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8330 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7860 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7712 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7348 # Per bank write bursts
125c125
< system.physmem.totGap 2871849883000 # Total gap between requests
---
> system.physmem.totGap 2871781902000 # Total gap between requests
132c132
< system.physmem.readPktSize::6 188090 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 188045 # Read request sizes (log2)
139,153c139,153
< system.physmem.writePktSize::6 133285 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 138613 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 15680 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 10206 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 8777 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 7036 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 5467 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 4577 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 3802 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3339 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 81 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 56 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 33 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 133193 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 15603 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 10240 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 8695 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 6977 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 5455 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 4557 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 3833 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3359 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 91 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 38 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
156,157c156,157
< system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
187,253c187,253
< system.physmem.wrQLenPdf::15 2732 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3200 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4416 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5092 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6617 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7823 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8913 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9011 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10422 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8444 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8402 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 9645 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 8273 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6958 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 367 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 363 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 32 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 87676 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 241.950454 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 136.764211 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 303.933653 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 46396 52.92% 52.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17641 20.12% 73.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5908 6.74% 79.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3515 4.01% 83.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2504 2.86% 86.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1565 1.78% 88.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 855 0.98% 89.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 945 1.08% 90.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8347 9.52% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 87676 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6535 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 30.251262 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 585.438505 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6533 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2692 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5083 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6358 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6921 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 7802 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8411 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8780 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 10954 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 8505 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7612 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1066 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 335 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 87582 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 242.110023 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 136.595388 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 304.444001 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 46635 53.25% 53.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 17297 19.75% 73.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6011 6.86% 79.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3421 3.91% 83.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2493 2.85% 86.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1531 1.75% 88.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 857 0.98% 89.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 971 1.11% 90.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8366 9.55% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 87582 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6415 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 30.812159 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 590.882305 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6413 99.97% 99.97% # Reads before turning the bus around for writes
256,296c256,298
< system.physmem.rdPerTurnAround::total 6535 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6535 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.469013 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.883832 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.598321 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5330 81.56% 81.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 483 7.39% 88.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 73 1.12% 90.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 153 2.34% 92.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 33 0.50% 92.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 123 1.88% 94.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 36 0.55% 95.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 26 0.40% 95.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 25 0.38% 96.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 15 0.23% 96.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.09% 96.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.09% 96.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 152 2.33% 98.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 6 0.09% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 2 0.03% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 26 0.40% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 7 0.11% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.02% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.05% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6535 # Writes before turning the bus around for reads
< system.physmem.totQLat 4503336233 # Total ticks spent queuing
< system.physmem.totMemAccLat 8210079983 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 988465000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 22779.44 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6415 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6415 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.835542 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.951972 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.109397 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5337 83.20% 83.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 463 7.22% 90.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 65 1.01% 91.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 41 0.64% 92.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 43 0.67% 92.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 15 0.23% 92.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 61 0.95% 93.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 12 0.19% 94.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 120 1.87% 95.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 12 0.19% 96.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 8 0.12% 96.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 12 0.19% 96.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 75 1.17% 97.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 9 0.14% 97.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.06% 97.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 25 0.39% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 75 1.17% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.02% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 11 0.17% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 3 0.05% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.02% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 5 0.08% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.03% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6415 # Writes before turning the bus around for reads
> system.physmem.totQLat 4510532456 # Total ticks spent queuing
> system.physmem.totMemAccLat 8216676206 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 988305000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 22819.54 # Average queueing delay per DRAM burst
298c300
< system.physmem.avgMemAccLat 41529.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 41569.54 # Average memory access latency per DRAM burst
301,302c303,304
< system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 4.20 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s
307,310c309,312
< system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 22.35 # Average write queue length when enqueuing
< system.physmem.readRowHits 165103 # Number of row buffer hits during reads
< system.physmem.writeRowHits 78678 # Number of row buffer hits during writes
---
> system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.88 # Average write queue length when enqueuing
> system.physmem.readRowHits 165067 # Number of row buffer hits during reads
> system.physmem.writeRowHits 78671 # Number of row buffer hits during writes
312,325c314,327
< system.physmem.writeRowHitRate 58.81 # Row buffer hit rate for writes
< system.physmem.avgGap 8559246.92 # Average gap between requests
< system.physmem.pageHitRate 73.54 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 341250840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 186198375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 812814600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 441624960 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 85820448015 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1647828636000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1923006208950 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.605484 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2741162536487 # Time in different power states
< system.physmem_0.memoryStateTime::REF 95897360000 # Time in different power states
---
> system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes
> system.physmem.avgGap 8562540.52 # Average gap between requests
> system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 341273520 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 186210750 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 814335600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 441495360 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 86023351485 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1647608604750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1922985930585 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.614762 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2740794855198 # Time in different power states
> system.physmem_0.memoryStateTime::REF 95895020000 # Time in different power states
327c329
< system.physmem_0.memoryStateTime::ACT 34789668513 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 35089613552 # Time in different power states
329,339c331,341
< system.physmem_1.actEnergy 321579720 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 175465125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 729183000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 425172240 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 84866434740 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1648665489750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1922758560735 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.519251 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2742561244982 # Time in different power states
< system.physmem_1.memoryStateTime::REF 95897360000 # Time in different power states
---
> system.physmem_1.actEnergy 320846400 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 175065000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 727412400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 424621440 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 84787415640 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1648692759000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1922698779000 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.514771 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2742610583350 # Time in different power states
> system.physmem_1.memoryStateTime::REF 95895020000 # Time in different power states
341c343
< system.physmem_1.memoryStateTime::ACT 33391555518 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 33276576650 # Time in different power states
397,412c399,417
< system.cpu0.dtb.walker.walks 8830 # Table walker walks requested
< system.cpu0.dtb.walker.walksShort 8830 # Table walker walks initiated with short descriptors
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1617 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7213 # Level at which table walker walks with short descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 8830 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 8830 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 8830 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 7312 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 6252.045789 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-32767 7284 99.62% 99.62% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-65535 24 0.33% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 7312 # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walks 8793 # Table walker walks requested
> system.cpu0.dtb.walker.walksShort 8793 # Table walker walks initiated with short descriptors
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1631 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7162 # Level at which table walker walks with short descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 8793 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 8793 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 8793 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 7275 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 5725.376750 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-16383 6764 92.98% 92.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::16384-32767 475 6.53% 99.51% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::32768-49151 28 0.38% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.05% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 7275 # Table walker service (enqueue to completion) latency
416,419c421,424
< system.cpu0.dtb.walker.walkPageSizes::4K 5742 78.53% 78.53% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::1M 1570 21.47% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 7312 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8830 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkPageSizes::4K 5691 78.23% 78.23% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::1M 1584 21.77% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 7275 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8793 # Table walker requests started/completed, data/inst
421,422c426,427
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8830 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7312 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8793 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7275 # Table walker requests started/completed, data/inst
424,425c429,430
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7312 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 16142 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7275 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 16068 # Table walker requests started/completed, data/inst
428,431c433,436
< system.cpu0.dtb.read_hits 25809403 # DTB read hits
< system.cpu0.dtb.read_misses 7606 # DTB read misses
< system.cpu0.dtb.write_hits 19327142 # DTB write hits
< system.cpu0.dtb.write_misses 1224 # DTB write misses
---
> system.cpu0.dtb.read_hits 25747110 # DTB read hits
> system.cpu0.dtb.read_misses 7587 # DTB read misses
> system.cpu0.dtb.write_hits 19248161 # DTB write hits
> system.cpu0.dtb.write_misses 1206 # DTB write misses
436c441
< system.cpu0.dtb.flush_entries 3761 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 3752 # Number of entries that have been flushed from TLB
438c443
< system.cpu0.dtb.prefetch_faults 1861 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 1822 # Number of TLB faults due to prefetch
441,442c446,447
< system.cpu0.dtb.read_accesses 25817009 # DTB read accesses
< system.cpu0.dtb.write_accesses 19328366 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 25754697 # DTB read accesses
> system.cpu0.dtb.write_accesses 19249367 # DTB write accesses
444,446c449,451
< system.cpu0.dtb.hits 45136545 # DTB hits
< system.cpu0.dtb.misses 8830 # DTB misses
< system.cpu0.dtb.accesses 45145375 # DTB accesses
---
> system.cpu0.dtb.hits 44995271 # DTB hits
> system.cpu0.dtb.misses 8793 # DTB misses
> system.cpu0.dtb.accesses 45004064 # DTB accesses
484,492c489,495
< system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 6240.244766 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-16383 2261 87.77% 87.77% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::16384-32767 282 10.95% 98.72% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-49151 30 1.16% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 7309.377161 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-32767 2541 98.64% 98.64% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-65535 33 1.28% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-163839 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-294911 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
507c510
< system.cpu0.itb.inst_hits 121850168 # ITB inst hits
---
> system.cpu0.itb.inst_hits 121581439 # ITB inst hits
524,525c527,528
< system.cpu0.itb.inst_accesses 121853842 # ITB inst accesses
< system.cpu0.itb.hits 121850168 # DTB hits
---
> system.cpu0.itb.inst_accesses 121585113 # ITB inst accesses
> system.cpu0.itb.hits 121581439 # DTB hits
527,528c530,531
< system.cpu0.itb.accesses 121853842 # DTB accesses
< system.cpu0.numCycles 5743700612 # number of cpu cycles simulated
---
> system.cpu0.itb.accesses 121585113 # DTB accesses
> system.cpu0.numCycles 5743564684 # number of cpu cycles simulated
532,535c535,538
< system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed
< system.cpu0.committedInsts 118029542 # Number of instructions committed
< system.cpu0.committedOps 142673635 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 126253590 # Number of integer alu accesses
---
> system.cpu0.kern.inst.quiesce 1899 # number of quiesce instructions executed
> system.cpu0.committedInsts 117764996 # Number of instructions committed
> system.cpu0.committedOps 142323546 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 125936873 # Number of integer alu accesses
537,539c540,542
< system.cpu0.num_func_calls 12792333 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 16043976 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 126253590 # number of integer instructions
---
> system.cpu0.num_func_calls 12772448 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 16008688 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 125936873 # number of integer instructions
541,542c544,545
< system.cpu0.num_int_register_reads 232324144 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 87654298 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 231719006 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 87450436 # number of times the integer registers were written
545,554c548,557
< system.cpu0.num_cc_register_reads 516734560 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 53610723 # number of times the CC registers were written
< system.cpu0.num_mem_refs 46299073 # number of memory refs
< system.cpu0.num_load_insts 26069844 # Number of load instructions
< system.cpu0.num_store_insts 20229229 # Number of store instructions
< system.cpu0.num_idle_cycles 5455076908.366100 # Number of idle cycles
< system.cpu0.num_busy_cycles 288623703.633900 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.050250 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.949750 # Percentage of idle cycles
< system.cpu0.Branches 29603215 # Number of branches fetched
---
> system.cpu0.num_cc_register_reads 515468589 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 53496392 # number of times the CC registers were written
> system.cpu0.num_mem_refs 46152180 # number of memory refs
> system.cpu0.num_load_insts 26006060 # Number of load instructions
> system.cpu0.num_store_insts 20146120 # Number of store instructions
> system.cpu0.num_idle_cycles 5455990176.452100 # Number of idle cycles
> system.cpu0.num_busy_cycles 287574507.547900 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.050069 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.949931 # Percentage of idle cycles
> system.cpu0.Branches 29546529 # Number of branches fetched
556,586c559,589
< system.cpu0.op_class::IntAlu 100054313 68.31% 68.31% # Class of executed instruction
< system.cpu0.op_class::IntMult 112340 0.08% 68.39% # Class of executed instruction
< system.cpu0.op_class::IntDiv 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 8369 0.01% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.39% # Class of executed instruction
< system.cpu0.op_class::MemRead 26069844 17.80% 86.19% # Class of executed instruction
< system.cpu0.op_class::MemWrite 20229229 13.81% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 99842345 68.33% 68.33% # Class of executed instruction
> system.cpu0.op_class::IntMult 112141 0.08% 68.41% # Class of executed instruction
> system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 8311 0.01% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction
> system.cpu0.op_class::MemRead 26006060 17.80% 86.21% # Class of executed instruction
> system.cpu0.op_class::MemWrite 20146120 13.79% 100.00% # Class of executed instruction
589,594c592,597
< system.cpu0.op_class::total 146476410 # Class of executed instruction
< system.cpu0.dcache.tags.replacements 740882 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 488.760528 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 44216040 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 741394 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 59.639058 # Average number of references to valid blocks.
---
> system.cpu0.op_class::total 146117292 # Class of executed instruction
> system.cpu0.dcache.tags.replacements 732778 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 487.345221 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 44083181 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 733290 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 60.116981 # Average number of references to valid blocks.
596,598c599,601
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.760528 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954610 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.954610 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.345221 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951846 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.951846 # Average percentage of cache occupancy
600,602c603,605
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
604,683c607,686
< system.cpu0.dcache.tags.tag_accesses 90957934 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 90957934 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 24496228 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 24496228 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 18570022 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 18570022 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 327271 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 327271 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374846 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 374846 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 372508 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 372508 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 43066250 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 43066250 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 43393521 # number of overall hits
< system.cpu0.dcache.overall_hits::total 43393521 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 423502 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 423502 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 340254 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 340254 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133712 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 133712 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22535 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 22535 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19849 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 19849 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 763756 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 763756 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 897468 # number of overall misses
< system.cpu0.dcache.overall_misses::total 897468 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5717292500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 5717292500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6989183500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 6989183500 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344979500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 344979500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 511150000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 511150000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1456500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1456500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 12706476000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 12706476000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 12706476000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 12706476000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 24919730 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 24919730 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 18910276 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 18910276 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 460983 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 460983 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397381 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 397381 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 392357 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 392357 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 43830006 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 43830006 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 44290989 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 44290989 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016995 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.016995 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017993 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.017993 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290058 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290058 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056709 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056709 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050589 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050589 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017425 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.017425 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020263 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.020263 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 90667478 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 90667478 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 24441740 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 24441740 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 18494582 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 18494582 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326232 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 326232 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374079 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 374079 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371656 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 371656 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 42936322 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 42936322 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 43262554 # number of overall hits
> system.cpu0.dcache.overall_hits::total 43262554 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 418013 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 418013 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 337667 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 337667 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133440 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 133440 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22337 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 22337 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19808 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 19808 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 755680 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 755680 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 889120 # number of overall misses
> system.cpu0.dcache.overall_misses::total 889120 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5665137000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 5665137000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6926542000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 6926542000 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 343483500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 343483500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 502731000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 502731000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1840500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1840500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 12591679000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 12591679000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 12591679000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 12591679000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859753 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 24859753 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 18832249 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 18832249 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459672 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 459672 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396416 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 396416 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391464 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 391464 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 43692002 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 43692002 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 44151674 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 44151674 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016815 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.016815 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017930 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.017930 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290294 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290294 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056347 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056347 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050600 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050600 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017296 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.017296 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020138 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.020138 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919 # average StoreCondReq miss latency
686,689c689,692
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 16662.713053 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14161.956766 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 14161.956766 # average overall miss latency
698,773c701,778
< system.cpu0.dcache.writebacks::writebacks 740882 # number of writebacks
< system.cpu0.dcache.writebacks::total 740882 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25304 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 25304 # number of ReadReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15852 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15852 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 25304 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 25304 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 25304 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 25304 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 398198 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 398198 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 340254 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 340254 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106613 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 106613 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6683 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6683 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19849 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 19849 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 738452 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 738452 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 845065 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 845065 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31860 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60413 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4887280000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4887280000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6648929500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6648929500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1745313500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1745313500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102495000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102495000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 491343000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 491343000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1414500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1414500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11536209500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 11536209500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13281523000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 13281523000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6641550500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6641550500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5414724500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5414724500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12056275000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12056275000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015979 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015979 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017993 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017993 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231273 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231273 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016818 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016818 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050589 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050589 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016848 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.016848 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019080 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.019080 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 732778 # number of writebacks
> system.cpu0.dcache.writebacks::total 732778 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25286 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 25286 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15664 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15664 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 25288 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 25288 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 25288 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 25288 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392727 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 392727 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337665 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 337665 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106338 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 106338 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6673 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6673 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19808 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 19808 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 730392 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 730392 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 836730 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 836730 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31820 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60319 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4843447000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4843447000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6588824500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6588824500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737105000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737105000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102846500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102846500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 482970000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482970000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1793500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432271500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 11432271500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13169376500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 13169376500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629050000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629050000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400878000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400878000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029928000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029928000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015798 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015798 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017930 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017930 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231335 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231335 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016833 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016833 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050600 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050600 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.016717 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018951 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.018951 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698 # average StoreCondReq mshr miss latency
776,785c781,790
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229 # average overall mshr uncacheable latency
787,791c792,796
< system.cpu0.icache.tags.replacements 1154605 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.321447 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 120695042 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1155117 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 104.487287 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 1147265 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.321425 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 120433653 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1147777 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 104.927746 # Average number of references to valid blocks.
793c798
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321447 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321425 # Average occupied blocks per requestor
797c802
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
799c804
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
801,838c806,843
< system.cpu0.icache.tags.tag_accesses 244855462 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 244855462 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 120695042 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 120695042 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 120695042 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 120695042 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 120695042 # number of overall hits
< system.cpu0.icache.overall_hits::total 120695042 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1155126 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1155126 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1155126 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1155126 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1155126 # number of overall misses
< system.cpu0.icache.overall_misses::total 1155126 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12352499000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 12352499000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 12352499000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 12352499000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 12352499000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 12352499000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 121850168 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 121850168 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 121850168 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 121850168 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 121850168 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 121850168 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009480 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009480 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009480 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10693.637750 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10693.637750 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 244310664 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 244310664 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 120433653 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 120433653 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 120433653 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 120433653 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 120433653 # number of overall hits
> system.cpu0.icache.overall_hits::total 120433653 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1147786 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1147786 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1147786 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1147786 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1147786 # number of overall misses
> system.cpu0.icache.overall_misses::total 1147786 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12247651500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 12247651500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 12247651500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 12247651500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 12247651500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 12247651500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 121581439 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 121581439 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 121581439 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 121581439 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 121581439 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 121581439 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009440 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.009440 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009440 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.009440 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009440 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.009440 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10670.675108 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10670.675108 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10670.675108 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10670.675108 # average overall miss latency
847,854c852,859
< system.cpu0.icache.writebacks::writebacks 1154605 # number of writebacks
< system.cpu0.icache.writebacks::total 1154605 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1155126 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1155126 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1155126 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1155126 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1155126 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1155126 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 1147265 # number of writebacks
> system.cpu0.icache.writebacks::total 1147265 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147786 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1147786 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147786 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1147786 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147786 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1147786 # number of overall MSHR misses
859,864c864,869
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11774936000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 11774936000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11774936000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 11774936000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11774936000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 11774936000 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11673758500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 11673758500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11673758500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 11673758500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11673758500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 11673758500 # number of overall MSHR miss cycles
869,880c874,885
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009480 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.009480 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.009480 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009440 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.009440 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.009440 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10170.675108 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency
886,888c891,893
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 1946486 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 1946511 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935691 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 1935756 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue
891,896c896,901
< system.cpu0.l2cache.prefetcher.pfSpanPage 246425 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 273842 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16083.519419 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 3089138 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 289977 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 10.653045 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 245684 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 272679 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16060.422672 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 3064880 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 288783 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 10.613090 # Average number of references to valid blocks.
898,903c903,908
< system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.644607 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.130850 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1489.168531 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.890721 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000039 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 14559.127845 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.514376 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.125186 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1500.655266 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.888619 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy
905,907c910,912
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090892 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.981660 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1031 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.091593 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.980250 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1021 # Occupied blocks per task id
909,914c914,920
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 282 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 325 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15080 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 262 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 312 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
916,921c922,927
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3285 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7655 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3857 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062927 # Percentage of cache occupancy per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7651 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3839 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062317 # Percentage of cache occupancy per task id
923,950c929,956
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 63340451 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 63340451 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11537 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4979 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 16516 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 507696 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 507696 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 1358751 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 1358751 # number of WritebackClean hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 241135 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 241135 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1108628 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 1108628 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 416937 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 416937 # number of ReadSharedReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11537 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4979 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1108628 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 658072 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1783216 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11537 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4979 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1108628 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 658072 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1783216 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 155 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses
---
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 62824015 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 62824015 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10929 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4820 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 15749 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 500939 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 500939 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 1350193 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 1350193 # number of WritebackClean hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238805 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 238805 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1101574 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 1101574 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411559 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 411559 # number of ReadSharedReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10929 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4820 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1101574 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 650364 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1767687 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10929 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4820 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1101574 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 650364 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1767687 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 174 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 78 # number of ReadReq misses
952,1030c958,1036
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55316 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 55316 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19844 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19844 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43803 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 43803 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46498 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 46498 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94557 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 94557 # number of ReadSharedReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 155 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 46498 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 138360 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 185110 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 155 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 46498 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 138360 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 185110 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4266000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2540500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 6806500 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 172322000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 172322000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43306000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43306000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1349997 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1349997 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2802544000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 2802544000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3338173500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3338173500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3246573500 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3246573500 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4266000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2540500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3338173500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 6049117500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 9394097500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4266000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2540500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3338173500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 6049117500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 9394097500 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11692 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5076 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 16768 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507696 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 507696 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 1358751 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 1358751 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55316 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 55316 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19844 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 19844 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 284938 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 284938 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1155126 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 1155126 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 511494 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 511494 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11692 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5076 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1155126 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 796432 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1968326 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11692 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5076 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1155126 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 796432 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1968326 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.019110 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55084 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 55084 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43776 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 43776 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46212 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 46212 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94179 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 94179 # number of ReadSharedReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 174 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 78 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 46212 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 137955 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 184419 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 174 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 78 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 46212 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 137955 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 184419 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4564500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2175000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 6739500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 163061000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 163061000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 40358000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 40358000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1721497 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1721497 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2789761000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 2789761000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3290416000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3290416000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3238432000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3238432000 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4564500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2175000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3290416000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 6028193000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 9325348500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4564500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2175000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3290416000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 6028193000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 9325348500 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11103 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4898 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 16001 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 500939 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 500939 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 1350193 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 1350193 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55084 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 55084 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282581 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 282581 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147786 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 1147786 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 505738 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 505738 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11103 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4898 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1147786 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 788319 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1952106 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11103 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4898 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1147786 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 788319 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1952106 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015925 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.015749 # miss rate for ReadReq accesses
1037,1078c1043,1084
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153728 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153728 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040254 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040254 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184864 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184864 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.019110 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040254 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.173725 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.094044 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.019110 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040254 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.173725 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.094044 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3115.228867 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3115.228867 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2182.322112 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2182.322112 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63980.640595 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394 # average ReadSharedReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 50748.730485 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154915 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154915 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040262 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040262 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186221 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186221 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015925 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040262 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.174999 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.094472 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015925 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040262 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.174999 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.094472 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27884.615385 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26744.047619 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2960.224385 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2960.224385 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2038.385777 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2038.385777 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 191277.444444 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 191277.444444 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63728.093019 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63728.093019 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71202.631351 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71202.631351 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34385.924675 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34385.924675 # average ReadSharedReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27884.615385 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71202.631351 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43696.806930 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 50566.094058 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27884.615385 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71202.631351 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43696.806930 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 50566.094058 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1080c1086
< system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1082c1088
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1086,1097c1092,1103
< system.cpu0.l2cache.writebacks::writebacks 232272 # number of writebacks
< system.cpu0.l2cache.writebacks::total 232272 # number of writebacks
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1851 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 1851 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 57 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 57 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1908 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 1908 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1908 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 1908 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 155 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 231522 # number of writebacks
> system.cpu0.l2cache.writebacks::total 231522 # number of writebacks
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1822 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 1822 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 60 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1882 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 1882 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1882 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 1882 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 174 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 78 # number of ReadReq MSHR misses
1099,1123c1105,1129
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 264558 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55316 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55316 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19844 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19844 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41952 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 41952 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46498 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46498 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94500 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94500 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 155 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46498 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136452 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 183202 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 155 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46498 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136452 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 447760 # number of overall MSHR misses
---
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264994 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 264994 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55084 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55084 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41954 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 41954 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46212 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46212 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94119 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94119 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 174 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 78 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46212 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136073 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 182537 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 174 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 78 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46212 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136073 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264994 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 447531 # number of overall MSHR misses
1125,1128c1131,1134
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40882 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40842 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
1130,1159c1136,1165
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69435 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1958500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5294500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20402670222 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1434169000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1434169000 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 342730000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 342730000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097997 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097997 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2366849000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2366849000 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3059185500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3059185500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2673492000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2673492000 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1958500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3059185500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5040341000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 8104821000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1958500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3059185500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5040341000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 28507491222 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69341 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1707000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5227500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20400229755 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20400229755 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1407285500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1407285500 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 334701500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 334701500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1439497 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1439497 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2354527500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2354527500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3013144000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3013144000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2666489000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2666489000 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1707000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3013144000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5021016500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 8039388000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1707000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3013144000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5021016500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20400229755 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 28439617755 # number of overall MSHR miss cycles
1161,1164c1167,1170
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6386259500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7572471000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5200454500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5200454500 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374077000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560288500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187014000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187014000 # number of WriteReq MSHR uncacheable cycles
1166,1170c1172,1176
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11586714000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12772925500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015029 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561091000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747302500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015749 # mshr miss rate for ReadReq accesses
1179,1193c1185,1199
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147232 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147232 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040254 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184753 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184753 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093075 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148467 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148467 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040262 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186102 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186102 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093508 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for overall accesses
1195,1223c1201,1229
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227483 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229255 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20744.047619 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76983.742104 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25547.990342 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25547.990342 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16904.969948 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16904.969948 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 159944.111111 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 159944.111111 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56121.645135 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56121.645135 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65202.631351 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28331.038366 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28331.038366 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44042.511929 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252 # average overall mshr miss latency
1225,1228c1231,1234
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434 # average WriteReq mshr uncacheable latency
1230,1231c1236,1237
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611 # average overall mshr uncacheable latency
1233,1270c1239,1276
< system.cpu0.toL2Bus.snoop_filter.tot_requests 3935499 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1983981 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 29039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 320941 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317478 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 63971 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1779248 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28553 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28553 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 740475 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 1358751 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 190136 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 311790 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 85728 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41989 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 112642 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 304006 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 300714 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1155126 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 580591 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3461069 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2699694 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12104 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27735 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 6200602 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146461624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 102248167 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20304 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46768 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 248776863 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 987005 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 2997932 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.122336 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.331180 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 3905249 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969182 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28911 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 320342 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316677 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3665 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 63843 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1765873 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 732965 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 1379104 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 189043 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 312150 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 85708 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41941 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 112560 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 301555 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 298207 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147786 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575214 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 3299 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460881 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2681738 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11926 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27058 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 6181603 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146919352 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101652834 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19592 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44412 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 248636190 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 986669 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 2981108 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.123159 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.332339 # Request fanout histogram
1272,1274c1278,1280
< system.cpu0.toL2Bus.snoop_fanout::0 2634639 87.88% 87.88% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 359830 12.00% 99.88% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 3463 0.12% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 2617624 87.81% 87.81% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 359819 12.07% 99.88% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 3665 0.12% 100.00% # Request fanout histogram
1278,1279c1284,1285
< system.cpu0.toL2Bus.snoop_fanout::total 2997932 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 3917122496 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 2981108 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 3885976496 # Layer occupancy (ticks)
1281c1287
< system.cpu0.toL2Bus.snoopLayer0.occupancy 115533329 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 115188451 # Layer occupancy (ticks)
1283c1289
< system.cpu0.toL2Bus.respLayer0.occupancy 1741711000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1730701000 # Layer occupancy (ticks)
1285c1291
< system.cpu0.toL2Bus.respLayer1.occupancy 1278424980 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1266054481 # Layer occupancy (ticks)
1289c1295
< system.cpu0.toL2Bus.respLayer3.occupancy 16050485 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 15961487 # Layer occupancy (ticks)
1320,1334c1326,1340
< system.cpu1.dtb.walker.walks 2352 # Table walker walks requested
< system.cpu1.dtb.walker.walksShort 2352 # Table walker walks initiated with short descriptors
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 487 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1865 # Level at which table walker walks with short descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 2352 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 2352 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 2352 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 1706 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 5645.878722 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-16383 1558 91.32% 91.32% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::16384-32767 139 8.15% 99.47% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walks 2346 # Table walker walks requested
> system.cpu1.dtb.walker.walksShort 2346 # Table walker walks initiated with short descriptors
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 473 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1873 # Level at which table walker walks with short descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 2346 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 2346 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 2346 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 1700 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 5957.546231 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-16383 1554 91.41% 91.41% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.94% 99.35% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.65% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.29% 99.94% # Table walker service (enqueue to completion) latency
1336c1342
< system.cpu1.dtb.walker.walkCompletionTime::total 1706 # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walkCompletionTime::total 1700 # Table walker service (enqueue to completion) latency
1340,1343c1346,1349
< system.cpu1.dtb.walker.walkPageSizes::4K 1219 71.45% 71.45% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::1M 487 28.55% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 1706 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2352 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkPageSizes::4K 1227 72.18% 72.18% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::1M 473 27.82% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 1700 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2346 # Table walker requests started/completed, data/inst
1345,1346c1351,1352
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2352 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1706 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2346 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1700 # Table walker requests started/completed, data/inst
1348,1349c1354,1355
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1706 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 4058 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1700 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 4046 # Table walker requests started/completed, data/inst
1352,1355c1358,1361
< system.cpu1.dtb.read_hits 3283088 # DTB read hits
< system.cpu1.dtb.read_misses 1969 # DTB read misses
< system.cpu1.dtb.write_hits 2849660 # DTB write hits
< system.cpu1.dtb.write_misses 383 # DTB write misses
---
> system.cpu1.dtb.read_hits 3334779 # DTB read hits
> system.cpu1.dtb.read_misses 1954 # DTB read misses
> system.cpu1.dtb.write_hits 2915242 # DTB write hits
> system.cpu1.dtb.write_misses 392 # DTB write misses
1360c1366
< system.cpu1.dtb.flush_entries 1653 # Number of entries that have been flushed from TLB
---
> system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB
1362c1368
< system.cpu1.dtb.prefetch_faults 218 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
1365,1366c1371,1372
< system.cpu1.dtb.read_accesses 3285057 # DTB read accesses
< system.cpu1.dtb.write_accesses 2850043 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 3336733 # DTB read accesses
> system.cpu1.dtb.write_accesses 2915634 # DTB write accesses
1368,1370c1374,1376
< system.cpu1.dtb.hits 6132748 # DTB hits
< system.cpu1.dtb.misses 2352 # DTB misses
< system.cpu1.dtb.accesses 6135100 # DTB accesses
---
> system.cpu1.dtb.hits 6250021 # DTB hits
> system.cpu1.dtb.misses 2346 # DTB misses
> system.cpu1.dtb.accesses 6252367 # DTB accesses
1408,1414c1414,1420
< system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 5216.232861 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::4096-8191 112 13.68% 13.68% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::8192-12287 592 72.28% 85.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::12288-16383 66 8.06% 94.02% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 94.87% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 5150.797327 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::8192-12287 577 70.45% 84.62% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::12288-16383 76 9.28% 93.89% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 94.87% # Table walker service (enqueue to completion) latency
1416,1419c1422,1425
< system.cpu1.itb.walker.walkCompletionTime::24576-28671 24 2.93% 98.05% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::28672-32767 5 0.61% 98.66% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.78% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.73% 99.51% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.80% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 98.78% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency
1421,1422c1427
< system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.24% 100.00% # Table walker service (enqueue to completion) latency
1437c1442
< system.cpu1.itb.inst_hits 13713445 # ITB inst hits
---
> system.cpu1.itb.inst_hits 13920333 # ITB inst hits
1454,1455c1459,1460
< system.cpu1.itb.inst_accesses 13714821 # ITB inst accesses
< system.cpu1.itb.hits 13713445 # DTB hits
---
> system.cpu1.itb.inst_accesses 13921709 # ITB inst accesses
> system.cpu1.itb.hits 13920333 # DTB hits
1457,1458c1462,1463
< system.cpu1.itb.accesses 13714821 # DTB accesses
< system.cpu1.numCycles 5742759797 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 13921709 # DTB accesses
> system.cpu1.numCycles 5742623362 # number of cpu cycles simulated
1462,1465c1467,1470
< system.cpu1.kern.inst.quiesce 2753 # number of quiesce instructions executed
< system.cpu1.committedInsts 13517417 # Number of instructions committed
< system.cpu1.committedOps 16437338 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 14911378 # Number of integer alu accesses
---
> system.cpu1.kern.inst.quiesce 2722 # number of quiesce instructions executed
> system.cpu1.committedInsts 13721353 # Number of instructions committed
> system.cpu1.committedOps 16716448 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 15155011 # Number of integer alu accesses
1467,1469c1472,1474
< system.cpu1.num_func_calls 901174 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 1468136 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 14911378 # number of integer instructions
---
> system.cpu1.num_func_calls 915079 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 1497955 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 15155011 # number of integer instructions
1471,1472c1476,1477
< system.cpu1.num_int_register_reads 27063131 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 10536793 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 27537464 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 10698089 # number of times the integer registers were written
1475,1484c1480,1489
< system.cpu1.num_cc_register_reads 60344215 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 5099594 # number of times the CC registers were written
< system.cpu1.num_mem_refs 6349896 # number of memory refs
< system.cpu1.num_load_insts 3389045 # Number of load instructions
< system.cpu1.num_store_insts 2960851 # Number of store instructions
< system.cpu1.num_idle_cycles 5696813538.222876 # Number of idle cycles
< system.cpu1.num_busy_cycles 45946258.777124 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.008001 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.991999 # Percentage of idle cycles
< system.cpu1.Branches 2418797 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 61338598 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 5194112 # number of times the CC registers were written
> system.cpu1.num_mem_refs 6464162 # number of memory refs
> system.cpu1.num_load_insts 3439477 # Number of load instructions
> system.cpu1.num_store_insts 3024685 # Number of store instructions
> system.cpu1.num_idle_cycles 5696031009.438875 # Number of idle cycles
> system.cpu1.num_busy_cycles 46592352.561125 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.008113 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.991887 # Percentage of idle cycles
> system.cpu1.Branches 2464329 # Number of branches fetched
1486,1516c1491,1521
< system.cpu1.op_class::IntAlu 10377527 61.94% 61.94% # Class of executed instruction
< system.cpu1.op_class::IntMult 24492 0.15% 62.08% # Class of executed instruction
< system.cpu1.op_class::IntDiv 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.08% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 3134 0.02% 62.10% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 62.10% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.10% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.10% # Class of executed instruction
< system.cpu1.op_class::MemRead 3389045 20.23% 82.33% # Class of executed instruction
< system.cpu1.op_class::MemWrite 2960851 17.67% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 10543721 61.89% 61.89% # Class of executed instruction
> system.cpu1.op_class::IntMult 24250 0.14% 62.04% # Class of executed instruction
> system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.05% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction
> system.cpu1.op_class::MemRead 3439477 20.19% 82.24% # Class of executed instruction
> system.cpu1.op_class::MemWrite 3024685 17.76% 100.00% # Class of executed instruction
1519,1529c1524,1534
< system.cpu1.op_class::total 16755073 # Class of executed instruction
< system.cpu1.dcache.tags.replacements 144073 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 473.219627 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 5912733 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 144418 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 40.941801 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 106295131000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.219627 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924257 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.924257 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id
---
> system.cpu1.op_class::total 17035345 # Class of executed instruction
> system.cpu1.dcache.tags.replacements 148314 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 469.091453 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 6019898 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 148666 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 40.492769 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 106291978000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.091453 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916194 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.916194 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id
1531,1612c1536,1617
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 26 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.673828 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 12441829 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 12441829 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 3018165 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3018165 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 2685196 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 2685196 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41245 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 41245 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69563 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 69563 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61182 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 61182 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 5703361 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 5703361 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 5744606 # number of overall hits
< system.cpu1.dcache.overall_hits::total 5744606 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 110713 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 110713 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 77621 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 77621 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23905 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 23905 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16417 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 16417 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23076 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23076 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 188334 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 188334 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 212239 # number of overall misses
< system.cpu1.dcache.overall_misses::total 212239 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1730591500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 1730591500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2713528000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2713528000 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316809000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 316809000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632764000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 632764000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3307000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3307000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4444119500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4444119500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4444119500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4444119500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3128878 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3128878 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 2762817 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 2762817 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65150 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 65150 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85980 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 85980 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84258 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 84258 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 5891695 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 5891695 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 5956845 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 5956845 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035384 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.035384 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028095 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.028095 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366922 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366922 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190940 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190940 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273873 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273873 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031966 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.031966 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035629 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.035629 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 12680697 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 12680697 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 3066133 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 3066133 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 2748576 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 2748576 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41842 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 41842 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69851 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 69851 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61610 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 61610 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 5814709 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 5814709 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 5856551 # number of overall hits
> system.cpu1.dcache.overall_hits::total 5856551 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 112800 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 112800 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 79377 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 79377 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24461 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 24461 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16636 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 16636 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23088 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23088 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 192177 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 192177 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 216638 # number of overall misses
> system.cpu1.dcache.overall_misses::total 216638 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1758096000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 1758096000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2710284000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 2710284000 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320294000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 320294000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 628163500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 628163500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3848000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3848000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4468380000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4468380000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4468380000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4468380000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178933 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 3178933 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 2827953 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 2827953 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66303 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 66303 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86487 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 86487 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84698 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 84698 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 6006886 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 6006886 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 6073189 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 6073189 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035484 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035484 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028069 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.028069 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368927 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368927 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192353 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192353 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272592 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272592 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031993 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.031993 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035671 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.035671 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801 # average StoreCondReq miss latency
1615,1618c1620,1623
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289 # average overall miss latency
1627,1702c1632,1707
< system.cpu1.dcache.writebacks::writebacks 144073 # number of writebacks
< system.cpu1.dcache.writebacks::total 144073 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11530 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11530 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 168 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 168 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 168 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110545 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 110545 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77621 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 77621 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23508 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 23508 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4887 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4887 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23076 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23076 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 188166 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 188166 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 211674 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 211674 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3107 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5537 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1611627000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1611627000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2635907000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2635907000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 421753500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 421753500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88480500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88480500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 609718000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 609718000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3277000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3277000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4247534000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 4247534000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4669287500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4669287500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 430617000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 430617000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 292641500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 292641500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 723258500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 723258500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035331 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035331 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028095 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028095 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360829 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360829 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056839 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056839 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273873 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273873 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031937 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.031937 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035535 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.035535 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 148314 # number of writebacks
> system.cpu1.dcache.writebacks::total 148314 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 199 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11732 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11732 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 199 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 199 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 199 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112601 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 112601 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79377 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 79377 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24003 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 24003 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4904 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4904 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23088 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23088 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 191978 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 191978 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 215981 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 215981 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3083 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5508 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1635811500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1635811500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2630907000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2630907000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 431572500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 431572500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89921000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89921000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 605110500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 605110500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3813000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3813000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4266718500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 4266718500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4698291000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4698291000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439541500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439541500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303268000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303268000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742809500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742809500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035421 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035421 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028069 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028069 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362020 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362020 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056702 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056702 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272592 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272592 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031960 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031960 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035563 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035563 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740 # average StoreCondReq mshr miss latency
1705,1714c1710,1719
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564 # average overall mshr uncacheable latency
1716,1724c1721,1729
< system.cpu1.icache.tags.replacements 461792 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.311266 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 13251136 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 462304 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 28.663252 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 106195905000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311266 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 463432 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.310833 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 13456384 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 463944 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 29.004328 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 106360036500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310833 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973263 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.973263 # Average percentage of cache occupancy
1730,1767c1735,1772
< system.cpu1.icache.tags.tag_accesses 27889184 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 27889184 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 13251136 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 13251136 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 13251136 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 13251136 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 13251136 # number of overall hits
< system.cpu1.icache.overall_hits::total 13251136 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 462304 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 462304 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 462304 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 462304 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 462304 # number of overall misses
< system.cpu1.icache.overall_misses::total 462304 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4149723500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4149723500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4149723500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4149723500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4149723500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4149723500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 13713440 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 13713440 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 13713440 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 13713440 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 13713440 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 13713440 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033712 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.033712 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033712 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.033712 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033712 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.033712 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8976.179094 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8976.179094 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8976.179094 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8976.179094 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 28304600 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 28304600 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 13456384 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 13456384 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 13456384 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 13456384 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 13456384 # number of overall hits
> system.cpu1.icache.overall_hits::total 13456384 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 463944 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 463944 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 463944 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 463944 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 463944 # number of overall misses
> system.cpu1.icache.overall_misses::total 463944 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214272500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4214272500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4214272500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4214272500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4214272500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4214272500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 13920328 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 13920328 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 13920328 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 13920328 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 13920328 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 13920328 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9083.580130 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 9083.580130 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 9083.580130 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 9083.580130 # average overall miss latency
1776,1783c1781,1788
< system.cpu1.icache.writebacks::writebacks 461792 # number of writebacks
< system.cpu1.icache.writebacks::total 461792 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 462304 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 462304 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 462304 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 462304 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 462304 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 462304 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 463432 # number of writebacks
> system.cpu1.icache.writebacks::total 463432 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463944 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 463944 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 463944 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 463944 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 463944 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 463944 # number of overall MSHR misses
1788,1793c1793,1798
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3918571500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3918571500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3918571500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3918571500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3918571500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3918571500 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982300500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982300500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982300500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3982300500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982300500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3982300500 # number of overall MSHR miss cycles
1798,1809c1803,1814
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033712 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.033712 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.033712 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8476.179094 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8583.580130 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency
1815,1817c1820,1822
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 106104 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 106112 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 118303 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 118321 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue
1820,1825c1825,1830
< system.cpu1.l2cache.prefetcher.pfSpanPage 50448 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 30131 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 14949.290291 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 1034569 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 45193 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 22.892240 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 50079 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 31154 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 14935.857031 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 1041086 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 46286 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 22.492460 # Average number of references to valid blocks.
1827,1841c1832,1846
< system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.312401 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.041451 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 430.459574 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.885893 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000141 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026273 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.912432 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 971 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14059 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 54 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 913 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 14446.292104 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.202140 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.081939 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 484.280848 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.881732 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000195 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029558 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.911612 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 38 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14113 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 47 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 926 # Occupied blocks per task id
1843,1952c1848,1962
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1365 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12304 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059265 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858093 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 20957142 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 20957142 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2443 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1453 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 3896 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 89055 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 89055 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 506752 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 506752 # number of WritebackClean hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16650 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 16650 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 453968 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 453968 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 75407 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 75407 # number of ReadSharedReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2443 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1453 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 453968 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 92057 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 549921 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2443 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1453 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 453968 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 92057 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 549921 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 301 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 650 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28928 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 28928 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23076 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 23076 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32043 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 32043 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8336 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 8336 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63533 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 63533 # number of ReadSharedReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 301 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 8336 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 95576 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 104562 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 301 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 8336 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 95576 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 104562 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7078500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6021500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 13100000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 62132500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 62132500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 59033500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 59033500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3231500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3231500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1646554500 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1646554500 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 475139500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 475139500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1418811000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1418811000 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7078500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6021500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 475139500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 3065365500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 3553605000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7078500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6021500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 475139500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 3065365500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 3553605000 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1754 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 4546 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 89055 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 89055 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 506752 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 506752 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28928 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 28928 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23076 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23076 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 48693 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 48693 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 462304 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 462304 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 138940 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 138940 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1754 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 462304 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 187633 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 654483 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1754 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 462304 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 187633 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 654483 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.171608 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.142983 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1668 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12049 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059875 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002319 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.861389 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 21151055 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 21151055 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2455 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1474 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 3929 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 92001 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 92001 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 509646 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 509646 # number of WritebackClean hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18183 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 18183 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455037 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 455037 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77628 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 77628 # number of ReadSharedReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2455 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1474 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 455037 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 95811 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 554777 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2455 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1474 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 455037 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 95811 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 554777 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 300 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 648 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28973 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 28973 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23087 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 23087 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32221 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 32221 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8907 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 8907 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63880 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 63880 # number of ReadSharedReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 300 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 8907 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 96101 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 105656 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 300 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 8907 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 96101 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 105656 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7097500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5968000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 13065500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64302000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 64302000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54899500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54899500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3760000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3760000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1640601500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1640601500 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 530446000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 530446000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1436061500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1436061500 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7097500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5968000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 530446000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 3076663000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 3620174500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7097500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5968000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 530446000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 3076663000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 3620174500 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2803 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1774 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 4577 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 92001 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 92001 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 509646 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 509646 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28973 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 28973 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23087 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23087 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50404 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 50404 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 463944 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 463944 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141508 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 141508 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2803 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1774 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 463944 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 191912 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 660433 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2803 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1774 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 463944 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 191912 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 660433 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.169109 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.141577 # miss rate for ReadReq accesses
1957,1998c1967,2010
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.658062 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.658062 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018031 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018031 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.457269 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.457269 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.171608 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018031 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509377 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.159763 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.171608 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018031 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509377 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.159763 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2147.832550 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2147.832550 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2558.220662 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2558.220662 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774 # average ReadSharedReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked
---
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.639255 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.639255 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019198 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019198 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.451423 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.451423 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.169109 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019198 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.500756 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.159980 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.169109 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019198 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.500756 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.159980 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19893.333333 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20162.808642 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2219.376661 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2219.376661 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2377.939966 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2377.939966 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3760000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3760000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50917.150306 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50917.150306 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59553.834063 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59553.834063 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22480.612085 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22480.612085 # average ReadSharedReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19893.333333 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59553.834063 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32014.890584 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 34263.785303 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19893.333333 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59553.834063 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32014.890584 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 34263.785303 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
2002c2014
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked
2006,2039c2018,2053
< system.cpu1.l2cache.writebacks::writebacks 25259 # number of writebacks
< system.cpu1.l2cache.writebacks::total 25259 # number of writebacks
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 80 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 80 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 80 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 80 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 349 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 301 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 650 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 18771 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28928 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28928 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23076 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23076 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31963 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 31963 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8336 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8336 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63533 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63533 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 349 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 301 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8336 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95496 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 104482 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 349 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 301 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8336 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95496 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 123253 # number of overall MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 25848 # number of writebacks
> system.cpu1.l2cache.writebacks::total 25848 # number of writebacks
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 72 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 72 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 72 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 72 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 348 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 300 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 648 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21105 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 21105 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28973 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28973 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23087 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23087 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32149 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 32149 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8907 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8907 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63880 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63880 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 348 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 300 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8907 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96029 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 105584 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 348 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 300 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8907 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96029 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21105 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 126689 # number of overall MSHR misses
2041,2044c2055,2058
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3284 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3260 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable
2046,2075c2060,2089
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5714 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4215500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9200000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 917123117 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 588451500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 588451500 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 436537000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 436537000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1446140000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1446140000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 425123500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 425123500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1037613000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1037613000 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4215500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 425123500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483753000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 2918076500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4215500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 425123500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483753000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 3835199617 # number of overall MSHR miss cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5685 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4168000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9177500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 934365172 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 934365172 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 576596500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 576596500 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 431875500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 431875500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3550000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3550000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1440609000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1440609000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 477004000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 477004000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1052781500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1052781500 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4168000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 477004000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2493390500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 2979572000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4168000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 477004000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493390500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 934365172 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 3913937172 # number of overall MSHR miss cycles
2077,2080c2091,2094
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 405408000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 427627000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 274409000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 274409000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414529000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436748000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 285072000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 285072000 # number of WriteReq MSHR uncacheable cycles
2082,2086c2096,2100
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 679817000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 702036000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.142983 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699601000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721820000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.141577 # mshr miss rate for ReadReq accesses
2093,2107c2107,2123
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.656419 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.656419 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018031 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457269 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457269 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159641 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637826 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637826 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019198 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451423 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451423 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159871 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for overall accesses
2109,2137c2125,2153
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.188321 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873 # average overall mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191827 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3550000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3550000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879 # average overall mshr miss latency
2139,2142c2155,2158
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403 # average WriteReq mshr uncacheable latency
---
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918 # average WriteReq mshr uncacheable latency
2144,2145c2160,2161
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238 # average overall mshr uncacheable latency
2147,2184c2163,2200
< system.cpu1.toL2Bus.snoop_filter.tot_requests 1312846 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 662941 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 166384 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164278 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 10119 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 648543 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2430 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2430 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 115438 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 506752 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 85166 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 22864 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 70245 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40855 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 84598 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 55915 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 53326 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 462304 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 211564 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 31 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1378500 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707096 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4372 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7009 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2096977 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58614596 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 23813135 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 82445915 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 350196 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 987919 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.185835 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.394416 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 1324645 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668824 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10099 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 169409 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166956 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2453 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 10097 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 652790 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2425 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2425 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 119017 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 519745 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 86537 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 25449 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 70337 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40896 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 84740 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 57665 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 55147 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463944 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215084 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391674 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722021 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4392 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7022 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2125109 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59352772 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24485096 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7096 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11212 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 83856176 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 356096 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 999531 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.187033 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.396182 # Request fanout histogram
2186,2188c2202,2204
< system.cpu1.toL2Bus.snoop_fanout::0 806435 81.63% 81.63% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 179378 18.16% 99.79% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 2106 0.21% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 815039 81.54% 81.54% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 182039 18.21% 99.75% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 2453 0.25% 100.00% # Request fanout histogram
2192,2193c2208,2209
< system.cpu1.toL2Bus.snoop_fanout::total 987919 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 1267256999 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 999531 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 1279051999 # Layer occupancy (ticks)
2195c2211
< system.cpu1.toL2Bus.snoopLayer0.occupancy 79126203 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 79434008 # Layer occupancy (ticks)
2197c2213
< system.cpu1.toL2Bus.respLayer0.occupancy 693633000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 696093000 # Layer occupancy (ticks)
2199c2215
< system.cpu1.toL2Bus.respLayer1.occupancy 311803500 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 318231000 # Layer occupancy (ticks)
2203c2219
< system.cpu1.toL2Bus.respLayer3.occupancy 4217000 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks)
2205,2206c2221,2222
< system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 31021 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31021 # Transaction distribution
2229,2231c2245,2247
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes)
2252,2255c2268,2271
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 48738000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 48746500 # Layer occupancy (ticks)
2259c2275
< system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
2267c2283
< system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks)
2277c2293
< system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2289c2305
< system.iobus.reqLayer23.occupancy 6150500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 6162500 # Layer occupancy (ticks)
2293c2309
< system.iobus.reqLayer25.occupancy 186301036 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187117449 # Layer occupancy (ticks)
2297c2313
< system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2299,2300c2315,2316
< system.iocache.tags.replacements 36433 # number of replacements
< system.iocache.tags.tagsinuse 1.018273 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36461 # number of replacements
> system.iocache.tags.tagsinuse 14.380044 # Cycle average of tags in use
2302c2318
< system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks.
2304,2307c2320,2323
< system.iocache.tags.warmup_cycle 290654223000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.018273 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.063642 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.063642 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 290746348000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.380044 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.898753 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.898753 # Average percentage of cache occupancy
2311,2314c2327,2330
< system.iocache.tags.tag_accesses 328203 # Number of tag accesses
< system.iocache.tags.data_accesses 328203 # Number of data accesses
< system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 328311 # Number of tag accesses
> system.iocache.tags.data_accesses 328311 # Number of data accesses
> system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2317,2330c2333,2346
< system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
< system.iocache.demand_misses::total 243 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 243 # number of overall misses
< system.iocache.overall_misses::total 243 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ide 31405376 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 31405376 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4738596660 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4738596660 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 31405376 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31405376 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31405376 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31405376 # number of overall miss cycles
< system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
> system.iocache.demand_misses::total 255 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 255 # number of overall misses
> system.iocache.overall_misses::total 255 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ide 32874877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 32874877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4582462572 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4582462572 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 32874877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 32874877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 32874877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 32874877 # number of overall miss cycles
> system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2333,2336c2349,2352
< system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
2345,2353c2361,2369
< system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 129240.230453 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 129240.230453 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 129240.230453 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 816 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 128921.086275 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 128921.086275 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 128921.086275 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked
2355c2371
< system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
2357c2373
< system.iocache.avg_blocked_cycles::no_mshrs 10.329114 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked
2361,2364c2377,2380
< system.iocache.writebacks::writebacks 36190 # number of writebacks
< system.iocache.writebacks::total 36190 # number of writebacks
< system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
---
> system.iocache.writebacks::writebacks 36206 # number of writebacks
> system.iocache.writebacks::total 36206 # number of writebacks
> system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2367,2378c2383,2394
< system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 19255376 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 19255376 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927396660 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2927396660 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 19255376 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 19255376 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 19255376 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 19255376 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 20124877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 20124877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2769551646 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2769551646 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 20124877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 20124877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 20124877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 20124877 # number of overall MSHR miss cycles
2387,2394c2403,2410
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency
2396,2400c2412,2416
< system.l2c.tags.replacements 123618 # number of replacements
< system.l2c.tags.tagsinuse 63093.840837 # Cycle average of tags in use
< system.l2c.tags.total_refs 421259 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 187589 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.245649 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 123661 # number of replacements
> system.l2c.tags.tagsinuse 63058.402721 # Cycle average of tags in use
> system.l2c.tags.total_refs 421257 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 187718 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.244095 # Average number of references to valid blocks.
2402,2417c2418,2433
< system.l2c.tags.occ_blocks::writebacks 13244.114990 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.878668 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.996497 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 7731.277102 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 2849.874177 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954483 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1120.568935 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 367.321258 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1502.766604 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.202089 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.117970 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.043486 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.553468 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 13491.325958 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.985555 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.052859 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 7361.006580 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 2805.566875 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35728.682862 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954518 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1443.499308 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 410.819619 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1814.508588 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.205861 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.112320 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.042810 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545176 # Average percentage of cache occupancy
2419,2446c2435,2461
< system.l2c.tags.occ_percent::cpu1.inst 0.017099 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.005605 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022930 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.962736 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 32107 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 31859 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 4716 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 27259 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 2381 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 29068 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.489914 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.486130 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 5836461 # Number of tag accesses
< system.l2c.tags.data_accesses 5836461 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 257531 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 257531 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 32441 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 1723 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 34164 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 2115 # number of SCUpgradeReq hits
---
> system.l2c.tags.occ_percent::cpu1.inst 0.022026 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.006269 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027687 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.962195 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 32044 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 32009 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5120 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 26618 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 2325 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 29253 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.488953 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.488419 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 5830329 # Number of tag accesses
> system.l2c.tags.data_accesses 5830329 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 257370 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 257370 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 32263 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 1924 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 34187 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 2044 # number of SCUpgradeReq hits
2448,2494c2463,2509
< system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4177 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 5519 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 92 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 28642 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 47295 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47544 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 6315 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 4707 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3005 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 137714 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 92 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 28642 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 51472 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 47544 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 15 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 6315 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 6049 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 3005 # number of demand (read+write) hits
< system.l2c.demand_hits::total 143233 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 92 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 28642 # number of overall hits
< system.l2c.overall_hits::cpu0.data 51472 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 47544 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 15 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 6315 # number of overall hits
< system.l2c.overall_hits::cpu1.data 6049 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 3005 # number of overall hits
< system.l2c.overall_hits::total 143233 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 9610 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 11910 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1322 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1977 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 11124 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 7851 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 18975 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses
---
> system.l2c.SCUpgradeReq_hits::total 2943 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4115 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 1385 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 5500 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 95 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 72 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 28709 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 46783 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47559 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 20 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 6543 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 5065 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3419 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 138278 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 95 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 72 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 28709 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 50898 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 47559 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 20 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 6543 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 6450 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 3419 # number of demand (read+write) hits
> system.l2c.demand_hits::total 143778 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 95 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 72 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 28709 # number of overall hits
> system.l2c.overall_hits::cpu0.data 50898 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 47559 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 20 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 6543 # number of overall hits
> system.l2c.overall_hits::cpu1.data 6450 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 3419 # number of overall hits
> system.l2c.overall_hits::total 143778 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 9386 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 2249 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 11635 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 587 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1308 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1895 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 11114 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 7777 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 18891 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 5 # number of ReadSharedReq misses
2496,2498c2511,2513
< system.l2c.ReadSharedReq_misses::cpu0.inst 17856 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 8887 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq misses
---
> system.l2c.ReadSharedReq_misses::cpu0.inst 17503 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 8876 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134571 # number of ReadSharedReq misses
2500,2504c2515,2519
< system.l2c.ReadSharedReq_misses::cpu1.inst 2021 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 752 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 169545 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses
---
> system.l2c.ReadSharedReq_misses::cpu1.inst 2364 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 804 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5455 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 169581 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
2506,2508c2521,2523
< system.l2c.demand_misses::cpu0.inst 17856 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 17503 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 19990 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) misses
2510,2514c2525,2529
< system.l2c.demand_misses::cpu1.inst 2021 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 8603 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) misses
< system.l2c.demand_misses::total 188520 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses
---
> system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 8581 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) misses
> system.l2c.demand_misses::total 188472 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses
2516,2518c2531,2533
< system.l2c.overall_misses::cpu0.inst 17856 # number of overall misses
< system.l2c.overall_misses::cpu0.data 20011 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 134682 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 17503 # number of overall misses
> system.l2c.overall_misses::cpu0.data 19990 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 134571 # number of overall misses
2520,2684c2535,2699
< system.l2c.overall_misses::cpu1.inst 2021 # number of overall misses
< system.l2c.overall_misses::cpu1.data 8603 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 5338 # number of overall misses
< system.l2c.overall_misses::total 188520 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 34729000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 5015500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 39744500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3979500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2518000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 6497500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 1612676500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 1029832500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 2642509000 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 823500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2350559500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 1210448500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 268405000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 104648000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 24352402389 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 823500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 2350559500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 2823125000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 268405000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1134480500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 26994911389 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 823500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 2350559500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 2823125000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 268405000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1134480500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 26994911389 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 257531 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 257531 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 42051 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 4023 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 46074 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 2770 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 2221 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 4991 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 9193 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 24494 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 87 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 46498 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 56182 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182226 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 8336 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 5459 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8343 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 307259 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 46498 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 71483 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182226 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 16 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 8336 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 14652 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8343 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 331753 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 46498 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 71483 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182226 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 16 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 8336 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 14652 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8343 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 331753 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228532 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.571713 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.258497 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.236462 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.595227 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.396113 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.727011 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.854019 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.774680 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021277 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.384017 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158182 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.242442 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.137754 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.551798 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.021277 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.384017 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.279941 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.242442 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.587155 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.568254 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.021277 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.384017 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.279941 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.242442 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.587155 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.568254 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3613.839750 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2180.652174 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 3337.069689 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6075.572519 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1904.689864 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 3286.545271 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144972.716649 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131172.143676 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 139262.661397 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137250 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131639.756944 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136204.399685 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132808.015834 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139159.574468 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 143633.857613 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 143193.886001 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 143193.886001 # average overall miss latency
---
> system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses
> system.l2c.overall_misses::cpu1.data 8581 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 5455 # number of overall misses
> system.l2c.overall_misses::total 188472 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 30248000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 5203000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 35451000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3836500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2726000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 6562500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 1620087000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 1017624500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 2637711500 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 677000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 362000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2302051000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 1209307000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19566804778 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 146500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 313582000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 113115000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 857081845 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 24363127123 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 677000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 362000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 2302051000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 2829394000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19566804778 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 146500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 313582000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 1130739500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 857081845 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 27000838623 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 677000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 362000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 2302051000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 2829394000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19566804778 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 146500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 313582000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 1130739500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 857081845 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 27000838623 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 257370 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 257370 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 41649 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 4173 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 45822 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 2631 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 2207 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 4838 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 15229 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 9162 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 24391 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 74 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 46212 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 55659 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182130 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 21 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 13 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 8907 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 5869 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8874 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 307859 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 74 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 46212 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 70888 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182130 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 21 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 13 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 8907 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 15031 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8874 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 332250 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 74 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 46212 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 70888 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182130 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 21 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 13 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 8907 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 15031 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8874 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 332250 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225360 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.538941 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.253917 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.223109 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592660 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.391691 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.729792 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.848832 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.774507 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027027 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.378754 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.159471 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.265409 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.136991 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.550840 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.027027 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.378754 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.281994 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.265409 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.570887 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.567260 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.027027 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.378754 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.281994 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.265409 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.570887 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.567260 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3222.672065 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2313.472655 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 3046.927374 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6535.775128 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2084.097859 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 3463.060686 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145769.929818 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130850.520766 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 139627.944524 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135400 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 181000 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131523.224590 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136244.592159 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 146500 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132648.900169 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140690.298507 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 143666.608423 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135400 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 181000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 131523.224590 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 141540.470235 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 146500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 132648.900169 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 131772.462417 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 143261.803467 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135400 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 181000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 131523.224590 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 141540.470235 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 146500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 132648.900169 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 131772.462417 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 143261.803467 # average overall miss latency
2693,2718c2708,2730
< system.l2c.writebacks::writebacks 97095 # number of writebacks
< system.l2c.writebacks::total 97095 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 17 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 2818 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 2818 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 9610 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 11910 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1322 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1977 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 11124 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 7851 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 18975 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses
---
> system.l2c.writebacks::writebacks 96987 # number of writebacks
> system.l2c.writebacks::total 96987 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 7 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 2809 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 2809 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 9386 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 2249 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 11635 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 587 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1308 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1895 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 11114 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 7777 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 18891 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 5 # number of ReadSharedReq MSHR misses
2720,2722c2732,2734
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17851 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8886 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17501 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8876 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of ReadSharedReq MSHR misses
2724,2728c2736,2740
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2010 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 752 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 169528 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2357 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 804 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 169572 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 5 # number of demand (read+write) MSHR misses
2730,2732c2742,2744
< system.l2c.demand_mshr_misses::cpu0.inst 17851 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 20010 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 17501 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 19990 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) MSHR misses
2734,2738c2746,2750
< system.l2c.demand_mshr_misses::cpu1.inst 2010 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 8603 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 188503 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.inst 2357 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 8581 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 188463 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 5 # number of overall MSHR misses
2740,2742c2752,2754
< system.l2c.overall_mshr_misses::cpu0.inst 17851 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 20010 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 17501 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 19990 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of overall MSHR misses
2744,2747c2756,2759
< system.l2c.overall_mshr_misses::cpu1.inst 2010 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 8603 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 188503 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu1.inst 2357 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 8581 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 188463 # number of overall MSHR misses
2749c2761
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
2751,2755c2763,2767
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3104 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 44163 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 30983 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3080 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 44099 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 30924 # number of WriteReq MSHR uncacheable
2757c2769
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses
2759,2799c2771,2811
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5534 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 75146 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 725072500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172861000 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 897933500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 50674000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101405500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 152079500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1501436500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 951322500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 2452759000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 763500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2171508000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1121559000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 247283000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 97128000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 22655529389 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 763500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 2171508000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 2622995500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 247283000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 1048450500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 25108288389 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 763500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 2171508000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 2622995500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 247283000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 1048450500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 25108288389 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 75023 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 682643500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 162589000 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 845232500 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 43754500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 96726500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 140481000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1508944512 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 939851506 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 2448796018 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 627000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 342000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2126838009 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1120542510 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 136500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 289400510 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 105072505 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 22666533824 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 627000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 342000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 2126838009 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 2629487022 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 136500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 289400510 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 1044924011 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 25115329842 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 627000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 342000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 2126838009 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 2629487022 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 136500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 289400510 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 1044924011 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 25115329842 # number of overall MSHR miss cycles
2801c2813
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5812758500 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801306000 # number of ReadReq MSHR uncacheable cycles
2803,2807c2815,2819
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 349483000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 7205089000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4715021500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 233050000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4948071500 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359044000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 7203197500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702516500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243805501 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4946322001 # number of WriteReq MSHR uncacheable cycles
2809c2821
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10527780000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503822500 # number of overall MSHR uncacheable cycles
2811,2812c2823,2824
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 582533000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 12153160500 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602849501 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 12149519501 # number of overall MSHR uncacheable cycles
2815,2892c2827,2904
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228532 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.571713 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.258497 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.236462 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.595227 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396113 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727011 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854019 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.774680 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158165 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.137754 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.551743 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.568203 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.568203 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225360 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.538941 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.253917 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.223109 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592660 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.391691 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729792 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.848832 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.774507 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159471 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136991 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.550811 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.567233 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.567233 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency
2894c2906
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349 # average ReadReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923 # average ReadReq mshr uncacheable latency
2896,2900c2908,2912
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945 # average WriteReq mshr uncacheable latency
2902c2914
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296 # average overall mshr uncacheable latency
2904,2905c2916,2917
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541 # average overall mshr uncacheable latency
2907,2915c2919,2927
< system.membus.trans_dist::ReadReq 44163 # Transaction distribution
< system.membus.trans_dist::ReadResp 213934 # Transaction distribution
< system.membus.trans_dist::WriteReq 30983 # Transaction distribution
< system.membus.trans_dist::WriteResp 30983 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 133285 # Transaction distribution
< system.membus.trans_dist::CleanEvict 14406 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 73490 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 39839 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 13966 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 44099 # Transaction distribution
> system.membus.trans_dist::ReadResp 213926 # Transaction distribution
> system.membus.trans_dist::WriteReq 30924 # Transaction distribution
> system.membus.trans_dist::WriteResp 30924 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 133193 # Transaction distribution
> system.membus.trans_dist::CleanEvict 14771 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 73670 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 39871 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2917,2919c2929,2931
< system.membus.trans_dist::ReadExReq 39499 # Transaction distribution
< system.membus.trans_dist::ReadExResp 18896 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 169771 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 39385 # Transaction distribution
> system.membus.trans_dist::ReadExResp 18791 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 169827 # Transaction distribution
2921d2932
< system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2924,2929c2935,2940
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14022 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664172 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 786162 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 895071 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13776 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650336 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 772080 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 845035 # Packet count per connected master and slave (bytes)
2932,2939c2943,2950
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28044 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18307596 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18498522 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20815642 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 120564 # Total snoops (count)
< system.membus.snoop_fanout::samples 581920 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27552 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18297804 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18488238 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 20806382 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 121083 # Total snoops (count)
> system.membus.snoop_fanout::samples 581994 # Request fanout histogram
2944c2955
< system.membus.snoop_fanout::1 581920 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 581994 100.00% 100.00% # Request fanout histogram
2949,2950c2960,2961
< system.membus.snoop_fanout::total 581920 # Request fanout histogram
< system.membus.reqLayer0.occupancy 88268000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 581994 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88286500 # Layer occupancy (ticks)
2954c2965
< system.membus.reqLayer2.occupancy 11611500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 11391000 # Layer occupancy (ticks)
2956c2967
< system.membus.reqLayer5.occupancy 967762037 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 968108262 # Layer occupancy (ticks)
2958c2969
< system.membus.respLayer2.occupancy 1134685490 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1106274782 # Layer occupancy (ticks)
2960c2971
< system.membus.respLayer3.occupancy 64105002 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1388877 # Layer occupancy (ticks)
3003,3022c3014,3033
< system.toL2Bus.snoop_filter.tot_requests 959770 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 518663 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 138023 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 20272 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 19432 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 44166 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 467162 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30983 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30983 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 390842 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 84262 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 107575 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 150428 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 50605 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 50605 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 423011 # Transaction distribution
---
> system.toL2Bus.snoop_filter.tot_requests 960339 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 518534 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 139328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 20435 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 19626 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 809 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 44102 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 468032 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30924 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30924 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 390589 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 105128 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 107757 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 42814 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 150571 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 50426 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 50426 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 423945 # Transaction distribution
3024,3033c3035,3044
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1226424 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 245800 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1472224 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34332563 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3643847 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 37976410 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 437847 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 895583 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.335708 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.474219 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240075 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253445 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1493520 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34222158 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3776032 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 37998190 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 438746 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 896439 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.337268 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.474682 # Request fanout histogram
3035,3037c3046,3048
< system.toL2Bus.snoop_fanout::0 595769 66.52% 66.52% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 298974 33.38% 99.91% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 840 0.09% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 594908 66.36% 66.36% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 300722 33.55% 99.91% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 809 0.09% 100.00% # Request fanout histogram
3041,3042c3052,3053
< system.toL2Bus.snoop_fanout::total 895583 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 863469481 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 896439 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 863728414 # Layer occupancy (ticks)
3044c3055
< system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks)
3046c3057
< system.toL2Bus.respLayer0.occupancy 647119226 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 645946273 # Layer occupancy (ticks)
3048c3059
< system.toL2Bus.respLayer1.occupancy 200312901 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 202615858 # Layer occupancy (ticks)