3,5c3,5
< sim_seconds 2.866923 # Number of seconds simulated
< sim_ticks 2866923142000 # Number of ticks simulated
< final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.866913 # Number of seconds simulated
> sim_ticks 2866913114000 # Number of ticks simulated
> final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 699616 # Simulator instruction rate (inst/s)
< host_op_rate 846245 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15203294122 # Simulator tick rate (ticks/s)
< host_mem_usage 599680 # Number of bytes of host memory used
< host_seconds 188.57 # Real time elapsed on the host
< sim_insts 131928295 # Number of instructions simulated
< sim_ops 159578500 # Number of ops (including micro ops) simulated
---
> host_inst_rate 786450 # Simulator instruction rate (inst/s)
> host_op_rate 951292 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 17090693254 # Simulator tick rate (ticks/s)
> host_mem_usage 609256 # Number of bytes of host memory used
> host_seconds 167.75 # Real time elapsed on the host
> sim_insts 131924636 # Number of instructions simulated
> sim_ops 159576421 # Number of ops (including micro ops) simulated
16d15
< system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
19,21c18,20
< system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory
24,32c23,31
< system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory
< system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
> system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory
35,36c34,35
< system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory
< system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
> system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory
39,41c38,40
< system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory
44,49c43,48
< system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory
52,53c51,52
< system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory
56,58c55,57
< system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s)
61,69c60,68
< system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s)
72,74c71,73
< system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s)
77,79c76,78
< system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s)
82,95c81,95
< system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 205337 # Number of read requests accepted
< system.physmem.writeReqs 140504 # Number of write requests accepted
< system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 205263 # Number of read requests accepted
> system.physmem.writeReqs 140582 # Number of write requests accepted
> system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue
97,129c97,129
< system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12897 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12279 # Per bank write bursts
< system.physmem.perBankRdBursts::2 13044 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12666 # Per bank write bursts
< system.physmem.perBankRdBursts::4 21207 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12512 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12819 # Per bank write bursts
< system.physmem.perBankRdBursts::7 13070 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12092 # Per bank write bursts
< system.physmem.perBankRdBursts::9 12100 # Per bank write bursts
< system.physmem.perBankRdBursts::10 12291 # Per bank write bursts
< system.physmem.perBankRdBursts::11 10982 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11837 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12135 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11741 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11403 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8736 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8619 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9216 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8724 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8630 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8715 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8820 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8946 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8394 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8545 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8627 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8114 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8397 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8288 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8182 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7606 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 12846 # Per bank write bursts
> system.physmem.perBankRdBursts::1 12299 # Per bank write bursts
> system.physmem.perBankRdBursts::2 13037 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12736 # Per bank write bursts
> system.physmem.perBankRdBursts::4 21227 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12513 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12853 # Per bank write bursts
> system.physmem.perBankRdBursts::7 12957 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12050 # Per bank write bursts
> system.physmem.perBankRdBursts::9 12106 # Per bank write bursts
> system.physmem.perBankRdBursts::10 12270 # Per bank write bursts
> system.physmem.perBankRdBursts::11 11010 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11804 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12158 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11709 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11437 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8735 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8638 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9213 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8824 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8594 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8713 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8840 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8875 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8399 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8546 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8611 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8118 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8409 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8327 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8185 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7610 # Per bank write bursts
132c132
< system.physmem.totGap 2866922767000 # Total gap between requests
---
> system.physmem.totGap 2866912757000 # Total gap between requests
139c139
< system.physmem.readPktSize::6 195567 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 195493 # Read request sizes (log2)
146,166c146,166
< system.physmem.writePktSize::6 136068 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 238 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 136146 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
194,237c194,237
< system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see
239,260c239,260
< system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes
263,287c263,287
< system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads
289,304c289,300
< system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads
< system.physmem.totQLat 6009454502 # Total ticks spent queuing
< system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads
> system.physmem.totQLat 5976562250 # Total ticks spent queuing
> system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst
306c302
< system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst
310c306
< system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s
315,316c311,312
< system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing
---
> system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing
318,324c314,320
< system.physmem.writeRowHits 85502 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes
< system.physmem.avgGap 8289713.39 # Average gap between requests
< system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states
< system.physmem.memoryStateTime::REF 95732780000 # Time in different power states
---
> system.physmem.writeRowHits 85700 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes
> system.physmem.avgGap 8289588.56 # Average gap between requests
> system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states
> system.physmem.memoryStateTime::REF 95732520000 # Time in different power states
326c322
< system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states
328,345c324,341
< system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.491656 # Core power per rank (mW)
< system.physmem.averagePower::1 669.352997 # Core power per rank (mW)
---
> system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.485397 # Core power per rank (mW)
> system.physmem.averagePower::1 669.364885 # Core power per rank (mW)
364,960d359
< system.membus.trans_dist::ReadReq 228669 # Transaction distribution
< system.membus.trans_dist::ReadResp 228668 # Transaction distribution
< system.membus.trans_dist::WriteReq 31179 # Transaction distribution
< system.membus.trans_dist::WriteResp 31179 # Transaction distribution
< system.membus.trans_dist::Writeback 99844 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
< system.membus.trans_dist::ReadExReq 28316 # Transaction distribution
< system.membus.trans_dist::ReadExResp 11444 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 128959 # Total snoops (count)
< system.membus.snoop_fanout::samples 475734 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 475734 # Request fanout histogram
< system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
< system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks)
< system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks)
< system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.l2c.tags.replacements 132855 # number of replacements
< system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use
< system.l2c.tags.total_refs 486769 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6123027 # Number of tag accesses
< system.l2c.tags.data_accesses 6123027 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits
< system.l2c.Writeback_hits::total 239796 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits
< system.l2c.demand_hits::total 274907 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits
< system.l2c.overall_hits::cpu0.data 33021 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits
< system.l2c.overall_hits::cpu1.data 12797 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits
< system.l2c.overall_hits::total 274907 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 769 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1415 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 184109 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 8503 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4264 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 881 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1309 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2190 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 6116 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 5504 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 11620 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 3114 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 13092 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 769 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 6919 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) misses
< system.l2c.demand_misses::total 195729 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 3114 # number of overall misses
< system.l2c.overall_misses::cpu0.data 13092 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 150483 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 769 # number of overall misses
< system.l2c.overall_misses::cpu1.data 6919 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 21339 # number of overall misses
< system.l2c.overall_misses::total 195729 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 706500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.inst 269607250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 570989749 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 266750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.itb.walker 88750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 69445999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 122855750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18430164853 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 8530144 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 9612086 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 18142230 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132453 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2244405 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 3376858 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 492352141 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 397195181 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 889547322 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 706500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 269607250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1063341890 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 266750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 88750 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 69445999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 520050931 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 19319712175 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 706500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 269607250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1063341890 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 266750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 88750 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 69445999 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 520050931 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 19319712175 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 146 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 134 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 13324 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 35839 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 317069 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 52 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 4966 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 11686 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69069 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 452332 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 239796 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 239796 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 18165 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5198 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 23363 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 1129 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1460 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2589 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 10274 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 8030 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 18304 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 146 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 134 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 13324 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 46113 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 317069 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 4966 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 19716 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69069 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 470636 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 146 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 134 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 13324 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 46113 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 317069 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.154853 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.121085 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.407022 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.468098 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.820316 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.546462 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.780337 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.896575 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.845886 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.595289 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.685430 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.634834 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.007463 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.233714 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.283911 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.154853 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.350933 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.415882 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86579.078356 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 81850.594753 # average ReadReq miss latency
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< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2254.241557 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1421.025300 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1285.417707 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1714.595111 # average SCUpgradeReq miss latency
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< system.l2c.blocked_cycles::no_mshrs 2 # number of cycles access was blocked
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< system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses
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< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency
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< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
< system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
< system.realview.ethernet.droppedPackets 0 # number of packets dropped
967,1108c366
< system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 304794 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram
< system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks)
< system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
< system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks)
< system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
< system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks)
< system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks)
< system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.iobus.trans_dist::ReadReq 31019 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31019 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59414 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
< system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
< system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
< system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
< system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
< system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
< system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
< system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
< system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
< system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
< system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
< system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
< system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
< system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks)
< system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks)
< system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks)
< system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
---
> system.cpu_clk_domain.clock 500 # Clock period in ticks
1132,1135c390,393
< system.cpu0.dtb.read_hits 24351510 # DTB read hits
< system.cpu0.dtb.read_misses 6410 # DTB read misses
< system.cpu0.dtb.write_hits 18124813 # DTB write hits
< system.cpu0.dtb.write_misses 1105 # DTB write misses
---
> system.cpu0.dtb.read_hits 24351477 # DTB read hits
> system.cpu0.dtb.read_misses 6408 # DTB read misses
> system.cpu0.dtb.write_hits 18124986 # DTB write hits
> system.cpu0.dtb.write_misses 1114 # DTB write misses
1140c398
< system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB
1142c400
< system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch
1145,1146c403,404
< system.cpu0.dtb.read_accesses 24357920 # DTB read accesses
< system.cpu0.dtb.write_accesses 18125918 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 24357885 # DTB read accesses
> system.cpu0.dtb.write_accesses 18126100 # DTB write accesses
1148,1150c406,408
< system.cpu0.dtb.hits 42476323 # DTB hits
< system.cpu0.dtb.misses 7515 # DTB misses
< system.cpu0.dtb.accesses 42483838 # DTB accesses
---
> system.cpu0.dtb.hits 42476463 # DTB hits
> system.cpu0.dtb.misses 7522 # DTB misses
> system.cpu0.dtb.accesses 42483985 # DTB accesses
1172,1173c430,431
< system.cpu0.itb.inst_hits 115065468 # ITB inst hits
< system.cpu0.itb.inst_misses 3349 # ITB inst misses
---
> system.cpu0.itb.inst_hits 115065570 # ITB inst hits
> system.cpu0.itb.inst_misses 3350 # ITB inst misses
1182c440
< system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
1189,1193c447,451
< system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses
< system.cpu0.itb.hits 115065468 # DTB hits
< system.cpu0.itb.misses 3349 # DTB misses
< system.cpu0.itb.accesses 115068817 # DTB accesses
< system.cpu0.numCycles 5733846284 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses
> system.cpu0.itb.hits 115065570 # DTB hits
> system.cpu0.itb.misses 3350 # DTB misses
> system.cpu0.itb.accesses 115068920 # DTB accesses
> system.cpu0.numCycles 5733826228 # number of cpu cycles simulated
1196,1198c454,456
< system.cpu0.committedInsts 111421342 # Number of instructions committed
< system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses
---
> system.cpu0.committedInsts 111421445 # Number of instructions committed
> system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses
1200,1202c458,460
< system.cpu0.num_func_calls 12527292 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 119417138 # number of integer instructions
---
> system.cpu0.num_func_calls 12527454 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 119418221 # number of integer instructions
1204,1205c462,463
< system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written
1208,1217c466,475
< system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written
< system.cpu0.num_mem_refs 43585643 # number of memory refs
< system.cpu0.num_load_insts 24597805 # Number of load instructions
< system.cpu0.num_store_insts 18987838 # Number of store instructions
< system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles
< system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles
< system.cpu0.Branches 28215087 # Number of branches fetched
---
> system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written
> system.cpu0.num_mem_refs 43585923 # number of memory refs
> system.cpu0.num_load_insts 24597873 # Number of load instructions
> system.cpu0.num_store_insts 18988050 # Number of store instructions
> system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles
> system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles
> system.cpu0.Branches 28215151 # Number of branches fetched
1219,1220c477,478
< system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction
< system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction
> system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction
1244c502
< system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction
---
> system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction
1248,1249c506,507
< system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction
< system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction
> system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction
1252c510
< system.cpu0.op_class::total 138425707 # Class of executed instruction
---
> system.cpu0.op_class::total 138426785 # Class of executed instruction
1254,1259c512,708
< system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed
< system.cpu0.icache.tags.replacements 1060721 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks.
---
> system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed
> system.cpu0.dcache.tags.replacements 658574 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits
> system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses
> system.cpu0.dcache.overall_misses::total 764106 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu0.dcache.fast_writes 0 # number of fast writes performed
> system.cpu0.dcache.cache_copies 0 # number of cache copies performed
> system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks
> system.cpu0.dcache.writebacks::total 483361 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu0.icache.tags.replacements 1061124 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks.
1261c710
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor
1265,1266c714,715
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
1269,1306c718,755
< system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits
< system.cpu0.icache.overall_hits::total 114004226 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses
< system.cpu0.icache.overall_misses::total 1061242 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits
> system.cpu0.icache.overall_hits::total 114003925 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses
> system.cpu0.icache.overall_misses::total 1061645 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency
1315,1326c764,775
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1061645 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407816003 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407816003 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407816003 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 7407816003 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407816003 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 7407816003 # number of overall MSHR miss cycles
1331,1342c780,791
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency
1348,1351c797,800
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue
1353,1355c802,804
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page
1357,1370c806,819
< system.cpu0.l2cache.tags.replacements 355628 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.tags.replacements 357554 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy
1372,1427c821,875
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 41 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 38013369 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 38013369 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7065 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3186 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1046032 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 372434 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 1428717 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 483361 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 483361 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10097 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 10097 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2054 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 2054 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212764 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 212764 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7065 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3186 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1046032 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 585198 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1641481 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7065 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3186 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1046032 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 585198 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1641481 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 284 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 213 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15613 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 83733 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 99843 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29803 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 29803 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19308 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19308 # number of SCUpgradeReq misses
1430,1475c878,923
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44911 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 44911 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 284 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 213 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 15613 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 128644 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 144754 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 284 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 213 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 15613 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 128644 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 144754 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6608000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4758500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598124482 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2271341908 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 2880832890 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522877259 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 522877259 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377985887 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377985887 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1224995 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1224995 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513514605 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 1513514605 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6608000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4758500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598124482 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 3784856513 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 4394347495 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6608000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4758500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598124482 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 3784856513 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 4394347495 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7349 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3399 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061645 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456167 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 1528560 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 483361 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 483361 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39900 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 39900 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21362 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 21362 # number of SCUpgradeReq accesses(hits+misses)
1478,1498c926,946
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257675 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 257675 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7349 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3399 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1061645 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 713842 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1786235 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7349 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3399 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1061645 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 713842 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1786235 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.062665 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014706 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183558 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.065318 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.746942 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.746942 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.903848 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.903848 # miss rate for SCUpgradeReq accesses
1501,1536c949,984
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174293 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174293 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.062665 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014706 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180214 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.081039 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.038645 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.062665 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014706 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180214 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.081039 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22340.375587 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38309.388458 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27126.006568 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28853.629098 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17544.450525 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19576.646312 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 153124.375000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 153124.375000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33700.309612 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33700.309612 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 30357.347604 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23267.605634 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22340.375587 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38309.388458 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 6544 # number of cycles access was blocked
1538c986
< system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 99 # number of cycles access was blocked
1540c988
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 66.101010 # average number of cycles each access was blocked
1544,1567c992,1015
< system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks
< system.cpu0.l2cache.writebacks::total 204753 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 205226 # number of writebacks
> system.cpu0.l2cache.writebacks::total 205226 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2290 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2728 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 5018 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2290 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3938 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6228 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2290 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3938 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6228 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 284 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 213 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13323 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 81005 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 94825 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 445317 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29803 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29803 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19308 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19308 # number of SCUpgradeReq MSHR misses
1570,1608c1018,1056
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489027550 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261183602 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261183602 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1027996 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1027996 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080146893 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080146893 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2974500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43701 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 43701 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 284 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 213 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13323 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124706 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 138526 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 284 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 213 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13323 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124706 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 445317 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 583843 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3267500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457593766 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1665461966 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2130941732 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17831693567 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489548028 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489548028 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261537598 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261537598 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 965995 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 965995 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080387358 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080387358 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3267500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457593766 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2745849324 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 3211329090 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4618500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3267500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457593766 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2745849324 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17831693567 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 21043022657 # number of overall MSHR miss cycles
1610,1613c1058,1061
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328411497 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975619997 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3986952006 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3986952006 # number of WriteReq MSHR uncacheable cycles
1615,1621c1063,1069
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315363503 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962572003 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177578 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062036 # mshr miss rate for ReadReq accesses
1624,1627c1072,1075
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.746942 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.746942 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.903848 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.903848 # mshr miss rate for SCUpgradeReq accesses
1630,1640c1078,1088
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077552 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses
1642,1668c1090,1116
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency
1678,1874c1126,1131
< system.cpu0.dcache.tags.replacements 659666 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits
< system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses
< system.cpu0.dcache.overall_misses::total 765091 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
< system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
< system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks
< system.cpu0.dcache.writebacks::total 484431 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
< system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution
1876,1879c1133,1136
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
---
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
1881,1896c1138,1153
< system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 985271 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram
---
> system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 988296 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram
1903,1904c1160,1161
< system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram
1908,1909c1165,1166
< system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks)
1911c1168
< system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks)
1913c1170
< system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks)
1915c1172
< system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks)
1917c1174
< system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks)
1919c1176
< system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks)
1944,1947c1201,1204
< system.cpu1.dtb.read_hits 4826536 # DTB read hits
< system.cpu1.dtb.read_misses 2746 # DTB read misses
< system.cpu1.dtb.write_hits 4130096 # DTB write hits
< system.cpu1.dtb.write_misses 525 # DTB write misses
---
> system.cpu1.dtb.read_hits 4826061 # DTB read hits
> system.cpu1.dtb.read_misses 2744 # DTB read misses
> system.cpu1.dtb.write_hits 4130169 # DTB write hits
> system.cpu1.dtb.write_misses 524 # DTB write misses
1954c1211
< system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch
1957,1958c1214,1215
< system.cpu1.dtb.read_accesses 4829282 # DTB read accesses
< system.cpu1.dtb.write_accesses 4130621 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 4828805 # DTB read accesses
> system.cpu1.dtb.write_accesses 4130693 # DTB write accesses
1960,1962c1217,1219
< system.cpu1.dtb.hits 8956632 # DTB hits
< system.cpu1.dtb.misses 3271 # DTB misses
< system.cpu1.dtb.accesses 8959903 # DTB accesses
---
> system.cpu1.dtb.hits 8956230 # DTB hits
> system.cpu1.dtb.misses 3268 # DTB misses
> system.cpu1.dtb.accesses 8959498 # DTB accesses
1984c1241
< system.cpu1.itb.inst_hits 20887785 # ITB inst hits
---
> system.cpu1.itb.inst_hits 20883965 # ITB inst hits
2001,2002c1258,1259
< system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses
< system.cpu1.itb.hits 20887785 # DTB hits
---
> system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses
> system.cpu1.itb.hits 20883965 # DTB hits
2004,2005c1261,1262
< system.cpu1.itb.accesses 20889532 # DTB accesses
< system.cpu1.numCycles 5732937622 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 20885712 # DTB accesses
> system.cpu1.numCycles 5732918807 # number of cpu cycles simulated
2008,2010c1265,1267
< system.cpu1.committedInsts 20506953 # Number of instructions committed
< system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses
---
> system.cpu1.committedInsts 20503191 # Number of instructions committed
> system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses
2012,2014c1269,1271
< system.cpu1.num_func_calls 1209546 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 22187475 # number of integer instructions
---
> system.cpu1.num_func_calls 1209330 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 22184707 # number of integer instructions
2016,2017c1273,1274
< system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written
2020,2029c1277,1286
< system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written
< system.cpu1.num_mem_refs 9246104 # number of memory refs
< system.cpu1.num_load_insts 4945808 # Number of load instructions
< system.cpu1.num_store_insts 4300296 # Number of store instructions
< system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles
< system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles
< system.cpu1.Branches 3892449 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written
> system.cpu1.num_mem_refs 9245671 # number of memory refs
> system.cpu1.num_load_insts 4945342 # Number of load instructions
> system.cpu1.num_store_insts 4300329 # Number of store instructions
> system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles
> system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles
> system.cpu1.Branches 3891928 # Number of branches fetched
2031,2032c1288,1289
< system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction
< system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction
> system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction
2056c1313
< system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction
---
> system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction
2060,2061c1317,1318
< system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction
< system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction
> system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction
2064c1321
< system.cpu1.op_class::total 25300005 # Class of executed instruction
---
> system.cpu1.op_class::total 25296825 # Class of executed instruction
2066,2073c1323,1522
< system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed
< system.cpu1.icache.tags.replacements 565422 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor
---
> system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed
> system.cpu1.dcache.tags.replacements 218952 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits
> system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses
> system.cpu1.dcache.overall_misses::total 293221 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu1.dcache.fast_writes 0 # number of fast writes performed
> system.cpu1.dcache.cache_copies 0 # number of cache copies performed
> system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks
> system.cpu1.dcache.writebacks::total 135060 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12325 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154894 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 154894 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103785 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 103785 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33053 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 33053 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5608 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5608 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23205 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23205 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 258679 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 258679 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 291732 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 291732 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1899677974 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1899677974 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2055753168 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2055753168 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496489496 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496489496 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84032750 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84032750 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490566779 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490566779 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1599500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1599500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3955431142 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3955431142 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4451920638 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4451920638 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961065499 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961065499 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382997 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382997 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794448496 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794448496 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033549 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033549 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025803 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025803 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.336038 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.336038 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053352 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225635 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225635 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033388 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.033388 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
> system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu1.icache.tags.replacements 565004 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor
2078,2079c1527,1528
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id
2081,2118c1530,1567
< system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits
< system.cpu1.icache.overall_hits::total 20321845 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses
< system.cpu1.icache.overall_misses::total 565935 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits
> system.cpu1.icache.overall_hits::total 20318443 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses
> system.cpu1.icache.overall_misses::total 565517 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency
2127,2138c1576,1587
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles
2143,2154c1592,1603
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency
2160,2163c1609,1612
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue
2165,2167c1614,1616
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page
2169,2193c1618,1642
< system.cpu1.l2cache.tags.replacements 85170 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.replacements 85089 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id
2195,2306c1644,1755
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 282 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 282 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 282 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 135060 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 135060 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1609 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1609 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 861 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 861 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39179 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 39179 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2996 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1704 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 559876 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 162423 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 726999 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2996 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1704 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 559876 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 162423 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 726999 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5641 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 70311 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 76567 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29399 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29399 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22337 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22337 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33598 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 33598 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 5641 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 103909 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 110165 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 5641 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 103909 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 110165 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6952000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5546000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192723218 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1546712890 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1751934108 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537154147 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 537154147 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436854563 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436854563 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1562500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1562500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1072389357 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1072389357 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6952000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5546000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192723218 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 2619102247 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 2824323465 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6952000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5546000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192723218 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 2619102247 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 2824323465 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3334 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565517 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193555 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 764387 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 135060 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 135060 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31008 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 31008 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23198 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23198 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72777 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 72777 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3334 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 565517 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 266332 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 837164 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3334 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 565517 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 266332 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 837164 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.139828 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009975 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363261 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.100168 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.948110 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.948110 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962885 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962885 # miss rate for SCUpgradeReq accesses
2309,2344c1758,1793
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.461657 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.461657 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.139828 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009975 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.390148 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.131593 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.139828 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009975 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.390148 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.131593 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 1642 # number of cycles access was blocked
2346c1795
< system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked
2348c1797
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.914286 # average number of cycles each access was blocked
2352,2416c1801,1865
< system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks
< system.cpu1.l2cache.writebacks::total 35043 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 282 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22356 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33253 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 33253 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 333 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 282 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4965 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103360 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 108940 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 282 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206735448 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3265998125 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430847649 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430847649 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306945673 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306945673 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1280500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1280500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 812696840 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 812696840 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3694250 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143766018 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1867420270 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 2019432288 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3694250 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles
---
> system.cpu1.l2cache.writebacks::writebacks 35198 # number of writebacks
> system.cpu1.l2cache.writebacks::total 35198 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 739 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 100 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 839 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 193 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 193 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 739 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 293 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 1032 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 739 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 293 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 1032 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 338 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4902 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70211 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 75728 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 119097 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29399 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29399 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22337 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22337 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33405 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 33405 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 338 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4902 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103616 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 109133 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 338 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4902 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103616 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 228230 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3607000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143902025 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1053014200 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1205109225 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3247389638 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430450689 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430450689 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306453691 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306453691 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1303500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1303500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820460623 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820460623 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3607000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143902025 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1873474823 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 2025569848 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3607000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143902025 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1873474823 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 5272959486 # number of overall MSHR miss cycles
2418,2421c1867,1870
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles
2423,2429c1872,1878
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses
2432,2435c1881,1884
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses
2438,2448c1887,1897
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses
2450,2476c1899,1925
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency
2486,2681c1935,1940
< system.cpu1.dcache.tags.replacements 218971 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits
< system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses
< system.cpu1.dcache.overall_misses::total 293049 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
< system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
< system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks
< system.cpu1.dcache.writebacks::total 134894 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
< system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution
2683,2685c1942,1944
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution
2688,2703c1947,1962
< system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 817024 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 818999 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram
2710,2711c1969,1970
< system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram
2715,2716c1974,1975
< system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks)
2718c1977
< system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks)
2720c1979
< system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks)
2722c1981
< system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks)
2724c1983
< system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks)
2726c1985
< system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks)
2728,2736c1987,2098
< system.iocache.tags.replacements 36427 # number of replacements
< system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use
< system.iocache.tags.total_refs 16 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy
---
> system.iobus.trans_dist::ReadReq 31019 # Transaction distribution
> system.iobus.trans_dist::ReadResp 31019 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59407 # Transaction distribution
> system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
> system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
> system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
> system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
> system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
> system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
> system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
> system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
> system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
> system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
> system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
> system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
> system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks)
> system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
> system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks)
> system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks)
> system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.iocache.tags.replacements 36443 # number of replacements
> system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use
> system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy
2740,2741c2102,2103
< system.iocache.tags.tag_accesses 328485 # Number of tag accesses
< system.iocache.tags.data_accesses 328485 # Number of data accesses
---
> system.iocache.tags.tag_accesses 328557 # Number of tag accesses
> system.iocache.tags.data_accesses 328557 # Number of data accesses
2746,2747c2108,2109
< system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses
---
> system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses
2752,2757c2114,2119
< system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles
2760,2761c2122,2123
< system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses)
2768,2769c2130,2131
< system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses
2774,2779c2136,2141
< system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency
2794,2801c2156,2163
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles
2808,2809c2170,2171
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency
2812,2815c2174,2177
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
2816a2179,2813
> system.l2c.tags.replacements 132935 # number of replacements
> system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use
> system.l2c.tags.total_refs 488817 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6143442 # Number of tag accesses
> system.l2c.tags.data_accesses 6143442 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits
> system.l2c.Writeback_hits::total 240423 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4104 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 2566 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 6670 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 146 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 155 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 10201 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 33543 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 168037 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 53 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 4112 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 47653 # number of demand (read+write) hits
> system.l2c.demand_hits::total 276883 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 146 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 155 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits
> system.l2c.overall_hits::cpu0.data 33543 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 53 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 4112 # number of overall hits
> system.l2c.overall_hits::cpu1.data 12939 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits
> system.l2c.overall_hits::total 276883 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.inst 3124 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 6991 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150306 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 786 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1400 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 8554 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 4191 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 6191 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 5553 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 11744 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 3124 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 13182 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 150306 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 786 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) misses
> system.l2c.demand_misses::total 195660 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 3124 # number of overall misses
> system.l2c.overall_misses::cpu0.data 13182 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 150306 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 786 # number of overall misses
> system.l2c.overall_misses::cpu1.data 6953 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 21296 # number of overall misses
> system.l2c.overall_misses::total 195660 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 598250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.inst 271876998 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 570375499 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 223500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 71055248 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 119227499 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 18387871837 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 9302615 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 9559091 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 18861706 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1287445 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2175907 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 3463352 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 491575637 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 403495431 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 895071068 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 598250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 271876998 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 1061951136 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 223500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 71055248 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 522722930 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 19282942905 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 598250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 271876998 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 1061951136 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15077807020 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 223500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 71055248 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 522722930 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 19282942905 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 154 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 156 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 13325 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 36430 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318343 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 56 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 4898 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 11773 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68949 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 454129 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 240423 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 240423 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 18187 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5191 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 23378 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 1140 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1430 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2570 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 10295 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 8119 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 18414 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 154 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 156 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 13325 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 46725 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318343 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 4898 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 19892 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68949 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 472543 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 154 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 156 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 13325 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 46725 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318343 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 4898 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 19892 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68949 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 472543 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006410 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.234447 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.191902 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.022222 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.160474 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.118916 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.404986 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.470336 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.807359 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.545171 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783333 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.904196 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.850584 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.601360 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.683951 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.637776 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.006410 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.234447 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.282119 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.022222 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.160474 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.349538 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.414058 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.006410 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.234447 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.282119 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.022222 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.160474 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.349538 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.414058 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 99979.728990 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1087.516367 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2280.861608 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1479.929855 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1441.707727 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1682.836040 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1584.333028 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 76215.179496 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 98553.321604 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 98553.321604 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 370 # number of cycles access was blocked
> system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
> system.l2c.blocked::no_targets 0 # number of cycles access was blocked
> system.l2c.avg_blocked_cycles::no_mshrs 46.250000 # average number of cycles each access was blocked
> system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.l2c.fast_writes 0 # number of fast writes performed
> system.l2c.cache_copies 0 # number of cache copies performed
> system.l2c.writebacks::writebacks 99922 # number of writebacks
> system.l2c.writebacks::total 99922 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.inst 3124 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 6991 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 786 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 1400 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 183915 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8554 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 4191 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 12745 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 893 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1293 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2186 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 6191 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 5553 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 11744 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 3124 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 13182 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 786 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 6953 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 195659 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 3124 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 13182 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 786 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 6953 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 195659 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 498750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233055498 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 483422499 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 187500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 61295748 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101745999 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 16105922337 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86281499 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42154679 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 128436178 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8967891 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12981791 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 21949682 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 414199861 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 333199069 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 747398930 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 233055498 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 897622360 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 187500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 61295748 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 434945068 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 16853321267 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 233055498 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 897622360 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 61295748 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 434945068 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 16853321267 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796922003 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814310000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6097036003 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540062000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712612000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4252674000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8336984003 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
> system.membus.trans_dist::ReadReq 228475 # Transaction distribution
> system.membus.trans_dist::ReadResp 228474 # Transaction distribution
> system.membus.trans_dist::WriteReq 31175 # Transaction distribution
> system.membus.trans_dist::WriteResp 31175 # Transaction distribution
> system.membus.trans_dist::Writeback 99922 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution
> system.membus.trans_dist::ReadExReq 28459 # Transaction distribution
> system.membus.trans_dist::ReadExResp 11563 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 129134 # Total snoops (count)
> system.membus.snoop_fanout::samples 475892 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 475892 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
> system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks)
> system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks)
> system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
> system.realview.ethernet.droppedPackets 0 # number of packets dropped
> system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 305031 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks)
> system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks)
> system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
> system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks)
> system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks)
> system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)