3,5c3,5
< sim_seconds 2.866929 # Number of seconds simulated
< sim_ticks 2866929256000 # Number of ticks simulated
< final_tick 2866929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.866923 # Number of seconds simulated
> sim_ticks 2866923142000 # Number of ticks simulated
> final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 703930 # Simulator instruction rate (inst/s)
< host_op_rate 851474 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15295798763 # Simulator tick rate (ticks/s)
< host_mem_usage 599572 # Number of bytes of host memory used
< host_seconds 187.43 # Real time elapsed on the host
< sim_insts 131939289 # Number of instructions simulated
< sim_ops 159593891 # Number of ops (including micro ops) simulated
---
> host_inst_rate 699616 # Simulator instruction rate (inst/s)
> host_op_rate 846245 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15203294122 # Simulator tick rate (ticks/s)
> host_mem_usage 599680 # Number of bytes of host memory used
> host_seconds 188.57 # Real time elapsed on the host
> sim_insts 131928295 # Number of instructions simulated
> sim_ops 159578500 # Number of ops (including micro ops) simulated
16,33d15
< system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s)
35c17
< system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
37,40c19,22
< system.physmem.bytes_read::cpu0.inst 234148 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 830144 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 9620672 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
43,46c25,28
< system.physmem.bytes_read::cpu1.data 440928 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365312 # Number of bytes read from this memory
< system.physmem.bytes_read::total 12542872 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 234148 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory
> system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory
48,49c30,31
< system.physmem.bytes_inst_read::total 284024 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6392960 # Number of bytes written to this memory
---
> system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory
53c35
< system.physmem.bytes_written::total 8729040 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory
55c37
< system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
57,60c39,42
< system.physmem.num_reads::cpu0.inst 12112 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 13497 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 150323 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
63,66c45,48
< system.physmem.num_reads::cpu1.data 6913 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 21333 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 205140 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 99890 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory
70c52
< system.physmem.num_writes::total 140550 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory
72c54
< system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s)
74,77c56,59
< system.physmem.bw_read::cpu0.inst 81672 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 289559 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 3355741 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s)
80,83c62,65
< system.physmem.bw_read::cpu1.data 153798 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 476228 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4375020 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 81672 # Instruction read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s)
85,87c67,69
< system.physmem.bw_inst_read::total 99069 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2229898 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::realview.ide 808648 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s)
90,93c72,75
< system.physmem.bw_write::total 3044735 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2229898 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 808983 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s)
95,98c77,80
< system.physmem.bw_total::cpu0.inst 81672 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 295734 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 3355741 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s)
101,124c83,106
< system.physmem.bw_total::cpu1.data 153812 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 476228 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7419755 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 205141 # Number of read requests accepted
< system.physmem.writeReqs 140550 # Number of write requests accepted
< system.physmem.readBursts 205141 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 140550 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 13114752 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 14272 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8743552 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12542936 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8729040 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 223 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3913 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 15151 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12845 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12298 # Per bank write bursts
< system.physmem.perBankRdBursts::2 13022 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12754 # Per bank write bursts
< system.physmem.perBankRdBursts::4 21257 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12515 # Per bank write bursts
< system.physmem.perBankRdBursts::6 12829 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12945 # Per bank write bursts
< system.physmem.perBankRdBursts::8 12057 # Per bank write bursts
---
> system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 205337 # Number of read requests accepted
> system.physmem.writeReqs 140504 # Number of write requests accepted
> system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 12555480 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8726096 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 262 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 15133 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 12897 # Per bank write bursts
> system.physmem.perBankRdBursts::1 12279 # Per bank write bursts
> system.physmem.perBankRdBursts::2 13044 # Per bank write bursts
> system.physmem.perBankRdBursts::3 12666 # Per bank write bursts
> system.physmem.perBankRdBursts::4 21207 # Per bank write bursts
> system.physmem.perBankRdBursts::5 12512 # Per bank write bursts
> system.physmem.perBankRdBursts::6 12819 # Per bank write bursts
> system.physmem.perBankRdBursts::7 13070 # Per bank write bursts
> system.physmem.perBankRdBursts::8 12092 # Per bank write bursts
126,147c108,129
< system.physmem.perBankRdBursts::10 12212 # Per bank write bursts
< system.physmem.perBankRdBursts::11 11004 # Per bank write bursts
< system.physmem.perBankRdBursts::12 11810 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12145 # Per bank write bursts
< system.physmem.perBankRdBursts::14 11734 # Per bank write bursts
< system.physmem.perBankRdBursts::15 11391 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8757 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8655 # Per bank write bursts
< system.physmem.perBankWrBursts::2 9184 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8823 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8606 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8736 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8840 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8881 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8404 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8549 # Per bank write bursts
< system.physmem.perBankWrBursts::10 8595 # Per bank write bursts
< system.physmem.perBankWrBursts::11 8133 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8369 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8306 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8199 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7581 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 12291 # Per bank write bursts
> system.physmem.perBankRdBursts::11 10982 # Per bank write bursts
> system.physmem.perBankRdBursts::12 11837 # Per bank write bursts
> system.physmem.perBankRdBursts::13 12135 # Per bank write bursts
> system.physmem.perBankRdBursts::14 11741 # Per bank write bursts
> system.physmem.perBankRdBursts::15 11403 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8736 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8619 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9216 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8724 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8630 # Per bank write bursts
> system.physmem.perBankWrBursts::5 8715 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8820 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8946 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8394 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8545 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8627 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8114 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8397 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8288 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8182 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7606 # Per bank write bursts
149,150c131,132
< system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
< system.physmem.totGap 2866928814500 # Total gap between requests
---
> system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
> system.physmem.totGap 2866922767000 # Total gap between requests
157c139
< system.physmem.readPktSize::6 195371 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 195567 # Read request sizes (log2)
164,174c146,156
< system.physmem.writePktSize::6 136114 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 121124 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 21708 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 13339 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 11204 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 9572 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 8231 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 7040 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 6218 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 5357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 501 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 136068 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 121119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 21791 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 13355 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 11180 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 9558 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 8252 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 7029 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 6254 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 5390 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see
176c158
< system.physmem.rdQLenPdf::11 142 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see
178,182c160,164
< system.physmem.rdQLenPdf::13 64 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 26 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::13 60 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
212,319c194,304
< system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5630 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6226 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7608 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8446 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 10203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9843 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9504 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9714 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7664 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7594 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 309 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 77 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 41 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 80974 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 269.941463 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 151.852686 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 318.869933 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 39277 48.51% 48.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16073 19.85% 68.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6267 7.74% 76.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3406 4.21% 80.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3201 3.95% 84.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1947 2.40% 86.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1140 1.41% 88.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1004 1.24% 89.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 8659 10.69% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 80974 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6724 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 30.475461 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 574.843547 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6723 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6724 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6724 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.317965 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.827449 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.656598 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5486 81.59% 81.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 426 6.34% 87.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 82 1.22% 89.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 201 2.99% 92.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 197 2.93% 95.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 21 0.31% 95.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 19 0.28% 95.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 16 0.24% 95.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 29 0.43% 96.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 5 0.07% 96.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 3 0.04% 96.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 175 2.60% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 8 0.12% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 7 0.10% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 4 0.06% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 7 0.10% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 2 0.03% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 6 0.09% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.01% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 4 0.06% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 3 0.04% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads
< system.physmem.totQLat 5972474500 # Total ticks spent queuing
< system.physmem.totMemAccLat 9814687000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 1024590000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 29145.68 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 2709 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3297 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6265 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7124 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7555 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 9035 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 10130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9746 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9513 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9237 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 9611 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7855 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7679 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 237 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 81121 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 269.529616 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 151.748883 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 318.565122 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 39339 48.49% 48.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16179 19.94% 68.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6333 7.81% 76.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3376 4.16% 80.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3166 3.90% 84.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1954 2.41% 86.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1081 1.33% 88.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1008 1.24% 89.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8685 10.71% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 81121 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6712 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 544.132444 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6710 99.97% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6712 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5518 82.21% 82.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 23 0.34% 95.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 12 0.18% 95.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads
> system.physmem.totQLat 6009454502 # Total ticks spent queuing
> system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst
321,322c306,307
< system.physmem.avgMemAccLat 47895.68 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 4.57 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s
330,339c315,324
< system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing
< system.physmem.readRowHits 175001 # Number of row buffer hits during reads
< system.physmem.writeRowHits 85560 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 85.40 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 62.62 # Row buffer hit rate for writes
< system.physmem.avgGap 8293327.90 # Average gap between requests
< system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2731384342500 # Time in different power states
< system.physmem.memoryStateTime::REF 95733040000 # Time in different power states
---
> system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing
> system.physmem.readRowHits 175010 # Number of row buffer hits during reads
> system.physmem.writeRowHits 85502 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes
> system.physmem.avgGap 8289713.39 # Average gap between requests
> system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states
> system.physmem.memoryStateTime::REF 95732780000 # Time in different power states
341c326
< system.physmem.memoryStateTime::ACT 39811853000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states
343,365c328,368
< system.physmem.actEnergy::0 323167320 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 288996120 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 176331375 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 157686375 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 861627000 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 736725600 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 456723360 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 428561280 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 187253826240 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 187253826240 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 82374692850 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 81185757210 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1647898682250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1648941608250 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1919345050395 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1918993161075 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.477790 # Core power per rank (mW)
< system.physmem.averagePower::1 669.355049 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 228441 # Transaction distribution
< system.membus.trans_dist::ReadResp 228440 # Transaction distribution
< system.membus.trans_dist::WriteReq 31177 # Transaction distribution
< system.membus.trans_dist::WriteResp 31177 # Transaction distribution
< system.membus.trans_dist::Writeback 99890 # Transaction distribution
---
> system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.491656 # Core power per rank (mW)
> system.physmem.averagePower::1 669.352997 # Core power per rank (mW)
> system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 228669 # Transaction distribution
> system.membus.trans_dist::ReadResp 228668 # Transaction distribution
> system.membus.trans_dist::WriteReq 31179 # Transaction distribution
> system.membus.trans_dist::WriteResp 31179 # Transaction distribution
> system.membus.trans_dist::Writeback 99844 # Transaction distribution
368,373c371,376
< system.membus.trans_dist::UpgradeReq 85859 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 41212 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 15151 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
< system.membus.trans_dist::ReadExReq 28398 # Transaction distribution
< system.membus.trans_dist::ReadExResp 11478 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
> system.membus.trans_dist::ReadExReq 28316 # Transaction distribution
> system.membus.trans_dist::ReadExResp 11444 # Transaction distribution
375,378c378,381
< system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14560 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678158 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 800720 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes)
381c384
< system.membus.pkt_count::total 873436 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes)
383,386c386,389
< system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18952616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 19144659 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes)
389,391c392,394
< system.membus.pkt_size::total 21463955 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 129081 # Total snoops (count)
< system.membus.snoop_fanout::samples 475718 # Request fanout histogram
---
> system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 128959 # Total snoops (count)
> system.membus.snoop_fanout::samples 475734 # Request fanout histogram
396c399
< system.membus.snoop_fanout::1 475718 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram
401,402c404,405
< system.membus.snoop_fanout::total 475718 # Request fanout histogram
< system.membus.reqLayer0.occupancy 88161999 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 475734 # Request fanout histogram
> system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks)
404c407
< system.membus.reqLayer1.occupancy 20500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
406c409
< system.membus.reqLayer2.occupancy 12079498 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks)
408c411
< system.membus.reqLayer5.occupancy 1514580499 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks)
410c413
< system.membus.respLayer2.occupancy 1969894164 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks)
412c415
< system.membus.respLayer3.occupancy 38592409 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks)
415,419c418,422
< system.l2c.tags.replacements 132728 # number of replacements
< system.l2c.tags.tagsinuse 64199.829322 # Cycle average of tags in use
< system.l2c.tags.total_refs 489645 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 197292 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 2.481829 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 132855 # number of replacements
> system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use
> system.l2c.tags.total_refs 486769 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks.
421,432c424,435
< system.l2c.tags.occ_blocks::writebacks 12574.713731 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.829645 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043526 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 1158.059566 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 1408.624866 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.540569 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007801 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 536.338892 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 908.008157 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8820.200180 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.191875 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy
434,438c437,441
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.017671 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.021494 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.591834 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000039 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy
440,452c443,454
< system.l2c.tags.occ_percent::cpu1.inst 0.008184 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.013855 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134586 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.979612 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 44718 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 19841 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 5098 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 39452 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
454,505c456,507
< system.l2c.tags.age_task_id_blocks_1024::3 1574 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 18054 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.682343 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.302750 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 6148253 # Number of tag accesses
< system.l2c.tags.data_accesses 6148253 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 127 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 159 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 10419 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 29225 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168428 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 62 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 4147 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 10318 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47800 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 270735 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 240561 # number of Writeback hits
< system.l2c.Writeback_hits::total 240561 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 9666 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 1017 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 10683 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 240 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 136 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 4189 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 2493 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 6682 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 127 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 159 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 10419 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 33414 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 168428 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 62 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 4147 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 12811 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 47800 # number of demand (read+write) hits
< system.l2c.demand_hits::total 277417 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 127 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 159 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 10419 # number of overall hits
< system.l2c.overall_hits::cpu0.data 33414 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 168428 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 62 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 4147 # number of overall hits
< system.l2c.overall_hits::cpu1.data 12811 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 47800 # number of overall hits
< system.l2c.overall_hits::total 277417 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses
---
> system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 6123027 # Number of tag accesses
> system.l2c.tags.data_accesses 6123027 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits
> system.l2c.Writeback_hits::total 239796 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits
> system.l2c.demand_hits::total 274907 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits
> system.l2c.overall_hits::cpu0.data 33021 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 166586 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 46 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 4197 # number of overall hits
> system.l2c.overall_hits::cpu1.data 12797 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 47730 # number of overall hits
> system.l2c.overall_hits::total 274907 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
507,510c509,512
< system.l2c.ReadReq_misses::cpu0.inst 3095 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 6926 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.inst 3114 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 6976 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
513,525c515,527
< system.l2c.ReadReq_misses::cpu1.data 1418 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 183878 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 8558 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 4221 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 12779 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1310 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 2199 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 6118 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 5533 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 11651 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu1.data 1415 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 184109 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 8503 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 4264 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 881 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1309 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2190 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 6116 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 5504 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 11620 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
527,530c529,532
< system.l2c.demand_misses::cpu0.inst 3095 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 13044 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 3114 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 13092 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
533,536c535,538
< system.l2c.demand_misses::cpu1.data 6951 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) misses
< system.l2c.demand_misses::total 195529 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
---
> system.l2c.demand_misses::cpu1.data 6919 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) misses
> system.l2c.demand_misses::total 195729 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
538,541c540,543
< system.l2c.overall_misses::cpu0.inst 3095 # number of overall misses
< system.l2c.overall_misses::cpu0.data 13044 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 150324 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 3114 # number of overall misses
> system.l2c.overall_misses::cpu0.data 13092 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 150483 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
544,547c546,549
< system.l2c.overall_misses::cpu1.data 6951 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 21333 # number of overall misses
< system.l2c.overall_misses::total 195529 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 510000 # number of ReadReq miss cycles
---
> system.l2c.overall_misses::cpu1.data 6919 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 21339 # number of overall misses
> system.l2c.overall_misses::total 195729 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 706500 # number of ReadReq miss cycles
549,567c551,569
< system.l2c.ReadReq_miss_latency::cpu0.inst 268587999 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 563686749 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 328000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.itb.walker 94250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 70493000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 122227750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18379241574 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 8946128 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 10070574 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 19016702 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1175950 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2179907 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 3355857 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 485246640 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 404862686 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 890109326 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 510000 # number of demand (read+write) miss cycles
---
> system.l2c.ReadReq_miss_latency::cpu0.inst 269607250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 570989749 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 266750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.itb.walker 88750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 69445999 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 122855750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 18430164853 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 8530144 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 9612086 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 18142230 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1132453 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2244405 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 3376858 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 492352141 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 397195181 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 889547322 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 706500 # number of demand (read+write) miss cycles
569,578c571,580
< system.l2c.demand_miss_latency::cpu0.inst 268587999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 1048933389 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 328000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 94250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 70493000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 527090436 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 19269350900 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 510000 # number of overall miss cycles
---
> system.l2c.demand_miss_latency::cpu0.inst 269607250 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 1063341890 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 266750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 88750 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 69445999 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 520050931 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 19319712175 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 706500 # number of overall miss cycles
580,604c582,606
< system.l2c.overall_miss_latency::cpu0.inst 268587999 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 1048933389 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15024629496 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 328000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 94250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 70493000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 527090436 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2328609330 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 19269350900 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 134 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 160 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 13514 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 36151 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318752 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 66 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 4916 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 11736 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69133 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 454613 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 240561 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 240561 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 18224 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 5238 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 23462 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.overall_miss_latency::cpu0.inst 269607250 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 1063341890 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15102363766 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 266750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 88750 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 69445999 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 520050931 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2293765339 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 19319712175 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 146 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 134 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 13324 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 35839 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 317069 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 52 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 4966 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 11686 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 69069 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 452332 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 239796 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 239796 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 18165 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 5198 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 23363 # number of UpgradeReq accesses(hits+misses)
606,675c608,677
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1446 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2575 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 10307 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 8026 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 18333 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 134 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 160 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 13514 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 46458 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318752 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 66 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 4916 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 19762 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69133 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 472946 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 134 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 160 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 13514 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 46458 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318752 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 66 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 4916 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 19762 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69133 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 472946 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006250 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.229022 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.191585 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.156428 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.120825 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.404471 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.469601 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805842 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.544668 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787422 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.905947 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.853981 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.593577 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.689385 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.635521 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.006250 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.229022 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.280770 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.156428 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.351736 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.413428 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.052239 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.006250 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.229022 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.280770 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.471602 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.060606 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.156428 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.351736 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308579 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.413428 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average ReadReq miss latency
---
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1460 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2589 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 10274 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 8030 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 18304 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 146 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 134 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 13324 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 46113 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 317069 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 4966 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 19716 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 69069 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 470636 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 146 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 134 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 13324 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 46113 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 317069 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 4966 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 19716 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 69069 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 470636 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007463 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.233714 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.194648 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021277 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.154853 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.121085 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.407022 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.468098 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.820316 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.546462 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.780337 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.896575 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.845886 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.595289 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.685430 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.634834 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.007463 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.233714 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.283911 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.021277 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.154853 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.350933 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.415882 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.054795 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.007463 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.233714 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.283911 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.474606 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.057692 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.021277 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.154853 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.350933 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308952 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.415882 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average ReadReq miss latency
677,695c679,697
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86781.259774 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 81387.055876 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 94250 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91668.400520 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 86197.284908 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 99953.455954 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1045.352652 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2385.826581 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 1488.121293 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1322.778403 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1664.051145 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1526.083220 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79314.586466 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73172.363275 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 76397.676251 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency
---
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86579.078356 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 81850.594753 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88750 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90306.890767 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 86823.851590 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 100104.638301 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1003.192285 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2254.241557 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 1421.025300 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1285.417707 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1714.595111 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1541.944292 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80502.312132 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72164.822129 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 76553.125818 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency
697,706c699,708
< system.l2c.demand_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 98549.836086 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 72857.142857 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 98706.436834 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88312.500000 # average overall miss latency
708,717c710,719
< system.l2c.overall_avg_miss_latency::cpu0.inst 86781.259774 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 80415.009890 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94250 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 91668.400520 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 75829.439793 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 98549.836086 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.overall_avg_miss_latency::cpu0.inst 86579.078356 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 81220.737091 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100359.268263 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88916.666667 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88750 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 90306.890767 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 75162.730308 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 107491.697783 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 98706.436834 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 2 # number of cycles access was blocked
719c721
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked
721c723
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked
725,727c727,735
< system.l2c.writebacks::writebacks 99890 # number of writebacks
< system.l2c.writebacks::total 99890 # number of writebacks
< system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses
---
> system.l2c.writebacks::writebacks 99844 # number of writebacks
> system.l2c.writebacks::total 99844 # number of writebacks
> system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
> system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
> system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses
729,732c737,740
< system.l2c.ReadReq_mshr_misses::cpu0.inst 3095 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 6926 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 3114 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 6976 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses
735,747c743,755
< system.l2c.ReadReq_mshr_misses::cpu1.data 1418 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 183878 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 8558 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 4221 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 12779 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1310 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 2199 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 6118 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 5533 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 11651 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu1.data 1414 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 184108 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 8503 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 4264 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 12767 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 881 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1309 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2190 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 6116 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 5504 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 11620 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses
749,752c757,760
< system.l2c.demand_mshr_misses::cpu0.inst 3095 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 13044 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
---
> system.l2c.demand_mshr_misses::cpu0.inst 3114 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 13092 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses
755,758c763,766
< system.l2c.demand_mshr_misses::cpu1.data 6951 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 195529 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.data 6918 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 195728 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses
760,763c768,771
< system.l2c.overall_mshr_misses::cpu0.inst 3095 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 13044 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150324 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
---
> system.l2c.overall_mshr_misses::cpu0.inst 3114 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 13092 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150483 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses
766,769c774,777
< system.l2c.overall_mshr_misses::cpu1.data 6951 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21333 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 195529 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 423500 # number of ReadReq MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu1.data 6918 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21339 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 195728 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 607500 # number of ReadReq MSHR miss cycles
771,789c779,797
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230146499 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 477536249 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 278000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 81250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60929000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 104521250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 16097880074 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86272013 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42559203 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 128831216 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8927886 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13175305 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 22103191 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 408771858 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 334873814 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 743645672 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 423500 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230914750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 484247749 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 228750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59892499 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105166750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 16146124355 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 85791947 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42794256 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 128586203 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8846879 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13136807 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 21983686 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 415913357 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 327528317 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 743441674 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 607500 # number of demand (read+write) MSHR miss cycles
791,800c799,808
< system.l2c.demand_mshr_miss_latency::cpu0.inst 230146499 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 886308107 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 278000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 81250 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 60929000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 439395064 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 16841525746 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 423500 # number of overall MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.inst 230914750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 900161106 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 228750 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 59892499 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 432695067 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 16889566029 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 607500 # number of overall MSHR miss cycles
802,866c810,874
< system.l2c.overall_mshr_miss_latency::cpu0.inst 230146499 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 886308107 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13155934996 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 278000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 81250 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 60929000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 439395064 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2067966830 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 16841525746 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476853500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4797337250 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9261250 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814340500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6097792500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540127500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712608500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 4252736000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476853500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337464750 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9261250 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526949000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 10350528500 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191585 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120825 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.404471 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.469601 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805842 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.544668 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787422 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.905947 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.853981 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593577 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.689385 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.635521 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.413428 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.052239 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006250 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229022 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.280770 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471602 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.060606 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.156428 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.351736 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308579 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.413428 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average ReadReq mshr miss latency
---
> system.l2c.overall_mshr_miss_latency::cpu0.inst 230914750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 900161106 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13231909268 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 228750 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 59892499 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 432695067 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2033018339 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 16889566029 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796970001 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814272500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6097046501 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540071000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712688499 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 4252759499 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8337041001 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526960999 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 10349806000 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.194648 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120999 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.407020 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.468098 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.820316 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.780337 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.896575 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845886 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595289 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.685430 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.634834 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.415880 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.054795 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007463 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.283911 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474606 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.415880 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average ReadReq mshr miss latency
868,886c876,894
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency
---
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69416.248423 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 87699.200225 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.609197 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10071.763374 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10041.860386 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10038.212785 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68004.146010 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59507.325036 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 63979.490017 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency
888,897c896,905
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 60500 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75937.500000 # average overall mshr miss latency
899,907c907,915
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69500 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 81250 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 86133.134962 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87929.595157 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 86291.006034 # average overall mshr miss latency
959,981c967,989
< system.toL2Bus.trans_dist::ReadReq 633918 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 633902 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 31177 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 31177 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 240561 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 96369 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 41588 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 137957 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 39943 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 39943 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1258028 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 400059 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1658087 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37640280 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8288315 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 45928595 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 305065 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 1044371 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.034928 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.183598 # Request fanout histogram
---
> system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 304794 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram
984,985c992,993
< system.toL2Bus.snoop_fanout::1 1007893 96.51% 96.51% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 36478 3.49% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram
989,990c997,998
< system.toL2Bus.snoop_fanout::total 1044371 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 1521180751 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks)
994c1002
< system.toL2Bus.respLayer0.occupancy 2136308825 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks)
996c1004
< system.toL2Bus.respLayer1.occupancy 850635338 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks)
1000c1008
< system.iobus.trans_dist::WriteReq 59408 # Transaction distribution
---
> system.iobus.trans_dist::WriteReq 59414 # Transaction distribution
1002c1010
< system.iobus.trans_dist::WriteInvalidateReq 32 # Transaction distribution
---
> system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution
1093c1101
< system.iobus.reqLayer27.occupancy 326676322 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks)
1099c1107
< system.iobus.respLayer3.occupancy 36842591 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks)
1124,1127c1132,1135
< system.cpu0.dtb.read_hits 24353899 # DTB read hits
< system.cpu0.dtb.read_misses 6408 # DTB read misses
< system.cpu0.dtb.write_hits 18126722 # DTB write hits
< system.cpu0.dtb.write_misses 1115 # DTB write misses
---
> system.cpu0.dtb.read_hits 24351510 # DTB read hits
> system.cpu0.dtb.read_misses 6410 # DTB read misses
> system.cpu0.dtb.write_hits 18124813 # DTB write hits
> system.cpu0.dtb.write_misses 1105 # DTB write misses
1132c1140
< system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB
---
> system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB
1134c1142
< system.cpu0.dtb.prefetch_faults 1442 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch
1137,1138c1145,1146
< system.cpu0.dtb.read_accesses 24360307 # DTB read accesses
< system.cpu0.dtb.write_accesses 18127837 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 24357920 # DTB read accesses
> system.cpu0.dtb.write_accesses 18125918 # DTB write accesses
1140,1142c1148,1150
< system.cpu0.dtb.hits 42480621 # DTB hits
< system.cpu0.dtb.misses 7523 # DTB misses
< system.cpu0.dtb.accesses 42488144 # DTB accesses
---
> system.cpu0.dtb.hits 42476323 # DTB hits
> system.cpu0.dtb.misses 7515 # DTB misses
> system.cpu0.dtb.accesses 42483838 # DTB accesses
1164,1165c1172,1173
< system.cpu0.itb.inst_hits 115074724 # ITB inst hits
< system.cpu0.itb.inst_misses 3350 # ITB inst misses
---
> system.cpu0.itb.inst_hits 115065468 # ITB inst hits
> system.cpu0.itb.inst_misses 3349 # ITB inst misses
1174c1182
< system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB
1181,1185c1189,1193
< system.cpu0.itb.inst_accesses 115078074 # ITB inst accesses
< system.cpu0.itb.hits 115074724 # DTB hits
< system.cpu0.itb.misses 3350 # DTB misses
< system.cpu0.itb.accesses 115078074 # DTB accesses
< system.cpu0.numCycles 5733858512 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses
> system.cpu0.itb.hits 115065468 # DTB hits
> system.cpu0.itb.misses 3349 # DTB misses
> system.cpu0.itb.accesses 115068817 # DTB accesses
> system.cpu0.numCycles 5733846284 # number of cpu cycles simulated
1188,1190c1196,1198
< system.cpu0.committedInsts 111430460 # Number of instructions committed
< system.cpu0.committedOps 134719109 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 119427816 # Number of integer alu accesses
---
> system.cpu0.committedInsts 111421342 # Number of instructions committed
> system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses
1192,1194c1200,1202
< system.cpu0.num_func_calls 12527987 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 14980229 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 119427816 # number of integer instructions
---
> system.cpu0.num_func_calls 12527292 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 119417138 # number of integer instructions
1196,1197c1204,1205
< system.cpu0.num_int_register_reads 220379706 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 83050844 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written
1200,1206c1208,1214
< system.cpu0.num_cc_register_reads 488414813 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 49991768 # number of times the CC registers were written
< system.cpu0.num_mem_refs 43590115 # number of memory refs
< system.cpu0.num_load_insts 24600281 # Number of load instructions
< system.cpu0.num_store_insts 18989834 # Number of store instructions
< system.cpu0.num_idle_cycles 5477713409.888090 # Number of idle cycles
< system.cpu0.num_busy_cycles 256145102.111911 # Number of busy cycles
---
> system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written
> system.cpu0.num_mem_refs 43585643 # number of memory refs
> system.cpu0.num_load_insts 24597805 # Number of load instructions
> system.cpu0.num_store_insts 18987838 # Number of store instructions
> system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles
> system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles
1209c1217
< system.cpu0.Branches 28216928 # Number of branches fetched
---
> system.cpu0.Branches 28215087 # Number of branches fetched
1211,1212c1219,1220
< system.cpu0.op_class::IntAlu 94734127 68.43% 68.43% # Class of executed instruction
< system.cpu0.op_class::IntMult 104105 0.08% 68.51% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction
> system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction
1236c1244
< system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction
---
> system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction
1240,1241c1248,1249
< system.cpu0.op_class::MemRead 24600281 17.77% 86.28% # Class of executed instruction
< system.cpu0.op_class::MemWrite 18989834 13.72% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction
> system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction
1244c1252
< system.cpu0.op_class::total 138438000 # Class of executed instruction
---
> system.cpu0.op_class::total 138425707 # Class of executed instruction
1246,1253c1254,1261
< system.cpu0.kern.inst.quiesce 2074 # number of quiesce instructions executed
< system.cpu0.icache.tags.replacements 1061133 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.483144 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 114013070 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1061645 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 107.392838 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 12807152500 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483144 # Average occupied blocks per requestor
---
> system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed
> system.cpu0.icache.tags.replacements 1060721 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor
1261,1298c1269,1306
< system.cpu0.icache.tags.tag_accesses 231211102 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 231211102 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 114013070 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 114013070 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 114013070 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 114013070 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 114013070 # number of overall hits
< system.cpu0.icache.overall_hits::total 114013070 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1061654 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1061654 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1061654 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1061654 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1061654 # number of overall misses
< system.cpu0.icache.overall_misses::total 1061654 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000777256 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 9000777256 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 9000777256 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 9000777256 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 9000777256 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 9000777256 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 115074724 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 115074724 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 115074724 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 115074724 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 115074724 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 115074724 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.070309 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.070309 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 8478.070309 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.070309 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 8478.070309 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 231192178 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 231192178 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 114004226 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 114004226 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 114004226 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 114004226 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 114004226 # number of overall hits
> system.cpu0.icache.overall_hits::total 114004226 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1061242 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1061242 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1061242 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1061242 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1061242 # number of overall misses
> system.cpu0.icache.overall_misses::total 1061242 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8993016265 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 8993016265 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 8993016265 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 8993016265 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 8993016265 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 8993016265 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065468 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 115065468 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 115065468 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 115065468 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 115065468 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 115065468 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009223 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.009223 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009223 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.009223 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009223 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.009223 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8474.048582 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 8474.048582 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 8474.048582 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8474.048582 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 8474.048582 # average overall miss latency
1307,1334c1315,1342
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061654 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 1061654 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061654 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 1061654 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061654 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 1061654 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407609744 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407609744 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407609744 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 7407609744 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407609744 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 7407609744 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719278000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719278000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719278000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 719278000 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.423665 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.423665 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.423665 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061242 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 1061242 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061242 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 1061242 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061242 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 1061242 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7400481735 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 7400481735 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7400481735 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 7400481735 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7400481735 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 7400481735 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009223 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.009223 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009223 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.009223 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6973.415804 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 6973.415804 # average overall mshr miss latency
1340,1343c1348,1351
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923568 # number of hwpf identified
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 227909 # number of hwpf that were already in mshr
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9246862 # number of hwpf that were already in the cache
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 529 # number of hwpf that were already in the prefetch queue
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9920146 # number of hwpf identified
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228501 # number of hwpf that were already in mshr
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9247232 # number of hwpf that were already in the cache
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 457 # number of hwpf that were already in the prefetch queue
1345,1347c1353,1355
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 49 # number of hwpf removed because MSHR allocated
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 448219 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778472 # number of hwpf spanning a virtual page
---
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 42 # number of hwpf removed because MSHR allocated
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 443914 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 777982 # number of hwpf spanning a virtual page
1349,1370c1357,1378
< system.cpu0.l2cache.tags.replacements 358131 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16113.840521 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1936015 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 374364 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 5.171477 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 6748.405331 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.298352 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.117074 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 799.968206 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1087.232896 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7475.818663 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.411890 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000140 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048826 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.066359 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.456288 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.983511 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7939 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8291 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.replacements 355628 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16102.172005 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1937789 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 371860 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 5.211071 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 2843494453500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 6709.486955 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.515536 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.136878 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 805.451650 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1129.365506 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7457.215481 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.409515 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.049161 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.068931 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455152 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.982799 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8004 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8222 # Occupied blocks per task id
1372,1376c1380,1384
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 127 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1966 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4890 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 915 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1974 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4878 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1002 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
1378,1490c1386,1498
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2895 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4675 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.484558 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.506042 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 38026831 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 38026831 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 6990 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3189 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045942 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 372788 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 1428909 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 483936 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 483936 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10087 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 10087 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2033 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 2033 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 212805 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 212805 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 6990 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3189 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1045942 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 585593 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1641714 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 6990 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3189 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1045942 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 585593 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1641714 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 263 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 219 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15712 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 83577 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 99771 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29878 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 29878 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19321 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44921 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 44921 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 263 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 219 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 15712 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 128498 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 144692 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 263 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 219 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 15712 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 128498 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 144692 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6061000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4899500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 598206723 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2260687668 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 2869854891 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 524614292 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 524614292 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377658880 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377658880 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1333497 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1333497 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1506710587 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 1506710587 # number of ReadExReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6061000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4899500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 598206723 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 3767398255 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 4376565478 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6061000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4899500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 598206723 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 3767398255 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 4376565478 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7253 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3408 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061654 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456365 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 1528680 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 483936 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 483936 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39965 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 39965 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21354 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 21354 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257726 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 257726 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7253 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3408 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1061654 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 714091 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1786406 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7253 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3408 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1061654 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 714091 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1786406 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064261 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014800 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.183136 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.065266 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.747604 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.747604 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.904795 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.904795 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4665 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 528 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.488525 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.501831 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 38047907 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 38047907 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7536 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3405 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1045714 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 373715 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 1430370 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 484430 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 484430 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 10145 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 10145 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2013 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 2013 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213040 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 213040 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7536 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3405 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1045714 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 586755 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1643410 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7536 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3405 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1045714 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 586755 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1643410 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 196 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 15528 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 83217 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 99215 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29791 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 29791 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19296 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 19296 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44826 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 44826 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 196 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 15528 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 128043 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 144041 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 196 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 15528 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 128043 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 144041 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 6536750 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 592785719 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2259626174 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 2863295143 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 522985276 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 522985276 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 377523884 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 377523884 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1293996 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1293996 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1513538321 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 1513538321 # number of ReadExReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 6536750 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 592785719 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 3773164495 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 4376833464 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 6536750 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 592785719 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 3773164495 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 4376833464 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7810 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3601 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1061242 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 456932 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 1529585 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 484430 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 484430 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 39936 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 39936 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21309 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 21309 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257866 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 257866 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7810 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3601 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1061242 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 714798 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1787451 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7810 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3601 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1061242 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 714798 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1787451 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054429 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.014632 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.182121 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.064864 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.745969 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.745969 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905533 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905533 # miss rate for SCUpgradeReq accesses
1493,1528c1501,1536
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174298 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174298 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064261 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014800 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179946 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.080996 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036261 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064261 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014800 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179946 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.080996 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22372.146119 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38073.238480 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27049.160271 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28764.419430 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17558.547828 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.549350 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190499.571429 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190499.571429 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33541.341177 # average ReadExReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 30247.459970 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23045.627376 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22372.146119 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38073.238480 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 5815 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.173834 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.173834 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054429 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.014632 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.179132 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.080585 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035083 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054429 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.014632 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.179132 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.080585 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22176.020408 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38175.278143 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27153.420263 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28859.498493 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17555.143365 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17555.143365 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19564.877902 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19564.877902 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 161749.500000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 161749.500000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33764.741913 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33764.741913 # average ReadExReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 30386.025257 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23856.751825 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22176.020408 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38175.278143 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29467.948228 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 30386.025257 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked
1530c1538
< system.cpu0.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 74 # number of cycles access was blocked
1532c1540
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 76.513158 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 74.675676 # average number of cycles each access was blocked
1536,1613c1544,1621
< system.cpu0.l2cache.writebacks::writebacks 205462 # number of writebacks
< system.cpu0.l2cache.writebacks::total 205462 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2206 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2737 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 4943 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1219 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 1219 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2206 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3956 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6162 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2206 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3956 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6162 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 263 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 219 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13506 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80840 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 94828 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 448214 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29878 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29878 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19321 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19321 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43702 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 43702 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 263 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 219 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13506 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124542 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 138530 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 263 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 219 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13506 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124542 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 448214 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 586744 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3366500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 457538021 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1656533968 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2121657489 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17785493022 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 490939499 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 490939499 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261550596 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261550596 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1060497 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1060497 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1074359119 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1074359119 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3366500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 457538021 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2730893087 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 3196016608 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4219000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3366500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 457538021 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2730893087 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17785493022 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 20981509630 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647388500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328873750 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5976262250 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987021005 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987021005 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647388500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315894755 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9963283255 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177139 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062033 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.writebacks::writebacks 204753 # number of writebacks
> system.cpu0.l2cache.writebacks::total 204753 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2208 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 2732 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 4940 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1247 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 1247 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2208 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3979 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6187 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2208 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3979 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6187 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 274 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 196 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 13320 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 80485 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 94275 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 443910 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 29791 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 29791 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19296 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19296 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43579 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 43579 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 274 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 196 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 13320 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 124064 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 137854 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 274 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 196 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 13320 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 124064 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 443910 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 581764 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2974500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 455365525 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1657319721 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2120277496 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17833673651 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 489027550 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 489027550 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 261183602 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 261183602 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1027996 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1027996 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1080146893 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1080146893 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2974500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 455365525 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 2737466614 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 3200424389 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4617750 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2974500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 455365525 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 2737466614 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17833673651 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 21034098040 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647208500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328493002 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975701502 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3987031009 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3987031009 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315524011 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962732511 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.176142 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.061634 # mshr miss rate for ReadReq accesses
1616,1619c1624,1627
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.747604 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.747604 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.904795 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.904795 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.745969 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.745969 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905533 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905533 # mshr miss rate for SCUpgradeReq accesses
1622,1632c1630,1640
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169568 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169568 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077547 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036261 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064261 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012722 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174406 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.168999 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.168999 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077123 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035083 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054429 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012551 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173565 # mshr miss rate for overall accesses
1634,1660c1642,1668
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.328449 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency
1670,1678c1678,1686
< system.cpu0.dcache.tags.replacements 658799 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 485.164758 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 41683742 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 659311 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 63.223186 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 1016179000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.164758 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947587 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.replacements 659666 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy
1680,1682c1688,1690
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id
1684,1763c1692,1771
< system.cpu0.dcache.tags.tag_accesses 85573160 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 85573160 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 23155425 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 23155425 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 17431620 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 17431620 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323179 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 323179 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358328 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 358328 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353864 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 353864 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 40587045 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 40587045 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 40910224 # number of overall hits
< system.cpu0.dcache.overall_hits::total 40910224 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 360428 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 360428 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 297691 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 297691 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106192 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 106192 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21416 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 21416 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 658119 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 658119 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 764311 # number of overall misses
< system.cpu0.dcache.overall_misses::total 764311 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4473033768 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 4473033768 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4445222415 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 4445222415 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335592501 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 335592501 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473344116 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 473344116 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1450500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1450500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 8918256183 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 8918256183 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 8918256183 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 8918256183 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 23515853 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 23515853 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 17729311 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 17729311 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429371 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 429371 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379744 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 379744 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375234 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 375234 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 41245164 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 41245164 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 41674535 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 41674535 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015327 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.015327 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016791 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.016791 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247320 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247320 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056396 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056396 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056951 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056951 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015956 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.015956 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018340 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.018340 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits
> system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses
> system.cpu0.dcache.overall_misses::total 765091 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency
1766,1769c1774,1777
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency
1778,1847c1786,1855
< system.cpu0.dcache.writebacks::writebacks 483937 # number of writebacks
< system.cpu0.dcache.writebacks::total 483937 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7364 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 7364 # number of ReadReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15075 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15075 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 7364 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 7364 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 7364 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 7364 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353064 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 353064 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297691 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 297691 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96960 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 96960 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6341 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6341 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21361 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 21361 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 650755 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 650755 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 747715 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 747715 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3674066732 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3674066732 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3839615585 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3839615585 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1190903244 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1190903244 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89864249 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89864249 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429815884 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429815884 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1372500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1372500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7513682317 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 7513682317 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8704585561 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 8704585561 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564939750 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564939750 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183945995 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183945995 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748885745 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748885745 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015014 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015014 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016791 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016791 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225819 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225819 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016698 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016698 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056927 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056927 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015778 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.015778 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017942 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.017942 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks
> system.cpu0.dcache.writebacks::total 484431 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency
1850,1853c1858,1861
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency
1861,1888c1869,1896
< system.cpu0.toL2Bus.trans_dist::ReadReq 1734717 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1628862 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 26256 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 26256 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 483936 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 598763 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 81012 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43653 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 101651 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 279403 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 269117 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141354 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2250253 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9809 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 20976 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 4422392 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981948 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80932636 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13632 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29012 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 148957228 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 991588 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 3219253 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 5.272771 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.445384 # Request fanout histogram
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 985271 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram
1895,1896c1903,1904
< system.cpu0.toL2Bus.snoop_fanout::5 2341135 72.72% 72.72% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::6 878118 27.28% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram
1900,1901c1908,1909
< system.cpu0.toL2Bus.snoop_fanout::total 3219253 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 1700320883 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks)
1903c1911
< system.cpu0.toL2Bus.snoopLayer0.occupancy 115643997 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks)
1905c1913
< system.cpu0.toL2Bus.respLayer0.occupancy 1603955756 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks)
1907c1915
< system.cpu0.toL2Bus.respLayer1.occupancy 1150860061 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks)
1909c1917
< system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
1911c1919
< system.cpu0.toL2Bus.respLayer3.occupancy 13723500 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks)
1936,1939c1944,1947
< system.cpu1.dtb.read_hits 4827395 # DTB read hits
< system.cpu1.dtb.read_misses 2744 # DTB read misses
< system.cpu1.dtb.write_hits 4131070 # DTB write hits
< system.cpu1.dtb.write_misses 524 # DTB write misses
---
> system.cpu1.dtb.read_hits 4826536 # DTB read hits
> system.cpu1.dtb.read_misses 2746 # DTB read misses
> system.cpu1.dtb.write_hits 4130096 # DTB write hits
> system.cpu1.dtb.write_misses 525 # DTB write misses
1946c1954
< system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch
1949,1950c1957,1958
< system.cpu1.dtb.read_accesses 4830139 # DTB read accesses
< system.cpu1.dtb.write_accesses 4131594 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 4829282 # DTB read accesses
> system.cpu1.dtb.write_accesses 4130621 # DTB write accesses
1952,1954c1960,1962
< system.cpu1.dtb.hits 8958465 # DTB hits
< system.cpu1.dtb.misses 3268 # DTB misses
< system.cpu1.dtb.accesses 8961733 # DTB accesses
---
> system.cpu1.dtb.hits 8956632 # DTB hits
> system.cpu1.dtb.misses 3271 # DTB misses
> system.cpu1.dtb.accesses 8959903 # DTB accesses
1976c1984
< system.cpu1.itb.inst_hits 20889672 # ITB inst hits
---
> system.cpu1.itb.inst_hits 20887785 # ITB inst hits
1993,1994c2001,2002
< system.cpu1.itb.inst_accesses 20891419 # ITB inst accesses
< system.cpu1.itb.hits 20889672 # DTB hits
---
> system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses
> system.cpu1.itb.hits 20887785 # DTB hits
1996,1997c2004,2005
< system.cpu1.itb.accesses 20891419 # DTB accesses
< system.cpu1.numCycles 5732950771 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 20889532 # DTB accesses
> system.cpu1.numCycles 5732937622 # number of cpu cycles simulated
2000,2002c2008,2010
< system.cpu1.committedInsts 20508829 # Number of instructions committed
< system.cpu1.committedOps 24874782 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 22190598 # Number of integer alu accesses
---
> system.cpu1.committedInsts 20506953 # Number of instructions committed
> system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses
2004,2006c2012,2014
< system.cpu1.num_func_calls 1209607 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 2572400 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 22190598 # number of integer instructions
---
> system.cpu1.num_func_calls 1209546 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 22187475 # number of integer instructions
2008,2009c2016,2017
< system.cpu1.num_int_register_reads 39855869 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 15449003 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written
2012,2021c2020,2029
< system.cpu1.num_cc_register_reads 90462747 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 8862782 # number of times the CC registers were written
< system.cpu1.num_mem_refs 9247846 # number of memory refs
< system.cpu1.num_load_insts 4946569 # Number of load instructions
< system.cpu1.num_store_insts 4301277 # Number of store instructions
< system.cpu1.num_idle_cycles 5671538888.273010 # Number of idle cycles
< system.cpu1.num_busy_cycles 61411882.726990 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.010712 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.989288 # Percentage of idle cycles
< system.cpu1.Branches 3892747 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written
> system.cpu1.num_mem_refs 9246104 # number of memory refs
> system.cpu1.num_load_insts 4945808 # Number of load instructions
> system.cpu1.num_store_insts 4300296 # Number of store instructions
> system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles
> system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles
> system.cpu1.Branches 3892449 # Number of branches fetched
2023,2024c2031,2032
< system.cpu1.op_class::IntAlu 16017837 63.30% 63.30% # Class of executed instruction
< system.cpu1.op_class::IntMult 33571 0.13% 63.44% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction
> system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction
2048c2056
< system.cpu1.op_class::SimdFloatMisc 4039 0.02% 63.45% # Class of executed instruction
---
> system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction
2052,2053c2060,2061
< system.cpu1.op_class::MemRead 4946569 19.55% 83.00% # Class of executed instruction
< system.cpu1.op_class::MemWrite 4301277 17.00% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction
> system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction
2056c2064
< system.cpu1.op_class::total 25303360 # Class of executed instruction
---
> system.cpu1.op_class::total 25300005 # Class of executed instruction
2058,2067c2066,2075
< system.cpu1.kern.inst.quiesce 2751 # number of quiesce instructions executed
< system.cpu1.icache.tags.replacements 565233 # number of replacements
< system.cpu1.icache.tags.tagsinuse 498.685358 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 20323921 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 565745 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 35.924173 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 115078716000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.685358 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973995 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.973995 # Average percentage of cache occupancy
---
> system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed
> system.cpu1.icache.tags.replacements 565422 # number of replacements
> system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy
2069,2070c2077,2078
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id
2073,2110c2081,2118
< system.cpu1.icache.tags.tag_accesses 42345080 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 42345080 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 20323921 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 20323921 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 20323921 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 20323921 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 20323921 # number of overall hits
< system.cpu1.icache.overall_hits::total 20323921 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 565746 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 565746 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 565746 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 565746 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 565746 # number of overall misses
< system.cpu1.icache.overall_misses::total 565746 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4684636281 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4684636281 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4684636281 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4684636281 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4684636281 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4684636281 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 20889667 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 20889667 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 20889667 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 20889667 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 20889667 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 20889667 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027083 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027083 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.027083 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027083 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.027083 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8280.458511 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 8280.458511 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 8280.458511 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8280.458511 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 8280.458511 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 20321845 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 20321845 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 20321845 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 20321845 # number of overall hits
> system.cpu1.icache.overall_hits::total 20321845 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 565935 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 565935 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 565935 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 565935 # number of overall misses
> system.cpu1.icache.overall_misses::total 565935 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4686937020 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4686937020 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4686937020 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 20887780 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 20887780 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 20887780 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 20887780 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027094 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency
2119,2146c2127,2154
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565746 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 565746 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 565746 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 565746 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 565746 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 565746 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835844219 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835844219 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835844219 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3835844219 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835844219 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3835844219 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14025750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14025750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14025750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 14025750 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027083 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.027083 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027083 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.027083 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6780.152611 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6780.152611 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 6780.152611 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565935 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 565935 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 565935 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 565935 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 565935 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 565935 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3837864980 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3837864980 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3837864980 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3837864980 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3837864980 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3837864980 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027094 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.027094 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027094 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.027094 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6781.458966 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6781.458966 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 6781.458966 # average overall mshr miss latency
2152,2155c2160,2163
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4613211 # number of hwpf identified
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23452 # number of hwpf that were already in mshr
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471751 # number of hwpf that were already in the cache
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 253 # number of hwpf that were already in the prefetch queue
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4614389 # number of hwpf identified
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 23334 # number of hwpf that were already in mshr
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4471466 # number of hwpf that were already in the cache
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 174 # number of hwpf that were already in the prefetch queue
2157,2159c2165,2167
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 21 # number of hwpf removed because MSHR allocated
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 117734 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522133 # number of hwpf spanning a virtual page
---
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 12 # number of hwpf removed because MSHR allocated
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119403 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 521875 # number of hwpf spanning a virtual page
2161,2185c2169,2193
< system.cpu1.l2cache.tags.replacements 85099 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15602.150946 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 830949 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 100297 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 8.284884 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 2855978416500 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 4730.109881 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.755019 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.314200 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 871.040386 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1529.848587 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8465.082873 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.288703 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000351 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000019 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053164 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.093375 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.516668 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.952280 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9308 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5882 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1130 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8114 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.replacements 85170 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15608.903517 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 832047 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 100420 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 8.285670 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 4763.037570 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.132590 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.368696 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 855.518210 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1503.059843 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8483.786608 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.290713 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000023 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052217 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091739 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517809 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.952692 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9266 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5973 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 72 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1188 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8006 # Occupied blocks per task id
2187,2219c2195,2227
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1134 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4474 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.568115 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359009 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 16690228 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 16690228 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3013 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1699 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560147 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 123235 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 688094 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 134926 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 134926 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1530 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 1530 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 889 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 889 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39290 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 39290 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3013 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1699 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 560147 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 162525 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 727384 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3013 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1699 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 560147 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 162525 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 727384 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 347 # number of ReadReq misses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4453 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.565552 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364563 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 16694338 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 16694338 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3134 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1760 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 560288 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 123283 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 688465 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 134894 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 134894 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1542 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 1542 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 898 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 898 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39293 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 39293 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3134 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1760 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 560288 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 162576 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 727758 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3134 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1760 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 560288 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 162576 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 727758 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 333 # number of ReadReq misses
2221,2232c2229,2240
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5599 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 70297 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 76525 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29432 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 29432 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22334 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22334 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33500 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 33500 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 347 # number of demand (read+write) misses
---
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5647 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 70211 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 76473 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29395 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 29395 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22356 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22356 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33464 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 33464 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 333 # number of demand (read+write) misses
2234,2237c2242,2245
< system.cpu1.l2cache.demand_misses::cpu1.inst 5599 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 103797 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 110025 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 347 # number of overall misses
---
> system.cpu1.l2cache.demand_misses::cpu1.inst 5647 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 103675 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 109937 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 333 # number of overall misses
2239,2298c2247,2306
< system.cpu1.l2cache.overall_misses::cpu1.inst 5599 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 103797 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 110025 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7263500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5687750 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191326469 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1549353898 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1753631617 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537113129 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 537113129 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436542574 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436542574 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1696500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1696500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1074535378 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 1074535378 # number of ReadExReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7263500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5687750 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191326469 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 2623889276 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 2828166995 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7263500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5687750 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191326469 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 2623889276 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 2828166995 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3360 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565746 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193532 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 764619 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 134926 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 134926 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30962 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 30962 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23223 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 23223 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72790 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 72790 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3360 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 565746 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 266322 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 837409 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3360 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 565746 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 266322 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 837409 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.142352 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009897 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363232 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.100083 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950585 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950585 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961719 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961719 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.overall_misses::cpu1.inst 5647 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 103675 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 109937 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6884250 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5668750 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192294729 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1548076900 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1752924629 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536345651 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 536345651 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436560063 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436560063 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1532500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1532500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1065249640 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 1065249640 # number of ReadExReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6884250 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5668750 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192294729 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 2613326540 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 2818174269 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6884250 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5668750 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192294729 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 2613326540 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 2818174269 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3467 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2042 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565935 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193494 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 764938 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 134894 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 134894 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30937 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 30937 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23254 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 23254 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72757 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 72757 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3467 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2042 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 565935 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 266251 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 837695 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3467 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2042 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 565935 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 266251 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 837695 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138100 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009978 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.362859 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.099973 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950157 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950157 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961383 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961383 # miss rate for SCUpgradeReq accesses
2301,2336c2309,2344
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.460228 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.460228 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.142352 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009897 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389742 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.131387 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103274 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.142352 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009897 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389742 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.131387 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 565500 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 565500 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925 # average ReadExReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 1025 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.459942 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.459942 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138100 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009978 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.389388 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.131238 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096048 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138100 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009978 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.389388 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.131238 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20101.950355 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34052.546308 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22048.922534 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22922.137604 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18246.152441 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18246.152441 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19527.646404 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19527.646404 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 255416.666667 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 255416.666667 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31832.704996 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31832.704996 # average ReadExReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 25634.447629 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20673.423423 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20101.950355 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34052.546308 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25206.911406 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 25634.447629 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked
2338c2346
< system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 41 # number of cycles access was blocked
2340c2348
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.285714 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28.463415 # average number of cycles each access was blocked
2344,2357c2352,2365
< system.cpu1.l2cache.writebacks::writebacks 35099 # number of writebacks
< system.cpu1.l2cache.writebacks::total 35099 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 685 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 96 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 214 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 214 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 685 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 310 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 995 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 685 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 310 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 995 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 347 # number of ReadReq MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 35043 # number of writebacks
> system.cpu1.l2cache.writebacks::total 35043 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 682 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 211 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 211 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 682 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 997 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 682 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 997 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 333 # number of ReadReq MSHR misses
2359,2372c2367,2380
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4914 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70201 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 75744 # number of ReadReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 117733 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29432 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29432 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22334 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22334 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33286 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 33286 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 347 # number of demand (read+write) MSHR misses
---
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4965 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70107 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 75687 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 119401 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29395 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29395 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22356 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22356 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33253 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 33253 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 333 # number of demand (read+write) MSHR misses
2374,2377c2382,2385
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4914 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103487 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 109030 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 347 # number of overall MSHR misses
---
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4965 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103360 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 108940 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 333 # number of overall MSHR misses
2379,2421c2387,2429
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4914 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103487 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 117733 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 226763 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3713250 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143751774 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1055636432 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1207934956 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3298666709 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 431077198 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 431077198 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306544179 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306544179 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1430500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1430500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820609092 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820609092 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3713250 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143751774 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1876245524 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 2028544048 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4833500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3713250 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143751774 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1876245524 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3298666709 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 5327210757 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12612250 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916010500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928622750 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796474001 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796474001 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12612250 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712484501 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725096751 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362736 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099061 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4965 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103360 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119401 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 228341 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3694250 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143766018 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1054723430 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206735448 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3265998125 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430847649 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430847649 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306945673 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306945673 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1280500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1280500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 812696840 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 812696840 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3694250 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143766018 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1867420270 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 2019432288 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4551750 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3694250 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143766018 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1867420270 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3265998125 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 5285430413 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 915969500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928445000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796605001 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796605001 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712574501 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1725050001 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362321 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.098945 # mshr miss rate for ReadReq accesses
2424,2427c2432,2435
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950585 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950585 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961719 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961719 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950157 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950157 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961383 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961383 # mshr miss rate for SCUpgradeReq accesses
2430,2440c2438,2448
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457288 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457288 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130199 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103274 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.142352 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008686 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388578 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.457042 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.457042 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130047 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096048 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138100 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008773 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388205 # mshr miss rate for overall accesses
2442,2468c2450,2476
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.270791 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122 # average overall mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272583 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15044.481008 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15943.761121 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27353.189044 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14657.174656 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14657.174656 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13729.901279 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13729.901279 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213416.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213416.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24439.805130 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency
2478,2570c2486,2578
< system.cpu1.dcache.tags.replacements 218932 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 479.958616 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 8645395 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 219287 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 39.425023 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 104115576500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.958616 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937419 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.937419 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 18161929 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 18161929 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 4463105 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 4463105 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 3919326 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 3919326 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64192 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 64192 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87200 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 87200 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79632 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 79632 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 8382431 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 8382431 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 8446623 # number of overall hits
< system.cpu1.dcache.overall_hits::total 8446623 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 155171 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 155171 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 103752 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 103752 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34196 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 34196 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17931 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 17931 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23276 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 23276 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 258923 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 258923 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 293119 # number of overall misses
< system.cpu1.dcache.overall_misses::total 293119 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220270266 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 2220270266 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2272762314 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2272762314 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325809000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 325809000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538454705 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 538454705 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1810500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1810500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 4493032580 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 4493032580 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 4493032580 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 4493032580 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 4618276 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 4618276 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 4023078 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 4023078 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98388 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 98388 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105131 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 105131 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102908 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 102908 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 8641354 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 8641354 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 8739742 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 8739742 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033599 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.033599 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025789 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.025789 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347563 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347563 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170559 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170559 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226183 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226183 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029963 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.029963 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033539 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.033539 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.replacements 218971 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits
> system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses
> system.cpu1.dcache.overall_misses::total 293049 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency
2573,2576c2581,2584
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency
2585,2654c2593,2662
< system.cpu1.dcache.writebacks::writebacks 134926 # number of writebacks
< system.cpu1.dcache.writebacks::total 134926 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12328 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12328 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 299 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 299 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 299 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 299 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154872 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 154872 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103752 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 103752 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33057 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 33057 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5603 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5603 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23226 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 23226 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 258624 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 258624 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 291681 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 291681 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901749734 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901749734 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2059007686 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2059007686 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496678249 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496678249 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84335500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84335500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490783295 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490783295 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1734500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1734500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3960757420 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 3960757420 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4457435669 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 4457435669 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961034499 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961034499 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382499 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382499 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794416998 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794416998 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033535 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033535 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025789 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025789 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335986 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335986 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053295 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053295 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225697 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225697 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029929 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.029929 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033374 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033374 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks
> system.cpu1.dcache.writebacks::total 134894 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency
2657,2660c2665,2668
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency
2668,2695c2676,2703
< system.cpu1.toL2Bus.trans_dist::ReadReq 1206103 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 816776 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 134926 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 169865 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 86284 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42512 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 89712 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 91056 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 78188 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131848 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880488 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9281 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 2026923 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36208456 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28775795 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13440 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 65005615 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 818131 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1761210 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 5.414931 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.492710 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 817024 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram
2702,2703c2710,2711
< system.cpu1.toL2Bus.snoop_fanout::5 1030430 58.51% 58.51% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::6 730780 41.49% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram
2707,2708c2715,2716
< system.cpu1.toL2Bus.snoop_fanout::total 1761210 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 658102724 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks)
2710c2718
< system.cpu1.toL2Bus.snoopLayer0.occupancy 89600499 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks)
2712c2720
< system.cpu1.toL2Bus.respLayer0.occupancy 848922781 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks)
2714c2722
< system.cpu1.toL2Bus.respLayer1.occupancy 438669538 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks)
2718c2726
< system.cpu1.toL2Bus.respLayer3.occupancy 5921500 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks)
2720,2728c2728,2736
< system.iocache.tags.replacements 36443 # number of replacements
< system.iocache.tags.tagsinuse 14.446814 # Cycle average of tags in use
< system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 277160524000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.446814 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.902926 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.902926 # Average percentage of cache occupancy
---
> system.iocache.tags.replacements 36427 # number of replacements
> system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use
> system.iocache.tags.total_refs 16 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy
2732,2733c2740,2741
< system.iocache.tags.tag_accesses 328549 # Number of tag accesses
< system.iocache.tags.data_accesses 328549 # Number of data accesses
---
> system.iocache.tags.tag_accesses 328485 # Number of tag accesses
> system.iocache.tags.data_accesses 328485 # Number of data accesses
2738,2739c2746,2747
< system.iocache.WriteInvalidateReq_misses::realview.ide 32 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 32 # number of WriteInvalidateReq misses
---
> system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses
2744,2749c2752,2757
< system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles
2752,2753c2760,2761
< system.iocache.WriteInvalidateReq_accesses::realview.ide 36256 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 36256 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::realview.ide 36250 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 36250 # number of WriteInvalidateReq accesses(hits+misses)
2760,2761c2768,2769
< system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000883 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000883 # miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000717 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 0.000717 # miss rate for WriteInvalidateReq accesses
2766,2771c2774,2779
< system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 124954.059289 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 124954.059289 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 124954.059289 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 124954.059289 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 124954.059289 # average overall miss latency
2786,2793c2794,2801
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2247085536 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2247085536 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 18456377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 18456377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2245537783 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2245537783 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 18456377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 18456377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 18456377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 18456377 # number of overall MSHR miss cycles
2800,2801c2808,2809
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72950.106719 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72950.106719 # average ReadReq mshr miss latency
2804,2807c2812,2815
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 72950.106719 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72950.106719 # average overall mshr miss latency