1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.207291 # Number of seconds simulated
4sim_ticks 1207290627000 # Number of ticks simulated
5final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.207291 # Number of seconds simulated
4sim_ticks 1207290627000 # Number of ticks simulated
5final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 965295 # Simulator instruction rate (inst/s)
8host_op_rate 1230212 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 18956490102 # Simulator tick rate (ticks/s)
10host_mem_usage 382720 # Number of bytes of host memory used
11host_seconds 63.69 # Real time elapsed on the host
| 7host_inst_rate 648322 # Simulator instruction rate (inst/s)
8host_op_rate 826248 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 12731770448 # Simulator tick rate (ticks/s)
10host_mem_usage 380152 # Number of bytes of host memory used
11host_seconds 94.83 # Real time elapsed on the host
|
12sim_insts 61477134 # Number of instructions simulated
13sim_ops 78349023 # Number of ops (including micro ops) simulated
| 12sim_insts 61477134 # Number of instructions simulated
13sim_ops 78349023 # Number of ops (including micro ops) simulated
|
14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
24system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
25system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
27system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
28system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s)
29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
30system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
31system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s)
| |
32system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory
33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
35system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory
36system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory
37system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
38system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
39system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory
40system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory
41system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory
42system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory
43system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory
44system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory
45system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory
46system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
47system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
48system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory
49system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory
50system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
51system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
52system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory
53system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory
54system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
55system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
56system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory
57system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory
58system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory
59system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory
60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
61system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
62system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory
63system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s)
65system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s)
66system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s)
67system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s)
68system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s)
69system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
70system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s)
71system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s)
72system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s)
73system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s)
74system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s)
75system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s)
76system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s)
77system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s)
78system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s)
79system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s)
80system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s)
85system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s)
86system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s)
87system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
88system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s)
89system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s)
90system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory
23system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory
24system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory
27system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory
28system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
29system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
30system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory
31system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory
40system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory
41system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory
42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
43system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
44system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory
45system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s)
56system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s)
60system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s)
|
| 73system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
74system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
75system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
76system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
77system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
78system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
79system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
80system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
81system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
82system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
83system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
84system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s)
85system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
86system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
87system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s)
88system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
89system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
90system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s)
|
91system.l2c.replacements 69267 # number of replacements
92system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use
93system.l2c.total_refs 1645693 # Total number of references to valid blocks.
94system.l2c.sampled_refs 134464 # Sample count of references to valid blocks.
95system.l2c.avg_refs 12.238912 # Average number of references to valid blocks.
96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
97system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor
98system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor
99system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor
100system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor
101system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor
102system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor
103system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor
104system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor
105system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor
106system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy
107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
109system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy
110system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy
111system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
113system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy
114system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy
115system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy
116system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits
117system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits
118system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits
119system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits
120system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits
121system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits
122system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits
123system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits
124system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits
125system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits
126system.l2c.Writeback_hits::total 572580 # number of Writeback hits
127system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits
128system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits
129system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits
130system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits
131system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits
132system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits
133system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits
134system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits
135system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits
136system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits
137system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits
138system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits
139system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits
140system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits
141system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits
142system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits
143system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits
144system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits
145system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits
146system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits
147system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits
148system.l2c.overall_hits::cpu0.data 262598 # number of overall hits
149system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits
150system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits
151system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits
152system.l2c.overall_hits::cpu1.data 197108 # number of overall hits
153system.l2c.overall_hits::total 1325620 # number of overall hits
154system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
155system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
156system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses
157system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses
158system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
160system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses
161system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses
162system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses
163system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses
164system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses
165system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses
166system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses
167system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses
168system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses
169system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses
170system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses
171system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses
172system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
173system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
174system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses
175system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses
176system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
178system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses
179system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses
180system.l2c.demand_misses::total 161841 # number of demand (read+write) misses
181system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
182system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
183system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses
184system.l2c.overall_misses::cpu0.data 75067 # number of overall misses
185system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
187system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses
188system.l2c.overall_misses::cpu1.data 75979 # number of overall misses
189system.l2c.overall_misses::total 161841 # number of overall misses
190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles
191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles
192system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles
193system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles
194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles
195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles
196system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles
197system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles
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435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles
436system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles
437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses
438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses
439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses
440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses
441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses
442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses
443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses
444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses
445system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses
446system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses
447system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses
448system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses
449system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses
450system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses
451system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses
452system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses
453system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses
454system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses
455system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses
456system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses
457system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses
458system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses
459system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses
460system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses
461system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses
462system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses
463system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses
464system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses
465system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses
466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses
467system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses
468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses
469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses
470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses
471system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses
472system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses
473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency
476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency
477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency
480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency
481system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency
482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency
483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency
484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency
485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency
486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency
487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency
488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency
489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency
490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency
491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency
494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency
495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency
498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
499system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency
500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency
503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency
504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency
507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
508system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency
509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
517system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
518system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
519system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
520system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
521system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
522system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
523system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
524system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
525system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
526system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
527system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
528system.cf0.dma_write_txs 0 # Number of DMA write transactions.
529system.cpu0.dtb.inst_hits 0 # ITB inst hits
530system.cpu0.dtb.inst_misses 0 # ITB inst misses
531system.cpu0.dtb.read_hits 7076084 # DTB read hits
532system.cpu0.dtb.read_misses 3743 # DTB read misses
533system.cpu0.dtb.write_hits 5660386 # DTB write hits
534system.cpu0.dtb.write_misses 804 # DTB write misses
535system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
536system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
537system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
538system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
539system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB
540system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
541system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
542system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
543system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
544system.cpu0.dtb.read_accesses 7079827 # DTB read accesses
545system.cpu0.dtb.write_accesses 5661190 # DTB write accesses
546system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
547system.cpu0.dtb.hits 12736470 # DTB hits
548system.cpu0.dtb.misses 4547 # DTB misses
549system.cpu0.dtb.accesses 12741017 # DTB accesses
550system.cpu0.itb.inst_hits 29574655 # ITB inst hits
551system.cpu0.itb.inst_misses 2205 # ITB inst misses
552system.cpu0.itb.read_hits 0 # DTB read hits
553system.cpu0.itb.read_misses 0 # DTB read misses
554system.cpu0.itb.write_hits 0 # DTB write hits
555system.cpu0.itb.write_misses 0 # DTB write misses
556system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
558system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
559system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
560system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
565system.cpu0.itb.read_accesses 0 # DTB read accesses
566system.cpu0.itb.write_accesses 0 # DTB write accesses
567system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses
568system.cpu0.itb.hits 29574655 # DTB hits
569system.cpu0.itb.misses 2205 # DTB misses
570system.cpu0.itb.accesses 29576860 # DTB accesses
571system.cpu0.numCycles 2414581254 # number of cpu cycles simulated
572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
574system.cpu0.committedInsts 28876799 # Number of instructions committed
575system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed
576system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses
577system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
578system.cpu0.num_func_calls 1241592 # number of times a function call or return occured
| 91system.l2c.replacements 69267 # number of replacements
92system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use
93system.l2c.total_refs 1645693 # Total number of references to valid blocks.
94system.l2c.sampled_refs 134464 # Sample count of references to valid blocks.
95system.l2c.avg_refs 12.238912 # Average number of references to valid blocks.
96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
97system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor
98system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor
99system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor
100system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor
101system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor
102system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor
103system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor
104system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor
105system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor
106system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy
107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
109system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy
110system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy
111system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
113system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy
114system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy
115system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy
116system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits
117system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits
118system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits
119system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits
120system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits
121system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits
122system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits
123system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits
124system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits
125system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits
126system.l2c.Writeback_hits::total 572580 # number of Writeback hits
127system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits
128system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits
129system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits
130system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits
131system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits
132system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits
133system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits
134system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits
135system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits
136system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits
137system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits
138system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits
139system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits
140system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits
141system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits
142system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits
143system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits
144system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits
145system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits
146system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits
147system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits
148system.l2c.overall_hits::cpu0.data 262598 # number of overall hits
149system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits
150system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits
151system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits
152system.l2c.overall_hits::cpu1.data 197108 # number of overall hits
153system.l2c.overall_hits::total 1325620 # number of overall hits
154system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
155system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
156system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses
157system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses
158system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
160system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses
161system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses
162system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses
163system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses
164system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses
165system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses
166system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses
167system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses
168system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses
169system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses
170system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses
171system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses
172system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
173system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
174system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses
175system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses
176system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
178system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses
179system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses
180system.l2c.demand_misses::total 161841 # number of demand (read+write) misses
181system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
182system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
183system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses
184system.l2c.overall_misses::cpu0.data 75067 # number of overall misses
185system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
187system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses
188system.l2c.overall_misses::cpu1.data 75979 # number of overall misses
189system.l2c.overall_misses::total 161841 # number of overall misses
190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles
191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles
192system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles
193system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles
194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles
195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles
196system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles
197system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles
198system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles
199system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles
200system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles
201system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles
202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles
203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles
204system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles
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439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses
440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses
441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses
442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses
443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses
444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses
445system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses
446system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses
447system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses
448system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses
449system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses
450system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses
451system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses
452system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses
453system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses
454system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses
455system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses
456system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses
457system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses
458system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses
459system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses
460system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses
461system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses
462system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses
463system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses
464system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses
465system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses
466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses
467system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses
468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses
469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses
470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses
471system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses
472system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses
473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency
476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency
477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency
480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency
481system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency
482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency
483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency
484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency
485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency
486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency
487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency
488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency
489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency
490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency
491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency
494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency
495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency
498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
499system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency
500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency
503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency
504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency
507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
508system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency
509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
517system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
518system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
519system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
520system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
521system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
522system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
523system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
524system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
525system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
526system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
527system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
528system.cf0.dma_write_txs 0 # Number of DMA write transactions.
529system.cpu0.dtb.inst_hits 0 # ITB inst hits
530system.cpu0.dtb.inst_misses 0 # ITB inst misses
531system.cpu0.dtb.read_hits 7076084 # DTB read hits
532system.cpu0.dtb.read_misses 3743 # DTB read misses
533system.cpu0.dtb.write_hits 5660386 # DTB write hits
534system.cpu0.dtb.write_misses 804 # DTB write misses
535system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
536system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
537system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
538system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
539system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB
540system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
541system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
542system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
543system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
544system.cpu0.dtb.read_accesses 7079827 # DTB read accesses
545system.cpu0.dtb.write_accesses 5661190 # DTB write accesses
546system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
547system.cpu0.dtb.hits 12736470 # DTB hits
548system.cpu0.dtb.misses 4547 # DTB misses
549system.cpu0.dtb.accesses 12741017 # DTB accesses
550system.cpu0.itb.inst_hits 29574655 # ITB inst hits
551system.cpu0.itb.inst_misses 2205 # ITB inst misses
552system.cpu0.itb.read_hits 0 # DTB read hits
553system.cpu0.itb.read_misses 0 # DTB read misses
554system.cpu0.itb.write_hits 0 # DTB write hits
555system.cpu0.itb.write_misses 0 # DTB write misses
556system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
558system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
559system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
560system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
565system.cpu0.itb.read_accesses 0 # DTB read accesses
566system.cpu0.itb.write_accesses 0 # DTB write accesses
567system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses
568system.cpu0.itb.hits 29574655 # DTB hits
569system.cpu0.itb.misses 2205 # DTB misses
570system.cpu0.itb.accesses 29576860 # DTB accesses
571system.cpu0.numCycles 2414581254 # number of cpu cycles simulated
572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
574system.cpu0.committedInsts 28876799 # Number of instructions committed
575system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed
576system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses
577system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
578system.cpu0.num_func_calls 1241592 # number of times a function call or return occured
|
579system.cpu0.num_conditional_control_insts 4354316 # number of instructions that are conditional controls
| 579system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls
|
580system.cpu0.num_int_insts 33114839 # number of integer instructions
581system.cpu0.num_fp_insts 3860 # number of float instructions
582system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read
583system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written
584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
586system.cpu0.num_mem_refs 13404188 # number of memory refs
587system.cpu0.num_load_insts 7413537 # Number of load instructions
588system.cpu0.num_store_insts 5990651 # Number of store instructions
589system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles
590system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles
591system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles
592system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles
593system.cpu0.kern.inst.arm 0 # number of arm instructions executed
594system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed
595system.cpu0.icache.replacements 408135 # number of replacements
596system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use
597system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks.
598system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks.
599system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks.
600system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit.
601system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor
602system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy
603system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy
604system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits
605system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits
606system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits
607system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits
608system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits
609system.cpu0.icache.overall_hits::total 29165991 # number of overall hits
610system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses
611system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses
612system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses
613system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses
614system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses
615system.cpu0.icache.overall_misses::total 408647 # number of overall misses
616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles
617system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles
618system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles
619system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles
620system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles
621system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles
622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses)
623system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses)
624system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses
625system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses
626system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses
627system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses
628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses
629system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses
630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses
631system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses
632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses
633system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses
634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency
635system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency
636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency
637system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency
638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency
639system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency
640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
646system.cpu0.icache.fast_writes 0 # number of fast writes performed
647system.cpu0.icache.cache_copies 0 # number of cache copies performed
648system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses
649system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses
650system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses
651system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses
652system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses
653system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses
654system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles
655system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles
656system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles
657system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles
658system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles
659system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles
660system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
661system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
662system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
663system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
664system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses
665system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses
666system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses
667system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses
668system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses
669system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses
670system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency
671system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency
672system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency
673system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency
674system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency
675system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency
676system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
677system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
678system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
679system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
680system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
681system.cpu0.dcache.replacements 330734 # number of replacements
682system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use
683system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks.
684system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks.
685system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks.
686system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit.
687system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor
688system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy
689system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy
690system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits
691system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits
692system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits
693system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits
694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits
695system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits
696system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits
697system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits
698system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits
699system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits
700system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits
701system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits
702system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses
703system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses
704system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses
705system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses
706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses
707system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses
708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses
709system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses
710system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses
711system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses
712system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses
713system.cpu0.dcache.overall_misses::total 369775 # number of overall misses
714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles
715system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles
716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles
717system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles
718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles
719system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles
720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles
721system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles
722system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles
723system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles
724system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles
725system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles
726system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses)
727system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses)
728system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses)
729system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses)
730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses)
731system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses)
732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses)
733system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses)
734system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses
735system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses
736system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses
737system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses
738system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses
739system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses
740system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses
741system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses
742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses
743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses
744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses
745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses
746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses
747system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses
748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses
749system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses
750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency
751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency
752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency
753system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency
754system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency
755system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency
756system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency
757system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency
758system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency
759system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency
760system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency
761system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency
762system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
763system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
764system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
765system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
766system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
767system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
768system.cpu0.dcache.fast_writes 0 # number of fast writes performed
769system.cpu0.dcache.cache_copies 0 # number of cache copies performed
770system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks
771system.cpu0.dcache.writebacks::total 306480 # number of writebacks
772system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses
773system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses
774system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses
775system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses
776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses
777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses
778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses
779system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses
780system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses
781system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses
782system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses
783system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses
784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles
785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles
786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles
787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles
788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles
789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles
790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles
791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles
792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles
793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles
794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles
795system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles
796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles
797system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles
798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles
799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles
800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles
801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles
802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles
803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles
804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses
805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses
806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses
807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses
808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses
809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses
810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses
811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses
812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses
813system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses
814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses
815system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses
816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency
817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency
818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency
819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency
820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency
821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency
822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency
823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency
824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
826system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
827system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
828system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
829system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
832system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
836system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
837system.cpu1.dtb.inst_hits 0 # ITB inst hits
838system.cpu1.dtb.inst_misses 0 # ITB inst misses
839system.cpu1.dtb.read_hits 8318170 # DTB read hits
840system.cpu1.dtb.read_misses 3663 # DTB read misses
841system.cpu1.dtb.write_hits 5832653 # DTB write hits
842system.cpu1.dtb.write_misses 1435 # DTB write misses
843system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
844system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
845system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
846system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
847system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB
848system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
849system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
850system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
851system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
852system.cpu1.dtb.read_accesses 8321833 # DTB read accesses
853system.cpu1.dtb.write_accesses 5834088 # DTB write accesses
854system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
855system.cpu1.dtb.hits 14150823 # DTB hits
856system.cpu1.dtb.misses 5098 # DTB misses
857system.cpu1.dtb.accesses 14155921 # DTB accesses
858system.cpu1.itb.inst_hits 33211066 # ITB inst hits
859system.cpu1.itb.inst_misses 2171 # ITB inst misses
860system.cpu1.itb.read_hits 0 # DTB read hits
861system.cpu1.itb.read_misses 0 # DTB read misses
862system.cpu1.itb.write_hits 0 # DTB write hits
863system.cpu1.itb.write_misses 0 # DTB write misses
864system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
865system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
866system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
867system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
868system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
869system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
870system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
871system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
872system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
873system.cpu1.itb.read_accesses 0 # DTB read accesses
874system.cpu1.itb.write_accesses 0 # DTB write accesses
875system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses
876system.cpu1.itb.hits 33211066 # DTB hits
877system.cpu1.itb.misses 2171 # DTB misses
878system.cpu1.itb.accesses 33213237 # DTB accesses
879system.cpu1.numCycles 2413083038 # number of cpu cycles simulated
880system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
881system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
882system.cpu1.committedInsts 32600335 # Number of instructions committed
883system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed
884system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses
885system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
886system.cpu1.num_func_calls 963082 # number of times a function call or return occured
| 580system.cpu0.num_int_insts 33114839 # number of integer instructions
581system.cpu0.num_fp_insts 3860 # number of float instructions
582system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read
583system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written
584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
586system.cpu0.num_mem_refs 13404188 # number of memory refs
587system.cpu0.num_load_insts 7413537 # Number of load instructions
588system.cpu0.num_store_insts 5990651 # Number of store instructions
589system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles
590system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles
591system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles
592system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles
593system.cpu0.kern.inst.arm 0 # number of arm instructions executed
594system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed
595system.cpu0.icache.replacements 408135 # number of replacements
596system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use
597system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks.
598system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks.
599system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks.
600system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit.
601system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor
602system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy
603system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy
604system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits
605system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits
606system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits
607system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits
608system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits
609system.cpu0.icache.overall_hits::total 29165991 # number of overall hits
610system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses
611system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses
612system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses
613system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses
614system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses
615system.cpu0.icache.overall_misses::total 408647 # number of overall misses
616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles
617system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles
618system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles
619system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles
620system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles
621system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles
622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses)
623system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses)
624system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses
625system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses
626system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses
627system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses
628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses
629system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses
630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses
631system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses
632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses
633system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses
634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency
635system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency
636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency
637system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency
638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency
639system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency
640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
646system.cpu0.icache.fast_writes 0 # number of fast writes performed
647system.cpu0.icache.cache_copies 0 # number of cache copies performed
648system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses
649system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses
650system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses
651system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses
652system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses
653system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses
654system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles
655system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles
656system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles
657system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles
658system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles
659system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles
660system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
661system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
662system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
663system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
664system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses
665system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses
666system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses
667system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses
668system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses
669system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses
670system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency
671system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency
672system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency
673system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency
674system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency
675system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency
676system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
677system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
678system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
679system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
680system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
681system.cpu0.dcache.replacements 330734 # number of replacements
682system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use
683system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks.
684system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks.
685system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks.
686system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit.
687system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor
688system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy
689system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy
690system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits
691system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits
692system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits
693system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits
694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits
695system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits
696system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits
697system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits
698system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits
699system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits
700system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits
701system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits
702system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses
703system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses
704system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses
705system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses
706system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses
707system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses
708system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses
709system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses
710system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses
711system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses
712system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses
713system.cpu0.dcache.overall_misses::total 369775 # number of overall misses
714system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles
715system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles
716system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles
717system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles
718system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles
719system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles
720system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles
721system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles
722system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles
723system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles
724system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles
725system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles
726system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses)
727system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses)
728system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses)
729system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses)
730system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses)
731system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses)
732system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses)
733system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses)
734system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses
735system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses
736system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses
737system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses
738system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses
739system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses
740system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses
741system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses
742system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses
743system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses
744system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses
745system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses
746system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses
747system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses
748system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses
749system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses
750system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency
751system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency
752system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency
753system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency
754system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency
755system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency
756system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency
757system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency
758system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency
759system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency
760system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency
761system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency
762system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
763system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
764system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
765system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
766system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
767system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
768system.cpu0.dcache.fast_writes 0 # number of fast writes performed
769system.cpu0.dcache.cache_copies 0 # number of cache copies performed
770system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks
771system.cpu0.dcache.writebacks::total 306480 # number of writebacks
772system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses
773system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses
774system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses
775system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses
776system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses
777system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses
778system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses
779system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses
780system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses
781system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses
782system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses
783system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses
784system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles
785system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles
786system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles
787system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles
788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles
789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles
790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles
791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles
792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles
793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles
794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles
795system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles
796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles
797system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles
798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles
799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles
800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles
801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles
802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles
803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles
804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses
805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses
806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses
807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses
808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses
809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses
810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses
811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses
812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses
813system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses
814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses
815system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses
816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency
817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency
818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency
819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency
820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency
821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency
822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency
823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency
824system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
826system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
827system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
828system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
829system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
830system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
832system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
834system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
836system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
837system.cpu1.dtb.inst_hits 0 # ITB inst hits
838system.cpu1.dtb.inst_misses 0 # ITB inst misses
839system.cpu1.dtb.read_hits 8318170 # DTB read hits
840system.cpu1.dtb.read_misses 3663 # DTB read misses
841system.cpu1.dtb.write_hits 5832653 # DTB write hits
842system.cpu1.dtb.write_misses 1435 # DTB write misses
843system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
844system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
845system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
846system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
847system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB
848system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
849system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
850system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
851system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
852system.cpu1.dtb.read_accesses 8321833 # DTB read accesses
853system.cpu1.dtb.write_accesses 5834088 # DTB write accesses
854system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
855system.cpu1.dtb.hits 14150823 # DTB hits
856system.cpu1.dtb.misses 5098 # DTB misses
857system.cpu1.dtb.accesses 14155921 # DTB accesses
858system.cpu1.itb.inst_hits 33211066 # ITB inst hits
859system.cpu1.itb.inst_misses 2171 # ITB inst misses
860system.cpu1.itb.read_hits 0 # DTB read hits
861system.cpu1.itb.read_misses 0 # DTB read misses
862system.cpu1.itb.write_hits 0 # DTB write hits
863system.cpu1.itb.write_misses 0 # DTB write misses
864system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
865system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
866system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
867system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
868system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
869system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
870system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
871system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
872system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
873system.cpu1.itb.read_accesses 0 # DTB read accesses
874system.cpu1.itb.write_accesses 0 # DTB write accesses
875system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses
876system.cpu1.itb.hits 33211066 # DTB hits
877system.cpu1.itb.misses 2171 # DTB misses
878system.cpu1.itb.accesses 33213237 # DTB accesses
879system.cpu1.numCycles 2413083038 # number of cpu cycles simulated
880system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
881system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
882system.cpu1.committedInsts 32600335 # Number of instructions committed
883system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed
884system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses
885system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
886system.cpu1.num_func_calls 963082 # number of times a function call or return occured
|
887system.cpu1.num_conditional_control_insts 3716244 # number of instructions that are conditional controls
| 887system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls
|
888system.cpu1.num_int_insts 37342001 # number of integer instructions
889system.cpu1.num_fp_insts 6793 # number of float instructions
890system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read
891system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written
892system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
893system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
894system.cpu1.num_mem_refs 14689113 # number of memory refs
895system.cpu1.num_load_insts 8640454 # Number of load instructions
896system.cpu1.num_store_insts 6048659 # Number of store instructions
897system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles
898system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles
899system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles
900system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles
901system.cpu1.kern.inst.arm 0 # number of arm instructions executed
902system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed
903system.cpu1.icache.replacements 455071 # number of replacements
904system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use
905system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks.
906system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks.
907system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks.
908system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit.
909system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor
910system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy
911system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy
912system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits
913system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits
914system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits
915system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits
916system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits
917system.cpu1.icache.overall_hits::total 32755479 # number of overall hits
918system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses
919system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses
920system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses
921system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses
922system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses
923system.cpu1.icache.overall_misses::total 455583 # number of overall misses
924system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles
925system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles
926system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles
927system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles
928system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles
929system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles
930system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses)
931system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses)
932system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses
933system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses
934system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses
935system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses
936system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses
937system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses
938system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses
939system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses
940system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses
941system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses
942system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency
943system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency
944system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
945system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency
946system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
947system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency
948system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
949system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
950system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
951system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
952system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
953system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
954system.cpu1.icache.fast_writes 0 # number of fast writes performed
955system.cpu1.icache.cache_copies 0 # number of cache copies performed
956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses
957system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses
958system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses
959system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses
960system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses
961system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses
962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles
963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles
964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles
965system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles
966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles
967system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles
968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses
973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses
974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses
975system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses
976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses
977system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses
978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency
979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency
980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency
981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency
982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency
983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency
984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
989system.cpu1.dcache.replacements 292605 # number of replacements
990system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use
991system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks.
992system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks.
993system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks.
994system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit.
995system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor
996system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy
997system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy
998system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits
999system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits
1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits
1001system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits
1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits
1003system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits
1004system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits
1005system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits
1006system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits
1007system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits
1008system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits
1009system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits
1010system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses
1011system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses
1012system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses
1013system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses
1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses
1015system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses
1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses
1017system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses
1018system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses
1019system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses
1020system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses
1021system.cpu1.dcache.overall_misses::total 321159 # number of overall misses
1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles
1023system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles
1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles
1025system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles
1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles
1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles
1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles
1029system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles
1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles
1031system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles
1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles
1033system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles
1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses)
1035system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses)
1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses)
1037system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses)
1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses)
1039system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses)
1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses)
1041system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses)
1042system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses
1043system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses
1044system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses
1045system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses
1046system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses
1047system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses
1048system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses
1049system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses
1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses
1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses
1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses
1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses
1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses
1055system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses
1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses
1057system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses
1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency
1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency
1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency
1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency
1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency
1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency
1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency
1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency
1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency
1067system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency
1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency
1069system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency
1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1078system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks
1079system.cpu1.dcache.writebacks::total 266100 # number of writebacks
1080system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses
1081system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses
1082system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses
1083system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses
1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses
1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses
1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses
1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses
1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses
1089system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses
1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses
1091system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses
1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles
1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles
1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles
1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles
1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles
1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles
1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles
1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles
1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles
1101system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles
1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles
1103system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles
1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles
1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles
1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles
1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles
1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles
1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles
1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses
1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses
1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses
1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses
1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses
1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses
1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses
1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses
1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses
1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses
1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses
1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses
1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency
1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency
1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency
1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency
1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency
1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency
1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency
1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency
1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1141system.iocache.replacements 0 # number of replacements
1142system.iocache.tagsinuse 0 # Cycle average of tags in use
1143system.iocache.total_refs 0 # Total number of references to valid blocks.
1144system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1145system.iocache.avg_refs nan # Average number of references to valid blocks.
1146system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1153system.iocache.fast_writes 0 # number of fast writes performed
1154system.iocache.cache_copies 0 # number of cache copies performed
1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles
1156system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles
1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles
1158system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles
1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1164
1165---------- End Simulation Statistics ----------
| 888system.cpu1.num_int_insts 37342001 # number of integer instructions
889system.cpu1.num_fp_insts 6793 # number of float instructions
890system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read
891system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written
892system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
893system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
894system.cpu1.num_mem_refs 14689113 # number of memory refs
895system.cpu1.num_load_insts 8640454 # Number of load instructions
896system.cpu1.num_store_insts 6048659 # Number of store instructions
897system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles
898system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles
899system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles
900system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles
901system.cpu1.kern.inst.arm 0 # number of arm instructions executed
902system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed
903system.cpu1.icache.replacements 455071 # number of replacements
904system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use
905system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks.
906system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks.
907system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks.
908system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit.
909system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor
910system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy
911system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy
912system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits
913system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits
914system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits
915system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits
916system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits
917system.cpu1.icache.overall_hits::total 32755479 # number of overall hits
918system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses
919system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses
920system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses
921system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses
922system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses
923system.cpu1.icache.overall_misses::total 455583 # number of overall misses
924system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles
925system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles
926system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles
927system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles
928system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles
929system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles
930system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses)
931system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses)
932system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses
933system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses
934system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses
935system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses
936system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses
937system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses
938system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses
939system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses
940system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses
941system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses
942system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency
943system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency
944system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
945system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency
946system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
947system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency
948system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
949system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
950system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
951system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
952system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
953system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
954system.cpu1.icache.fast_writes 0 # number of fast writes performed
955system.cpu1.icache.cache_copies 0 # number of cache copies performed
956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses
957system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses
958system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses
959system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses
960system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses
961system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses
962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles
963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles
964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles
965system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles
966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles
967system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles
968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses
973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses
974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses
975system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses
976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses
977system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses
978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency
979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency
980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency
981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency
982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency
983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency
984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
989system.cpu1.dcache.replacements 292605 # number of replacements
990system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use
991system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks.
992system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks.
993system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks.
994system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit.
995system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor
996system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy
997system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy
998system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits
999system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits
1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits
1001system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits
1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits
1003system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits
1004system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits
1005system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits
1006system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits
1007system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits
1008system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits
1009system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits
1010system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses
1011system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses
1012system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses
1013system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses
1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses
1015system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses
1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses
1017system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses
1018system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses
1019system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses
1020system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses
1021system.cpu1.dcache.overall_misses::total 321159 # number of overall misses
1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles
1023system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles
1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles
1025system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles
1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles
1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles
1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles
1029system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles
1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles
1031system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles
1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles
1033system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles
1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses)
1035system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses)
1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses)
1037system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses)
1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses)
1039system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses)
1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses)
1041system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses)
1042system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses
1043system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses
1044system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses
1045system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses
1046system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses
1047system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses
1048system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses
1049system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses
1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses
1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses
1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses
1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses
1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses
1055system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses
1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses
1057system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses
1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency
1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency
1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency
1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency
1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency
1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency
1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency
1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency
1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency
1067system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency
1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency
1069system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency
1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1078system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks
1079system.cpu1.dcache.writebacks::total 266100 # number of writebacks
1080system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses
1081system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses
1082system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses
1083system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses
1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses
1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses
1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses
1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses
1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses
1089system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses
1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses
1091system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses
1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles
1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles
1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles
1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles
1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles
1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles
1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles
1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles
1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles
1101system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles
1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles
1103system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles
1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles
1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles
1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles
1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles
1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles
1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles
1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses
1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses
1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses
1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses
1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses
1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses
1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses
1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses
1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses
1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses
1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses
1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses
1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency
1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency
1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency
1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency
1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency
1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency
1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency
1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency
1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1141system.iocache.replacements 0 # number of replacements
1142system.iocache.tagsinuse 0 # Cycle average of tags in use
1143system.iocache.total_refs 0 # Total number of references to valid blocks.
1144system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1145system.iocache.avg_refs nan # Average number of references to valid blocks.
1146system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1153system.iocache.fast_writes 0 # number of fast writes performed
1154system.iocache.cache_copies 0 # number of cache copies performed
1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles
1156system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles
1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles
1158system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles
1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1164
1165---------- End Simulation Statistics ----------
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