1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.169707 # Number of seconds simulated
4sim_ticks 1169707043000 # Number of ticks simulated
5final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.169707 # Number of seconds simulated
4sim_ticks 1169707043000 # Number of ticks simulated
5final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 754175 # Simulator instruction rate (inst/s)
8host_op_rate 964493 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 14598169556 # Simulator tick rate (ticks/s)
10host_mem_usage 379804 # Number of bytes of host memory used
11host_seconds 80.13 # Real time elapsed on the host
| 7host_inst_rate 657704 # Simulator instruction rate (inst/s)
8host_op_rate 841119 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 12730829062 # Simulator tick rate (ticks/s)
10host_mem_usage 382856 # Number of bytes of host memory used
11host_seconds 91.88 # Real time elapsed on the host
|
12sim_insts 60429704 # Number of instructions simulated
13sim_ops 77281862 # Number of ops (including micro ops) simulated
| 12sim_insts 60429704 # Number of instructions simulated
13sim_ops 77281862 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 61898788 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10078928 # Number of bytes written to this memory
17system.physmem.num_reads 6478591 # Number of read requests responded to by this memory
18system.physmem.num_writes 867017 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s)
| 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
24system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
25system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
27system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
28system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s)
29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
30system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
31system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory
33system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory
34system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
35system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory
36system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory
37system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory
38system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory
39system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory
40system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory
41system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory
42system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory
43system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory
44system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory
45system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory
46system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
47system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
48system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory
49system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory
50system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory
51system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
52system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory
53system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory
54system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory
55system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory
56system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory
57system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory
58system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory
59system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory
60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
61system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
62system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory
63system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s)
65system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s)
66system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s)
67system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s)
68system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s)
69system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s)
70system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s)
71system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s)
72system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s)
73system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s)
74system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s)
75system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s)
76system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s)
77system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s)
78system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s)
79system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s)
80system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s)
85system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s)
86system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s)
87system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s)
88system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s)
89system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s)
90system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s)
|
33system.l2c.replacements 125934 # number of replacements
34system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use
35system.l2c.total_refs 1500548 # Total number of references to valid blocks.
36system.l2c.sampled_refs 155551 # Sample count of references to valid blocks.
37system.l2c.avg_refs 9.646663 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor
44system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor
45system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor
46system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor
47system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor
48system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy
49system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy
50system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
51system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy
52system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy
53system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy
54system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
55system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy
56system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy
57system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy
58system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits
59system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits
60system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits
61system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits
62system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits
63system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits
64system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits
65system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits
66system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits
67system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits
68system.l2c.Writeback_hits::total 577354 # number of Writeback hits
69system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits
70system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits
71system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits
72system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits
73system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits
74system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits
75system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits
76system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits
77system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits
78system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits
79system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits
80system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits
81system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits
82system.l2c.demand_hits::cpu1.dtb.walker 5680 # number of demand (read+write) hits
83system.l2c.demand_hits::cpu1.itb.walker 1949 # number of demand (read+write) hits
84system.l2c.demand_hits::cpu1.inst 446193 # number of demand (read+write) hits
85system.l2c.demand_hits::cpu1.data 190485 # number of demand (read+write) hits
86system.l2c.demand_hits::total 1309210 # number of demand (read+write) hits
87system.l2c.overall_hits::cpu0.dtb.walker 4097 # number of overall hits
88system.l2c.overall_hits::cpu0.itb.walker 1763 # number of overall hits
89system.l2c.overall_hits::cpu0.inst 399350 # number of overall hits
90system.l2c.overall_hits::cpu0.data 259693 # number of overall hits
91system.l2c.overall_hits::cpu1.dtb.walker 5680 # number of overall hits
92system.l2c.overall_hits::cpu1.itb.walker 1949 # number of overall hits
93system.l2c.overall_hits::cpu1.inst 446193 # number of overall hits
94system.l2c.overall_hits::cpu1.data 190485 # number of overall hits
95system.l2c.overall_hits::total 1309210 # number of overall hits
96system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses
97system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
98system.l2c.ReadReq_misses::cpu0.inst 7942 # number of ReadReq misses
99system.l2c.ReadReq_misses::cpu0.data 11318 # number of ReadReq misses
100system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses
101system.l2c.ReadReq_misses::cpu1.itb.walker 5 # number of ReadReq misses
102system.l2c.ReadReq_misses::cpu1.inst 7342 # number of ReadReq misses
103system.l2c.ReadReq_misses::cpu1.data 8301 # number of ReadReq misses
104system.l2c.ReadReq_misses::total 34940 # number of ReadReq misses
105system.l2c.UpgradeReq_misses::cpu0.data 4674 # number of UpgradeReq misses
106system.l2c.UpgradeReq_misses::cpu1.data 3622 # number of UpgradeReq misses
107system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses
108system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses
109system.l2c.SCUpgradeReq_misses::cpu1.data 452 # number of SCUpgradeReq misses
110system.l2c.SCUpgradeReq_misses::total 1019 # number of SCUpgradeReq misses
111system.l2c.ReadExReq_misses::cpu0.data 71101 # number of ReadExReq misses
112system.l2c.ReadExReq_misses::cpu1.data 76239 # number of ReadExReq misses
113system.l2c.ReadExReq_misses::total 147340 # number of ReadExReq misses
114system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses
115system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
116system.l2c.demand_misses::cpu0.inst 7942 # number of demand (read+write) misses
117system.l2c.demand_misses::cpu0.data 82419 # number of demand (read+write) misses
118system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses
119system.l2c.demand_misses::cpu1.itb.walker 5 # number of demand (read+write) misses
120system.l2c.demand_misses::cpu1.inst 7342 # number of demand (read+write) misses
121system.l2c.demand_misses::cpu1.data 84540 # number of demand (read+write) misses
122system.l2c.demand_misses::total 182280 # number of demand (read+write) misses
123system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses
124system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
125system.l2c.overall_misses::cpu0.inst 7942 # number of overall misses
126system.l2c.overall_misses::cpu0.data 82419 # number of overall misses
127system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses
128system.l2c.overall_misses::cpu1.itb.walker 5 # number of overall misses
129system.l2c.overall_misses::cpu1.inst 7342 # number of overall misses
130system.l2c.overall_misses::cpu1.data 84540 # number of overall misses
131system.l2c.overall_misses::total 182280 # number of overall misses
132system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 520000 # number of ReadReq miss cycles
133system.l2c.ReadReq_miss_latency::cpu0.itb.walker 208500 # number of ReadReq miss cycles
134system.l2c.ReadReq_miss_latency::cpu0.inst 414166000 # number of ReadReq miss cycles
135system.l2c.ReadReq_miss_latency::cpu0.data 589465000 # number of ReadReq miss cycles
136system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 940000 # number of ReadReq miss cycles
137system.l2c.ReadReq_miss_latency::cpu1.itb.walker 260000 # number of ReadReq miss cycles
138system.l2c.ReadReq_miss_latency::cpu1.inst 383790500 # number of ReadReq miss cycles
139system.l2c.ReadReq_miss_latency::cpu1.data 432860500 # number of ReadReq miss cycles
140system.l2c.ReadReq_miss_latency::total 1822210500 # number of ReadReq miss cycles
141system.l2c.UpgradeReq_miss_latency::cpu0.data 30607000 # number of UpgradeReq miss cycles
142system.l2c.UpgradeReq_miss_latency::cpu1.data 30466000 # number of UpgradeReq miss cycles
143system.l2c.UpgradeReq_miss_latency::total 61073000 # number of UpgradeReq miss cycles
144system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4060000 # number of SCUpgradeReq miss cycles
145system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5045000 # number of SCUpgradeReq miss cycles
146system.l2c.SCUpgradeReq_miss_latency::total 9105000 # number of SCUpgradeReq miss cycles
147system.l2c.ReadExReq_miss_latency::cpu0.data 3700498000 # number of ReadExReq miss cycles
148system.l2c.ReadExReq_miss_latency::cpu1.data 3973370000 # number of ReadExReq miss cycles
149system.l2c.ReadExReq_miss_latency::total 7673868000 # number of ReadExReq miss cycles
150system.l2c.demand_miss_latency::cpu0.dtb.walker 520000 # number of demand (read+write) miss cycles
151system.l2c.demand_miss_latency::cpu0.itb.walker 208500 # number of demand (read+write) miss cycles
152system.l2c.demand_miss_latency::cpu0.inst 414166000 # number of demand (read+write) miss cycles
153system.l2c.demand_miss_latency::cpu0.data 4289963000 # number of demand (read+write) miss cycles
154system.l2c.demand_miss_latency::cpu1.dtb.walker 940000 # number of demand (read+write) miss cycles
155system.l2c.demand_miss_latency::cpu1.itb.walker 260000 # number of demand (read+write) miss cycles
156system.l2c.demand_miss_latency::cpu1.inst 383790500 # number of demand (read+write) miss cycles
157system.l2c.demand_miss_latency::cpu1.data 4406230500 # number of demand (read+write) miss cycles
158system.l2c.demand_miss_latency::total 9496078500 # number of demand (read+write) miss cycles
159system.l2c.overall_miss_latency::cpu0.dtb.walker 520000 # number of overall miss cycles
160system.l2c.overall_miss_latency::cpu0.itb.walker 208500 # number of overall miss cycles
161system.l2c.overall_miss_latency::cpu0.inst 414166000 # number of overall miss cycles
162system.l2c.overall_miss_latency::cpu0.data 4289963000 # number of overall miss cycles
163system.l2c.overall_miss_latency::cpu1.dtb.walker 940000 # number of overall miss cycles
164system.l2c.overall_miss_latency::cpu1.itb.walker 260000 # number of overall miss cycles
165system.l2c.overall_miss_latency::cpu1.inst 383790500 # number of overall miss cycles
166system.l2c.overall_miss_latency::cpu1.data 4406230500 # number of overall miss cycles
167system.l2c.overall_miss_latency::total 9496078500 # number of overall miss cycles
168system.l2c.ReadReq_accesses::cpu0.dtb.walker 4107 # number of ReadReq accesses(hits+misses)
169system.l2c.ReadReq_accesses::cpu0.itb.walker 1767 # number of ReadReq accesses(hits+misses)
170system.l2c.ReadReq_accesses::cpu0.inst 407292 # number of ReadReq accesses(hits+misses)
171system.l2c.ReadReq_accesses::cpu0.data 217184 # number of ReadReq accesses(hits+misses)
172system.l2c.ReadReq_accesses::cpu1.dtb.walker 5698 # number of ReadReq accesses(hits+misses)
173system.l2c.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses)
174system.l2c.ReadReq_accesses::cpu1.inst 453535 # number of ReadReq accesses(hits+misses)
175system.l2c.ReadReq_accesses::cpu1.data 149081 # number of ReadReq accesses(hits+misses)
176system.l2c.ReadReq_accesses::total 1240618 # number of ReadReq accesses(hits+misses)
177system.l2c.Writeback_accesses::writebacks 577354 # number of Writeback accesses(hits+misses)
178system.l2c.Writeback_accesses::total 577354 # number of Writeback accesses(hits+misses)
179system.l2c.UpgradeReq_accesses::cpu0.data 5863 # number of UpgradeReq accesses(hits+misses)
180system.l2c.UpgradeReq_accesses::cpu1.data 4171 # number of UpgradeReq accesses(hits+misses)
181system.l2c.UpgradeReq_accesses::total 10034 # number of UpgradeReq accesses(hits+misses)
182system.l2c.SCUpgradeReq_accesses::cpu0.data 790 # number of SCUpgradeReq accesses(hits+misses)
183system.l2c.SCUpgradeReq_accesses::cpu1.data 645 # number of SCUpgradeReq accesses(hits+misses)
184system.l2c.SCUpgradeReq_accesses::total 1435 # number of SCUpgradeReq accesses(hits+misses)
185system.l2c.ReadExReq_accesses::cpu0.data 124928 # number of ReadExReq accesses(hits+misses)
186system.l2c.ReadExReq_accesses::cpu1.data 125944 # number of ReadExReq accesses(hits+misses)
187system.l2c.ReadExReq_accesses::total 250872 # number of ReadExReq accesses(hits+misses)
188system.l2c.demand_accesses::cpu0.dtb.walker 4107 # number of demand (read+write) accesses
189system.l2c.demand_accesses::cpu0.itb.walker 1767 # number of demand (read+write) accesses
190system.l2c.demand_accesses::cpu0.inst 407292 # number of demand (read+write) accesses
191system.l2c.demand_accesses::cpu0.data 342112 # number of demand (read+write) accesses
192system.l2c.demand_accesses::cpu1.dtb.walker 5698 # number of demand (read+write) accesses
193system.l2c.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses
194system.l2c.demand_accesses::cpu1.inst 453535 # number of demand (read+write) accesses
195system.l2c.demand_accesses::cpu1.data 275025 # number of demand (read+write) accesses
196system.l2c.demand_accesses::total 1491490 # number of demand (read+write) accesses
197system.l2c.overall_accesses::cpu0.dtb.walker 4107 # number of overall (read+write) accesses
198system.l2c.overall_accesses::cpu0.itb.walker 1767 # number of overall (read+write) accesses
199system.l2c.overall_accesses::cpu0.inst 407292 # number of overall (read+write) accesses
200system.l2c.overall_accesses::cpu0.data 342112 # number of overall (read+write) accesses
201system.l2c.overall_accesses::cpu1.dtb.walker 5698 # number of overall (read+write) accesses
202system.l2c.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses
203system.l2c.overall_accesses::cpu1.inst 453535 # number of overall (read+write) accesses
204system.l2c.overall_accesses::cpu1.data 275025 # number of overall (read+write) accesses
205system.l2c.overall_accesses::total 1491490 # number of overall (read+write) accesses
206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses
207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses
208system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses
209system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses
210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses
211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses
212system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses
213system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses
| 91system.l2c.replacements 125934 # number of replacements
92system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use
93system.l2c.total_refs 1500548 # Total number of references to valid blocks.
94system.l2c.sampled_refs 155551 # Sample count of references to valid blocks.
95system.l2c.avg_refs 9.646663 # Average number of references to valid blocks.
96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
97system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor
98system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor
99system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor
100system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor
101system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor
102system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor
103system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor
104system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor
105system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor
106system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy
107system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy
108system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
109system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy
110system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy
111system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy
112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
113system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy
114system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy
115system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy
116system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits
117system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits
118system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits
119system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits
120system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits
121system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits
122system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits
123system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits
124system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits
125system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits
126system.l2c.Writeback_hits::total 577354 # number of Writeback hits
127system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits
128system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits
129system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits
130system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits
131system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits
132system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits
133system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits
134system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits
135system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits
136system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits
137system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits
138system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits
139system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits
140system.l2c.demand_hits::cpu1.dtb.walker 5680 # number of demand (read+write) hits
141system.l2c.demand_hits::cpu1.itb.walker 1949 # number of demand (read+write) hits
142system.l2c.demand_hits::cpu1.inst 446193 # number of demand (read+write) hits
143system.l2c.demand_hits::cpu1.data 190485 # number of demand (read+write) hits
144system.l2c.demand_hits::total 1309210 # number of demand (read+write) hits
145system.l2c.overall_hits::cpu0.dtb.walker 4097 # number of overall hits
146system.l2c.overall_hits::cpu0.itb.walker 1763 # number of overall hits
147system.l2c.overall_hits::cpu0.inst 399350 # number of overall hits
148system.l2c.overall_hits::cpu0.data 259693 # number of overall hits
149system.l2c.overall_hits::cpu1.dtb.walker 5680 # number of overall hits
150system.l2c.overall_hits::cpu1.itb.walker 1949 # number of overall hits
151system.l2c.overall_hits::cpu1.inst 446193 # number of overall hits
152system.l2c.overall_hits::cpu1.data 190485 # number of overall hits
153system.l2c.overall_hits::total 1309210 # number of overall hits
154system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses
155system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
156system.l2c.ReadReq_misses::cpu0.inst 7942 # number of ReadReq misses
157system.l2c.ReadReq_misses::cpu0.data 11318 # number of ReadReq misses
158system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses
159system.l2c.ReadReq_misses::cpu1.itb.walker 5 # number of ReadReq misses
160system.l2c.ReadReq_misses::cpu1.inst 7342 # number of ReadReq misses
161system.l2c.ReadReq_misses::cpu1.data 8301 # number of ReadReq misses
162system.l2c.ReadReq_misses::total 34940 # number of ReadReq misses
163system.l2c.UpgradeReq_misses::cpu0.data 4674 # number of UpgradeReq misses
164system.l2c.UpgradeReq_misses::cpu1.data 3622 # number of UpgradeReq misses
165system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses
166system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses
167system.l2c.SCUpgradeReq_misses::cpu1.data 452 # number of SCUpgradeReq misses
168system.l2c.SCUpgradeReq_misses::total 1019 # number of SCUpgradeReq misses
169system.l2c.ReadExReq_misses::cpu0.data 71101 # number of ReadExReq misses
170system.l2c.ReadExReq_misses::cpu1.data 76239 # number of ReadExReq misses
171system.l2c.ReadExReq_misses::total 147340 # number of ReadExReq misses
172system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses
173system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
174system.l2c.demand_misses::cpu0.inst 7942 # number of demand (read+write) misses
175system.l2c.demand_misses::cpu0.data 82419 # number of demand (read+write) misses
176system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses
177system.l2c.demand_misses::cpu1.itb.walker 5 # number of demand (read+write) misses
178system.l2c.demand_misses::cpu1.inst 7342 # number of demand (read+write) misses
179system.l2c.demand_misses::cpu1.data 84540 # number of demand (read+write) misses
180system.l2c.demand_misses::total 182280 # number of demand (read+write) misses
181system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses
182system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
183system.l2c.overall_misses::cpu0.inst 7942 # number of overall misses
184system.l2c.overall_misses::cpu0.data 82419 # number of overall misses
185system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses
186system.l2c.overall_misses::cpu1.itb.walker 5 # number of overall misses
187system.l2c.overall_misses::cpu1.inst 7342 # number of overall misses
188system.l2c.overall_misses::cpu1.data 84540 # number of overall misses
189system.l2c.overall_misses::total 182280 # number of overall misses
190system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 520000 # number of ReadReq miss cycles
191system.l2c.ReadReq_miss_latency::cpu0.itb.walker 208500 # number of ReadReq miss cycles
192system.l2c.ReadReq_miss_latency::cpu0.inst 414166000 # number of ReadReq miss cycles
193system.l2c.ReadReq_miss_latency::cpu0.data 589465000 # number of ReadReq miss cycles
194system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 940000 # number of ReadReq miss cycles
195system.l2c.ReadReq_miss_latency::cpu1.itb.walker 260000 # number of ReadReq miss cycles
196system.l2c.ReadReq_miss_latency::cpu1.inst 383790500 # number of ReadReq miss cycles
197system.l2c.ReadReq_miss_latency::cpu1.data 432860500 # number of ReadReq miss cycles
198system.l2c.ReadReq_miss_latency::total 1822210500 # number of ReadReq miss cycles
199system.l2c.UpgradeReq_miss_latency::cpu0.data 30607000 # number of UpgradeReq miss cycles
200system.l2c.UpgradeReq_miss_latency::cpu1.data 30466000 # number of UpgradeReq miss cycles
201system.l2c.UpgradeReq_miss_latency::total 61073000 # number of UpgradeReq miss cycles
202system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4060000 # number of SCUpgradeReq miss cycles
203system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5045000 # number of SCUpgradeReq miss cycles
204system.l2c.SCUpgradeReq_miss_latency::total 9105000 # number of SCUpgradeReq miss cycles
205system.l2c.ReadExReq_miss_latency::cpu0.data 3700498000 # number of ReadExReq miss cycles
206system.l2c.ReadExReq_miss_latency::cpu1.data 3973370000 # number of ReadExReq miss cycles
207system.l2c.ReadExReq_miss_latency::total 7673868000 # number of ReadExReq miss cycles
208system.l2c.demand_miss_latency::cpu0.dtb.walker 520000 # number of demand (read+write) miss cycles
209system.l2c.demand_miss_latency::cpu0.itb.walker 208500 # number of demand (read+write) miss cycles
210system.l2c.demand_miss_latency::cpu0.inst 414166000 # number of demand (read+write) miss cycles
211system.l2c.demand_miss_latency::cpu0.data 4289963000 # number of demand (read+write) miss cycles
212system.l2c.demand_miss_latency::cpu1.dtb.walker 940000 # number of demand (read+write) miss cycles
213system.l2c.demand_miss_latency::cpu1.itb.walker 260000 # number of demand (read+write) miss cycles
214system.l2c.demand_miss_latency::cpu1.inst 383790500 # number of demand (read+write) miss cycles
215system.l2c.demand_miss_latency::cpu1.data 4406230500 # number of demand (read+write) miss cycles
216system.l2c.demand_miss_latency::total 9496078500 # number of demand (read+write) miss cycles
217system.l2c.overall_miss_latency::cpu0.dtb.walker 520000 # number of overall miss cycles
218system.l2c.overall_miss_latency::cpu0.itb.walker 208500 # number of overall miss cycles
219system.l2c.overall_miss_latency::cpu0.inst 414166000 # number of overall miss cycles
220system.l2c.overall_miss_latency::cpu0.data 4289963000 # number of overall miss cycles
221system.l2c.overall_miss_latency::cpu1.dtb.walker 940000 # number of overall miss cycles
222system.l2c.overall_miss_latency::cpu1.itb.walker 260000 # number of overall miss cycles
223system.l2c.overall_miss_latency::cpu1.inst 383790500 # number of overall miss cycles
224system.l2c.overall_miss_latency::cpu1.data 4406230500 # number of overall miss cycles
225system.l2c.overall_miss_latency::total 9496078500 # number of overall miss cycles
226system.l2c.ReadReq_accesses::cpu0.dtb.walker 4107 # number of ReadReq accesses(hits+misses)
227system.l2c.ReadReq_accesses::cpu0.itb.walker 1767 # number of ReadReq accesses(hits+misses)
228system.l2c.ReadReq_accesses::cpu0.inst 407292 # number of ReadReq accesses(hits+misses)
229system.l2c.ReadReq_accesses::cpu0.data 217184 # number of ReadReq accesses(hits+misses)
230system.l2c.ReadReq_accesses::cpu1.dtb.walker 5698 # number of ReadReq accesses(hits+misses)
231system.l2c.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses)
232system.l2c.ReadReq_accesses::cpu1.inst 453535 # number of ReadReq accesses(hits+misses)
233system.l2c.ReadReq_accesses::cpu1.data 149081 # number of ReadReq accesses(hits+misses)
234system.l2c.ReadReq_accesses::total 1240618 # number of ReadReq accesses(hits+misses)
235system.l2c.Writeback_accesses::writebacks 577354 # number of Writeback accesses(hits+misses)
236system.l2c.Writeback_accesses::total 577354 # number of Writeback accesses(hits+misses)
237system.l2c.UpgradeReq_accesses::cpu0.data 5863 # number of UpgradeReq accesses(hits+misses)
238system.l2c.UpgradeReq_accesses::cpu1.data 4171 # number of UpgradeReq accesses(hits+misses)
239system.l2c.UpgradeReq_accesses::total 10034 # number of UpgradeReq accesses(hits+misses)
240system.l2c.SCUpgradeReq_accesses::cpu0.data 790 # number of SCUpgradeReq accesses(hits+misses)
241system.l2c.SCUpgradeReq_accesses::cpu1.data 645 # number of SCUpgradeReq accesses(hits+misses)
242system.l2c.SCUpgradeReq_accesses::total 1435 # number of SCUpgradeReq accesses(hits+misses)
243system.l2c.ReadExReq_accesses::cpu0.data 124928 # number of ReadExReq accesses(hits+misses)
244system.l2c.ReadExReq_accesses::cpu1.data 125944 # number of ReadExReq accesses(hits+misses)
245system.l2c.ReadExReq_accesses::total 250872 # number of ReadExReq accesses(hits+misses)
246system.l2c.demand_accesses::cpu0.dtb.walker 4107 # number of demand (read+write) accesses
247system.l2c.demand_accesses::cpu0.itb.walker 1767 # number of demand (read+write) accesses
248system.l2c.demand_accesses::cpu0.inst 407292 # number of demand (read+write) accesses
249system.l2c.demand_accesses::cpu0.data 342112 # number of demand (read+write) accesses
250system.l2c.demand_accesses::cpu1.dtb.walker 5698 # number of demand (read+write) accesses
251system.l2c.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses
252system.l2c.demand_accesses::cpu1.inst 453535 # number of demand (read+write) accesses
253system.l2c.demand_accesses::cpu1.data 275025 # number of demand (read+write) accesses
254system.l2c.demand_accesses::total 1491490 # number of demand (read+write) accesses
255system.l2c.overall_accesses::cpu0.dtb.walker 4107 # number of overall (read+write) accesses
256system.l2c.overall_accesses::cpu0.itb.walker 1767 # number of overall (read+write) accesses
257system.l2c.overall_accesses::cpu0.inst 407292 # number of overall (read+write) accesses
258system.l2c.overall_accesses::cpu0.data 342112 # number of overall (read+write) accesses
259system.l2c.overall_accesses::cpu1.dtb.walker 5698 # number of overall (read+write) accesses
260system.l2c.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses
261system.l2c.overall_accesses::cpu1.inst 453535 # number of overall (read+write) accesses
262system.l2c.overall_accesses::cpu1.data 275025 # number of overall (read+write) accesses
263system.l2c.overall_accesses::total 1491490 # number of overall (read+write) accesses
264system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses
265system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses
266system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses
267system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses
268system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses
269system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses
270system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses
271system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses
|
| 272system.l2c.ReadReq_miss_rate::total 0.028163 # miss rate for ReadReq accesses
|
214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses
215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses
| 273system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses
274system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses
|
| 275system.l2c.UpgradeReq_miss_rate::total 0.826789 # miss rate for UpgradeReq accesses
|
216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses
217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses
| 276system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses
277system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses
|
| 278system.l2c.SCUpgradeReq_miss_rate::total 0.710105 # miss rate for SCUpgradeReq accesses
|
218system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses
219system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses
| 279system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses
280system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses
|
| 281system.l2c.ReadExReq_miss_rate::total 0.587311 # miss rate for ReadExReq accesses
|
220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses
221system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses
222system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses
223system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses
224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses
225system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses
226system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses
227system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses
| 282system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses
283system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses
284system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses
285system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses
286system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses
287system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses
288system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses
289system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses
|
| 290system.l2c.demand_miss_rate::total 0.122213 # miss rate for demand accesses
|
228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses
229system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses
230system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses
231system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses
232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses
233system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses
234system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses
235system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses
| 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses
292system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses
293system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses
294system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses
295system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses
296system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses
297system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses
298system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses
|
| 299system.l2c.overall_miss_rate::total 0.122213 # miss rate for overall accesses
|
236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency
238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency
239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency
240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency
241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency
243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency
| 300system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
301system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency
302system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency
303system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency
304system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency
305system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
306system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency
307system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency
|
| 308system.l2c.ReadReq_avg_miss_latency::total 52152.561534 # average ReadReq miss latency
|
244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency
245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency
| 309system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency
310system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency
|
| 311system.l2c.UpgradeReq_avg_miss_latency::total 7361.740598 # average UpgradeReq miss latency
|
246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency
247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency
| 312system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency
313system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency
|
| 314system.l2c.SCUpgradeReq_avg_miss_latency::total 8935.230618 # average SCUpgradeReq miss latency
|
248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency
249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency
| 315system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency
316system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency
|
| 317system.l2c.ReadExReq_avg_miss_latency::total 52082.720239 # average ReadExReq miss latency
|
250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
252system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
253system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
256system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
257system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
| 318system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
319system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
320system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
321system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
322system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
323system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
324system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
325system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
|
| 326system.l2c.demand_avg_miss_latency::total 52096.107637 # average overall miss latency
|
258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
260system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
261system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
264system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
265system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
| 327system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
328system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
329system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
330system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
331system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
332system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
333system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
334system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
|
| 335system.l2c.overall_avg_miss_latency::total 52096.107637 # average overall miss latency
|
266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
269system.l2c.blocked::no_targets 0 # number of cycles access was blocked
270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
272system.l2c.fast_writes 0 # number of fast writes performed
273system.l2c.cache_copies 0 # number of cache copies performed
274system.l2c.writebacks::writebacks 110181 # number of writebacks
275system.l2c.writebacks::total 110181 # number of writebacks
276system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
277system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
278system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
279system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
280system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
281system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
282system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses
283system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
284system.l2c.ReadReq_mshr_misses::cpu0.inst 7941 # number of ReadReq MSHR misses
285system.l2c.ReadReq_mshr_misses::cpu0.data 11318 # number of ReadReq MSHR misses
286system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses
287system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 5 # number of ReadReq MSHR misses
288system.l2c.ReadReq_mshr_misses::cpu1.inst 7342 # number of ReadReq MSHR misses
289system.l2c.ReadReq_mshr_misses::cpu1.data 8301 # number of ReadReq MSHR misses
290system.l2c.ReadReq_mshr_misses::total 34939 # number of ReadReq MSHR misses
291system.l2c.UpgradeReq_mshr_misses::cpu0.data 4674 # number of UpgradeReq MSHR misses
292system.l2c.UpgradeReq_mshr_misses::cpu1.data 3622 # number of UpgradeReq MSHR misses
293system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses
294system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 567 # number of SCUpgradeReq MSHR misses
295system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 452 # number of SCUpgradeReq MSHR misses
296system.l2c.SCUpgradeReq_mshr_misses::total 1019 # number of SCUpgradeReq MSHR misses
297system.l2c.ReadExReq_mshr_misses::cpu0.data 71101 # number of ReadExReq MSHR misses
298system.l2c.ReadExReq_mshr_misses::cpu1.data 76239 # number of ReadExReq MSHR misses
299system.l2c.ReadExReq_mshr_misses::total 147340 # number of ReadExReq MSHR misses
300system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses
301system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
302system.l2c.demand_mshr_misses::cpu0.inst 7941 # number of demand (read+write) MSHR misses
303system.l2c.demand_mshr_misses::cpu0.data 82419 # number of demand (read+write) MSHR misses
304system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses
305system.l2c.demand_mshr_misses::cpu1.itb.walker 5 # number of demand (read+write) MSHR misses
306system.l2c.demand_mshr_misses::cpu1.inst 7342 # number of demand (read+write) MSHR misses
307system.l2c.demand_mshr_misses::cpu1.data 84540 # number of demand (read+write) MSHR misses
308system.l2c.demand_mshr_misses::total 182279 # number of demand (read+write) MSHR misses
309system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses
310system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
311system.l2c.overall_mshr_misses::cpu0.inst 7941 # number of overall MSHR misses
312system.l2c.overall_mshr_misses::cpu0.data 82419 # number of overall MSHR misses
313system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses
314system.l2c.overall_mshr_misses::cpu1.itb.walker 5 # number of overall MSHR misses
315system.l2c.overall_mshr_misses::cpu1.inst 7342 # number of overall MSHR misses
316system.l2c.overall_mshr_misses::cpu1.data 84540 # number of overall MSHR misses
317system.l2c.overall_mshr_misses::total 182279 # number of overall MSHR misses
318system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles
319system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadReq MSHR miss cycles
320system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 318844000 # number of ReadReq MSHR miss cycles
321system.l2c.ReadReq_mshr_miss_latency::cpu0.data 453649000 # number of ReadReq MSHR miss cycles
322system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 724000 # number of ReadReq MSHR miss cycles
323system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 200000 # number of ReadReq MSHR miss cycles
324system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 295681000 # number of ReadReq MSHR miss cycles
325system.l2c.ReadReq_mshr_miss_latency::cpu1.data 333248000 # number of ReadReq MSHR miss cycles
326system.l2c.ReadReq_mshr_miss_latency::total 1402906000 # number of ReadReq MSHR miss cycles
327system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187154000 # number of UpgradeReq MSHR miss cycles
328system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 145115000 # number of UpgradeReq MSHR miss cycles
329system.l2c.UpgradeReq_mshr_miss_latency::total 332269000 # number of UpgradeReq MSHR miss cycles
330system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22686000 # number of SCUpgradeReq MSHR miss cycles
331system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18114000 # number of SCUpgradeReq MSHR miss cycles
332system.l2c.SCUpgradeReq_mshr_miss_latency::total 40800000 # number of SCUpgradeReq MSHR miss cycles
333system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2847286000 # number of ReadExReq MSHR miss cycles
334system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3058502000 # number of ReadExReq MSHR miss cycles
335system.l2c.ReadExReq_mshr_miss_latency::total 5905788000 # number of ReadExReq MSHR miss cycles
336system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles
337system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
338system.l2c.demand_mshr_miss_latency::cpu0.inst 318844000 # number of demand (read+write) MSHR miss cycles
339system.l2c.demand_mshr_miss_latency::cpu0.data 3300935000 # number of demand (read+write) MSHR miss cycles
340system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 724000 # number of demand (read+write) MSHR miss cycles
341system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
342system.l2c.demand_mshr_miss_latency::cpu1.inst 295681000 # number of demand (read+write) MSHR miss cycles
343system.l2c.demand_mshr_miss_latency::cpu1.data 3391750000 # number of demand (read+write) MSHR miss cycles
344system.l2c.demand_mshr_miss_latency::total 7308694000 # number of demand (read+write) MSHR miss cycles
345system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles
346system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles
347system.l2c.overall_mshr_miss_latency::cpu0.inst 318844000 # number of overall MSHR miss cycles
348system.l2c.overall_mshr_miss_latency::cpu0.data 3300935000 # number of overall MSHR miss cycles
349system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 724000 # number of overall MSHR miss cycles
350system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 200000 # number of overall MSHR miss cycles
351system.l2c.overall_mshr_miss_latency::cpu1.inst 295681000 # number of overall MSHR miss cycles
352system.l2c.overall_mshr_miss_latency::cpu1.data 3391750000 # number of overall MSHR miss cycles
353system.l2c.overall_mshr_miss_latency::total 7308694000 # number of overall MSHR miss cycles
354system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles
355system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9316699500 # number of ReadReq MSHR uncacheable cycles
356system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles
357system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122238098500 # number of ReadReq MSHR uncacheable cycles
358system.l2c.ReadReq_mshr_uncacheable_latency::total 131824279000 # number of ReadReq MSHR uncacheable cycles
359system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699595000 # number of WriteReq MSHR uncacheable cycles
360system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30626242500 # number of WriteReq MSHR uncacheable cycles
361system.l2c.WriteReq_mshr_uncacheable_latency::total 31325837500 # number of WriteReq MSHR uncacheable cycles
362system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles
363system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10016294500 # number of overall MSHR uncacheable cycles
364system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles
365system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles
366system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles
367system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses
368system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses
369system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses
370system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses
371system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses
372system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses
373system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses
374system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses
| 336system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
337system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
338system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
339system.l2c.blocked::no_targets 0 # number of cycles access was blocked
340system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
341system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
342system.l2c.fast_writes 0 # number of fast writes performed
343system.l2c.cache_copies 0 # number of cache copies performed
344system.l2c.writebacks::writebacks 110181 # number of writebacks
345system.l2c.writebacks::total 110181 # number of writebacks
346system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
347system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
348system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
349system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
350system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
351system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
352system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses
353system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
354system.l2c.ReadReq_mshr_misses::cpu0.inst 7941 # number of ReadReq MSHR misses
355system.l2c.ReadReq_mshr_misses::cpu0.data 11318 # number of ReadReq MSHR misses
356system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses
357system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 5 # number of ReadReq MSHR misses
358system.l2c.ReadReq_mshr_misses::cpu1.inst 7342 # number of ReadReq MSHR misses
359system.l2c.ReadReq_mshr_misses::cpu1.data 8301 # number of ReadReq MSHR misses
360system.l2c.ReadReq_mshr_misses::total 34939 # number of ReadReq MSHR misses
361system.l2c.UpgradeReq_mshr_misses::cpu0.data 4674 # number of UpgradeReq MSHR misses
362system.l2c.UpgradeReq_mshr_misses::cpu1.data 3622 # number of UpgradeReq MSHR misses
363system.l2c.UpgradeReq_mshr_misses::total 8296 # number of UpgradeReq MSHR misses
364system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 567 # number of SCUpgradeReq MSHR misses
365system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 452 # number of SCUpgradeReq MSHR misses
366system.l2c.SCUpgradeReq_mshr_misses::total 1019 # number of SCUpgradeReq MSHR misses
367system.l2c.ReadExReq_mshr_misses::cpu0.data 71101 # number of ReadExReq MSHR misses
368system.l2c.ReadExReq_mshr_misses::cpu1.data 76239 # number of ReadExReq MSHR misses
369system.l2c.ReadExReq_mshr_misses::total 147340 # number of ReadExReq MSHR misses
370system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses
371system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
372system.l2c.demand_mshr_misses::cpu0.inst 7941 # number of demand (read+write) MSHR misses
373system.l2c.demand_mshr_misses::cpu0.data 82419 # number of demand (read+write) MSHR misses
374system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses
375system.l2c.demand_mshr_misses::cpu1.itb.walker 5 # number of demand (read+write) MSHR misses
376system.l2c.demand_mshr_misses::cpu1.inst 7342 # number of demand (read+write) MSHR misses
377system.l2c.demand_mshr_misses::cpu1.data 84540 # number of demand (read+write) MSHR misses
378system.l2c.demand_mshr_misses::total 182279 # number of demand (read+write) MSHR misses
379system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses
380system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
381system.l2c.overall_mshr_misses::cpu0.inst 7941 # number of overall MSHR misses
382system.l2c.overall_mshr_misses::cpu0.data 82419 # number of overall MSHR misses
383system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses
384system.l2c.overall_mshr_misses::cpu1.itb.walker 5 # number of overall MSHR misses
385system.l2c.overall_mshr_misses::cpu1.inst 7342 # number of overall MSHR misses
386system.l2c.overall_mshr_misses::cpu1.data 84540 # number of overall MSHR misses
387system.l2c.overall_mshr_misses::total 182279 # number of overall MSHR misses
388system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles
389system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadReq MSHR miss cycles
390system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 318844000 # number of ReadReq MSHR miss cycles
391system.l2c.ReadReq_mshr_miss_latency::cpu0.data 453649000 # number of ReadReq MSHR miss cycles
392system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 724000 # number of ReadReq MSHR miss cycles
393system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 200000 # number of ReadReq MSHR miss cycles
394system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 295681000 # number of ReadReq MSHR miss cycles
395system.l2c.ReadReq_mshr_miss_latency::cpu1.data 333248000 # number of ReadReq MSHR miss cycles
396system.l2c.ReadReq_mshr_miss_latency::total 1402906000 # number of ReadReq MSHR miss cycles
397system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187154000 # number of UpgradeReq MSHR miss cycles
398system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 145115000 # number of UpgradeReq MSHR miss cycles
399system.l2c.UpgradeReq_mshr_miss_latency::total 332269000 # number of UpgradeReq MSHR miss cycles
400system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22686000 # number of SCUpgradeReq MSHR miss cycles
401system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18114000 # number of SCUpgradeReq MSHR miss cycles
402system.l2c.SCUpgradeReq_mshr_miss_latency::total 40800000 # number of SCUpgradeReq MSHR miss cycles
403system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2847286000 # number of ReadExReq MSHR miss cycles
404system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3058502000 # number of ReadExReq MSHR miss cycles
405system.l2c.ReadExReq_mshr_miss_latency::total 5905788000 # number of ReadExReq MSHR miss cycles
406system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles
407system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
408system.l2c.demand_mshr_miss_latency::cpu0.inst 318844000 # number of demand (read+write) MSHR miss cycles
409system.l2c.demand_mshr_miss_latency::cpu0.data 3300935000 # number of demand (read+write) MSHR miss cycles
410system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 724000 # number of demand (read+write) MSHR miss cycles
411system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
412system.l2c.demand_mshr_miss_latency::cpu1.inst 295681000 # number of demand (read+write) MSHR miss cycles
413system.l2c.demand_mshr_miss_latency::cpu1.data 3391750000 # number of demand (read+write) MSHR miss cycles
414system.l2c.demand_mshr_miss_latency::total 7308694000 # number of demand (read+write) MSHR miss cycles
415system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles
416system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles
417system.l2c.overall_mshr_miss_latency::cpu0.inst 318844000 # number of overall MSHR miss cycles
418system.l2c.overall_mshr_miss_latency::cpu0.data 3300935000 # number of overall MSHR miss cycles
419system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 724000 # number of overall MSHR miss cycles
420system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 200000 # number of overall MSHR miss cycles
421system.l2c.overall_mshr_miss_latency::cpu1.inst 295681000 # number of overall MSHR miss cycles
422system.l2c.overall_mshr_miss_latency::cpu1.data 3391750000 # number of overall MSHR miss cycles
423system.l2c.overall_mshr_miss_latency::total 7308694000 # number of overall MSHR miss cycles
424system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles
425system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9316699500 # number of ReadReq MSHR uncacheable cycles
426system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles
427system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122238098500 # number of ReadReq MSHR uncacheable cycles
428system.l2c.ReadReq_mshr_uncacheable_latency::total 131824279000 # number of ReadReq MSHR uncacheable cycles
429system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 699595000 # number of WriteReq MSHR uncacheable cycles
430system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30626242500 # number of WriteReq MSHR uncacheable cycles
431system.l2c.WriteReq_mshr_uncacheable_latency::total 31325837500 # number of WriteReq MSHR uncacheable cycles
432system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles
433system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10016294500 # number of overall MSHR uncacheable cycles
434system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles
435system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles
436system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles
437system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses
438system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses
439system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses
440system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses
441system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses
442system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses
443system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses
444system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses
|
| 445system.l2c.ReadReq_mshr_miss_rate::total 0.028163 # mshr miss rate for ReadReq accesses
|
375system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses
376system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses
| 446system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses
447system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses
|
| 448system.l2c.UpgradeReq_mshr_miss_rate::total 0.826789 # mshr miss rate for UpgradeReq accesses
|
377system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses
378system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses
| 449system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses
450system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses
|
| 451system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710105 # mshr miss rate for SCUpgradeReq accesses
|
379system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses
380system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses
| 452system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses
453system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses
|
| 454system.l2c.ReadExReq_mshr_miss_rate::total 0.587311 # mshr miss rate for ReadExReq accesses
|
381system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses
382system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses
383system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses
384system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses
385system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses
386system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses
387system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses
388system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses
| 455system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses
456system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses
457system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses
458system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses
459system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses
460system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses
461system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses
462system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses
|
| 463system.l2c.demand_mshr_miss_rate::total 0.122213 # mshr miss rate for demand accesses
|
389system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses
390system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses
391system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses
392system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses
393system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses
394system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses
395system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses
396system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses
| 464system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses
465system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses
466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses
467system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses
468system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses
469system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses
470system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses
471system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses
|
| 472system.l2c.overall_mshr_miss_rate::total 0.122213 # mshr miss rate for overall accesses
|
397system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
398system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
399system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency
400system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency
401system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency
402system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
403system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency
404system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency
| 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
474system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
475system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency
476system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency
477system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency
478system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
479system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency
480system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency
|
| 481system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531 # average ReadReq mshr miss latency
|
405system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency
406system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency
| 482system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency
483system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency
|
| 484system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668 # average UpgradeReq mshr miss latency
|
407system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency
408system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency
| 485system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency
486system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency
|
| 487system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171 # average SCUpgradeReq mshr miss latency
|
409system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency
410system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency
| 488system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency
489system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency
|
| 490system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239 # average ReadExReq mshr miss latency
|
411system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
412system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
413system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
414system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
415system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
416system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
417system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
418system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
| 491system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
492system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
493system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
494system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
495system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
496system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
497system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
498system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
|
| 499system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency
|
419system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
420system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
421system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
422system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
423system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
424system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
425system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
426system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
| 500system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
501system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
502system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
503system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
504system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
505system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
506system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
507system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
|
| 508system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency
|
427system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
428system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
429system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
430system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
| 509system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
510system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
511system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
512system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
| 513system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
431system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
432system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
| 514system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
515system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
| 516system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
433system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
434system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
435system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
436system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
| 517system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
518system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
519system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
520system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
| 521system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
437system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
438system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
439system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
440system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
441system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
442system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
443system.cf0.dma_write_txs 0 # Number of DMA write transactions.
444system.cpu0.dtb.inst_hits 0 # ITB inst hits
445system.cpu0.dtb.inst_misses 0 # ITB inst misses
446system.cpu0.dtb.read_hits 7070142 # DTB read hits
447system.cpu0.dtb.read_misses 3739 # DTB read misses
448system.cpu0.dtb.write_hits 5655287 # DTB write hits
449system.cpu0.dtb.write_misses 802 # DTB write misses
450system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
451system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
452system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
453system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
454system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB
455system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
456system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
457system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
458system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
459system.cpu0.dtb.read_accesses 7073881 # DTB read accesses
460system.cpu0.dtb.write_accesses 5656089 # DTB write accesses
461system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
462system.cpu0.dtb.hits 12725429 # DTB hits
463system.cpu0.dtb.misses 4541 # DTB misses
464system.cpu0.dtb.accesses 12729970 # DTB accesses
465system.cpu0.itb.inst_hits 29439632 # ITB inst hits
466system.cpu0.itb.inst_misses 2205 # ITB inst misses
467system.cpu0.itb.read_hits 0 # DTB read hits
468system.cpu0.itb.read_misses 0 # DTB read misses
469system.cpu0.itb.write_hits 0 # DTB write hits
470system.cpu0.itb.write_misses 0 # DTB write misses
471system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
472system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
473system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
474system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
475system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
476system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
477system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
478system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
479system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
480system.cpu0.itb.read_accesses 0 # DTB read accesses
481system.cpu0.itb.write_accesses 0 # DTB write accesses
482system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses
483system.cpu0.itb.hits 29439632 # DTB hits
484system.cpu0.itb.misses 2205 # DTB misses
485system.cpu0.itb.accesses 29441837 # DTB accesses
486system.cpu0.numCycles 2339414086 # number of cpu cycles simulated
487system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
488system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
489system.cpu0.committedInsts 28747266 # Number of instructions committed
490system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed
491system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses
492system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
493system.cpu0.num_func_calls 1116936 # number of times a function call or return occured
494system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls
495system.cpu0.num_int_insts 33031535 # number of integer instructions
496system.cpu0.num_fp_insts 3860 # number of float instructions
497system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read
498system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written
499system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
500system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
501system.cpu0.num_mem_refs 13393398 # number of memory refs
502system.cpu0.num_load_insts 7407664 # Number of load instructions
503system.cpu0.num_store_insts 5985734 # Number of store instructions
504system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles
505system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles
506system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles
507system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles
508system.cpu0.kern.inst.arm 0 # number of arm instructions executed
509system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed
510system.cpu0.icache.replacements 408172 # number of replacements
511system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use
512system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks.
513system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks.
514system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks.
515system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit.
516system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor
517system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy
518system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy
519system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits
520system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits
521system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits
522system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits
523system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits
524system.cpu0.icache.overall_hits::total 29030930 # number of overall hits
525system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses
526system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses
527system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses
528system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses
529system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses
530system.cpu0.icache.overall_misses::total 408685 # number of overall misses
531system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles
532system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles
533system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles
534system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles
535system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles
536system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles
537system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses)
538system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses)
539system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses
540system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses
541system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses
542system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses
543system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses
| 522system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
523system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
524system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
525system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
526system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
527system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
528system.cf0.dma_write_txs 0 # Number of DMA write transactions.
529system.cpu0.dtb.inst_hits 0 # ITB inst hits
530system.cpu0.dtb.inst_misses 0 # ITB inst misses
531system.cpu0.dtb.read_hits 7070142 # DTB read hits
532system.cpu0.dtb.read_misses 3739 # DTB read misses
533system.cpu0.dtb.write_hits 5655287 # DTB write hits
534system.cpu0.dtb.write_misses 802 # DTB write misses
535system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
536system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
537system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
538system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
539system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB
540system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
541system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
542system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
543system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
544system.cpu0.dtb.read_accesses 7073881 # DTB read accesses
545system.cpu0.dtb.write_accesses 5656089 # DTB write accesses
546system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
547system.cpu0.dtb.hits 12725429 # DTB hits
548system.cpu0.dtb.misses 4541 # DTB misses
549system.cpu0.dtb.accesses 12729970 # DTB accesses
550system.cpu0.itb.inst_hits 29439632 # ITB inst hits
551system.cpu0.itb.inst_misses 2205 # ITB inst misses
552system.cpu0.itb.read_hits 0 # DTB read hits
553system.cpu0.itb.read_misses 0 # DTB read misses
554system.cpu0.itb.write_hits 0 # DTB write hits
555system.cpu0.itb.write_misses 0 # DTB write misses
556system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
558system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
559system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
560system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
564system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
565system.cpu0.itb.read_accesses 0 # DTB read accesses
566system.cpu0.itb.write_accesses 0 # DTB write accesses
567system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses
568system.cpu0.itb.hits 29439632 # DTB hits
569system.cpu0.itb.misses 2205 # DTB misses
570system.cpu0.itb.accesses 29441837 # DTB accesses
571system.cpu0.numCycles 2339414086 # number of cpu cycles simulated
572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
574system.cpu0.committedInsts 28747266 # Number of instructions committed
575system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed
576system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses
577system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
578system.cpu0.num_func_calls 1116936 # number of times a function call or return occured
579system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls
580system.cpu0.num_int_insts 33031535 # number of integer instructions
581system.cpu0.num_fp_insts 3860 # number of float instructions
582system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read
583system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written
584system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
585system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
586system.cpu0.num_mem_refs 13393398 # number of memory refs
587system.cpu0.num_load_insts 7407664 # Number of load instructions
588system.cpu0.num_store_insts 5985734 # Number of store instructions
589system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles
590system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles
591system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles
592system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles
593system.cpu0.kern.inst.arm 0 # number of arm instructions executed
594system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed
595system.cpu0.icache.replacements 408172 # number of replacements
596system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use
597system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks.
598system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks.
599system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks.
600system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit.
601system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor
602system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy
603system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy
604system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits
605system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits
606system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits
607system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits
608system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits
609system.cpu0.icache.overall_hits::total 29030930 # number of overall hits
610system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses
611system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses
612system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses
613system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses
614system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses
615system.cpu0.icache.overall_misses::total 408685 # number of overall misses
616system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles
617system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles
618system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles
619system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles
620system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles
621system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles
622system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses)
623system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses)
624system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses
625system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses
626system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses
627system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses
628system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses
|
| 629system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses
|
544system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses
| 630system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses
|
| 631system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses
|
545system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses
| 632system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses
|
| 633system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses
|
546system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency
| 634system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency
|
| 635system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency
|
547system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
| 636system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
|
| 637system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency
|
548system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
| 638system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
|
| 639system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency
|
549system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
552system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
553system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555system.cpu0.icache.fast_writes 0 # number of fast writes performed
556system.cpu0.icache.cache_copies 0 # number of cache copies performed
557system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks
558system.cpu0.icache.writebacks::total 16458 # number of writebacks
559system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses
560system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses
561system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses
562system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses
563system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses
564system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses
565system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles
566system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles
567system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles
568system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles
569system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles
570system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles
571system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
572system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
573system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
574system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
575system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses
| 640system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
641system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
642system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
643system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
644system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
645system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
646system.cpu0.icache.fast_writes 0 # number of fast writes performed
647system.cpu0.icache.cache_copies 0 # number of cache copies performed
648system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks
649system.cpu0.icache.writebacks::total 16458 # number of writebacks
650system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses
651system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses
652system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses
653system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses
654system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses
655system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses
656system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles
657system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles
658system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles
659system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles
660system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles
661system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles
662system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
663system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
664system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
665system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
666system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses
|
| 667system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses
|
576system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses
| 668system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses
|
| 669system.cpu0.icache.demand_mshr_miss_rate::total 0.013882 # mshr miss rate for demand accesses
|
577system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses
| 670system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses
|
| 671system.cpu0.icache.overall_mshr_miss_rate::total 0.013882 # mshr miss rate for overall accesses
|
578system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency
| 672system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency
|
| 673system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947 # average ReadReq mshr miss latency
|
579system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
| 674system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
|
| 675system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency
|
580system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
| 676system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
|
| 677system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency
|
581system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
| 678system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
| 679system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
582system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
| 680system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
| 681system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
583system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
584system.cpu0.dcache.replacements 335831 # number of replacements
585system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use
586system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks.
587system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks.
588system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks.
589system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
590system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor
591system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy
592system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy
593system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # number of ReadReq hits
594system.cpu0.dcache.ReadReq_hits::total 6596660 # number of ReadReq hits
595system.cpu0.dcache.WriteReq_hits::cpu0.data 5349249 # number of WriteReq hits
596system.cpu0.dcache.WriteReq_hits::total 5349249 # number of WriteReq hits
597system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147717 # number of LoadLockedReq hits
598system.cpu0.dcache.LoadLockedReq_hits::total 147717 # number of LoadLockedReq hits
599system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149695 # number of StoreCondReq hits
600system.cpu0.dcache.StoreCondReq_hits::total 149695 # number of StoreCondReq hits
601system.cpu0.dcache.demand_hits::cpu0.data 11945909 # number of demand (read+write) hits
602system.cpu0.dcache.demand_hits::total 11945909 # number of demand (read+write) hits
603system.cpu0.dcache.overall_hits::cpu0.data 11945909 # number of overall hits
604system.cpu0.dcache.overall_hits::total 11945909 # number of overall hits
605system.cpu0.dcache.ReadReq_misses::cpu0.data 231189 # number of ReadReq misses
606system.cpu0.dcache.ReadReq_misses::total 231189 # number of ReadReq misses
607system.cpu0.dcache.WriteReq_misses::cpu0.data 142616 # number of WriteReq misses
608system.cpu0.dcache.WriteReq_misses::total 142616 # number of WriteReq misses
609system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9505 # number of LoadLockedReq misses
610system.cpu0.dcache.LoadLockedReq_misses::total 9505 # number of LoadLockedReq misses
611system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses
612system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses
613system.cpu0.dcache.demand_misses::cpu0.data 373805 # number of demand (read+write) misses
614system.cpu0.dcache.demand_misses::total 373805 # number of demand (read+write) misses
615system.cpu0.dcache.overall_misses::cpu0.data 373805 # number of overall misses
616system.cpu0.dcache.overall_misses::total 373805 # number of overall misses
617system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3541904000 # number of ReadReq miss cycles
618system.cpu0.dcache.ReadReq_miss_latency::total 3541904000 # number of ReadReq miss cycles
619system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5075999000 # number of WriteReq miss cycles
620system.cpu0.dcache.WriteReq_miss_latency::total 5075999000 # number of WriteReq miss cycles
621system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104931000 # number of LoadLockedReq miss cycles
622system.cpu0.dcache.LoadLockedReq_miss_latency::total 104931000 # number of LoadLockedReq miss cycles
623system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68264000 # number of StoreCondReq miss cycles
624system.cpu0.dcache.StoreCondReq_miss_latency::total 68264000 # number of StoreCondReq miss cycles
625system.cpu0.dcache.demand_miss_latency::cpu0.data 8617903000 # number of demand (read+write) miss cycles
626system.cpu0.dcache.demand_miss_latency::total 8617903000 # number of demand (read+write) miss cycles
627system.cpu0.dcache.overall_miss_latency::cpu0.data 8617903000 # number of overall miss cycles
628system.cpu0.dcache.overall_miss_latency::total 8617903000 # number of overall miss cycles
629system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827849 # number of ReadReq accesses(hits+misses)
630system.cpu0.dcache.ReadReq_accesses::total 6827849 # number of ReadReq accesses(hits+misses)
631system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491865 # number of WriteReq accesses(hits+misses)
632system.cpu0.dcache.WriteReq_accesses::total 5491865 # number of WriteReq accesses(hits+misses)
633system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157222 # number of LoadLockedReq accesses(hits+misses)
634system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses)
635system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses)
636system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses)
637system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses
638system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses
639system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses
640system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses
641system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses
| 682system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
683system.cpu0.dcache.replacements 335831 # number of replacements
684system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use
685system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks.
686system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks.
687system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks.
688system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
689system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor
690system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy
691system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy
692system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # number of ReadReq hits
693system.cpu0.dcache.ReadReq_hits::total 6596660 # number of ReadReq hits
694system.cpu0.dcache.WriteReq_hits::cpu0.data 5349249 # number of WriteReq hits
695system.cpu0.dcache.WriteReq_hits::total 5349249 # number of WriteReq hits
696system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147717 # number of LoadLockedReq hits
697system.cpu0.dcache.LoadLockedReq_hits::total 147717 # number of LoadLockedReq hits
698system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149695 # number of StoreCondReq hits
699system.cpu0.dcache.StoreCondReq_hits::total 149695 # number of StoreCondReq hits
700system.cpu0.dcache.demand_hits::cpu0.data 11945909 # number of demand (read+write) hits
701system.cpu0.dcache.demand_hits::total 11945909 # number of demand (read+write) hits
702system.cpu0.dcache.overall_hits::cpu0.data 11945909 # number of overall hits
703system.cpu0.dcache.overall_hits::total 11945909 # number of overall hits
704system.cpu0.dcache.ReadReq_misses::cpu0.data 231189 # number of ReadReq misses
705system.cpu0.dcache.ReadReq_misses::total 231189 # number of ReadReq misses
706system.cpu0.dcache.WriteReq_misses::cpu0.data 142616 # number of WriteReq misses
707system.cpu0.dcache.WriteReq_misses::total 142616 # number of WriteReq misses
708system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9505 # number of LoadLockedReq misses
709system.cpu0.dcache.LoadLockedReq_misses::total 9505 # number of LoadLockedReq misses
710system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses
711system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses
712system.cpu0.dcache.demand_misses::cpu0.data 373805 # number of demand (read+write) misses
713system.cpu0.dcache.demand_misses::total 373805 # number of demand (read+write) misses
714system.cpu0.dcache.overall_misses::cpu0.data 373805 # number of overall misses
715system.cpu0.dcache.overall_misses::total 373805 # number of overall misses
716system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3541904000 # number of ReadReq miss cycles
717system.cpu0.dcache.ReadReq_miss_latency::total 3541904000 # number of ReadReq miss cycles
718system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5075999000 # number of WriteReq miss cycles
719system.cpu0.dcache.WriteReq_miss_latency::total 5075999000 # number of WriteReq miss cycles
720system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104931000 # number of LoadLockedReq miss cycles
721system.cpu0.dcache.LoadLockedReq_miss_latency::total 104931000 # number of LoadLockedReq miss cycles
722system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68264000 # number of StoreCondReq miss cycles
723system.cpu0.dcache.StoreCondReq_miss_latency::total 68264000 # number of StoreCondReq miss cycles
724system.cpu0.dcache.demand_miss_latency::cpu0.data 8617903000 # number of demand (read+write) miss cycles
725system.cpu0.dcache.demand_miss_latency::total 8617903000 # number of demand (read+write) miss cycles
726system.cpu0.dcache.overall_miss_latency::cpu0.data 8617903000 # number of overall miss cycles
727system.cpu0.dcache.overall_miss_latency::total 8617903000 # number of overall miss cycles
728system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827849 # number of ReadReq accesses(hits+misses)
729system.cpu0.dcache.ReadReq_accesses::total 6827849 # number of ReadReq accesses(hits+misses)
730system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491865 # number of WriteReq accesses(hits+misses)
731system.cpu0.dcache.WriteReq_accesses::total 5491865 # number of WriteReq accesses(hits+misses)
732system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157222 # number of LoadLockedReq accesses(hits+misses)
733system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses)
734system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses)
735system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses)
736system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses
737system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses
738system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses
739system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses
740system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses
|
| 741system.cpu0.dcache.ReadReq_miss_rate::total 0.033860 # miss rate for ReadReq accesses
|
642system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses
| 742system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses
|
| 743system.cpu0.dcache.WriteReq_miss_rate::total 0.025969 # miss rate for WriteReq accesses
|
643system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses
| 744system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses
|
| 745system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060456 # miss rate for LoadLockedReq accesses
|
644system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses
| 746system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses
|
| 747system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047493 # miss rate for StoreCondReq accesses
|
645system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses
| 748system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses
|
| 749system.cpu0.dcache.demand_miss_rate::total 0.030342 # miss rate for demand accesses
|
646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses
| 750system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses
|
| 751system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses
|
647system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency
| 752system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency
|
| 753system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency
|
648system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency
| 754system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency
|
| 755system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency
|
649system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency
| 756system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency
|
| 757system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency
|
650system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency
| 758system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency
|
| 759system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency
|
651system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
| 760system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
|
| 761system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency
|
652system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
| 762system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
|
| 763system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency
|
653system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
654system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
655system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
656system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
657system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
658system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
659system.cpu0.dcache.fast_writes 0 # number of fast writes performed
660system.cpu0.dcache.cache_copies 0 # number of cache copies performed
661system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks
662system.cpu0.dcache.writebacks::total 287163 # number of writebacks
663system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses
664system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses
665system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses
666system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses
667system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses
668system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses
669system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses
670system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses
671system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses
672system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses
673system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses
674system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses
675system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles
676system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles
677system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles
678system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles
679system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles
680system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles
681system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles
682system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles
683system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles
684system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles
685system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles
686system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles
687system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles
688system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles
689system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles
690system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles
691system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles
692system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles
693system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses
| 764system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
765system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
766system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
767system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
768system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
769system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
770system.cpu0.dcache.fast_writes 0 # number of fast writes performed
771system.cpu0.dcache.cache_copies 0 # number of cache copies performed
772system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks
773system.cpu0.dcache.writebacks::total 287163 # number of writebacks
774system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses
775system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses
776system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses
777system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses
778system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses
779system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses
780system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses
781system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses
782system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses
783system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses
784system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses
785system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses
786system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles
787system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles
788system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles
789system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles
790system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles
791system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles
792system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles
793system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles
794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles
795system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles
796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles
797system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles
798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles
799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles
800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles
801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles
802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles
803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles
804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses
|
| 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses
|
694system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses
| 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses
|
| 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses
|
695system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses
| 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses
|
| 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses
|
696system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses
| 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses
|
| 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses
|
697system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses
| 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses
|
| 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses
|
698system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses
| 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses
|
| 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses
|
699system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency
| 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency
|
| 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency
|
700system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency
| 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency
|
| 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency
|
701system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency
| 820system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency
|
| 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency
|
702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency
| 822system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency
|
| 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency
|
703system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
| 824system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
|
| 825system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency
|
704system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
| 826system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
|
| 827system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency
|
705system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
| 828system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
| 829system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
706system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
| 830system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
| 831system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
707system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
| 832system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
| 833system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
708system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
709system.cpu1.dtb.inst_hits 0 # ITB inst hits
710system.cpu1.dtb.inst_misses 0 # ITB inst misses
711system.cpu1.dtb.read_hits 8313009 # DTB read hits
712system.cpu1.dtb.read_misses 3663 # DTB read misses
713system.cpu1.dtb.write_hits 5829499 # DTB write hits
714system.cpu1.dtb.write_misses 1439 # DTB write misses
715system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
716system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
717system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
718system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
719system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB
720system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
721system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
722system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
723system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
724system.cpu1.dtb.read_accesses 8316672 # DTB read accesses
725system.cpu1.dtb.write_accesses 5830938 # DTB write accesses
726system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
727system.cpu1.dtb.hits 14142508 # DTB hits
728system.cpu1.dtb.misses 5102 # DTB misses
729system.cpu1.dtb.accesses 14147610 # DTB accesses
730system.cpu1.itb.inst_hits 32286240 # ITB inst hits
731system.cpu1.itb.inst_misses 2171 # ITB inst misses
732system.cpu1.itb.read_hits 0 # DTB read hits
733system.cpu1.itb.read_misses 0 # DTB read misses
734system.cpu1.itb.write_hits 0 # DTB write hits
735system.cpu1.itb.write_misses 0 # DTB write misses
736system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
737system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
738system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
739system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
740system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
741system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
742system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
743system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
744system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
745system.cpu1.itb.read_accesses 0 # DTB read accesses
746system.cpu1.itb.write_accesses 0 # DTB write accesses
747system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses
748system.cpu1.itb.hits 32286240 # DTB hits
749system.cpu1.itb.misses 2171 # DTB misses
750system.cpu1.itb.accesses 32288411 # DTB accesses
751system.cpu1.numCycles 2338003468 # number of cpu cycles simulated
752system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
753system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
754system.cpu1.committedInsts 31682438 # Number of instructions committed
755system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed
756system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses
757system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
758system.cpu1.num_func_calls 909270 # number of times a function call or return occured
759system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls
760system.cpu1.num_int_insts 36868206 # number of integer instructions
761system.cpu1.num_fp_insts 6793 # number of float instructions
762system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read
763system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written
764system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
765system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
766system.cpu1.num_mem_refs 14680299 # number of memory refs
767system.cpu1.num_load_insts 8634860 # Number of load instructions
768system.cpu1.num_store_insts 6045439 # Number of store instructions
769system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles
770system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles
771system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles
772system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles
773system.cpu1.kern.inst.arm 0 # number of arm instructions executed
774system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed
775system.cpu1.icache.replacements 454317 # number of replacements
776system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use
777system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks.
778system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks.
779system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks.
780system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit.
781system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor
782system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy
783system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy
784system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits
785system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits
786system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits
787system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits
788system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits
789system.cpu1.icache.overall_hits::total 31831407 # number of overall hits
790system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses
791system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses
792system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses
793system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses
794system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses
795system.cpu1.icache.overall_misses::total 454829 # number of overall misses
796system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles
797system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles
798system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles
799system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles
800system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles
801system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles
802system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses)
803system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses)
804system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses
805system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses
806system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses
807system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses
808system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses
| 834system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
835system.cpu1.dtb.inst_hits 0 # ITB inst hits
836system.cpu1.dtb.inst_misses 0 # ITB inst misses
837system.cpu1.dtb.read_hits 8313009 # DTB read hits
838system.cpu1.dtb.read_misses 3663 # DTB read misses
839system.cpu1.dtb.write_hits 5829499 # DTB write hits
840system.cpu1.dtb.write_misses 1439 # DTB write misses
841system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
842system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
843system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
844system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
845system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB
846system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
847system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch
848system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
849system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
850system.cpu1.dtb.read_accesses 8316672 # DTB read accesses
851system.cpu1.dtb.write_accesses 5830938 # DTB write accesses
852system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
853system.cpu1.dtb.hits 14142508 # DTB hits
854system.cpu1.dtb.misses 5102 # DTB misses
855system.cpu1.dtb.accesses 14147610 # DTB accesses
856system.cpu1.itb.inst_hits 32286240 # ITB inst hits
857system.cpu1.itb.inst_misses 2171 # ITB inst misses
858system.cpu1.itb.read_hits 0 # DTB read hits
859system.cpu1.itb.read_misses 0 # DTB read misses
860system.cpu1.itb.write_hits 0 # DTB write hits
861system.cpu1.itb.write_misses 0 # DTB write misses
862system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
863system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
864system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
865system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
866system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
867system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
868system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
869system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
870system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
871system.cpu1.itb.read_accesses 0 # DTB read accesses
872system.cpu1.itb.write_accesses 0 # DTB write accesses
873system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses
874system.cpu1.itb.hits 32286240 # DTB hits
875system.cpu1.itb.misses 2171 # DTB misses
876system.cpu1.itb.accesses 32288411 # DTB accesses
877system.cpu1.numCycles 2338003468 # number of cpu cycles simulated
878system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
879system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
880system.cpu1.committedInsts 31682438 # Number of instructions committed
881system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed
882system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses
883system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
884system.cpu1.num_func_calls 909270 # number of times a function call or return occured
885system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls
886system.cpu1.num_int_insts 36868206 # number of integer instructions
887system.cpu1.num_fp_insts 6793 # number of float instructions
888system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read
889system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written
890system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
891system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
892system.cpu1.num_mem_refs 14680299 # number of memory refs
893system.cpu1.num_load_insts 8634860 # Number of load instructions
894system.cpu1.num_store_insts 6045439 # Number of store instructions
895system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles
896system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles
897system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles
898system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles
899system.cpu1.kern.inst.arm 0 # number of arm instructions executed
900system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed
901system.cpu1.icache.replacements 454317 # number of replacements
902system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use
903system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks.
904system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks.
905system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks.
906system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit.
907system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor
908system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy
909system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy
910system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits
911system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits
912system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits
913system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits
914system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits
915system.cpu1.icache.overall_hits::total 31831407 # number of overall hits
916system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses
917system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses
918system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses
919system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses
920system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses
921system.cpu1.icache.overall_misses::total 454829 # number of overall misses
922system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles
923system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles
924system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles
925system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles
926system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles
927system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles
928system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses)
929system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses)
930system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses
931system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses
932system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses
933system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses
934system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses
|
| 935system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses
|
809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses
| 936system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses
|
| 937system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses
|
810system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses
| 938system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses
|
| 939system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses
|
811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency
| 940system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency
|
| 941system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency
|
812system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
| 942system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
|
| 943system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency
|
813system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
| 944system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
|
| 945system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency
|
814system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
815system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
816system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
817system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
818system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
819system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
820system.cpu1.icache.fast_writes 0 # number of fast writes performed
821system.cpu1.icache.cache_copies 0 # number of cache copies performed
822system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks
823system.cpu1.icache.writebacks::total 19149 # number of writebacks
824system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses
825system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses
826system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses
827system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses
828system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses
829system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses
830system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles
831system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles
832system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles
833system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles
834system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles
835system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles
836system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
838system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
839system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
840system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses
| 946system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
947system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
948system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
949system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
950system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
951system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
952system.cpu1.icache.fast_writes 0 # number of fast writes performed
953system.cpu1.icache.cache_copies 0 # number of cache copies performed
954system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks
955system.cpu1.icache.writebacks::total 19149 # number of writebacks
956system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses
957system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses
958system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses
959system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses
960system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses
961system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses
962system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles
963system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles
964system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles
965system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles
966system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles
967system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles
968system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
969system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
970system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
971system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
972system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses
|
| 973system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses
|
841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses
| 974system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses
|
| 975system.cpu1.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses
|
842system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses
| 976system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses
|
| 977system.cpu1.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses
|
843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency
| 978system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency
|
| 979system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965 # average ReadReq mshr miss latency
|
844system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
| 980system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
|
| 981system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency
|
845system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
| 982system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
|
| 983system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency
|
846system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
| 984system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
| 985system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
847system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
| 986system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
| 987system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
848system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
849system.cpu1.dcache.replacements 294642 # number of replacements
850system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use
851system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks.
852system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks.
853system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks.
854system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit.
855system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor
856system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy
857system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy
858system.cpu1.dcache.ReadReq_hits::cpu1.data 6946891 # number of ReadReq hits
859system.cpu1.dcache.ReadReq_hits::total 6946891 # number of ReadReq hits
860system.cpu1.dcache.WriteReq_hits::cpu1.data 4828705 # number of WriteReq hits
861system.cpu1.dcache.WriteReq_hits::total 4828705 # number of WriteReq hits
862system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81776 # number of LoadLockedReq hits
863system.cpu1.dcache.LoadLockedReq_hits::total 81776 # number of LoadLockedReq hits
864system.cpu1.dcache.StoreCondReq_hits::cpu1.data 83111 # number of StoreCondReq hits
865system.cpu1.dcache.StoreCondReq_hits::total 83111 # number of StoreCondReq hits
866system.cpu1.dcache.demand_hits::cpu1.data 11775596 # number of demand (read+write) hits
867system.cpu1.dcache.demand_hits::total 11775596 # number of demand (read+write) hits
868system.cpu1.dcache.overall_hits::cpu1.data 11775596 # number of overall hits
869system.cpu1.dcache.overall_hits::total 11775596 # number of overall hits
870system.cpu1.dcache.ReadReq_misses::cpu1.data 172105 # number of ReadReq misses
871system.cpu1.dcache.ReadReq_misses::total 172105 # number of ReadReq misses
872system.cpu1.dcache.WriteReq_misses::cpu1.data 150416 # number of WriteReq misses
873system.cpu1.dcache.WriteReq_misses::total 150416 # number of WriteReq misses
874system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11123 # number of LoadLockedReq misses
875system.cpu1.dcache.LoadLockedReq_misses::total 11123 # number of LoadLockedReq misses
876system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9715 # number of StoreCondReq misses
877system.cpu1.dcache.StoreCondReq_misses::total 9715 # number of StoreCondReq misses
878system.cpu1.dcache.demand_misses::cpu1.data 322521 # number of demand (read+write) misses
879system.cpu1.dcache.demand_misses::total 322521 # number of demand (read+write) misses
880system.cpu1.dcache.overall_misses::cpu1.data 322521 # number of overall misses
881system.cpu1.dcache.overall_misses::total 322521 # number of overall misses
882system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2496186500 # number of ReadReq miss cycles
883system.cpu1.dcache.ReadReq_miss_latency::total 2496186500 # number of ReadReq miss cycles
884system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5287724000 # number of WriteReq miss cycles
885system.cpu1.dcache.WriteReq_miss_latency::total 5287724000 # number of WriteReq miss cycles
886system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124574500 # number of LoadLockedReq miss cycles
887system.cpu1.dcache.LoadLockedReq_miss_latency::total 124574500 # number of LoadLockedReq miss cycles
888system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 73632000 # number of StoreCondReq miss cycles
889system.cpu1.dcache.StoreCondReq_miss_latency::total 73632000 # number of StoreCondReq miss cycles
890system.cpu1.dcache.demand_miss_latency::cpu1.data 7783910500 # number of demand (read+write) miss cycles
891system.cpu1.dcache.demand_miss_latency::total 7783910500 # number of demand (read+write) miss cycles
892system.cpu1.dcache.overall_miss_latency::cpu1.data 7783910500 # number of overall miss cycles
893system.cpu1.dcache.overall_miss_latency::total 7783910500 # number of overall miss cycles
894system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118996 # number of ReadReq accesses(hits+misses)
895system.cpu1.dcache.ReadReq_accesses::total 7118996 # number of ReadReq accesses(hits+misses)
896system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979121 # number of WriteReq accesses(hits+misses)
897system.cpu1.dcache.WriteReq_accesses::total 4979121 # number of WriteReq accesses(hits+misses)
898system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92899 # number of LoadLockedReq accesses(hits+misses)
899system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses)
900system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses)
901system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses)
902system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses
903system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses
904system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses
905system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses
906system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses
| 988system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
989system.cpu1.dcache.replacements 294642 # number of replacements
990system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use
991system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks.
992system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks.
993system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks.
994system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit.
995system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor
996system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy
997system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy
998system.cpu1.dcache.ReadReq_hits::cpu1.data 6946891 # number of ReadReq hits
999system.cpu1.dcache.ReadReq_hits::total 6946891 # number of ReadReq hits
1000system.cpu1.dcache.WriteReq_hits::cpu1.data 4828705 # number of WriteReq hits
1001system.cpu1.dcache.WriteReq_hits::total 4828705 # number of WriteReq hits
1002system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81776 # number of LoadLockedReq hits
1003system.cpu1.dcache.LoadLockedReq_hits::total 81776 # number of LoadLockedReq hits
1004system.cpu1.dcache.StoreCondReq_hits::cpu1.data 83111 # number of StoreCondReq hits
1005system.cpu1.dcache.StoreCondReq_hits::total 83111 # number of StoreCondReq hits
1006system.cpu1.dcache.demand_hits::cpu1.data 11775596 # number of demand (read+write) hits
1007system.cpu1.dcache.demand_hits::total 11775596 # number of demand (read+write) hits
1008system.cpu1.dcache.overall_hits::cpu1.data 11775596 # number of overall hits
1009system.cpu1.dcache.overall_hits::total 11775596 # number of overall hits
1010system.cpu1.dcache.ReadReq_misses::cpu1.data 172105 # number of ReadReq misses
1011system.cpu1.dcache.ReadReq_misses::total 172105 # number of ReadReq misses
1012system.cpu1.dcache.WriteReq_misses::cpu1.data 150416 # number of WriteReq misses
1013system.cpu1.dcache.WriteReq_misses::total 150416 # number of WriteReq misses
1014system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11123 # number of LoadLockedReq misses
1015system.cpu1.dcache.LoadLockedReq_misses::total 11123 # number of LoadLockedReq misses
1016system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9715 # number of StoreCondReq misses
1017system.cpu1.dcache.StoreCondReq_misses::total 9715 # number of StoreCondReq misses
1018system.cpu1.dcache.demand_misses::cpu1.data 322521 # number of demand (read+write) misses
1019system.cpu1.dcache.demand_misses::total 322521 # number of demand (read+write) misses
1020system.cpu1.dcache.overall_misses::cpu1.data 322521 # number of overall misses
1021system.cpu1.dcache.overall_misses::total 322521 # number of overall misses
1022system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2496186500 # number of ReadReq miss cycles
1023system.cpu1.dcache.ReadReq_miss_latency::total 2496186500 # number of ReadReq miss cycles
1024system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5287724000 # number of WriteReq miss cycles
1025system.cpu1.dcache.WriteReq_miss_latency::total 5287724000 # number of WriteReq miss cycles
1026system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124574500 # number of LoadLockedReq miss cycles
1027system.cpu1.dcache.LoadLockedReq_miss_latency::total 124574500 # number of LoadLockedReq miss cycles
1028system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 73632000 # number of StoreCondReq miss cycles
1029system.cpu1.dcache.StoreCondReq_miss_latency::total 73632000 # number of StoreCondReq miss cycles
1030system.cpu1.dcache.demand_miss_latency::cpu1.data 7783910500 # number of demand (read+write) miss cycles
1031system.cpu1.dcache.demand_miss_latency::total 7783910500 # number of demand (read+write) miss cycles
1032system.cpu1.dcache.overall_miss_latency::cpu1.data 7783910500 # number of overall miss cycles
1033system.cpu1.dcache.overall_miss_latency::total 7783910500 # number of overall miss cycles
1034system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118996 # number of ReadReq accesses(hits+misses)
1035system.cpu1.dcache.ReadReq_accesses::total 7118996 # number of ReadReq accesses(hits+misses)
1036system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979121 # number of WriteReq accesses(hits+misses)
1037system.cpu1.dcache.WriteReq_accesses::total 4979121 # number of WriteReq accesses(hits+misses)
1038system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92899 # number of LoadLockedReq accesses(hits+misses)
1039system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses)
1040system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses)
1041system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses)
1042system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses
1043system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses
1044system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses
1045system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses
1046system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses
|
| 1047system.cpu1.dcache.ReadReq_miss_rate::total 0.024175 # miss rate for ReadReq accesses
|
907system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses
| 1048system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses
|
| 1049system.cpu1.dcache.WriteReq_miss_rate::total 0.030209 # miss rate for WriteReq accesses
|
908system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses
| 1050system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses
|
| 1051system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119732 # miss rate for LoadLockedReq accesses
|
909system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses
| 1052system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses
|
| 1053system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104658 # miss rate for StoreCondReq accesses
|
910system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses
| 1054system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses
|
| 1055system.cpu1.dcache.demand_miss_rate::total 0.026659 # miss rate for demand accesses
|
911system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses
| 1056system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses
|
| 1057system.cpu1.dcache.overall_miss_rate::total 0.026659 # miss rate for overall accesses
|
912system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency
| 1058system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency
|
| 1059system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110 # average ReadReq miss latency
|
913system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency
| 1060system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency
|
| 1061system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575 # average WriteReq miss latency
|
914system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency
| 1062system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency
|
| 1063system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298 # average LoadLockedReq miss latency
|
915system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency
| 1064system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency
|
| 1065system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7579.207411 # average StoreCondReq miss latency
|
916system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
| 1066system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
|
| 1067system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035 # average overall miss latency
|
917system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
| 1068system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
|
| 1069system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035 # average overall miss latency
|
918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
924system.cpu1.dcache.fast_writes 0 # number of fast writes performed
925system.cpu1.dcache.cache_copies 0 # number of cache copies performed
926system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks
927system.cpu1.dcache.writebacks::total 254584 # number of writebacks
928system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses
929system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses
930system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses
931system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses
932system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses
933system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses
934system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses
935system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses
936system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses
937system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses
938system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses
939system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses
940system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles
941system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles
942system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles
943system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles
944system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles
945system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles
946system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles
947system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles
948system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles
949system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles
950system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles
951system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles
952system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles
953system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles
954system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles
955system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles
956system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles
957system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles
958system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses
| 1070system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1071system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1072system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1073system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1074system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1075system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1076system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1077system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1078system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks
1079system.cpu1.dcache.writebacks::total 254584 # number of writebacks
1080system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses
1081system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses
1082system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses
1083system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses
1084system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses
1085system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses
1086system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses
1087system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses
1088system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses
1089system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses
1090system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses
1091system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses
1092system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles
1093system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles
1094system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles
1095system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles
1096system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles
1097system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles
1098system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles
1099system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles
1100system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles
1101system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles
1102system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles
1103system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles
1104system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles
1105system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles
1106system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles
1107system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles
1108system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles
1109system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles
1110system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses
|
| 1111system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses
|
959system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses
| 1112system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses
|
| 1113system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses
|
960system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses
| 1114system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses
|
| 1115system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses
|
961system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses
| 1116system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses
|
| 1117system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses
|
962system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses
| 1118system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses
|
| 1119system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses
|
963system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses
| 1120system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses
|
| 1121system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses
|
964system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency
| 1122system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency
|
| 1123system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency
|
965system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency
| 1124system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency
|
| 1125system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency
|
966system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency
| 1126system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency
|
| 1127system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency
|
967system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency
| 1128system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency
|
| 1129system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency
|
968system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
| 1130system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
|
| 1131system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency
|
969system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
| 1132system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
|
| 1133system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency
|
970system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
| 1134system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
| 1135system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
971system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
| 1136system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
| 1137system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
972system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
| 1138system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
| 1139system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
973system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
974system.iocache.replacements 0 # number of replacements
975system.iocache.tagsinuse 0 # Cycle average of tags in use
976system.iocache.total_refs 0 # Total number of references to valid blocks.
977system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
978system.iocache.avg_refs nan # Average number of references to valid blocks.
979system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
980system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
981system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
982system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
983system.iocache.blocked::no_targets 0 # number of cycles access was blocked
984system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
985system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
986system.iocache.fast_writes 0 # number of fast writes performed
987system.iocache.cache_copies 0 # number of cache copies performed
988system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles
989system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles
990system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles
991system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles
992system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
| 1140system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1141system.iocache.replacements 0 # number of replacements
1142system.iocache.tagsinuse 0 # Cycle average of tags in use
1143system.iocache.total_refs 0 # Total number of references to valid blocks.
1144system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
1145system.iocache.avg_refs nan # Average number of references to valid blocks.
1146system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1147system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1148system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1149system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1150system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1151system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1152system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1153system.iocache.fast_writes 0 # number of fast writes performed
1154system.iocache.cache_copies 0 # number of cache copies performed
1155system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles
1156system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles
1157system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles
1158system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles
1159system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
| 1160system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
993system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
| 1161system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
| 1162system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
994system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
995
996---------- End Simulation Statistics ----------
| 1163system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1164
1165---------- End Simulation Statistics ----------
|