Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.669611 # Number of seconds simulated
4sim_ticks 2669611225000 # Number of ticks simulated
5final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 887100 # Simulator instruction rate (inst/s)
8host_op_rate 1134851 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38636092154 # Simulator tick rate (ticks/s)
10host_mem_usage 379132 # Number of bytes of host memory used
11host_seconds 69.10 # Real time elapsed on the host

7host_inst_rate 280373 # Simulator instruction rate (inst/s)
8host_op_rate 358676 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 12211141498 # Simulator tick rate (ticks/s)
10host_mem_usage 385748 # Number of bytes of host memory used
11host_seconds 218.62 # Real time elapsed on the host

12sim_insts 61295282 # Number of instructions simulated
13sim_ops 78413979 # Number of ops (including micro ops) simulated

14system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
15system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
17system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
20system.realview.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s)
21system.realview.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s)
22system.realview.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s)

23system.physmem.bytes_read 134334820 # Number of bytes read from this memory
24system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory
25system.physmem.bytes_written 10194256 # Number of bytes written to this memory
26system.physmem.num_reads 15523876 # Number of read requests responded to by this memory
27system.physmem.num_writes 869239 # Number of write requests responded to by this memory
28system.physmem.num_other 0 # Number of other requests responded to by this memory
29system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s)

14system.physmem.bytes_read 134334820 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10194256 # Number of bytes written to this memory
17system.physmem.num_reads 15523876 # Number of read requests responded to by this memory
18system.physmem.num_writes 869239 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s)

24system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s)

33system.l2c.replacements 127749 # number of replacements
34system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use
35system.l2c.total_refs 1540413 # Total number of references to valid blocks.
36system.l2c.sampled_refs 157158 # Sample count of references to valid blocks.
37system.l2c.avg_refs 9.801684 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu0.inst 2680.486070 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu0.data 3670.979881 # Average occupied blocks per requestor
44system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor
45system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor
46system.l2c.occ_blocks::cpu1.inst 2441.904061 # Average occupied blocks per requestor
47system.l2c.occ_blocks::cpu1.data 2173.000034 # Average occupied blocks per requestor
48system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy
49system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy
50system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
51system.l2c.occ_percent::cpu0.inst 0.040901 # Average percentage of cache occupancy
52system.l2c.occ_percent::cpu0.data 0.056015 # Average percentage of cache occupancy
53system.l2c.occ_percent::cpu1.dtb.walker 0.000001 # Average percentage of cache occupancy
54system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
55system.l2c.occ_percent::cpu1.inst 0.037260 # Average percentage of cache occupancy
56system.l2c.occ_percent::cpu1.data 0.033157 # Average percentage of cache occupancy
57system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy
58system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits
59system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # number of ReadReq hits
60system.l2c.ReadReq_hits::cpu0.inst 371107 # number of ReadReq hits
61system.l2c.ReadReq_hits::cpu0.data 191753 # number of ReadReq hits
62system.l2c.ReadReq_hits::cpu1.dtb.walker 4185 # number of ReadReq hits
63system.l2c.ReadReq_hits::cpu1.itb.walker 1874 # number of ReadReq hits
64system.l2c.ReadReq_hits::cpu1.inst 499097 # number of ReadReq hits
65system.l2c.ReadReq_hits::cpu1.data 157046 # number of ReadReq hits
66system.l2c.ReadReq_hits::total 1230801 # number of ReadReq hits
67system.l2c.Writeback_hits::writebacks 589400 # number of Writeback hits
68system.l2c.Writeback_hits::total 589400 # number of Writeback hits
69system.l2c.UpgradeReq_hits::cpu0.data 1143 # number of UpgradeReq hits
70system.l2c.UpgradeReq_hits::cpu1.data 692 # number of UpgradeReq hits
71system.l2c.UpgradeReq_hits::total 1835 # number of UpgradeReq hits
72system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits
73system.l2c.SCUpgradeReq_hits::cpu1.data 186 # number of SCUpgradeReq hits
74system.l2c.SCUpgradeReq_hits::total 354 # number of SCUpgradeReq hits
75system.l2c.ReadExReq_hits::cpu0.data 42506 # number of ReadExReq hits
76system.l2c.ReadExReq_hits::cpu1.data 58554 # number of ReadExReq hits
77system.l2c.ReadExReq_hits::total 101060 # number of ReadExReq hits
78system.l2c.demand_hits::cpu0.dtb.walker 4237 # number of demand (read+write) hits
79system.l2c.demand_hits::cpu0.itb.walker 1502 # number of demand (read+write) hits
80system.l2c.demand_hits::cpu0.inst 371107 # number of demand (read+write) hits
81system.l2c.demand_hits::cpu0.data 234259 # number of demand (read+write) hits
82system.l2c.demand_hits::cpu1.dtb.walker 4185 # number of demand (read+write) hits
83system.l2c.demand_hits::cpu1.itb.walker 1874 # number of demand (read+write) hits
84system.l2c.demand_hits::cpu1.inst 499097 # number of demand (read+write) hits
85system.l2c.demand_hits::cpu1.data 215600 # number of demand (read+write) hits
86system.l2c.demand_hits::total 1331861 # number of demand (read+write) hits
87system.l2c.overall_hits::cpu0.dtb.walker 4237 # number of overall hits
88system.l2c.overall_hits::cpu0.itb.walker 1502 # number of overall hits
89system.l2c.overall_hits::cpu0.inst 371107 # number of overall hits
90system.l2c.overall_hits::cpu0.data 234259 # number of overall hits
91system.l2c.overall_hits::cpu1.dtb.walker 4185 # number of overall hits
92system.l2c.overall_hits::cpu1.itb.walker 1874 # number of overall hits
93system.l2c.overall_hits::cpu1.inst 499097 # number of overall hits
94system.l2c.overall_hits::cpu1.data 215600 # number of overall hits
95system.l2c.overall_hits::total 1331861 # number of overall hits
96system.l2c.ReadReq_misses::cpu0.dtb.walker 24 # number of ReadReq misses
97system.l2c.ReadReq_misses::cpu0.itb.walker 14 # number of ReadReq misses
98system.l2c.ReadReq_misses::cpu0.inst 7728 # number of ReadReq misses
99system.l2c.ReadReq_misses::cpu0.data 10927 # number of ReadReq misses
100system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses
101system.l2c.ReadReq_misses::cpu1.itb.walker 4 # number of ReadReq misses
102system.l2c.ReadReq_misses::cpu1.inst 7533 # number of ReadReq misses
103system.l2c.ReadReq_misses::cpu1.data 8501 # number of ReadReq misses
104system.l2c.ReadReq_misses::total 34739 # number of ReadReq misses
105system.l2c.UpgradeReq_misses::cpu0.data 3515 # number of UpgradeReq misses
106system.l2c.UpgradeReq_misses::cpu1.data 5223 # number of UpgradeReq misses
107system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses
108system.l2c.SCUpgradeReq_misses::cpu0.data 546 # number of SCUpgradeReq misses
109system.l2c.SCUpgradeReq_misses::cpu1.data 614 # number of SCUpgradeReq misses
110system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses
111system.l2c.ReadExReq_misses::cpu0.data 97324 # number of ReadExReq misses
112system.l2c.ReadExReq_misses::cpu1.data 51524 # number of ReadExReq misses
113system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses
114system.l2c.demand_misses::cpu0.dtb.walker 24 # number of demand (read+write) misses
115system.l2c.demand_misses::cpu0.itb.walker 14 # number of demand (read+write) misses
116system.l2c.demand_misses::cpu0.inst 7728 # number of demand (read+write) misses
117system.l2c.demand_misses::cpu0.data 108251 # number of demand (read+write) misses
118system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses
119system.l2c.demand_misses::cpu1.itb.walker 4 # number of demand (read+write) misses
120system.l2c.demand_misses::cpu1.inst 7533 # number of demand (read+write) misses
121system.l2c.demand_misses::cpu1.data 60025 # number of demand (read+write) misses
122system.l2c.demand_misses::total 183587 # number of demand (read+write) misses
123system.l2c.overall_misses::cpu0.dtb.walker 24 # number of overall misses
124system.l2c.overall_misses::cpu0.itb.walker 14 # number of overall misses
125system.l2c.overall_misses::cpu0.inst 7728 # number of overall misses
126system.l2c.overall_misses::cpu0.data 108251 # number of overall misses
127system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses
128system.l2c.overall_misses::cpu1.itb.walker 4 # number of overall misses
129system.l2c.overall_misses::cpu1.inst 7533 # number of overall misses
130system.l2c.overall_misses::cpu1.data 60025 # number of overall misses
131system.l2c.overall_misses::total 183587 # number of overall misses
132system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1250500 # number of ReadReq miss cycles
133system.l2c.ReadReq_miss_latency::cpu0.itb.walker 728500 # number of ReadReq miss cycles
134system.l2c.ReadReq_miss_latency::cpu0.inst 402353500 # number of ReadReq miss cycles
135system.l2c.ReadReq_miss_latency::cpu0.data 568569000 # number of ReadReq miss cycles
136system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 416000 # number of ReadReq miss cycles
137system.l2c.ReadReq_miss_latency::cpu1.itb.walker 208000 # number of ReadReq miss cycles
138system.l2c.ReadReq_miss_latency::cpu1.inst 393731000 # number of ReadReq miss cycles
139system.l2c.ReadReq_miss_latency::cpu1.data 445248000 # number of ReadReq miss cycles
140system.l2c.ReadReq_miss_latency::total 1812504500 # number of ReadReq miss cycles
141system.l2c.UpgradeReq_miss_latency::cpu0.data 25676000 # number of UpgradeReq miss cycles
142system.l2c.UpgradeReq_miss_latency::cpu1.data 30795000 # number of UpgradeReq miss cycles
143system.l2c.UpgradeReq_miss_latency::total 56471000 # number of UpgradeReq miss cycles
144system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1664000 # number of SCUpgradeReq miss cycles
145system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4636000 # number of SCUpgradeReq miss cycles
146system.l2c.SCUpgradeReq_miss_latency::total 6300000 # number of SCUpgradeReq miss cycles
147system.l2c.ReadExReq_miss_latency::cpu0.data 5064009000 # number of ReadExReq miss cycles
148system.l2c.ReadExReq_miss_latency::cpu1.data 2687534000 # number of ReadExReq miss cycles
149system.l2c.ReadExReq_miss_latency::total 7751543000 # number of ReadExReq miss cycles
150system.l2c.demand_miss_latency::cpu0.dtb.walker 1250500 # number of demand (read+write) miss cycles
151system.l2c.demand_miss_latency::cpu0.itb.walker 728500 # number of demand (read+write) miss cycles
152system.l2c.demand_miss_latency::cpu0.inst 402353500 # number of demand (read+write) miss cycles
153system.l2c.demand_miss_latency::cpu0.data 5632578000 # number of demand (read+write) miss cycles
154system.l2c.demand_miss_latency::cpu1.dtb.walker 416000 # number of demand (read+write) miss cycles
155system.l2c.demand_miss_latency::cpu1.itb.walker 208000 # number of demand (read+write) miss cycles
156system.l2c.demand_miss_latency::cpu1.inst 393731000 # number of demand (read+write) miss cycles
157system.l2c.demand_miss_latency::cpu1.data 3132782000 # number of demand (read+write) miss cycles
158system.l2c.demand_miss_latency::total 9564047500 # number of demand (read+write) miss cycles
159system.l2c.overall_miss_latency::cpu0.dtb.walker 1250500 # number of overall miss cycles
160system.l2c.overall_miss_latency::cpu0.itb.walker 728500 # number of overall miss cycles
161system.l2c.overall_miss_latency::cpu0.inst 402353500 # number of overall miss cycles
162system.l2c.overall_miss_latency::cpu0.data 5632578000 # number of overall miss cycles
163system.l2c.overall_miss_latency::cpu1.dtb.walker 416000 # number of overall miss cycles
164system.l2c.overall_miss_latency::cpu1.itb.walker 208000 # number of overall miss cycles
165system.l2c.overall_miss_latency::cpu1.inst 393731000 # number of overall miss cycles
166system.l2c.overall_miss_latency::cpu1.data 3132782000 # number of overall miss cycles
167system.l2c.overall_miss_latency::total 9564047500 # number of overall miss cycles
168system.l2c.ReadReq_accesses::cpu0.dtb.walker 4261 # number of ReadReq accesses(hits+misses)
169system.l2c.ReadReq_accesses::cpu0.itb.walker 1516 # number of ReadReq accesses(hits+misses)
170system.l2c.ReadReq_accesses::cpu0.inst 378835 # number of ReadReq accesses(hits+misses)
171system.l2c.ReadReq_accesses::cpu0.data 202680 # number of ReadReq accesses(hits+misses)
172system.l2c.ReadReq_accesses::cpu1.dtb.walker 4193 # number of ReadReq accesses(hits+misses)
173system.l2c.ReadReq_accesses::cpu1.itb.walker 1878 # number of ReadReq accesses(hits+misses)
174system.l2c.ReadReq_accesses::cpu1.inst 506630 # number of ReadReq accesses(hits+misses)
175system.l2c.ReadReq_accesses::cpu1.data 165547 # number of ReadReq accesses(hits+misses)
176system.l2c.ReadReq_accesses::total 1265540 # number of ReadReq accesses(hits+misses)
177system.l2c.Writeback_accesses::writebacks 589400 # number of Writeback accesses(hits+misses)
178system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses)
179system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses)
180system.l2c.UpgradeReq_accesses::cpu1.data 5915 # number of UpgradeReq accesses(hits+misses)
181system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses)
182system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses)
183system.l2c.SCUpgradeReq_accesses::cpu1.data 800 # number of SCUpgradeReq accesses(hits+misses)
184system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses)
185system.l2c.ReadExReq_accesses::cpu0.data 139830 # number of ReadExReq accesses(hits+misses)
186system.l2c.ReadExReq_accesses::cpu1.data 110078 # number of ReadExReq accesses(hits+misses)
187system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses)
188system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses
189system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses
190system.l2c.demand_accesses::cpu0.inst 378835 # number of demand (read+write) accesses
191system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses
192system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses
193system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses
194system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses
195system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses
196system.l2c.demand_accesses::total 1515448 # number of demand (read+write) accesses
197system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses
198system.l2c.overall_accesses::cpu0.itb.walker 1516 # number of overall (read+write) accesses
199system.l2c.overall_accesses::cpu0.inst 378835 # number of overall (read+write) accesses
200system.l2c.overall_accesses::cpu0.data 342510 # number of overall (read+write) accesses
201system.l2c.overall_accesses::cpu1.dtb.walker 4193 # number of overall (read+write) accesses
202system.l2c.overall_accesses::cpu1.itb.walker 1878 # number of overall (read+write) accesses
203system.l2c.overall_accesses::cpu1.inst 506630 # number of overall (read+write) accesses
204system.l2c.overall_accesses::cpu1.data 275625 # number of overall (read+write) accesses
205system.l2c.overall_accesses::total 1515448 # number of overall (read+write) accesses
206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for ReadReq accesses
207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.009235 # miss rate for ReadReq accesses
208system.l2c.ReadReq_miss_rate::cpu0.inst 0.020399 # miss rate for ReadReq accesses
209system.l2c.ReadReq_miss_rate::cpu0.data 0.053913 # miss rate for ReadReq accesses
210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for ReadReq accesses
211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002130 # miss rate for ReadReq accesses
212system.l2c.ReadReq_miss_rate::cpu1.inst 0.014869 # miss rate for ReadReq accesses
213system.l2c.ReadReq_miss_rate::cpu1.data 0.051351 # miss rate for ReadReq accesses
214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754616 # miss rate for UpgradeReq accesses
215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.883009 # miss rate for UpgradeReq accesses
216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764706 # miss rate for SCUpgradeReq accesses
217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.767500 # miss rate for SCUpgradeReq accesses
218system.l2c.ReadExReq_miss_rate::cpu0.data 0.696017 # miss rate for ReadExReq accesses
219system.l2c.ReadExReq_miss_rate::cpu1.data 0.468068 # miss rate for ReadExReq accesses
220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for demand accesses
221system.l2c.demand_miss_rate::cpu0.itb.walker 0.009235 # miss rate for demand accesses
222system.l2c.demand_miss_rate::cpu0.inst 0.020399 # miss rate for demand accesses
223system.l2c.demand_miss_rate::cpu0.data 0.316052 # miss rate for demand accesses
224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for demand accesses
225system.l2c.demand_miss_rate::cpu1.itb.walker 0.002130 # miss rate for demand accesses
226system.l2c.demand_miss_rate::cpu1.inst 0.014869 # miss rate for demand accesses
227system.l2c.demand_miss_rate::cpu1.data 0.217778 # miss rate for demand accesses
228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for overall accesses
229system.l2c.overall_miss_rate::cpu0.itb.walker 0.009235 # miss rate for overall accesses
230system.l2c.overall_miss_rate::cpu0.inst 0.020399 # miss rate for overall accesses
231system.l2c.overall_miss_rate::cpu0.data 0.316052 # miss rate for overall accesses
232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for overall accesses
233system.l2c.overall_miss_rate::cpu1.itb.walker 0.002130 # miss rate for overall accesses
234system.l2c.overall_miss_rate::cpu1.inst 0.014869 # miss rate for overall accesses
235system.l2c.overall_miss_rate::cpu1.data 0.217778 # miss rate for overall accesses
236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average ReadReq miss latency
237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52035.714286 # average ReadReq miss latency
238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52064.376294 # average ReadReq miss latency
239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52033.403496 # average ReadReq miss latency
240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency
241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52267.489712 # average ReadReq miss latency
243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375.955770 # average ReadReq miss latency
244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7304.694168 # average UpgradeReq miss latency
245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5896.036760 # average UpgradeReq miss latency
246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3047.619048 # average SCUpgradeReq miss latency
247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7550.488599 # average SCUpgradeReq miss latency
248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.479142 # average ReadExReq miss latency
249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52160.818259 # average ReadExReq miss latency
250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency
251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency
252system.l2c.demand_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency
253system.l2c.demand_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency
254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency
255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
256system.l2c.demand_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency
257system.l2c.demand_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency
258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency
259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency
260system.l2c.overall_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency
261system.l2c.overall_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency
262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency
263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
264system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency
265system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency
266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
269system.l2c.blocked::no_targets 0 # number of cycles access was blocked

270system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

272system.l2c.fast_writes 0 # number of fast writes performed
273system.l2c.cache_copies 0 # number of cache copies performed
274system.l2c.writebacks::writebacks 111955 # number of writebacks
275system.l2c.writebacks::total 111955 # number of writebacks
276system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
277system.l2c.ReadReq_mshr_hits::cpu0.data 8 # number of ReadReq MSHR hits
278system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
279system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
280system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits
281system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
282system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
283system.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits
284system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
285system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 24 # number of ReadReq MSHR misses
286system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 14 # number of ReadReq MSHR misses
287system.l2c.ReadReq_mshr_misses::cpu0.inst 7727 # number of ReadReq MSHR misses
288system.l2c.ReadReq_mshr_misses::cpu0.data 10919 # number of ReadReq MSHR misses
289system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses
290system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 4 # number of ReadReq MSHR misses
291system.l2c.ReadReq_mshr_misses::cpu1.inst 7533 # number of ReadReq MSHR misses
292system.l2c.ReadReq_mshr_misses::cpu1.data 8501 # number of ReadReq MSHR misses
293system.l2c.ReadReq_mshr_misses::total 34730 # number of ReadReq MSHR misses
294system.l2c.UpgradeReq_mshr_misses::cpu0.data 3515 # number of UpgradeReq MSHR misses
295system.l2c.UpgradeReq_mshr_misses::cpu1.data 5223 # number of UpgradeReq MSHR misses
296system.l2c.UpgradeReq_mshr_misses::total 8738 # number of UpgradeReq MSHR misses
297system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 546 # number of SCUpgradeReq MSHR misses
298system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 614 # number of SCUpgradeReq MSHR misses
299system.l2c.SCUpgradeReq_mshr_misses::total 1160 # number of SCUpgradeReq MSHR misses
300system.l2c.ReadExReq_mshr_misses::cpu0.data 97324 # number of ReadExReq MSHR misses
301system.l2c.ReadExReq_mshr_misses::cpu1.data 51524 # number of ReadExReq MSHR misses
302system.l2c.ReadExReq_mshr_misses::total 148848 # number of ReadExReq MSHR misses
303system.l2c.demand_mshr_misses::cpu0.dtb.walker 24 # number of demand (read+write) MSHR misses
304system.l2c.demand_mshr_misses::cpu0.itb.walker 14 # number of demand (read+write) MSHR misses
305system.l2c.demand_mshr_misses::cpu0.inst 7727 # number of demand (read+write) MSHR misses
306system.l2c.demand_mshr_misses::cpu0.data 108243 # number of demand (read+write) MSHR misses
307system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses
308system.l2c.demand_mshr_misses::cpu1.itb.walker 4 # number of demand (read+write) MSHR misses
309system.l2c.demand_mshr_misses::cpu1.inst 7533 # number of demand (read+write) MSHR misses
310system.l2c.demand_mshr_misses::cpu1.data 60025 # number of demand (read+write) MSHR misses
311system.l2c.demand_mshr_misses::total 183578 # number of demand (read+write) MSHR misses
312system.l2c.overall_mshr_misses::cpu0.dtb.walker 24 # number of overall MSHR misses
313system.l2c.overall_mshr_misses::cpu0.itb.walker 14 # number of overall MSHR misses
314system.l2c.overall_mshr_misses::cpu0.inst 7727 # number of overall MSHR misses
315system.l2c.overall_mshr_misses::cpu0.data 108243 # number of overall MSHR misses
316system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses
317system.l2c.overall_mshr_misses::cpu1.itb.walker 4 # number of overall MSHR misses
318system.l2c.overall_mshr_misses::cpu1.inst 7533 # number of overall MSHR misses
319system.l2c.overall_mshr_misses::cpu1.data 60025 # number of overall MSHR misses
320system.l2c.overall_mshr_misses::total 183578 # number of overall MSHR misses
321system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 962000 # number of ReadReq MSHR miss cycles
322system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 560000 # number of ReadReq MSHR miss cycles
323system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 309600000 # number of ReadReq MSHR miss cycles
324system.l2c.ReadReq_mshr_miss_latency::cpu0.data 437141000 # number of ReadReq MSHR miss cycles
325system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 320000 # number of ReadReq MSHR miss cycles
326system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 160000 # number of ReadReq MSHR miss cycles
327system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 303331000 # number of ReadReq MSHR miss cycles
328system.l2c.ReadReq_mshr_miss_latency::cpu1.data 343236000 # number of ReadReq MSHR miss cycles
329system.l2c.ReadReq_mshr_miss_latency::total 1395310000 # number of ReadReq MSHR miss cycles
330system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 140869500 # number of UpgradeReq MSHR miss cycles
331system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 209724000 # number of UpgradeReq MSHR miss cycles
332system.l2c.UpgradeReq_mshr_miss_latency::total 350593500 # number of UpgradeReq MSHR miss cycles
333system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 21887000 # number of SCUpgradeReq MSHR miss cycles
334system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 24659000 # number of SCUpgradeReq MSHR miss cycles
335system.l2c.SCUpgradeReq_mshr_miss_latency::total 46546000 # number of SCUpgradeReq MSHR miss cycles
336system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3896121000 # number of ReadExReq MSHR miss cycles
337system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2069246000 # number of ReadExReq MSHR miss cycles
338system.l2c.ReadExReq_mshr_miss_latency::total 5965367000 # number of ReadExReq MSHR miss cycles
339system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 962000 # number of demand (read+write) MSHR miss cycles
340system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 560000 # number of demand (read+write) MSHR miss cycles
341system.l2c.demand_mshr_miss_latency::cpu0.inst 309600000 # number of demand (read+write) MSHR miss cycles
342system.l2c.demand_mshr_miss_latency::cpu0.data 4333262000 # number of demand (read+write) MSHR miss cycles
343system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 320000 # number of demand (read+write) MSHR miss cycles
344system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
345system.l2c.demand_mshr_miss_latency::cpu1.inst 303331000 # number of demand (read+write) MSHR miss cycles
346system.l2c.demand_mshr_miss_latency::cpu1.data 2412482000 # number of demand (read+write) MSHR miss cycles
347system.l2c.demand_mshr_miss_latency::total 7360677000 # number of demand (read+write) MSHR miss cycles
348system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 962000 # number of overall MSHR miss cycles
349system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 560000 # number of overall MSHR miss cycles
350system.l2c.overall_mshr_miss_latency::cpu0.inst 309600000 # number of overall MSHR miss cycles
351system.l2c.overall_mshr_miss_latency::cpu0.data 4333262000 # number of overall MSHR miss cycles
352system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 320000 # number of overall MSHR miss cycles
353system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 160000 # number of overall MSHR miss cycles
354system.l2c.overall_mshr_miss_latency::cpu1.inst 303331000 # number of overall MSHR miss cycles
355system.l2c.overall_mshr_miss_latency::cpu1.data 2412482000 # number of overall MSHR miss cycles
356system.l2c.overall_mshr_miss_latency::total 7360677000 # number of overall MSHR miss cycles
357system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles
358system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8189961000 # number of ReadReq MSHR uncacheable cycles
359system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles
360system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123467229000 # number of ReadReq MSHR uncacheable cycles
361system.l2c.ReadReq_mshr_uncacheable_latency::total 131926671000 # number of ReadReq MSHR uncacheable cycles
362system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 30961750000 # number of WriteReq MSHR uncacheable cycles
363system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 410629500 # number of WriteReq MSHR uncacheable cycles
364system.l2c.WriteReq_mshr_uncacheable_latency::total 31372379500 # number of WriteReq MSHR uncacheable cycles
365system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles
366system.l2c.overall_mshr_uncacheable_latency::cpu0.data 39151711000 # number of overall MSHR uncacheable cycles
367system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles
368system.l2c.overall_mshr_uncacheable_latency::cpu1.data 123877858500 # number of overall MSHR uncacheable cycles
369system.l2c.overall_mshr_uncacheable_latency::total 163299050500 # number of overall MSHR uncacheable cycles
370system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for ReadReq accesses
371system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for ReadReq accesses
372system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for ReadReq accesses
373system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.053873 # mshr miss rate for ReadReq accesses
374system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for ReadReq accesses
375system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for ReadReq accesses
376system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for ReadReq accesses
377system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051351 # mshr miss rate for ReadReq accesses
378system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754616 # mshr miss rate for UpgradeReq accesses
379system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.883009 # mshr miss rate for UpgradeReq accesses
380system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764706 # mshr miss rate for SCUpgradeReq accesses
381system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.767500 # mshr miss rate for SCUpgradeReq accesses
382system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.696017 # mshr miss rate for ReadExReq accesses
383system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468068 # mshr miss rate for ReadExReq accesses
384system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for demand accesses
385system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for demand accesses
386system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for demand accesses
387system.l2c.demand_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for demand accesses
388system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for demand accesses
389system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for demand accesses
390system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for demand accesses
391system.l2c.demand_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for demand accesses
392system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for overall accesses
393system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for overall accesses
394system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for overall accesses
395system.l2c.overall_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for overall accesses
396system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for overall accesses
397system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for overall accesses
398system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for overall accesses
399system.l2c.overall_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for overall accesses
400system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average ReadReq mshr miss latency
401system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
402system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average ReadReq mshr miss latency
403system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40034.893305 # average ReadReq mshr miss latency
404system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
405system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
406system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average ReadReq mshr miss latency
407system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40375.955770 # average ReadReq mshr miss latency
408system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40076.671408 # average UpgradeReq mshr miss latency
409system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40153.934520 # average UpgradeReq mshr miss latency
410system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40086.080586 # average SCUpgradeReq mshr miss latency
411system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785 # average SCUpgradeReq mshr miss latency
412system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.479142 # average ReadExReq mshr miss latency
413system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259 # average ReadExReq mshr miss latency
414system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency
415system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
416system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency
417system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency
418system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
419system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
420system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency
421system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency
422system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency
423system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
424system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency
425system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency
426system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
427system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
428system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency
429system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency
430system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
431system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
432system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
433system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
434system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
435system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
436system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
437system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
438system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
439system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
440system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
441system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
442system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
443system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
444system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
445system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
446system.cf0.dma_write_txs 0 # Number of DMA write transactions.
447system.cpu0.dtb.inst_hits 0 # ITB inst hits
448system.cpu0.dtb.inst_misses 0 # ITB inst misses
449system.cpu0.dtb.read_hits 7857580 # DTB read hits
450system.cpu0.dtb.read_misses 1898 # DTB read misses
451system.cpu0.dtb.write_hits 6224259 # DTB write hits
452system.cpu0.dtb.write_misses 1143 # DTB write misses
453system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
454system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
455system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
456system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
457system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB
458system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
459system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch
460system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
461system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions
462system.cpu0.dtb.read_accesses 7859478 # DTB read accesses
463system.cpu0.dtb.write_accesses 6225402 # DTB write accesses
464system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
465system.cpu0.dtb.hits 14081839 # DTB hits
466system.cpu0.dtb.misses 3041 # DTB misses
467system.cpu0.dtb.accesses 14084880 # DTB accesses
468system.cpu0.itb.inst_hits 35747911 # ITB inst hits
469system.cpu0.itb.inst_misses 1204 # ITB inst misses
470system.cpu0.itb.read_hits 0 # DTB read hits
471system.cpu0.itb.read_misses 0 # DTB read misses
472system.cpu0.itb.write_hits 0 # DTB write hits
473system.cpu0.itb.write_misses 0 # DTB write misses
474system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
475system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
476system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
477system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
478system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB
479system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
480system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
481system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
482system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
483system.cpu0.itb.read_accesses 0 # DTB read accesses
484system.cpu0.itb.write_accesses 0 # DTB write accesses
485system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses
486system.cpu0.itb.hits 35747911 # DTB hits
487system.cpu0.itb.misses 1204 # DTB misses
488system.cpu0.itb.accesses 35749115 # DTB accesses
489system.cpu0.numCycles 5337805216 # number of cpu cycles simulated
490system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
491system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
492system.cpu0.committedInsts 35373502 # Number of instructions committed
493system.cpu0.committedOps 43969024 # Number of ops (including micro ops) committed
494system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses
495system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses
496system.cpu0.num_func_calls 977479 # number of times a function call or return occured
497system.cpu0.num_conditional_control_insts 4455595 # number of instructions that are conditional controls
498system.cpu0.num_int_insts 39881498 # number of integer instructions
499system.cpu0.num_fp_insts 4107 # number of float instructions
500system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read
501system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written
502system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read
503system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written
504system.cpu0.num_mem_refs 14677999 # number of memory refs
505system.cpu0.num_load_insts 8148547 # Number of load instructions
506system.cpu0.num_store_insts 6529452 # Number of store instructions
507system.cpu0.num_idle_cycles 5107410767.568501 # Number of idle cycles
508system.cpu0.num_busy_cycles 230394448.431500 # Number of busy cycles
509system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles
510system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles
511system.cpu0.kern.inst.arm 0 # number of arm instructions executed
512system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed
513system.cpu0.icache.replacements 380070 # number of replacements
514system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use
515system.cpu0.icache.total_refs 35367310 # Total number of references to valid blocks.
516system.cpu0.icache.sampled_refs 380582 # Sample count of references to valid blocks.
517system.cpu0.icache.avg_refs 92.929539 # Average number of references to valid blocks.
518system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit.
519system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor
520system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy
521system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy
522system.cpu0.icache.ReadReq_hits::cpu0.inst 35367310 # number of ReadReq hits
523system.cpu0.icache.ReadReq_hits::total 35367310 # number of ReadReq hits
524system.cpu0.icache.demand_hits::cpu0.inst 35367310 # number of demand (read+write) hits
525system.cpu0.icache.demand_hits::total 35367310 # number of demand (read+write) hits
526system.cpu0.icache.overall_hits::cpu0.inst 35367310 # number of overall hits
527system.cpu0.icache.overall_hits::total 35367310 # number of overall hits
528system.cpu0.icache.ReadReq_misses::cpu0.inst 380584 # number of ReadReq misses
529system.cpu0.icache.ReadReq_misses::total 380584 # number of ReadReq misses
530system.cpu0.icache.demand_misses::cpu0.inst 380584 # number of demand (read+write) misses
531system.cpu0.icache.demand_misses::total 380584 # number of demand (read+write) misses
532system.cpu0.icache.overall_misses::cpu0.inst 380584 # number of overall misses
533system.cpu0.icache.overall_misses::total 380584 # number of overall misses
534system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651447000 # number of ReadReq miss cycles
535system.cpu0.icache.ReadReq_miss_latency::total 5651447000 # number of ReadReq miss cycles
536system.cpu0.icache.demand_miss_latency::cpu0.inst 5651447000 # number of demand (read+write) miss cycles
537system.cpu0.icache.demand_miss_latency::total 5651447000 # number of demand (read+write) miss cycles
538system.cpu0.icache.overall_miss_latency::cpu0.inst 5651447000 # number of overall miss cycles
539system.cpu0.icache.overall_miss_latency::total 5651447000 # number of overall miss cycles
540system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses)
541system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses)
542system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses
543system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses
544system.cpu0.icache.overall_accesses::cpu0.inst 35747894 # number of overall (read+write) accesses
545system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses
546system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses
547system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses
548system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses
549system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency
550system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency
551system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency
552system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
553system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
554system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
555system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked

556system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
557system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

556system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
557system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

558system.cpu0.icache.fast_writes 0 # number of fast writes performed
559system.cpu0.icache.cache_copies 0 # number of cache copies performed
560system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks
561system.cpu0.icache.writebacks::total 12960 # number of writebacks
562system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380584 # number of ReadReq MSHR misses
563system.cpu0.icache.ReadReq_mshr_misses::total 380584 # number of ReadReq MSHR misses
564system.cpu0.icache.demand_mshr_misses::cpu0.inst 380584 # number of demand (read+write) MSHR misses
565system.cpu0.icache.demand_mshr_misses::total 380584 # number of demand (read+write) MSHR misses
566system.cpu0.icache.overall_mshr_misses::cpu0.inst 380584 # number of overall MSHR misses
567system.cpu0.icache.overall_mshr_misses::total 380584 # number of overall MSHR misses
568system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509193500 # number of ReadReq MSHR miss cycles
569system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509193500 # number of ReadReq MSHR miss cycles
570system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509193500 # number of demand (read+write) MSHR miss cycles
571system.cpu0.icache.demand_mshr_miss_latency::total 4509193500 # number of demand (read+write) MSHR miss cycles
572system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509193500 # number of overall MSHR miss cycles
573system.cpu0.icache.overall_mshr_miss_latency::total 4509193500 # number of overall MSHR miss cycles
574system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
575system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
576system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
577system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
578system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses
579system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses
580system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses
581system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average ReadReq mshr miss latency
582system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency
583system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency
584system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
585system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
586system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
587system.cpu0.dcache.replacements 334596 # number of replacements
588system.cpu0.dcache.tagsinuse 450.118379 # Cycle average of tags in use
589system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks.
590system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks.
591system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks.
592system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
593system.cpu0.dcache.occ_blocks::cpu0.data 450.118379 # Average occupied blocks per requestor
594system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy
595system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy
596system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits
597system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits
598system.cpu0.dcache.WriteReq_hits::cpu0.data 5172633 # number of WriteReq hits
599system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits
600system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126778 # number of LoadLockedReq hits
601system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits
602system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127996 # number of StoreCondReq hits
603system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits
604system.cpu0.dcache.demand_hits::cpu0.data 12601242 # number of demand (read+write) hits
605system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits
606system.cpu0.dcache.overall_hits::cpu0.data 12601242 # number of overall hits
607system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits
608system.cpu0.dcache.ReadReq_misses::cpu0.data 217330 # number of ReadReq misses
609system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses
610system.cpu0.dcache.WriteReq_misses::cpu0.data 155538 # number of WriteReq misses
611system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses
612system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9456 # number of LoadLockedReq misses
613system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses
614system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8189 # number of StoreCondReq misses
615system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses
616system.cpu0.dcache.demand_misses::cpu0.data 372868 # number of demand (read+write) misses
617system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses
618system.cpu0.dcache.overall_misses::cpu0.data 372868 # number of overall misses
619system.cpu0.dcache.overall_misses::total 372868 # number of overall misses
620system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3330686000 # number of ReadReq miss cycles
621system.cpu0.dcache.ReadReq_miss_latency::total 3330686000 # number of ReadReq miss cycles
622system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6317758500 # number of WriteReq miss cycles
623system.cpu0.dcache.WriteReq_miss_latency::total 6317758500 # number of WriteReq miss cycles
624system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100249000 # number of LoadLockedReq miss cycles
625system.cpu0.dcache.LoadLockedReq_miss_latency::total 100249000 # number of LoadLockedReq miss cycles
626system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 70240000 # number of StoreCondReq miss cycles
627system.cpu0.dcache.StoreCondReq_miss_latency::total 70240000 # number of StoreCondReq miss cycles
628system.cpu0.dcache.demand_miss_latency::cpu0.data 9648444500 # number of demand (read+write) miss cycles
629system.cpu0.dcache.demand_miss_latency::total 9648444500 # number of demand (read+write) miss cycles
630system.cpu0.dcache.overall_miss_latency::cpu0.data 9648444500 # number of overall miss cycles
631system.cpu0.dcache.overall_miss_latency::total 9648444500 # number of overall miss cycles
632system.cpu0.dcache.ReadReq_accesses::cpu0.data 7645939 # number of ReadReq accesses(hits+misses)
633system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses)
634system.cpu0.dcache.WriteReq_accesses::cpu0.data 5328171 # number of WriteReq accesses(hits+misses)
635system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses)
636system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 136234 # number of LoadLockedReq accesses(hits+misses)
637system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses)
638system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 136185 # number of StoreCondReq accesses(hits+misses)
639system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses)
640system.cpu0.dcache.demand_accesses::cpu0.data 12974110 # number of demand (read+write) accesses
641system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses
642system.cpu0.dcache.overall_accesses::cpu0.data 12974110 # number of overall (read+write) accesses
643system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses
644system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028424 # miss rate for ReadReq accesses
645system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029192 # miss rate for WriteReq accesses
646system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.069410 # miss rate for LoadLockedReq accesses
647system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.060131 # miss rate for StoreCondReq accesses
648system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028739 # miss rate for demand accesses
649system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028739 # miss rate for overall accesses
650system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385 # average ReadReq miss latency
651system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901 # average WriteReq miss latency
652system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency
653system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency
654system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency
655system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency
656system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
657system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
658system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
659system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked

660system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
661system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

660system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
661system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

662system.cpu0.dcache.fast_writes 0 # number of fast writes performed
663system.cpu0.dcache.cache_copies 0 # number of cache copies performed
664system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks
665system.cpu0.dcache.writebacks::total 294891 # number of writebacks
666system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses
667system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses
668system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses
669system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses
670system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9456 # number of LoadLockedReq MSHR misses
671system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9456 # number of LoadLockedReq MSHR misses
672system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8184 # number of StoreCondReq MSHR misses
673system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses
674system.cpu0.dcache.demand_mshr_misses::cpu0.data 372868 # number of demand (read+write) MSHR misses
675system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses
676system.cpu0.dcache.overall_mshr_misses::cpu0.data 372868 # number of overall MSHR misses
677system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses
678system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678673500 # number of ReadReq MSHR miss cycles
679system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678673500 # number of ReadReq MSHR miss cycles
680system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5851029000 # number of WriteReq MSHR miss cycles
681system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles
682system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71881000 # number of LoadLockedReq MSHR miss cycles
683system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles
684system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45691000 # number of StoreCondReq MSHR miss cycles
685system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45691000 # number of StoreCondReq MSHR miss cycles
686system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
687system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
688system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8529702500 # number of demand (read+write) MSHR miss cycles
689system.cpu0.dcache.demand_mshr_miss_latency::total 8529702500 # number of demand (read+write) MSHR miss cycles
690system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8529702500 # number of overall MSHR miss cycles
691system.cpu0.dcache.overall_mshr_miss_latency::total 8529702500 # number of overall MSHR miss cycles
692system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9171180500 # number of ReadReq MSHR uncacheable cycles
693system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles
694system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles
695system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 40129379500 # number of WriteReq MSHR uncacheable cycles
696system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 49300560000 # number of overall MSHR uncacheable cycles
697system.cpu0.dcache.overall_mshr_uncacheable_latency::total 49300560000 # number of overall MSHR uncacheable cycles
698system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses
699system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029192 # mshr miss rate for WriteReq accesses
700system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses
701system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.060095 # mshr miss rate for StoreCondReq accesses
702system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for demand accesses
703system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses
704system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency
705system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency
706system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency
707system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5582.966764 # average StoreCondReq mshr miss latency
708system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
709system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency
710system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency
711system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
712system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
713system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
714system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
715system.cpu1.dtb.inst_hits 0 # ITB inst hits
716system.cpu1.dtb.inst_misses 0 # ITB inst misses
717system.cpu1.dtb.read_hits 7762498 # DTB read hits
718system.cpu1.dtb.read_misses 5432 # DTB read misses
719system.cpu1.dtb.write_hits 5411649 # DTB write hits
720system.cpu1.dtb.write_misses 1096 # DTB write misses
721system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
722system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
723system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
724system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
725system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB
726system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
727system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch
728system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
729system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions
730system.cpu1.dtb.read_accesses 7767930 # DTB read accesses
731system.cpu1.dtb.write_accesses 5412745 # DTB write accesses
732system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
733system.cpu1.dtb.hits 13174147 # DTB hits
734system.cpu1.dtb.misses 6528 # DTB misses
735system.cpu1.dtb.accesses 13180675 # DTB accesses
736system.cpu1.itb.inst_hits 26848300 # ITB inst hits
737system.cpu1.itb.inst_misses 3154 # ITB inst misses
738system.cpu1.itb.read_hits 0 # DTB read hits
739system.cpu1.itb.read_misses 0 # DTB read misses
740system.cpu1.itb.write_hits 0 # DTB write hits
741system.cpu1.itb.write_misses 0 # DTB write misses
742system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
743system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
744system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
745system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
746system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB
747system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
748system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
749system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
750system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
751system.cpu1.itb.read_accesses 0 # DTB read accesses
752system.cpu1.itb.write_accesses 0 # DTB write accesses
753system.cpu1.itb.inst_accesses 26851454 # ITB inst accesses
754system.cpu1.itb.hits 26848300 # DTB hits
755system.cpu1.itb.misses 3154 # DTB misses
756system.cpu1.itb.accesses 26851454 # DTB accesses
757system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
758system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
759system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
760system.cpu1.committedInsts 25921780 # Number of instructions committed
761system.cpu1.committedOps 34444955 # Number of ops (including micro ops) committed
762system.cpu1.num_int_alu_accesses 31033271 # Number of integer alu accesses
763system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
764system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
765system.cpu1.num_conditional_control_insts 3472619 # number of instructions that are conditional controls
766system.cpu1.num_int_insts 31033271 # number of integer instructions
767system.cpu1.num_fp_insts 5714 # number of float instructions
768system.cpu1.num_int_register_reads 181157292 # number of times the integer registers were read
769system.cpu1.num_int_register_writes 32585326 # number of times the integer registers were written
770system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read
771system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written
772system.cpu1.num_mem_refs 13796846 # number of memory refs
773system.cpu1.num_load_insts 8139021 # Number of load instructions
774system.cpu1.num_store_insts 5657825 # Number of store instructions
775system.cpu1.num_idle_cycles 4950307196.068146 # Number of idle cycles
776system.cpu1.num_busy_cycles 388915253.931854 # Number of busy cycles
777system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles
778system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles
779system.cpu1.kern.inst.arm 0 # number of arm instructions executed
780system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed
781system.cpu1.icache.replacements 508221 # number of replacements
782system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use
783system.cpu1.icache.total_refs 26339563 # Total number of references to valid blocks.
784system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
785system.cpu1.icache.avg_refs 51.774827 # Average number of references to valid blocks.
786system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
787system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor
788system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy
789system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy
790system.cpu1.icache.ReadReq_hits::cpu1.inst 26339563 # number of ReadReq hits
791system.cpu1.icache.ReadReq_hits::total 26339563 # number of ReadReq hits
792system.cpu1.icache.demand_hits::cpu1.inst 26339563 # number of demand (read+write) hits
793system.cpu1.icache.demand_hits::total 26339563 # number of demand (read+write) hits
794system.cpu1.icache.overall_hits::cpu1.inst 26339563 # number of overall hits
795system.cpu1.icache.overall_hits::total 26339563 # number of overall hits
796system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses
797system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses
798system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses
799system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses
800system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses
801system.cpu1.icache.overall_misses::total 508733 # number of overall misses
802system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436443000 # number of ReadReq miss cycles
803system.cpu1.icache.ReadReq_miss_latency::total 7436443000 # number of ReadReq miss cycles
804system.cpu1.icache.demand_miss_latency::cpu1.inst 7436443000 # number of demand (read+write) miss cycles
805system.cpu1.icache.demand_miss_latency::total 7436443000 # number of demand (read+write) miss cycles
806system.cpu1.icache.overall_miss_latency::cpu1.inst 7436443000 # number of overall miss cycles
807system.cpu1.icache.overall_miss_latency::total 7436443000 # number of overall miss cycles
808system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848296 # number of ReadReq accesses(hits+misses)
809system.cpu1.icache.ReadReq_accesses::total 26848296 # number of ReadReq accesses(hits+misses)
810system.cpu1.icache.demand_accesses::cpu1.inst 26848296 # number of demand (read+write) accesses
811system.cpu1.icache.demand_accesses::total 26848296 # number of demand (read+write) accesses
812system.cpu1.icache.overall_accesses::cpu1.inst 26848296 # number of overall (read+write) accesses
813system.cpu1.icache.overall_accesses::total 26848296 # number of overall (read+write) accesses
814system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses
815system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses
816system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses
817system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency
818system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency
819system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency
820system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
821system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
822system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
823system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked

824system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
825system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

824system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
825system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

826system.cpu1.icache.fast_writes 0 # number of fast writes performed
827system.cpu1.icache.cache_copies 0 # number of cache copies performed
828system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks
829system.cpu1.icache.writebacks::total 27998 # number of writebacks
830system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses
831system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses
832system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses
833system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses
834system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses
835system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses
836system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908061000 # number of ReadReq MSHR miss cycles
837system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908061000 # number of ReadReq MSHR miss cycles
838system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908061000 # number of demand (read+write) MSHR miss cycles
839system.cpu1.icache.demand_mshr_miss_latency::total 5908061000 # number of demand (read+write) MSHR miss cycles
840system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908061000 # number of overall MSHR miss cycles
841system.cpu1.icache.overall_mshr_miss_latency::total 5908061000 # number of overall MSHR miss cycles
842system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
843system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
844system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
845system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
846system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses
847system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses
848system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses
849system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average ReadReq mshr miss latency
850system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency
851system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency
852system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
853system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
854system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
855system.cpu1.dcache.replacements 295754 # number of replacements
856system.cpu1.dcache.tagsinuse 467.166428 # Cycle average of tags in use
857system.cpu1.dcache.total_refs 11737110 # Total number of references to valid blocks.
858system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
859system.cpu1.dcache.avg_refs 39.616797 # Average number of references to valid blocks.
860system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
861system.cpu1.dcache.occ_blocks::cpu1.data 467.166428 # Average occupied blocks per requestor
862system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy
863system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy
864system.cpu1.dcache.ReadReq_hits::cpu1.data 6345292 # number of ReadReq hits
865system.cpu1.dcache.ReadReq_hits::total 6345292 # number of ReadReq hits
866system.cpu1.dcache.WriteReq_hits::cpu1.data 5152611 # number of WriteReq hits
867system.cpu1.dcache.WriteReq_hits::total 5152611 # number of WriteReq hits
868system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits
869system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
870system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits
871system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
872system.cpu1.dcache.demand_hits::cpu1.data 11497903 # number of demand (read+write) hits
873system.cpu1.dcache.demand_hits::total 11497903 # number of demand (read+write) hits
874system.cpu1.dcache.overall_hits::cpu1.data 11497903 # number of overall hits
875system.cpu1.dcache.overall_hits::total 11497903 # number of overall hits
876system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses
877system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
878system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses
879system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses
880system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11557 # number of LoadLockedReq misses
881system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses
882system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9906 # number of StoreCondReq misses
883system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses
884system.cpu1.dcache.demand_misses::cpu1.data 325738 # number of demand (read+write) misses
885system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
886system.cpu1.dcache.overall_misses::cpu1.data 325738 # number of overall misses
887system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
888system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729025500 # number of ReadReq miss cycles
889system.cpu1.dcache.ReadReq_miss_latency::total 2729025500 # number of ReadReq miss cycles
890system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles
891system.cpu1.dcache.WriteReq_miss_latency::total 4123985000 # number of WriteReq miss cycles
892system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131720000 # number of LoadLockedReq miss cycles
893system.cpu1.dcache.LoadLockedReq_miss_latency::total 131720000 # number of LoadLockedReq miss cycles
894system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 82493000 # number of StoreCondReq miss cycles
895system.cpu1.dcache.StoreCondReq_miss_latency::total 82493000 # number of StoreCondReq miss cycles
896system.cpu1.dcache.demand_miss_latency::cpu1.data 6853010500 # number of demand (read+write) miss cycles
897system.cpu1.dcache.demand_miss_latency::total 6853010500 # number of demand (read+write) miss cycles
898system.cpu1.dcache.overall_miss_latency::cpu1.data 6853010500 # number of overall miss cycles
899system.cpu1.dcache.overall_miss_latency::total 6853010500 # number of overall miss cycles
900system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533537 # number of ReadReq accesses(hits+misses)
901system.cpu1.dcache.ReadReq_accesses::total 6533537 # number of ReadReq accesses(hits+misses)
902system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290104 # number of WriteReq accesses(hits+misses)
903system.cpu1.dcache.WriteReq_accesses::total 5290104 # number of WriteReq accesses(hits+misses)
904system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses)
905system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
906system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses)
907system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
908system.cpu1.dcache.demand_accesses::cpu1.data 11823641 # number of demand (read+write) accesses
909system.cpu1.dcache.demand_accesses::total 11823641 # number of demand (read+write) accesses
910system.cpu1.dcache.overall_accesses::cpu1.data 11823641 # number of overall (read+write) accesses
911system.cpu1.dcache.overall_accesses::total 11823641 # number of overall (read+write) accesses
912system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses
913system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses
914system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses
915system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses
916system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses
917system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses
918system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.200457 # average ReadReq miss latency
919system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency
920system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.421476 # average LoadLockedReq miss latency
921system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency
922system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency
923system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.412773 # average overall miss latency
924system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
925system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
926system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
927system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked

928system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
929system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

928system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
929system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

930system.cpu1.dcache.fast_writes 0 # number of fast writes performed
931system.cpu1.dcache.cache_copies 0 # number of cache copies performed
932system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks
933system.cpu1.dcache.writebacks::total 253551 # number of writebacks
934system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses
935system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses
936system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses
937system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses
938system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses
939system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses
940system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses
941system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses
942system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses
943system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses
944system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses
945system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses
946system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164155000 # number of ReadReq MSHR miss cycles
947system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164155000 # number of ReadReq MSHR miss cycles
948system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles
949system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles
950system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97049000 # number of LoadLockedReq MSHR miss cycles
951system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97049000 # number of LoadLockedReq MSHR miss cycles
952system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles
953system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles
954system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875621500 # number of demand (read+write) MSHR miss cycles
955system.cpu1.dcache.demand_mshr_miss_latency::total 5875621500 # number of demand (read+write) MSHR miss cycles
956system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875621500 # number of overall MSHR miss cycles
957system.cpu1.dcache.overall_mshr_miss_latency::total 5875621500 # number of overall MSHR miss cycles
958system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931976000 # number of ReadReq MSHR uncacheable cycles
959system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931976000 # number of ReadReq MSHR uncacheable cycles
960system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470527000 # number of WriteReq MSHR uncacheable cycles
961system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470527000 # number of WriteReq MSHR uncacheable cycles
962system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402503000 # number of overall MSHR uncacheable cycles
963system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402503000 # number of overall MSHR uncacheable cycles
964system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses
965system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses
966system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses
967system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses
968system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses
969system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses
970system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.480650 # average ReadReq mshr miss latency
971system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency
972system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.421476 # average LoadLockedReq mshr miss latency
973system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency
974system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency
975system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency
976system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
977system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
978system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
979system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
980system.iocache.replacements 0 # number of replacements
981system.iocache.tagsinuse 0 # Cycle average of tags in use
982system.iocache.total_refs 0 # Total number of references to valid blocks.
983system.iocache.sampled_refs 0 # Sample count of references to valid blocks.

984system.iocache.avg_refs no_value # Average number of references to valid blocks.

984system.iocache.avg_refs nan # Average number of references to valid blocks.

985system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
986system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
987system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
988system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
989system.iocache.blocked::no_targets 0 # number of cycles access was blocked

990system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
991system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked

990system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
991system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked