Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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stats.txt (11680:b4d943429dc6)	stats.txt (11687:b3d5f0e9e258)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.870823 # Number of seconds simulated 4sim_ticks 2870822663000 # Number of ticks simulated 5final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.870823 # Number of seconds simulated 4sim_ticks 2870822663000 # Number of ticks simulated 5final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 442891 # Simulator instruction rate (inst/s) 8host_op_rate 535691 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9664154143 # Simulator tick rate (ticks/s) 10host_mem_usage 616988 # Number of bytes of host memory used 11host_seconds 297.06 # Real time elapsed on the host	7host_inst_rate 1048966 # Simulator instruction rate (inst/s) 8host_op_rate 1268757 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22889064818 # Simulator tick rate (ticks/s) 10host_mem_usage 618276 # Number of bytes of host memory used 11host_seconds 125.42 # Real time elapsed on the host
12sim_insts 131564747 # Number of instructions simulated 13sim_ops 159131669 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.readReqs 198466 # Number of read requests accepted 77system.physmem.writeReqs 140553 # Number of write requests accepted 78system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue 79system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue 80system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM 81system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue 82system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM 83system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side 84system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side 85system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue 86system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 87system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 88system.physmem.perBankRdBursts::0 11821 # Per bank write bursts 89system.physmem.perBankRdBursts::1 11810 # Per bank write bursts 90system.physmem.perBankRdBursts::2 12062 # Per bank write bursts 91system.physmem.perBankRdBursts::3 12027 # Per bank write bursts 92system.physmem.perBankRdBursts::4 20473 # Per bank write bursts 93system.physmem.perBankRdBursts::5 12098 # Per bank write bursts 94system.physmem.perBankRdBursts::6 12277 # Per bank write bursts 95system.physmem.perBankRdBursts::7 12432 # Per bank write bursts 96system.physmem.perBankRdBursts::8 12179 # Per bank write bursts 97system.physmem.perBankRdBursts::9 12459 # Per bank write bursts 98system.physmem.perBankRdBursts::10 11810 # Per bank write bursts 99system.physmem.perBankRdBursts::11 11367 # Per bank write bursts 100system.physmem.perBankRdBursts::12 11535 # Per bank write bursts 101system.physmem.perBankRdBursts::13 11583 # Per bank write bursts 102system.physmem.perBankRdBursts::14 11073 # Per bank write bursts 103system.physmem.perBankRdBursts::15 11307 # Per bank write bursts 104system.physmem.perBankWrBursts::0 8516 # Per bank write bursts 105system.physmem.perBankWrBursts::1 8730 # Per bank write bursts 106system.physmem.perBankWrBursts::2 8955 # Per bank write bursts 107system.physmem.perBankWrBursts::3 8735 # Per bank write bursts 108system.physmem.perBankWrBursts::4 8248 # Per bank write bursts 109system.physmem.perBankWrBursts::5 8655 # Per bank write bursts 110system.physmem.perBankWrBursts::6 8964 # Per bank write bursts 111system.physmem.perBankWrBursts::7 8852 # Per bank write bursts 112system.physmem.perBankWrBursts::8 8742 # Per bank write bursts 113system.physmem.perBankWrBursts::9 8980 # Per bank write bursts 114system.physmem.perBankWrBursts::10 8644 # Per bank write bursts 115system.physmem.perBankWrBursts::11 8478 # Per bank write bursts 116system.physmem.perBankWrBursts::12 8438 # Per bank write bursts 117system.physmem.perBankWrBursts::13 8004 # Per bank write bursts 118system.physmem.perBankWrBursts::14 7925 # Per bank write bursts 119system.physmem.perBankWrBursts::15 7759 # Per bank write bursts 120system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 121system.physmem.numWrRetry 91 # Number of times write queue was full causing retry 122system.physmem.totGap 2870821632000 # Total gap between requests 123system.physmem.readPktSize::0 0 # Read request sizes (log2) 124system.physmem.readPktSize::1 0 # Read request sizes (log2) 125system.physmem.readPktSize::2 9732 # Read request sizes (log2) 126system.physmem.readPktSize::3 28 # Read request sizes (log2) 127system.physmem.readPktSize::4 0 # Read request sizes (log2) 128system.physmem.readPktSize::5 0 # Read request sizes (log2) 129system.physmem.readPktSize::6 188706 # Read request sizes (log2) 130system.physmem.writePktSize::0 0 # Write request sizes (log2) 131system.physmem.writePktSize::1 0 # Write request sizes (log2) 132system.physmem.writePktSize::2 4391 # Write request sizes (log2) 133system.physmem.writePktSize::3 0 # Write request sizes (log2) 134system.physmem.writePktSize::4 0 # Write request sizes (log2) 135system.physmem.writePktSize::5 0 # Write request sizes (log2) 136system.physmem.writePktSize::6 136162 # Write request sizes (log2) 137system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 169system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see 233system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation 247system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes 254system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads 295system.physmem.totQLat 9353740299 # Total ticks spent queuing 296system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.06 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing 311system.physmem.readRowHits 165583 # Number of row buffer hits during reads 312system.physmem.writeRowHits 84490 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes 315system.physmem.avgGap 8468025.78 # Average gap between requests 316system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined 317system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ) 318system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ) 319system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ) 320system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ) 321system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ) 322system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ) 323system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ) 324system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ) 325system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ) 326system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ) 327system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ) 328system.physmem_0.averagePower 247.210424 # Core power per rank (mW) 329system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank 330system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states 331system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states 332system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states 336system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ) 343system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ) 344system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ) 345system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ) 346system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ) 347system.physmem_1.averagePower 247.137601 # Core power per rank (mW) 348system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank 349system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states 350system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states 351system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states 352system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states 353system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states 354system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states 355system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 356system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 359system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 362system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 365system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 374system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 375system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 376system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 377system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 378system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 379system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 380system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 381system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 382system.cf0.dma_write_txs 631 # Number of DMA write transactions. 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 394system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 395system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 396system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 397system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 398system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 404system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 406system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 409system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 410system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 411system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 412system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 413system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 414system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 415system.cpu0.dtb.walker.walks 7793 # Table walker walks requested 416system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors 417system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate 418system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate 419system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution 433system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution 434system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution 435system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated 436system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated 437system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated 438system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst 439system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst 441system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst 442system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst 445system.cpu0.dtb.inst_hits 0 # ITB inst hits 446system.cpu0.dtb.inst_misses 0 # ITB inst misses 447system.cpu0.dtb.read_hits 25156364 # DTB read hits 448system.cpu0.dtb.read_misses 6669 # DTB read misses 449system.cpu0.dtb.write_hits 18748845 # DTB write hits 450system.cpu0.dtb.write_misses 1124 # DTB write misses 451system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 452system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 453system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 454system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 455system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB 456system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 457system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch 458system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 459system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 460system.cpu0.dtb.read_accesses 25163033 # DTB read accesses 461system.cpu0.dtb.write_accesses 18749969 # DTB write accesses 462system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 463system.cpu0.dtb.hits 43905209 # DTB hits 464system.cpu0.dtb.misses 7793 # DTB misses 465system.cpu0.dtb.accesses 43913002 # DTB accesses 466system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 467system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 476system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 477system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 478system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 479system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 480system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 481system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 482system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 483system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 484system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 485system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 486system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 487system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 488system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 489system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 490system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 491system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 492system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 493system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 494system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 495system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 496system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 497system.cpu0.itb.walker.walks 3349 # Table walker walks requested 498system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 499system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 500system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 501system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 502system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 503system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 504system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution 520system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution 521system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution 522system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated 523system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated 524system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated 525system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 526system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst 527system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst 528system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 529system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst 530system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst 532system.cpu0.itb.inst_hits 119019454 # ITB inst hits 533system.cpu0.itb.inst_misses 3349 # ITB inst misses 534system.cpu0.itb.read_hits 0 # DTB read hits 535system.cpu0.itb.read_misses 0 # DTB read misses 536system.cpu0.itb.write_hits 0 # DTB write hits 537system.cpu0.itb.write_misses 0 # DTB write misses 538system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 539system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 540system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 541system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 542system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB 543system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 544system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 545system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 546system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 547system.cpu0.itb.read_accesses 0 # DTB read accesses 548system.cpu0.itb.write_accesses 0 # DTB write accesses 549system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses 550system.cpu0.itb.hits 119019454 # DTB hits 551system.cpu0.itb.misses 3349 # DTB misses 552system.cpu0.itb.accesses 119022803 # DTB accesses 553system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions 554system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state 555system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state 556system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state 557system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state 558system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state 559system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 560system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states 565system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states 566system.cpu0.numCycles 5741645326 # number of cpu cycles simulated 567system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 568system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 569system.cpu0.kern.inst.arm 0 # number of arm instructions executed 570system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed 571system.cpu0.committedInsts 115354991 # Number of instructions committed 572system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed 573system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses 574system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses 575system.cpu0.num_func_calls 12675511 # number of times a function call or return occured 576system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls 577system.cpu0.num_int_insts 123361088 # number of integer instructions 578system.cpu0.num_fp_insts 9690 # number of float instructions 579system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read 580system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written 581system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read 582system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 583system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read 584system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written 585system.cpu0.num_mem_refs 45041487 # number of memory refs 586system.cpu0.num_load_insts 25408167 # Number of load instructions 587system.cpu0.num_store_insts 19633320 # Number of store instructions 588system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles 589system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles 590system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles 591system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles 592system.cpu0.Branches 29114863 # Number of branches fetched 593system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 594system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction 595system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction 596system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction 597system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction 598system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction 599system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction 600system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction	12sim_insts 131564747 # Number of instructions simulated 13sim_ops 159131669 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.readReqs 198466 # Number of read requests accepted 77system.physmem.writeReqs 140553 # Number of write requests accepted 78system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue 79system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue 80system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM 81system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue 82system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM 83system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side 84system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side 85system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue 86system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one 87system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 88system.physmem.perBankRdBursts::0 11821 # Per bank write bursts 89system.physmem.perBankRdBursts::1 11810 # Per bank write bursts 90system.physmem.perBankRdBursts::2 12062 # Per bank write bursts 91system.physmem.perBankRdBursts::3 12027 # Per bank write bursts 92system.physmem.perBankRdBursts::4 20473 # Per bank write bursts 93system.physmem.perBankRdBursts::5 12098 # Per bank write bursts 94system.physmem.perBankRdBursts::6 12277 # Per bank write bursts 95system.physmem.perBankRdBursts::7 12432 # Per bank write bursts 96system.physmem.perBankRdBursts::8 12179 # Per bank write bursts 97system.physmem.perBankRdBursts::9 12459 # Per bank write bursts 98system.physmem.perBankRdBursts::10 11810 # Per bank write bursts 99system.physmem.perBankRdBursts::11 11367 # Per bank write bursts 100system.physmem.perBankRdBursts::12 11535 # Per bank write bursts 101system.physmem.perBankRdBursts::13 11583 # Per bank write bursts 102system.physmem.perBankRdBursts::14 11073 # Per bank write bursts 103system.physmem.perBankRdBursts::15 11307 # Per bank write bursts 104system.physmem.perBankWrBursts::0 8516 # Per bank write bursts 105system.physmem.perBankWrBursts::1 8730 # Per bank write bursts 106system.physmem.perBankWrBursts::2 8955 # Per bank write bursts 107system.physmem.perBankWrBursts::3 8735 # Per bank write bursts 108system.physmem.perBankWrBursts::4 8248 # Per bank write bursts 109system.physmem.perBankWrBursts::5 8655 # Per bank write bursts 110system.physmem.perBankWrBursts::6 8964 # Per bank write bursts 111system.physmem.perBankWrBursts::7 8852 # Per bank write bursts 112system.physmem.perBankWrBursts::8 8742 # Per bank write bursts 113system.physmem.perBankWrBursts::9 8980 # Per bank write bursts 114system.physmem.perBankWrBursts::10 8644 # Per bank write bursts 115system.physmem.perBankWrBursts::11 8478 # Per bank write bursts 116system.physmem.perBankWrBursts::12 8438 # Per bank write bursts 117system.physmem.perBankWrBursts::13 8004 # Per bank write bursts 118system.physmem.perBankWrBursts::14 7925 # Per bank write bursts 119system.physmem.perBankWrBursts::15 7759 # Per bank write bursts 120system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 121system.physmem.numWrRetry 91 # Number of times write queue was full causing retry 122system.physmem.totGap 2870821632000 # Total gap between requests 123system.physmem.readPktSize::0 0 # Read request sizes (log2) 124system.physmem.readPktSize::1 0 # Read request sizes (log2) 125system.physmem.readPktSize::2 9732 # Read request sizes (log2) 126system.physmem.readPktSize::3 28 # Read request sizes (log2) 127system.physmem.readPktSize::4 0 # Read request sizes (log2) 128system.physmem.readPktSize::5 0 # Read request sizes (log2) 129system.physmem.readPktSize::6 188706 # Read request sizes (log2) 130system.physmem.writePktSize::0 0 # Write request sizes (log2) 131system.physmem.writePktSize::1 0 # Write request sizes (log2) 132system.physmem.writePktSize::2 4391 # Write request sizes (log2) 133system.physmem.writePktSize::3 0 # Write request sizes (log2) 134system.physmem.writePktSize::4 0 # Write request sizes (log2) 135system.physmem.writePktSize::5 0 # Write request sizes (log2) 136system.physmem.writePktSize::6 136162 # Write request sizes (log2) 137system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 169system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see 233system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation 247system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes 254system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads 295system.physmem.totQLat 9353740299 # Total ticks spent queuing 296system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM 297system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers 298system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 0.06 # Data bus utilization in percentage 307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing 311system.physmem.readRowHits 165583 # Number of row buffer hits during reads 312system.physmem.writeRowHits 84490 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes 315system.physmem.avgGap 8468025.78 # Average gap between requests 316system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined 317system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ) 318system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ) 319system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ) 320system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ) 321system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ) 322system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ) 323system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ) 324system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ) 325system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ) 326system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ) 327system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ) 328system.physmem_0.averagePower 247.210424 # Core power per rank (mW) 329system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank 330system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states 331system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states 332system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states 336system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ) 343system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ) 344system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ) 345system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ) 346system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ) 347system.physmem_1.averagePower 247.137601 # Core power per rank (mW) 348system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank 349system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states 350system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states 351system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states 352system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states 353system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states 354system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states 355system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 356system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 359system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 362system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 363system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 365system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 374system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 375system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 376system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 377system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 378system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 379system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 380system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 381system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 382system.cf0.dma_write_txs 631 # Number of DMA write transactions. 383system.cpu_clk_domain.clock 500 # Clock period in ticks 384system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 394system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 395system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 396system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 397system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 398system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 401system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 403system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 404system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 406system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 409system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 410system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 411system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 412system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 413system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 414system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 415system.cpu0.dtb.walker.walks 7793 # Table walker walks requested 416system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors 417system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate 418system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate 419system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution 433system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution 434system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution 435system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated 436system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated 437system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated 438system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst 439system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 440system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst 441system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst 442system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 443system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst 444system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst 445system.cpu0.dtb.inst_hits 0 # ITB inst hits 446system.cpu0.dtb.inst_misses 0 # ITB inst misses 447system.cpu0.dtb.read_hits 25156364 # DTB read hits 448system.cpu0.dtb.read_misses 6669 # DTB read misses 449system.cpu0.dtb.write_hits 18748845 # DTB write hits 450system.cpu0.dtb.write_misses 1124 # DTB write misses 451system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 452system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 453system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 454system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 455system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB 456system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 457system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch 458system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 459system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 460system.cpu0.dtb.read_accesses 25163033 # DTB read accesses 461system.cpu0.dtb.write_accesses 18749969 # DTB write accesses 462system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 463system.cpu0.dtb.hits 43905209 # DTB hits 464system.cpu0.dtb.misses 7793 # DTB misses 465system.cpu0.dtb.accesses 43913002 # DTB accesses 466system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 467system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 476system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 477system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 478system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 479system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 480system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 481system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 482system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 483system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 484system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 485system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 486system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 487system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 488system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 489system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 490system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 491system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 492system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 493system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 494system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 495system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 496system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 497system.cpu0.itb.walker.walks 3349 # Table walker walks requested 498system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 499system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 500system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 501system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 502system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 503system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 504system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency 507system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency 508system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency 509system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution 520system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution 521system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution 522system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated 523system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated 524system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated 525system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 526system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst 527system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst 528system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 529system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst 530system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst 532system.cpu0.itb.inst_hits 119019454 # ITB inst hits 533system.cpu0.itb.inst_misses 3349 # ITB inst misses 534system.cpu0.itb.read_hits 0 # DTB read hits 535system.cpu0.itb.read_misses 0 # DTB read misses 536system.cpu0.itb.write_hits 0 # DTB write hits 537system.cpu0.itb.write_misses 0 # DTB write misses 538system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 539system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 540system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 541system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 542system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB 543system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 544system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 545system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 546system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 547system.cpu0.itb.read_accesses 0 # DTB read accesses 548system.cpu0.itb.write_accesses 0 # DTB write accesses 549system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses 550system.cpu0.itb.hits 119019454 # DTB hits 551system.cpu0.itb.misses 3349 # DTB misses 552system.cpu0.itb.accesses 119022803 # DTB accesses 553system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions 554system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state 555system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state 556system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state 557system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state 558system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state 559system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 560system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state 561system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 562system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state 563system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state 564system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states 565system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states 566system.cpu0.numCycles 5741645326 # number of cpu cycles simulated 567system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 568system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 569system.cpu0.kern.inst.arm 0 # number of arm instructions executed 570system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed 571system.cpu0.committedInsts 115354991 # Number of instructions committed 572system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed 573system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses 574system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses 575system.cpu0.num_func_calls 12675511 # number of times a function call or return occured 576system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls 577system.cpu0.num_int_insts 123361088 # number of integer instructions 578system.cpu0.num_fp_insts 9690 # number of float instructions 579system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read 580system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written 581system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read 582system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 583system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read 584system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written 585system.cpu0.num_mem_refs 45041487 # number of memory refs 586system.cpu0.num_load_insts 25408167 # Number of load instructions 587system.cpu0.num_store_insts 19633320 # Number of store instructions 588system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles 589system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles 590system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles 591system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles 592system.cpu0.Branches 29114863 # Number of branches fetched 593system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 594system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction 595system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction 596system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction 597system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction 598system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction 599system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction 600system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
	601system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction
601system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction	602system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
	603system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction
602system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction 603system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction 604system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction 605system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction 606system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction 607system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction 608system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction 609system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction 610system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction 611system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction 612system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction 613system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction 614system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction 615system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction 616system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction 617system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction 618system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction 619system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction 620system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 621system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 622system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction	604system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction 605system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction 606system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction 607system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction 608system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction 609system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction 610system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction 611system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction 612system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction 613system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction 614system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction 615system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction 616system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction 617system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction 618system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction 619system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction 620system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction 621system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction 622system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 623system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 624system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction
623system.cpu0.op_class::MemRead 25408167 17.75% 86.28% # Class of executed instruction 624system.cpu0.op_class::MemWrite 19633320 13.72% 100.00% # Class of executed instruction	625system.cpu0.op_class::MemRead 25405911 17.75% 86.28% # Class of executed instruction 626system.cpu0.op_class::MemWrite 19625890 13.71% 99.99% # Class of executed instruction 627system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction 628system.cpu0.op_class::FloatMemWrite 7430 0.01% 100.00% # Class of executed instruction
625system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 626system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 627system.cpu0.op_class::total 143146475 # Class of executed instruction 628system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 629system.cpu0.dcache.tags.replacements 692883 # number of replacements 630system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use 631system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks. 632system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks. 633system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks. 634system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit. 635system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor 636system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy 637system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy 638system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 639system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 640system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 641system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 642system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 643system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses 644system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses 645system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 646system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits 647system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits 648system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits 649system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits 650system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits 651system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits 652system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits 653system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits 654system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits 655system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits 656system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits 657system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits 658system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits 659system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits 660system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses 661system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses 662system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses 663system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses 664system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses 665system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses 666system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses 667system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses 668system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses 669system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses 670system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses 671system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses 672system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses 673system.cpu0.dcache.overall_misses::total 849725 # number of overall misses 674system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles 675system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles 676system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles 677system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles 678system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles 679system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles 680system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles 681system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles 682system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles 683system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles 684system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles 685system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles 686system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles 687system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles 688system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses) 689system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses) 690system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses) 691system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses) 692system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses) 693system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses) 698system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses 708system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses 709system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses 710system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses 711system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses 712system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses 713system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses 714system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses 715system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses 716system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency 717system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency 718system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency 719system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency 720system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency 721system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency 722system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency 723system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency 724system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 725system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 726system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency 727system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency 728system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency 729system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency 730system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 731system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 732system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 734system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 735system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 736system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks 737system.cpu0.dcache.writebacks::total 692883 # number of writebacks 738system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits 739system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits 740system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits 741system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 742system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits 743system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits 744system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits 745system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits 746system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits 747system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits 748system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses 749system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses 750system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses 751system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses 752system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses 753system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses 754system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses 755system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses 756system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses 757system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses 758system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses 759system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses 760system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses 761system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses 762system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable 763system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable 764system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable 765system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable 766system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses 767system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses 768system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles 769system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles 770system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles 771system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles 772system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles 773system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles 774system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles 775system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles 776system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles 777system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles 778system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles 779system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles 780system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles 781system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles 782system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles 783system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles 784system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles 785system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles 786system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles 787system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles 788system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses 789system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses 790system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses 791system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses 792system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses 793system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses 794system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses 795system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses 796system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses 797system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses 798system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses 799system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses 800system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses 801system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses 802system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency 803system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency 804system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency 805system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency 806system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency 807system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency 808system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency 809system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency 810system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency 811system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency 812system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 813system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 814system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency 815system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency 816system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency 817system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency 818system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency 819system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency 820system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency 821system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency 822system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 823system.cpu0.icache.tags.replacements 1103683 # number of replacements 824system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use 825system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks. 826system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks. 827system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks. 828system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit. 829system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor 830system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy 831system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy 832system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 833system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 834system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 835system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 836system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 837system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses 838system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses 839system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 840system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits 841system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits 842system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits 843system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits 844system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits 845system.cpu0.icache.overall_hits::total 117915250 # number of overall hits 846system.cpu0.icache.ReadReq_misses::cpu0.inst 1104204 # number of ReadReq misses 847system.cpu0.icache.ReadReq_misses::total 1104204 # number of ReadReq misses 848system.cpu0.icache.demand_misses::cpu0.inst 1104204 # number of demand (read+write) misses 849system.cpu0.icache.demand_misses::total 1104204 # number of demand (read+write) misses 850system.cpu0.icache.overall_misses::cpu0.inst 1104204 # number of overall misses 851system.cpu0.icache.overall_misses::total 1104204 # number of overall misses 852system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11911095000 # number of ReadReq miss cycles 853system.cpu0.icache.ReadReq_miss_latency::total 11911095000 # number of ReadReq miss cycles 854system.cpu0.icache.demand_miss_latency::cpu0.inst 11911095000 # number of demand (read+write) miss cycles 855system.cpu0.icache.demand_miss_latency::total 11911095000 # number of demand (read+write) miss cycles 856system.cpu0.icache.overall_miss_latency::cpu0.inst 11911095000 # number of overall miss cycles 857system.cpu0.icache.overall_miss_latency::total 11911095000 # number of overall miss cycles 858system.cpu0.icache.ReadReq_accesses::cpu0.inst 119019454 # number of ReadReq accesses(hits+misses) 859system.cpu0.icache.ReadReq_accesses::total 119019454 # number of ReadReq accesses(hits+misses) 860system.cpu0.icache.demand_accesses::cpu0.inst 119019454 # number of demand (read+write) accesses 861system.cpu0.icache.demand_accesses::total 119019454 # number of demand (read+write) accesses 862system.cpu0.icache.overall_accesses::cpu0.inst 119019454 # number of overall (read+write) accesses 863system.cpu0.icache.overall_accesses::total 119019454 # number of overall (read+write) accesses 864system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009278 # miss rate for ReadReq accesses 865system.cpu0.icache.ReadReq_miss_rate::total 0.009278 # miss rate for ReadReq accesses 866system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009278 # miss rate for demand accesses 867system.cpu0.icache.demand_miss_rate::total 0.009278 # miss rate for demand accesses 868system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009278 # miss rate for overall accesses 869system.cpu0.icache.overall_miss_rate::total 0.009278 # miss rate for overall accesses 870system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068 # average ReadReq miss latency 871system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068 # average ReadReq miss latency 872system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency 873system.cpu0.icache.demand_avg_miss_latency::total 10787.042068 # average overall miss latency 874system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency 875system.cpu0.icache.overall_avg_miss_latency::total 10787.042068 # average overall miss latency 876system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 877system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 878system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 879system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 880system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 881system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 882system.cpu0.icache.writebacks::writebacks 1103683 # number of writebacks 883system.cpu0.icache.writebacks::total 1103683 # number of writebacks 884system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104204 # number of ReadReq MSHR misses 885system.cpu0.icache.ReadReq_mshr_misses::total 1104204 # number of ReadReq MSHR misses 886system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104204 # number of demand (read+write) MSHR misses 887system.cpu0.icache.demand_mshr_misses::total 1104204 # number of demand (read+write) MSHR misses 888system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104204 # number of overall MSHR misses 889system.cpu0.icache.overall_mshr_misses::total 1104204 # number of overall MSHR misses 890system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 891system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 892system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 893system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 894system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles 895system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles 896system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles 897system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles 898system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles 899system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles 900system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles 901system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles 902system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles 903system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles 904system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses 905system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses 906system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for demand accesses 907system.cpu0.icache.demand_mshr_miss_rate::total 0.009278 # mshr miss rate for demand accesses 908system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for overall accesses 909system.cpu0.icache.overall_mshr_miss_rate::total 0.009278 # mshr miss rate for overall accesses 910system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average ReadReq mshr miss latency 911system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068 # average ReadReq mshr miss latency 912system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency 913system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency 914system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency 915system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency 916system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency 917system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency 918system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency 919system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency 920system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 921system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued 922system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified 923system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue 924system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 925system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 926system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing 927system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 928system.cpu0.l2cache.tags.replacements 259898 # number of replacements 929system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use 930system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks. 931system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks. 932system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks. 933system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 934system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor 935system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor 936system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor 937system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor 938system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy 939system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy 940system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 941system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy 942system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy 943system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id 944system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 945system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id 946system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 947system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id 948system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id 949system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id 950system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 951system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 952system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 953system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 954system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id 955system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6084 # Occupied blocks per task id 956system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id 957system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1977 # Occupied blocks per task id 958system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020752 # Percentage of cache occupancy per task id 959system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 960system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933411 # Percentage of cache occupancy per task id 961system.cpu0.l2cache.tags.tag_accesses 61320295 # Number of tag accesses 962system.cpu0.l2cache.tags.data_accesses 61320295 # Number of data accesses 963system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 964system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9508 # number of ReadReq hits 965system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4316 # number of ReadReq hits 966system.cpu0.l2cache.ReadReq_hits::total 13824 # number of ReadReq hits 967system.cpu0.l2cache.WritebackDirty_hits::writebacks 476285 # number of WritebackDirty hits 968system.cpu0.l2cache.WritebackDirty_hits::total 476285 # number of WritebackDirty hits 969system.cpu0.l2cache.WritebackClean_hits::writebacks 1292383 # number of WritebackClean hits 970system.cpu0.l2cache.WritebackClean_hits::total 1292383 # number of WritebackClean hits 971system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227392 # number of ReadExReq hits 972system.cpu0.l2cache.ReadExReq_hits::total 227392 # number of ReadExReq hits 973system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1042059 # number of ReadCleanReq hits 974system.cpu0.l2cache.ReadCleanReq_hits::total 1042059 # number of ReadCleanReq hits 975system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376265 # number of ReadSharedReq hits 976system.cpu0.l2cache.ReadSharedReq_hits::total 376265 # number of ReadSharedReq hits 977system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9508 # number of demand (read+write) hits 978system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4316 # number of demand (read+write) hits 979system.cpu0.l2cache.demand_hits::cpu0.inst 1042059 # number of demand (read+write) hits 980system.cpu0.l2cache.demand_hits::cpu0.data 603657 # number of demand (read+write) hits 981system.cpu0.l2cache.demand_hits::total 1659540 # number of demand (read+write) hits 982system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9508 # number of overall hits 983system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4316 # number of overall hits 984system.cpu0.l2cache.overall_hits::cpu0.inst 1042059 # number of overall hits 985system.cpu0.l2cache.overall_hits::cpu0.data 603657 # number of overall hits 986system.cpu0.l2cache.overall_hits::total 1659540 # number of overall hits 987system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 306 # number of ReadReq misses 988system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 159 # number of ReadReq misses 989system.cpu0.l2cache.ReadReq_misses::total 465 # number of ReadReq misses 990system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55222 # number of UpgradeReq misses 991system.cpu0.l2cache.UpgradeReq_misses::total 55222 # number of UpgradeReq misses 992system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19651 # number of SCUpgradeReq misses 993system.cpu0.l2cache.SCUpgradeReq_misses::total 19651 # number of SCUpgradeReq misses 994system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 995system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 996system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43215 # number of ReadExReq misses 997system.cpu0.l2cache.ReadExReq_misses::total 43215 # number of ReadExReq misses 998system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62145 # number of ReadCleanReq misses 999system.cpu0.l2cache.ReadCleanReq_misses::total 62145 # number of ReadCleanReq misses 1000system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101544 # number of ReadSharedReq misses 1001system.cpu0.l2cache.ReadSharedReq_misses::total 101544 # number of ReadSharedReq misses 1002system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 306 # number of demand (read+write) misses 1003system.cpu0.l2cache.demand_misses::cpu0.itb.walker 159 # number of demand (read+write) misses 1004system.cpu0.l2cache.demand_misses::cpu0.inst 62145 # number of demand (read+write) misses 1005system.cpu0.l2cache.demand_misses::cpu0.data 144759 # number of demand (read+write) misses 1006system.cpu0.l2cache.demand_misses::total 207369 # number of demand (read+write) misses 1007system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 306 # number of overall misses 1008system.cpu0.l2cache.overall_misses::cpu0.itb.walker 159 # number of overall misses 1009system.cpu0.l2cache.overall_misses::cpu0.inst 62145 # number of overall misses 1010system.cpu0.l2cache.overall_misses::cpu0.data 144759 # number of overall misses 1011system.cpu0.l2cache.overall_misses::total 207369 # number of overall misses 1012system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8941000 # number of ReadReq miss cycles 1013system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3729500 # number of ReadReq miss cycles 1014system.cpu0.l2cache.ReadReq_miss_latency::total 12670500 # number of ReadReq miss cycles 1015system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32046500 # number of UpgradeReq miss cycles 1016system.cpu0.l2cache.UpgradeReq_miss_latency::total 32046500 # number of UpgradeReq miss cycles 1017system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9591500 # number of SCUpgradeReq miss cycles 1018system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9591500 # number of SCUpgradeReq miss cycles 1019system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1480500 # number of SCUpgradeFailReq miss cycles 1020system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1480500 # number of SCUpgradeFailReq miss cycles 1021system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2734835500 # number of ReadExReq miss cycles 1022system.cpu0.l2cache.ReadExReq_miss_latency::total 2734835500 # number of ReadExReq miss cycles 1023system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3426232500 # number of ReadCleanReq miss cycles 1024system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3426232500 # number of ReadCleanReq miss cycles 1025system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3359763500 # number of ReadSharedReq miss cycles 1026system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3359763500 # number of ReadSharedReq miss cycles 1027system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8941000 # number of demand (read+write) miss cycles 1028system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3729500 # number of demand (read+write) miss cycles 1029system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3426232500 # number of demand (read+write) miss cycles 1030system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094599000 # number of demand (read+write) miss cycles 1031system.cpu0.l2cache.demand_miss_latency::total 9533502000 # number of demand (read+write) miss cycles 1032system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8941000 # number of overall miss cycles 1033system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3729500 # number of overall miss cycles 1034system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3426232500 # number of overall miss cycles 1035system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094599000 # number of overall miss cycles 1036system.cpu0.l2cache.overall_miss_latency::total 9533502000 # number of overall miss cycles 1037system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9814 # number of ReadReq accesses(hits+misses) 1038system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4475 # number of ReadReq accesses(hits+misses) 1039system.cpu0.l2cache.ReadReq_accesses::total 14289 # number of ReadReq accesses(hits+misses) 1040system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476285 # number of WritebackDirty accesses(hits+misses) 1041system.cpu0.l2cache.WritebackDirty_accesses::total 476285 # number of WritebackDirty accesses(hits+misses) 1042system.cpu0.l2cache.WritebackClean_accesses::writebacks 1292383 # number of WritebackClean accesses(hits+misses) 1043system.cpu0.l2cache.WritebackClean_accesses::total 1292383 # number of WritebackClean accesses(hits+misses) 1044system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55222 # number of UpgradeReq accesses(hits+misses) 1045system.cpu0.l2cache.UpgradeReq_accesses::total 55222 # number of UpgradeReq accesses(hits+misses) 1046system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19651 # number of SCUpgradeReq accesses(hits+misses) 1047system.cpu0.l2cache.SCUpgradeReq_accesses::total 19651 # number of SCUpgradeReq accesses(hits+misses) 1048system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1049system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1050system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270607 # number of ReadExReq accesses(hits+misses) 1051system.cpu0.l2cache.ReadExReq_accesses::total 270607 # number of ReadExReq accesses(hits+misses) 1052system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104204 # number of ReadCleanReq accesses(hits+misses) 1053system.cpu0.l2cache.ReadCleanReq_accesses::total 1104204 # number of ReadCleanReq accesses(hits+misses) 1054system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477809 # number of ReadSharedReq accesses(hits+misses) 1055system.cpu0.l2cache.ReadSharedReq_accesses::total 477809 # number of ReadSharedReq accesses(hits+misses) 1056system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9814 # number of demand (read+write) accesses 1057system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4475 # number of demand (read+write) accesses 1058system.cpu0.l2cache.demand_accesses::cpu0.inst 1104204 # number of demand (read+write) accesses 1059system.cpu0.l2cache.demand_accesses::cpu0.data 748416 # number of demand (read+write) accesses 1060system.cpu0.l2cache.demand_accesses::total 1866909 # number of demand (read+write) accesses 1061system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9814 # number of overall (read+write) accesses 1062system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4475 # number of overall (read+write) accesses 1063system.cpu0.l2cache.overall_accesses::cpu0.inst 1104204 # number of overall (read+write) accesses 1064system.cpu0.l2cache.overall_accesses::cpu0.data 748416 # number of overall (read+write) accesses 1065system.cpu0.l2cache.overall_accesses::total 1866909 # number of overall (read+write) accesses 1066system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for ReadReq accesses 1067system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035531 # miss rate for ReadReq accesses 1068system.cpu0.l2cache.ReadReq_miss_rate::total 0.032543 # miss rate for ReadReq accesses 1069system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1070system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1071system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1072system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1073system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1074system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1075system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159697 # miss rate for ReadExReq accesses 1076system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159697 # miss rate for ReadExReq accesses 1077system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056280 # miss rate for ReadCleanReq accesses 1078system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056280 # miss rate for ReadCleanReq accesses 1079system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212520 # miss rate for ReadSharedReq accesses 1080system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212520 # miss rate for ReadSharedReq accesses 1081system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for demand accesses 1082system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035531 # miss rate for demand accesses 1083system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056280 # miss rate for demand accesses 1084system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193421 # miss rate for demand accesses 1085system.cpu0.l2cache.demand_miss_rate::total 0.111076 # miss rate for demand accesses 1086system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for overall accesses 1087system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035531 # miss rate for overall accesses 1088system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056280 # miss rate for overall accesses 1089system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193421 # miss rate for overall accesses 1090system.cpu0.l2cache.overall_miss_rate::total 0.111076 # miss rate for overall accesses 1091system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average ReadReq miss latency 1092system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843 # average ReadReq miss latency 1093system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097 # average ReadReq miss latency 1094system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 580.321249 # average UpgradeReq miss latency 1095system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 580.321249 # average UpgradeReq miss latency 1096system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 488.092209 # average SCUpgradeReq miss latency 1097system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 488.092209 # average SCUpgradeReq miss latency 1098system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 493500 # average SCUpgradeFailReq miss latency 1099system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 493500 # average SCUpgradeFailReq miss latency 1100system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564 # average ReadExReq miss latency 1101system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564 # average ReadExReq miss latency 1102system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728 # average ReadCleanReq miss latency 1103system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728 # average ReadCleanReq miss latency 1104system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191 # average ReadSharedReq miss latency 1105system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191 # average ReadSharedReq miss latency 1106system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency 1107system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency 1108system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency 1109system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency 1110system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256 # average overall miss latency 1111system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency 1112system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency 1113system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency 1114system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency 1115system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256 # average overall miss latency 1116system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1117system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1119system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1120system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1121system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1122system.cpu0.l2cache.unused_prefetches 10606 # number of HardPF blocks evicted w/o reference 1123system.cpu0.l2cache.writebacks::writebacks 227429 # number of writebacks 1124system.cpu0.l2cache.writebacks::total 227429 # number of writebacks 1125system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1561 # number of ReadExReq MSHR hits 1126system.cpu0.l2cache.ReadExReq_mshr_hits::total 1561 # number of ReadExReq MSHR hits 1127system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits 1128system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits 1129system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1594 # number of demand (read+write) MSHR hits 1130system.cpu0.l2cache.demand_mshr_hits::total 1594 # number of demand (read+write) MSHR hits 1131system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1594 # number of overall MSHR hits 1132system.cpu0.l2cache.overall_mshr_hits::total 1594 # number of overall MSHR hits 1133system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 306 # number of ReadReq MSHR misses 1134system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses 1135system.cpu0.l2cache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses 1136system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of HardPFReq MSHR misses 1137system.cpu0.l2cache.HardPFReq_mshr_misses::total 264666 # number of HardPFReq MSHR misses 1138system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55222 # number of UpgradeReq MSHR misses 1139system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55222 # number of UpgradeReq MSHR misses 1140system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19651 # number of SCUpgradeReq MSHR misses 1141system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19651 # number of SCUpgradeReq MSHR misses 1142system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1143system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1144system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41654 # number of ReadExReq MSHR misses 1145system.cpu0.l2cache.ReadExReq_mshr_misses::total 41654 # number of ReadExReq MSHR misses 1146system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62145 # number of ReadCleanReq MSHR misses 1147system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62145 # number of ReadCleanReq MSHR misses 1148system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101511 # number of ReadSharedReq MSHR misses 1149system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101511 # number of ReadSharedReq MSHR misses 1150system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 306 # number of demand (read+write) MSHR misses 1151system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses 1152system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62145 # number of demand (read+write) MSHR misses 1153system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143165 # number of demand (read+write) MSHR misses 1154system.cpu0.l2cache.demand_mshr_misses::total 205775 # number of demand (read+write) MSHR misses 1155system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 306 # number of overall MSHR misses 1156system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses 1157system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62145 # number of overall MSHR misses 1158system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143165 # number of overall MSHR misses 1159system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of overall MSHR misses 1160system.cpu0.l2cache.overall_mshr_misses::total 470441 # number of overall MSHR misses 1161system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1162system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable 1163system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40812 # number of ReadReq MSHR uncacheable 1164system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable 1165system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable 1166system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1167system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses 1168system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69276 # number of overall MSHR uncacheable misses 1169system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of ReadReq MSHR miss cycles 1170system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq MSHR miss cycles 1171system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9880500 # number of ReadReq MSHR miss cycles 1172system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of HardPFReq MSHR miss cycles 1173system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16752910842 # number of HardPFReq MSHR miss cycles 1174system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 946229000 # number of UpgradeReq MSHR miss cycles 1175system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 946229000 # number of UpgradeReq MSHR miss cycles 1176system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294413000 # number of SCUpgradeReq MSHR miss cycles 1177system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294413000 # number of SCUpgradeReq MSHR miss cycles 1178system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1198500 # number of SCUpgradeFailReq MSHR miss cycles 1179system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1198500 # number of SCUpgradeFailReq MSHR miss cycles 1180system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2205065500 # number of ReadExReq MSHR miss cycles 1181system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles 1182system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles 1183system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles 1184system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles 1185system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles 1186system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles 1187system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles 1188system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles 1189system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles 1190system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles 1191system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles 1192system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles 1193system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles 1194system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles 1195system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles 1196system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles 1197system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles 1198system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles 1199system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles 1200system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles 1201system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles 1202system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles 1203system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses 1204system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses 1205system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses 1206system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1207system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1208system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1209system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1210system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1211system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1212system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1213system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1214system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses 1215system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses 1216system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses 1217system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses 1218system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses 1219system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses 1220system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses 1221system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses 1222system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses 1223system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses 1224system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses 1225system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses 1226system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses 1227system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses 1228system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses 1229system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1230system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses 1231system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency 1232system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency 1233system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency 1234system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency 1235system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency 1236system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency 1237system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency 1238system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency 1239system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency 1240system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency 1241system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency 1242system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency 1243system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency 1244system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency 1245system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency 1246system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency 1247system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency 1248system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency 1249system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency 1250system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency 1251system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency 1252system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency 1253system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency 1254system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency 1255system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency 1256system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency 1257system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency 1258system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency 1259system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency 1260system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency 1261system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency 1262system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency 1263system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency 1264system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency 1265system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter. 1266system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1267system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1268system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter. 1269system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1270system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1271system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1272system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution 1273system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution 1274system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution 1275system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution 1276system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution 1290system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes) 1291system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes) 1292system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes) 1293system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes) 1294system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes) 1295system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes) 1296system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes) 1297system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes) 1298system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes) 1299system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes) 1300system.cpu0.toL2Bus.snoops 888922 # Total snoops (count) 1301system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes) 1302system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram 1303system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram 1304system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram 1305system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1306system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram 1307system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram 1308system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram 1309system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1310system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1311system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1312system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram 1313system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks) 1314system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1315system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks) 1316system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1317system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks) 1318system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1319system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks) 1320system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1321system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1322system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1323system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks) 1324system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1325system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1326system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1327system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1328system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1329system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1330system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1331system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1332system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1334system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1335system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1336system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1337system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1338system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1339system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1340system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1341system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1342system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1343system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1344system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1345system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1346system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1347system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1348system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1349system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1350system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1351system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1352system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1353system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1354system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1355system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1356system.cpu1.dtb.walker.walks 3333 # Table walker walks requested 1357system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors 1358system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate 1359system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate 1360system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency 1361system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1362system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency 1363system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency 1364system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency 1365system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency 1366system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency 1367system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency 1368system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency 1369system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency 1370system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency 1371system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution 1382system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution 1383system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution 1384system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated 1385system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated 1386system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated 1387system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst 1388system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1389system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst 1390system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst 1391system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1392system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst 1393system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.inst_hits 0 # ITB inst hits 1395system.cpu1.dtb.inst_misses 0 # ITB inst misses 1396system.cpu1.dtb.read_hits 3943012 # DTB read hits 1397system.cpu1.dtb.read_misses 2827 # DTB read misses 1398system.cpu1.dtb.write_hits 3420749 # DTB write hits 1399system.cpu1.dtb.write_misses 506 # DTB write misses 1400system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1401system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1402system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1403system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1404system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB 1405system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1406system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch 1407system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1408system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1409system.cpu1.dtb.read_accesses 3945839 # DTB read accesses 1410system.cpu1.dtb.write_accesses 3421255 # DTB write accesses 1411system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1412system.cpu1.dtb.hits 7363761 # DTB hits 1413system.cpu1.dtb.misses 3333 # DTB misses 1414system.cpu1.dtb.accesses 7367094 # DTB accesses 1415system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1416system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1417system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1418system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1419system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1420system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1425system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1426system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1427system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1428system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1429system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1430system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1431system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1432system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1433system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1434system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1435system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1436system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1437system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1438system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1439system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1440system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1441system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1442system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1443system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1444system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1445system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1446system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1447system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1448system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1449system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1450system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1451system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1452system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1453system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1454system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency 1455system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency 1456system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency 1457system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency 1458system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution 1470system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution 1471system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution 1472system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1473system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1474system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1475system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1476system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1477system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1478system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1479system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1480system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1481system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.inst_hits 16565425 # ITB inst hits 1483system.cpu1.itb.inst_misses 1746 # ITB inst misses 1484system.cpu1.itb.read_hits 0 # DTB read hits 1485system.cpu1.itb.read_misses 0 # DTB read misses 1486system.cpu1.itb.write_hits 0 # DTB write hits 1487system.cpu1.itb.write_misses 0 # DTB write misses 1488system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1489system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1490system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1491system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1492system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB 1493system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1494system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1495system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1496system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1497system.cpu1.itb.read_accesses 0 # DTB read accesses 1498system.cpu1.itb.write_accesses 0 # DTB write accesses 1499system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses 1500system.cpu1.itb.hits 16565425 # DTB hits 1501system.cpu1.itb.misses 1746 # DTB misses 1502system.cpu1.itb.accesses 16567171 # DTB accesses 1503system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions 1504system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state 1505system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state 1506system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state 1507system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state 1508system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state 1509system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1510system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states 1518system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states 1519system.cpu1.numCycles 5740713090 # number of cpu cycles simulated 1520system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1521system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1522system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1523system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed 1524system.cpu1.committedInsts 16209756 # Number of instructions committed 1525system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed 1526system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses 1527system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 1528system.cpu1.num_func_calls 1029227 # number of times a function call or return occured 1529system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls 1530system.cpu1.num_int_insts 17811459 # number of integer instructions 1531system.cpu1.num_fp_insts 1792 # number of float instructions 1532system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read 1533system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written 1534system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 1535system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1536system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read 1537system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written 1538system.cpu1.num_mem_refs 7597281 # number of memory refs 1539system.cpu1.num_load_insts 4054552 # Number of load instructions 1540system.cpu1.num_store_insts 3542729 # Number of store instructions 1541system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles 1542system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles 1543system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles 1544system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles 1545system.cpu1.Branches 2922489 # Number of branches fetched 1546system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1547system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction 1548system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction 1549system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction 1550system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction 1551system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction 1552system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction 1553system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction	629system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 630system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 631system.cpu0.op_class::total 143146475 # Class of executed instruction 632system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 633system.cpu0.dcache.tags.replacements 692883 # number of replacements 634system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use 635system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks. 636system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks. 637system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks. 638system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit. 639system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor 640system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy 641system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy 642system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 643system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 644system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 645system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 646system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 647system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses 648system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses 649system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 650system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits 651system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits 652system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits 653system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits 654system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits 655system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits 656system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits 657system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits 658system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits 659system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits 660system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits 661system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits 662system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits 663system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits 664system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses 665system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses 666system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses 667system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses 668system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses 669system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses 670system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses 671system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses 672system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses 673system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses 674system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses 675system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses 676system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses 677system.cpu0.dcache.overall_misses::total 849725 # number of overall misses 678system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles 679system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles 680system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles 681system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles 682system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles 683system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles 684system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles 685system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles 686system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles 687system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles 688system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles 689system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles 690system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles 691system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles 692system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses) 693system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses) 694system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses) 695system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses) 696system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses) 697system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses) 698system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses) 699system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses) 700system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses) 701system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses) 702system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses 703system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses 704system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses 705system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses 706system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses 707system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses 708system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses 709system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses 710system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses 711system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses 712system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses 713system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses 714system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses 715system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses 716system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses 717system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses 718system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses 719system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses 720system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency 721system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency 722system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency 723system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks 741system.cpu0.dcache.writebacks::total 692883 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits 743system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits 744system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits 745system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits 746system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits 747system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits 748system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits 749system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits 750system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits 751system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits 752system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses 753system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses 754system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses 755system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses 756system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses 757system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses 758system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses 759system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses 760system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses 761system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses 762system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses 763system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses 764system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses 765system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses 766system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable 767system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable 768system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable 769system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable 770system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses 771system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses 772system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles 773system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles 774system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles 775system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles 776system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles 777system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles 778system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles 779system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles 780system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles 781system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles 782system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles 783system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles 784system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles 785system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles 786system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles 787system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles 788system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles 789system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles 790system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles 791system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses 793system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses 794system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses 795system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses 796system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses 797system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses 798system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses 799system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses 800system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses 801system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses 802system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses 803system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses 804system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses 805system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses 806system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency 807system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency 808system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency 809system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency 810system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency 811system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency 812system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency 813system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency 814system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency 815system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency 816system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 817system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 818system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency 819system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency 820system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency 821system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency 822system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency 823system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency 824system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency 825system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency 826system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 827system.cpu0.icache.tags.replacements 1103683 # number of replacements 828system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use 829system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks. 830system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks. 831system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks. 832system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit. 833system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor 834system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy 835system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy 836system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 837system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 838system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 839system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 840system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 841system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses 842system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses 843system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 844system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits 845system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits 846system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits 847system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits 848system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits 849system.cpu0.icache.overall_hits::total 117915250 # number of overall hits 850system.cpu0.icache.ReadReq_misses::cpu0.inst 1104204 # number of ReadReq misses 851system.cpu0.icache.ReadReq_misses::total 1104204 # number of ReadReq misses 852system.cpu0.icache.demand_misses::cpu0.inst 1104204 # number of demand (read+write) misses 853system.cpu0.icache.demand_misses::total 1104204 # number of demand (read+write) misses 854system.cpu0.icache.overall_misses::cpu0.inst 1104204 # number of overall misses 855system.cpu0.icache.overall_misses::total 1104204 # number of overall misses 856system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11911095000 # number of ReadReq miss cycles 857system.cpu0.icache.ReadReq_miss_latency::total 11911095000 # number of ReadReq miss cycles 858system.cpu0.icache.demand_miss_latency::cpu0.inst 11911095000 # number of demand (read+write) miss cycles 859system.cpu0.icache.demand_miss_latency::total 11911095000 # number of demand (read+write) miss cycles 860system.cpu0.icache.overall_miss_latency::cpu0.inst 11911095000 # number of overall miss cycles 861system.cpu0.icache.overall_miss_latency::total 11911095000 # number of overall miss cycles 862system.cpu0.icache.ReadReq_accesses::cpu0.inst 119019454 # number of ReadReq accesses(hits+misses) 863system.cpu0.icache.ReadReq_accesses::total 119019454 # number of ReadReq accesses(hits+misses) 864system.cpu0.icache.demand_accesses::cpu0.inst 119019454 # number of demand (read+write) accesses 865system.cpu0.icache.demand_accesses::total 119019454 # number of demand (read+write) accesses 866system.cpu0.icache.overall_accesses::cpu0.inst 119019454 # number of overall (read+write) accesses 867system.cpu0.icache.overall_accesses::total 119019454 # number of overall (read+write) accesses 868system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009278 # miss rate for ReadReq accesses 869system.cpu0.icache.ReadReq_miss_rate::total 0.009278 # miss rate for ReadReq accesses 870system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009278 # miss rate for demand accesses 871system.cpu0.icache.demand_miss_rate::total 0.009278 # miss rate for demand accesses 872system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009278 # miss rate for overall accesses 873system.cpu0.icache.overall_miss_rate::total 0.009278 # miss rate for overall accesses 874system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068 # average ReadReq miss latency 875system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068 # average ReadReq miss latency 876system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency 877system.cpu0.icache.demand_avg_miss_latency::total 10787.042068 # average overall miss latency 878system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068 # average overall miss latency 879system.cpu0.icache.overall_avg_miss_latency::total 10787.042068 # average overall miss latency 880system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 881system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 882system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 883system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 884system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 885system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 886system.cpu0.icache.writebacks::writebacks 1103683 # number of writebacks 887system.cpu0.icache.writebacks::total 1103683 # number of writebacks 888system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104204 # number of ReadReq MSHR misses 889system.cpu0.icache.ReadReq_mshr_misses::total 1104204 # number of ReadReq MSHR misses 890system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104204 # number of demand (read+write) MSHR misses 891system.cpu0.icache.demand_mshr_misses::total 1104204 # number of demand (read+write) MSHR misses 892system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104204 # number of overall MSHR misses 893system.cpu0.icache.overall_mshr_misses::total 1104204 # number of overall MSHR misses 894system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 895system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 896system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 897system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 898system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles 899system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles 900system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles 901system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles 902system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles 903system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles 904system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles 905system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles 906system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles 907system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles 908system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses 909system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses 910system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for demand accesses 911system.cpu0.icache.demand_mshr_miss_rate::total 0.009278 # mshr miss rate for demand accesses 912system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for overall accesses 913system.cpu0.icache.overall_mshr_miss_rate::total 0.009278 # mshr miss rate for overall accesses 914system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average ReadReq mshr miss latency 915system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068 # average ReadReq mshr miss latency 916system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency 917system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency 918system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068 # average overall mshr miss latency 919system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068 # average overall mshr miss latency 920system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency 921system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency 922system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency 923system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency 924system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 925system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued 926system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified 927system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue 928system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 929system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 930system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing 931system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 932system.cpu0.l2cache.tags.replacements 259898 # number of replacements 933system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use 934system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks. 935system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks. 936system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks. 937system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 938system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor 939system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor 940system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor 941system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor 942system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy 943system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy 944system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 945system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy 946system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy 947system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id 948system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 949system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id 950system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 951system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id 952system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id 953system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id 954system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 955system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 956system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 957system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 958system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id 959system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6084 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1977 # Occupied blocks per task id 962system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020752 # Percentage of cache occupancy per task id 963system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 964system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933411 # Percentage of cache occupancy per task id 965system.cpu0.l2cache.tags.tag_accesses 61320295 # Number of tag accesses 966system.cpu0.l2cache.tags.data_accesses 61320295 # Number of data accesses 967system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 968system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9508 # number of ReadReq hits 969system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4316 # number of ReadReq hits 970system.cpu0.l2cache.ReadReq_hits::total 13824 # number of ReadReq hits 971system.cpu0.l2cache.WritebackDirty_hits::writebacks 476285 # number of WritebackDirty hits 972system.cpu0.l2cache.WritebackDirty_hits::total 476285 # number of WritebackDirty hits 973system.cpu0.l2cache.WritebackClean_hits::writebacks 1292383 # number of WritebackClean hits 974system.cpu0.l2cache.WritebackClean_hits::total 1292383 # number of WritebackClean hits 975system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227392 # number of ReadExReq hits 976system.cpu0.l2cache.ReadExReq_hits::total 227392 # number of ReadExReq hits 977system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1042059 # number of ReadCleanReq hits 978system.cpu0.l2cache.ReadCleanReq_hits::total 1042059 # number of ReadCleanReq hits 979system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 376265 # number of ReadSharedReq hits 980system.cpu0.l2cache.ReadSharedReq_hits::total 376265 # number of ReadSharedReq hits 981system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9508 # number of demand (read+write) hits 982system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4316 # number of demand (read+write) hits 983system.cpu0.l2cache.demand_hits::cpu0.inst 1042059 # number of demand (read+write) hits 984system.cpu0.l2cache.demand_hits::cpu0.data 603657 # number of demand (read+write) hits 985system.cpu0.l2cache.demand_hits::total 1659540 # number of demand (read+write) hits 986system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9508 # number of overall hits 987system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4316 # number of overall hits 988system.cpu0.l2cache.overall_hits::cpu0.inst 1042059 # number of overall hits 989system.cpu0.l2cache.overall_hits::cpu0.data 603657 # number of overall hits 990system.cpu0.l2cache.overall_hits::total 1659540 # number of overall hits 991system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 306 # number of ReadReq misses 992system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 159 # number of ReadReq misses 993system.cpu0.l2cache.ReadReq_misses::total 465 # number of ReadReq misses 994system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55222 # number of UpgradeReq misses 995system.cpu0.l2cache.UpgradeReq_misses::total 55222 # number of UpgradeReq misses 996system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19651 # number of SCUpgradeReq misses 997system.cpu0.l2cache.SCUpgradeReq_misses::total 19651 # number of SCUpgradeReq misses 998system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 999system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1000system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43215 # number of ReadExReq misses 1001system.cpu0.l2cache.ReadExReq_misses::total 43215 # number of ReadExReq misses 1002system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62145 # number of ReadCleanReq misses 1003system.cpu0.l2cache.ReadCleanReq_misses::total 62145 # number of ReadCleanReq misses 1004system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101544 # number of ReadSharedReq misses 1005system.cpu0.l2cache.ReadSharedReq_misses::total 101544 # number of ReadSharedReq misses 1006system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 306 # number of demand (read+write) misses 1007system.cpu0.l2cache.demand_misses::cpu0.itb.walker 159 # number of demand (read+write) misses 1008system.cpu0.l2cache.demand_misses::cpu0.inst 62145 # number of demand (read+write) misses 1009system.cpu0.l2cache.demand_misses::cpu0.data 144759 # number of demand (read+write) misses 1010system.cpu0.l2cache.demand_misses::total 207369 # number of demand (read+write) misses 1011system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 306 # number of overall misses 1012system.cpu0.l2cache.overall_misses::cpu0.itb.walker 159 # number of overall misses 1013system.cpu0.l2cache.overall_misses::cpu0.inst 62145 # number of overall misses 1014system.cpu0.l2cache.overall_misses::cpu0.data 144759 # number of overall misses 1015system.cpu0.l2cache.overall_misses::total 207369 # number of overall misses 1016system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8941000 # number of ReadReq miss cycles 1017system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3729500 # number of ReadReq miss cycles 1018system.cpu0.l2cache.ReadReq_miss_latency::total 12670500 # number of ReadReq miss cycles 1019system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 32046500 # number of UpgradeReq miss cycles 1020system.cpu0.l2cache.UpgradeReq_miss_latency::total 32046500 # number of UpgradeReq miss cycles 1021system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9591500 # number of SCUpgradeReq miss cycles 1022system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9591500 # number of SCUpgradeReq miss cycles 1023system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1480500 # number of SCUpgradeFailReq miss cycles 1024system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1480500 # number of SCUpgradeFailReq miss cycles 1025system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2734835500 # number of ReadExReq miss cycles 1026system.cpu0.l2cache.ReadExReq_miss_latency::total 2734835500 # number of ReadExReq miss cycles 1027system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3426232500 # number of ReadCleanReq miss cycles 1028system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3426232500 # number of ReadCleanReq miss cycles 1029system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3359763500 # number of ReadSharedReq miss cycles 1030system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3359763500 # number of ReadSharedReq miss cycles 1031system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8941000 # number of demand (read+write) miss cycles 1032system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3729500 # number of demand (read+write) miss cycles 1033system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3426232500 # number of demand (read+write) miss cycles 1034system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094599000 # number of demand (read+write) miss cycles 1035system.cpu0.l2cache.demand_miss_latency::total 9533502000 # number of demand (read+write) miss cycles 1036system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8941000 # number of overall miss cycles 1037system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3729500 # number of overall miss cycles 1038system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3426232500 # number of overall miss cycles 1039system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094599000 # number of overall miss cycles 1040system.cpu0.l2cache.overall_miss_latency::total 9533502000 # number of overall miss cycles 1041system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9814 # number of ReadReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4475 # number of ReadReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadReq_accesses::total 14289 # number of ReadReq accesses(hits+misses) 1044system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476285 # number of WritebackDirty accesses(hits+misses) 1045system.cpu0.l2cache.WritebackDirty_accesses::total 476285 # number of WritebackDirty accesses(hits+misses) 1046system.cpu0.l2cache.WritebackClean_accesses::writebacks 1292383 # number of WritebackClean accesses(hits+misses) 1047system.cpu0.l2cache.WritebackClean_accesses::total 1292383 # number of WritebackClean accesses(hits+misses) 1048system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55222 # number of UpgradeReq accesses(hits+misses) 1049system.cpu0.l2cache.UpgradeReq_accesses::total 55222 # number of UpgradeReq accesses(hits+misses) 1050system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19651 # number of SCUpgradeReq accesses(hits+misses) 1051system.cpu0.l2cache.SCUpgradeReq_accesses::total 19651 # number of SCUpgradeReq accesses(hits+misses) 1052system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1053system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1054system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270607 # number of ReadExReq accesses(hits+misses) 1055system.cpu0.l2cache.ReadExReq_accesses::total 270607 # number of ReadExReq accesses(hits+misses) 1056system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104204 # number of ReadCleanReq accesses(hits+misses) 1057system.cpu0.l2cache.ReadCleanReq_accesses::total 1104204 # number of ReadCleanReq accesses(hits+misses) 1058system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477809 # number of ReadSharedReq accesses(hits+misses) 1059system.cpu0.l2cache.ReadSharedReq_accesses::total 477809 # number of ReadSharedReq accesses(hits+misses) 1060system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9814 # number of demand (read+write) accesses 1061system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4475 # number of demand (read+write) accesses 1062system.cpu0.l2cache.demand_accesses::cpu0.inst 1104204 # number of demand (read+write) accesses 1063system.cpu0.l2cache.demand_accesses::cpu0.data 748416 # number of demand (read+write) accesses 1064system.cpu0.l2cache.demand_accesses::total 1866909 # number of demand (read+write) accesses 1065system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9814 # number of overall (read+write) accesses 1066system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4475 # number of overall (read+write) accesses 1067system.cpu0.l2cache.overall_accesses::cpu0.inst 1104204 # number of overall (read+write) accesses 1068system.cpu0.l2cache.overall_accesses::cpu0.data 748416 # number of overall (read+write) accesses 1069system.cpu0.l2cache.overall_accesses::total 1866909 # number of overall (read+write) accesses 1070system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for ReadReq accesses 1071system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035531 # miss rate for ReadReq accesses 1072system.cpu0.l2cache.ReadReq_miss_rate::total 0.032543 # miss rate for ReadReq accesses 1073system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1074system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1075system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1076system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1077system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1078system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1079system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159697 # miss rate for ReadExReq accesses 1080system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159697 # miss rate for ReadExReq accesses 1081system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056280 # miss rate for ReadCleanReq accesses 1082system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056280 # miss rate for ReadCleanReq accesses 1083system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212520 # miss rate for ReadSharedReq accesses 1084system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212520 # miss rate for ReadSharedReq accesses 1085system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for demand accesses 1086system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035531 # miss rate for demand accesses 1087system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056280 # miss rate for demand accesses 1088system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193421 # miss rate for demand accesses 1089system.cpu0.l2cache.demand_miss_rate::total 0.111076 # miss rate for demand accesses 1090system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.031180 # miss rate for overall accesses 1091system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035531 # miss rate for overall accesses 1092system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056280 # miss rate for overall accesses 1093system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193421 # miss rate for overall accesses 1094system.cpu0.l2cache.overall_miss_rate::total 0.111076 # miss rate for overall accesses 1095system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average ReadReq miss latency 1096system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843 # average ReadReq miss latency 1097system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097 # average ReadReq miss latency 1098system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 580.321249 # average UpgradeReq miss latency 1099system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 580.321249 # average UpgradeReq miss latency 1100system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 488.092209 # average SCUpgradeReq miss latency 1101system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 488.092209 # average SCUpgradeReq miss latency 1102system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 493500 # average SCUpgradeFailReq miss latency 1103system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 493500 # average SCUpgradeFailReq miss latency 1104system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564 # average ReadExReq miss latency 1105system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564 # average ReadExReq miss latency 1106system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728 # average ReadCleanReq miss latency 1107system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728 # average ReadCleanReq miss latency 1108system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191 # average ReadSharedReq miss latency 1109system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191 # average ReadSharedReq miss latency 1110system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency 1111system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency 1112system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency 1113system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency 1114system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256 # average overall miss latency 1115system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248 # average overall miss latency 1116system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843 # average overall miss latency 1117system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728 # average overall miss latency 1118system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159 # average overall miss latency 1119system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256 # average overall miss latency 1120system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1121system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1122system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1123system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1124system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1125system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1126system.cpu0.l2cache.unused_prefetches 10606 # number of HardPF blocks evicted w/o reference 1127system.cpu0.l2cache.writebacks::writebacks 227429 # number of writebacks 1128system.cpu0.l2cache.writebacks::total 227429 # number of writebacks 1129system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1561 # number of ReadExReq MSHR hits 1130system.cpu0.l2cache.ReadExReq_mshr_hits::total 1561 # number of ReadExReq MSHR hits 1131system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits 1132system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits 1133system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1594 # number of demand (read+write) MSHR hits 1134system.cpu0.l2cache.demand_mshr_hits::total 1594 # number of demand (read+write) MSHR hits 1135system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1594 # number of overall MSHR hits 1136system.cpu0.l2cache.overall_mshr_hits::total 1594 # number of overall MSHR hits 1137system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 306 # number of ReadReq MSHR misses 1138system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 159 # number of ReadReq MSHR misses 1139system.cpu0.l2cache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses 1140system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of HardPFReq MSHR misses 1141system.cpu0.l2cache.HardPFReq_mshr_misses::total 264666 # number of HardPFReq MSHR misses 1142system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55222 # number of UpgradeReq MSHR misses 1143system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55222 # number of UpgradeReq MSHR misses 1144system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19651 # number of SCUpgradeReq MSHR misses 1145system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19651 # number of SCUpgradeReq MSHR misses 1146system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1147system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1148system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41654 # number of ReadExReq MSHR misses 1149system.cpu0.l2cache.ReadExReq_mshr_misses::total 41654 # number of ReadExReq MSHR misses 1150system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62145 # number of ReadCleanReq MSHR misses 1151system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62145 # number of ReadCleanReq MSHR misses 1152system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101511 # number of ReadSharedReq MSHR misses 1153system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101511 # number of ReadSharedReq MSHR misses 1154system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 306 # number of demand (read+write) MSHR misses 1155system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 159 # number of demand (read+write) MSHR misses 1156system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62145 # number of demand (read+write) MSHR misses 1157system.cpu0.l2cache.demand_mshr_misses::cpu0.data 143165 # number of demand (read+write) MSHR misses 1158system.cpu0.l2cache.demand_mshr_misses::total 205775 # number of demand (read+write) MSHR misses 1159system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 306 # number of overall MSHR misses 1160system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 159 # number of overall MSHR misses 1161system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62145 # number of overall MSHR misses 1162system.cpu0.l2cache.overall_mshr_misses::cpu0.data 143165 # number of overall MSHR misses 1163system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264666 # number of overall MSHR misses 1164system.cpu0.l2cache.overall_mshr_misses::total 470441 # number of overall MSHR misses 1165system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1166system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable 1167system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40812 # number of ReadReq MSHR uncacheable 1168system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable 1169system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable 1170system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1171system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses 1172system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69276 # number of overall MSHR uncacheable misses 1173system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of ReadReq MSHR miss cycles 1174system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2775500 # number of ReadReq MSHR miss cycles 1175system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9880500 # number of ReadReq MSHR miss cycles 1176system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of HardPFReq MSHR miss cycles 1177system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16752910842 # number of HardPFReq MSHR miss cycles 1178system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 946229000 # number of UpgradeReq MSHR miss cycles 1179system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 946229000 # number of UpgradeReq MSHR miss cycles 1180system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 294413000 # number of SCUpgradeReq MSHR miss cycles 1181system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 294413000 # number of SCUpgradeReq MSHR miss cycles 1182system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1198500 # number of SCUpgradeFailReq MSHR miss cycles 1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1198500 # number of SCUpgradeFailReq MSHR miss cycles 1184system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2205065500 # number of ReadExReq MSHR miss cycles 1185system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles 1186system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles 1187system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles 1188system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles 1189system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles 1190system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles 1191system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles 1192system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles 1193system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles 1194system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles 1195system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles 1196system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles 1197system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles 1198system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles 1199system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles 1200system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles 1201system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles 1203system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles 1204system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles 1205system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles 1206system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles 1207system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses 1208system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses 1209system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses 1210system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1211system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1212system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1213system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1214system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1215system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1216system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1217system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1218system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses 1219system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses 1220system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses 1221system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses 1222system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses 1223system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses 1224system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses 1225system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses 1226system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses 1230system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses 1231system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1234system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses 1235system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency 1236system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency 1237system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency 1238system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency 1239system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency 1240system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency 1241system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency 1242system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency 1243system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency 1244system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency 1245system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency 1246system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency 1247system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency 1248system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency 1249system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency 1250system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency 1251system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency 1252system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency 1253system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency 1254system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency 1255system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency 1256system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency 1257system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency 1258system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency 1259system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency 1260system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency 1261system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency 1263system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency 1264system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency 1265system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency 1266system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency 1267system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency 1268system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency 1269system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter. 1270system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1271system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1272system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter. 1273system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1274system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1275system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1276system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution 1288system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution 1289system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution 1290system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution 1291system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution 1292system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution 1293system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution 1294system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes) 1295system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes) 1296system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes) 1297system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes) 1298system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes) 1299system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes) 1300system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes) 1304system.cpu0.toL2Bus.snoops 888922 # Total snoops (count) 1305system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes) 1306system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram 1307system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram 1308system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram 1309system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1310system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram 1311system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram 1312system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram 1313system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1314system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1315system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1316system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram 1317system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks) 1318system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1319system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks) 1320system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1321system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks) 1322system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1323system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks) 1324system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1325system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1326system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1327system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks) 1328system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1329system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1330system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1331system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1332system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1339system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1340system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1341system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1342system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1343system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1344system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1345system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1346system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1347system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1348system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1349system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1350system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1351system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1352system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1353system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1354system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1355system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1356system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1357system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1358system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1359system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1360system.cpu1.dtb.walker.walks 3333 # Table walker walks requested 1361system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors 1362system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate 1363system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate 1364system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency 1365system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1366system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency 1367system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency 1368system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency 1369system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency 1370system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency 1371system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution 1386system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution 1387system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution 1388system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated 1389system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated 1390system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated 1391system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst 1392system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst 1395system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst 1398system.cpu1.dtb.inst_hits 0 # ITB inst hits 1399system.cpu1.dtb.inst_misses 0 # ITB inst misses 1400system.cpu1.dtb.read_hits 3943012 # DTB read hits 1401system.cpu1.dtb.read_misses 2827 # DTB read misses 1402system.cpu1.dtb.write_hits 3420749 # DTB write hits 1403system.cpu1.dtb.write_misses 506 # DTB write misses 1404system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1405system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1406system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1407system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1408system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB 1409system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1410system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch 1411system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1412system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1413system.cpu1.dtb.read_accesses 3945839 # DTB read accesses 1414system.cpu1.dtb.write_accesses 3421255 # DTB write accesses 1415system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1416system.cpu1.dtb.hits 7363761 # DTB hits 1417system.cpu1.dtb.misses 3333 # DTB misses 1418system.cpu1.dtb.accesses 7367094 # DTB accesses 1419system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1420system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1427system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1428system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1429system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1430system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1431system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1432system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1433system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1434system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1435system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1436system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1437system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1438system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1439system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1440system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1441system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1442system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1443system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1444system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1445system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1446system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1447system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1448system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1449system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1450system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1451system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1452system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1453system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1454system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1455system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1456system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1457system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1458system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution 1474system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution 1475system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1477system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1478system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1479system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1480system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1482system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1483system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.inst_hits 16565425 # ITB inst hits 1487system.cpu1.itb.inst_misses 1746 # ITB inst misses 1488system.cpu1.itb.read_hits 0 # DTB read hits 1489system.cpu1.itb.read_misses 0 # DTB read misses 1490system.cpu1.itb.write_hits 0 # DTB write hits 1491system.cpu1.itb.write_misses 0 # DTB write misses 1492system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1493system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1494system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1495system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1496system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB 1497system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1498system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1499system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1500system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1501system.cpu1.itb.read_accesses 0 # DTB read accesses 1502system.cpu1.itb.write_accesses 0 # DTB write accesses 1503system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses 1504system.cpu1.itb.hits 16565425 # DTB hits 1505system.cpu1.itb.misses 1746 # DTB misses 1506system.cpu1.itb.accesses 16567171 # DTB accesses 1507system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions 1508system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state 1509system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state 1510system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state 1511system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state 1512system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state 1513system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1514system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1515system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1516system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1517system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1518system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1519system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state 1520system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state 1521system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states 1522system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states 1523system.cpu1.numCycles 5740713090 # number of cpu cycles simulated 1524system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1525system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1526system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1527system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed 1528system.cpu1.committedInsts 16209756 # Number of instructions committed 1529system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed 1530system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses 1531system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 1532system.cpu1.num_func_calls 1029227 # number of times a function call or return occured 1533system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls 1534system.cpu1.num_int_insts 17811459 # number of integer instructions 1535system.cpu1.num_fp_insts 1792 # number of float instructions 1536system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read 1537system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written 1538system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 1539system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1540system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read 1541system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written 1542system.cpu1.num_mem_refs 7597281 # number of memory refs 1543system.cpu1.num_load_insts 4054552 # Number of load instructions 1544system.cpu1.num_store_insts 3542729 # Number of store instructions 1545system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles 1546system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles 1547system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles 1548system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles 1549system.cpu1.Branches 2922489 # Number of branches fetched 1550system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1551system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction 1552system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction 1553system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction 1554system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction 1555system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction 1556system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction 1557system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
	1558system.cpu1.op_class::FloatMultAcc 0 0.00% 62.19% # Class of executed instruction
1554system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction	1559system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
	1560system.cpu1.op_class::FloatMisc 0 0.00% 62.19% # Class of executed instruction
1555system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction 1556system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction 1557system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction 1558system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction 1559system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction 1560system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction 1561system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction 1562system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction 1563system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction 1564system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction 1565system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction 1566system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction 1567system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction 1568system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction 1569system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction 1570system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction 1571system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction 1572system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction 1573system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction 1574system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction 1575system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction	1561system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction 1562system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction 1563system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction 1564system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction 1565system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction 1566system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction 1567system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction 1568system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction 1569system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction 1570system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction 1571system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction 1572system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction 1573system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction 1574system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction 1575system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction 1576system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction 1577system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction 1578system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction 1579system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction 1580system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction 1581system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction
1576system.cpu1.op_class::MemRead 4054552 20.17% 82.38% # Class of executed instruction 1577system.cpu1.op_class::MemWrite 3542729 17.62% 100.00% # Class of executed instruction	1582system.cpu1.op_class::MemRead 4054036 20.17% 82.37% # Class of executed instruction 1583system.cpu1.op_class::MemWrite 3541453 17.62% 99.99% # Class of executed instruction 1584system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction 1585system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction
1578system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1579system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1580system.cpu1.op_class::total 20100990 # Class of executed instruction 1581system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1582system.cpu1.dcache.tags.replacements 186832 # number of replacements 1583system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use 1584system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks. 1585system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks. 1586system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks. 1587system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit. 1588system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor 1589system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy 1590system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy 1591system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 1592system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 1593system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id 1594system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id 1595system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses 1596system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses 1597system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1598system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits 1599system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits 1600system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits 1601system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits 1602system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits 1603system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits 1604system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits 1605system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits 1606system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits 1607system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits 1608system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits 1609system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits 1610system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits 1611system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits 1612system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses 1613system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses 1614system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses 1615system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses 1616system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses 1617system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses 1618system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses 1619system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses 1620system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses 1621system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses 1622system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses 1623system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses 1624system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses 1625system.cpu1.dcache.overall_misses::total 255886 # number of overall misses 1626system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles 1627system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles 1628system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles 1629system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles 1630system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles 1631system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles 1632system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles 1633system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles 1634system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles 1635system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles 1636system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles 1637system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles 1638system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles 1639system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles 1640system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses) 1641system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses) 1642system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses) 1643system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses) 1644system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses) 1645system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses) 1646system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses) 1647system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses) 1648system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses) 1649system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses) 1650system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses 1651system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses 1652system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses 1653system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses 1654system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses 1655system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses 1656system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses 1657system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses 1658system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses 1659system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses 1660system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses 1661system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses 1662system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses 1663system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses 1664system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses 1665system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses 1666system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses 1667system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses 1668system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency 1669system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency 1670system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency 1671system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency 1672system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency 1673system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency 1674system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency 1675system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency 1676system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1677system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1678system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency 1679system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency 1680system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency 1681system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency 1682system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1683system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1684system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1685system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1686system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1687system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1688system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks 1689system.cpu1.dcache.writebacks::total 186832 # number of writebacks 1690system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits 1691system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits 1692system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits 1693system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits 1694system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits 1695system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits 1696system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits 1697system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits 1698system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses 1699system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses 1700system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses 1701system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses 1702system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses 1703system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses 1704system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses 1705system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses 1706system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses 1707system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses 1708system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses 1709system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses 1710system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses 1711system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses 1712system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable 1713system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable 1714system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable 1715system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable 1716system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses 1717system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses 1718system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles 1719system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles 1720system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles 1721system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles 1722system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles 1723system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles 1724system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles 1725system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles 1726system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles 1727system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles 1728system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles 1729system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles 1730system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles 1731system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles 1732system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles 1733system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles 1734system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles 1735system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles 1736system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles 1737system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles 1738system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses 1739system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses 1740system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses 1741system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses 1742system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses 1743system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses 1744system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses 1745system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses 1746system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses 1747system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses 1748system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses 1749system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses 1750system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses 1751system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses 1752system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency 1753system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency 1754system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency 1755system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency 1756system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency 1757system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency 1758system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency 1759system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency 1760system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency 1761system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency 1762system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1763system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1764system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency 1765system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency 1766system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency 1767system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency 1768system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency 1769system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency 1770system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency 1771system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency 1772system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1773system.cpu1.icache.tags.replacements 505764 # number of replacements 1774system.cpu1.icache.tags.tagsinuse 498.454577 # Cycle average of tags in use 1775system.cpu1.icache.tags.total_refs 16059144 # Total number of references to valid blocks. 1776system.cpu1.icache.tags.sampled_refs 506276 # Sample count of references to valid blocks. 1777system.cpu1.icache.tags.avg_refs 31.720137 # Average number of references to valid blocks. 1778system.cpu1.icache.tags.warmup_cycle 85411536000 # Cycle when the warmup percentage was hit. 1779system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.454577 # Average occupied blocks per requestor 1780system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973544 # Average percentage of cache occupancy 1781system.cpu1.icache.tags.occ_percent::total 0.973544 # Average percentage of cache occupancy 1782system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1783system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1784system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id 1785system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1786system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1787system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses 1788system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses 1789system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1790system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits 1791system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits 1792system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits 1793system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits 1794system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits 1795system.cpu1.icache.overall_hits::total 16059144 # number of overall hits 1796system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses 1797system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses 1798system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses 1799system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses 1800system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses 1801system.cpu1.icache.overall_misses::total 506276 # number of overall misses 1802system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles 1803system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles 1804system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles 1805system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles 1806system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles 1807system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles 1808system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses) 1809system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses) 1810system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses 1811system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses 1812system.cpu1.icache.overall_accesses::cpu1.inst 16565420 # number of overall (read+write) accesses 1813system.cpu1.icache.overall_accesses::total 16565420 # number of overall (read+write) accesses 1814system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030562 # miss rate for ReadReq accesses 1815system.cpu1.icache.ReadReq_miss_rate::total 0.030562 # miss rate for ReadReq accesses 1816system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030562 # miss rate for demand accesses 1817system.cpu1.icache.demand_miss_rate::total 0.030562 # miss rate for demand accesses 1818system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030562 # miss rate for overall accesses 1819system.cpu1.icache.overall_miss_rate::total 0.030562 # miss rate for overall accesses 1820system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9427.881235 # average ReadReq miss latency 1821system.cpu1.icache.ReadReq_avg_miss_latency::total 9427.881235 # average ReadReq miss latency 1822system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency 1823system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency 1824system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency 1825system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency 1826system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1827system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1828system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1829system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1830system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1831system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1832system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks 1833system.cpu1.icache.writebacks::total 505764 # number of writebacks 1834system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses 1835system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses 1836system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses 1837system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses 1838system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses 1839system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses 1840system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1841system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1842system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1843system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1844system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles 1845system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles 1846system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles 1847system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles 1848system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles 1849system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles 1850system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles 1851system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles 1852system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles 1853system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles 1854system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses 1855system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses 1856system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses 1857system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses 1858system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses 1859system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses 1860system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency 1861system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency 1862system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency 1863system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency 1864system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency 1865system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency 1866system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency 1867system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency 1868system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency 1869system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency 1870system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1871system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued 1872system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified 1873system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1874system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1875system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1876system.cpu1.l2cache.prefetcher.pfSpanPage 59073 # number of prefetches not generated due to page crossing 1877system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1878system.cpu1.l2cache.tags.replacements 42341 # number of replacements 1879system.cpu1.l2cache.tags.tagsinuse 14550.545082 # Cycle average of tags in use 1880system.cpu1.l2cache.tags.total_refs 605184 # Total number of references to valid blocks. 1881system.cpu1.l2cache.tags.sampled_refs 56718 # Sample count of references to valid blocks. 1882system.cpu1.l2cache.tags.avg_refs 10.670052 # Average number of references to valid blocks. 1883system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1884system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor 1885system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor 1886system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor 1887system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor 1888system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy 1889system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy 1890system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy 1891system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy 1892system.cpu1.l2cache.tags.occ_percent::total 0.888095 # Average percentage of cache occupancy 1893system.cpu1.l2cache.tags.occ_task_id_blocks::1022 333 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id 1902system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2799 # Occupied blocks per task id 1903system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10333 # Occupied blocks per task id 1904system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020325 # Percentage of cache occupancy per task id 1905system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 1906system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id 1907system.cpu1.l2cache.tags.tag_accesses 24327160 # Number of tag accesses 1908system.cpu1.l2cache.tags.data_accesses 24327160 # Number of data accesses 1909system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1910system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3447 # number of ReadReq hits 1911system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1877 # number of ReadReq hits 1912system.cpu1.l2cache.ReadReq_hits::total 5324 # number of ReadReq hits 1913system.cpu1.l2cache.WritebackDirty_hits::writebacks 114448 # number of WritebackDirty hits 1914system.cpu1.l2cache.WritebackDirty_hits::total 114448 # number of WritebackDirty hits 1915system.cpu1.l2cache.WritebackClean_hits::writebacks 567034 # number of WritebackClean hits 1916system.cpu1.l2cache.WritebackClean_hits::total 567034 # number of WritebackClean hits 1917system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27676 # number of ReadExReq hits 1918system.cpu1.l2cache.ReadExReq_hits::total 27676 # number of ReadExReq hits 1919system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485156 # number of ReadCleanReq hits 1920system.cpu1.l2cache.ReadCleanReq_hits::total 485156 # number of ReadCleanReq hits 1921system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98414 # number of ReadSharedReq hits 1922system.cpu1.l2cache.ReadSharedReq_hits::total 98414 # number of ReadSharedReq hits 1923system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3447 # number of demand (read+write) hits 1924system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1877 # number of demand (read+write) hits 1925system.cpu1.l2cache.demand_hits::cpu1.inst 485156 # number of demand (read+write) hits 1926system.cpu1.l2cache.demand_hits::cpu1.data 126090 # number of demand (read+write) hits 1927system.cpu1.l2cache.demand_hits::total 616570 # number of demand (read+write) hits 1928system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3447 # number of overall hits 1929system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1877 # number of overall hits 1930system.cpu1.l2cache.overall_hits::cpu1.inst 485156 # number of overall hits 1931system.cpu1.l2cache.overall_hits::cpu1.data 126090 # number of overall hits 1932system.cpu1.l2cache.overall_hits::total 616570 # number of overall hits 1933system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 422 # number of ReadReq misses 1934system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 327 # number of ReadReq misses 1935system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses 1936system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29541 # number of UpgradeReq misses 1937system.cpu1.l2cache.UpgradeReq_misses::total 29541 # number of UpgradeReq misses 1938system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23233 # number of SCUpgradeReq misses 1939system.cpu1.l2cache.SCUpgradeReq_misses::total 23233 # number of SCUpgradeReq misses 1940system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 1941system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1942system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34651 # number of ReadExReq misses 1943system.cpu1.l2cache.ReadExReq_misses::total 34651 # number of ReadExReq misses 1944system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21120 # number of ReadCleanReq misses 1945system.cpu1.l2cache.ReadCleanReq_misses::total 21120 # number of ReadCleanReq misses 1946system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69614 # number of ReadSharedReq misses 1947system.cpu1.l2cache.ReadSharedReq_misses::total 69614 # number of ReadSharedReq misses 1948system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 422 # number of demand (read+write) misses 1949system.cpu1.l2cache.demand_misses::cpu1.itb.walker 327 # number of demand (read+write) misses 1950system.cpu1.l2cache.demand_misses::cpu1.inst 21120 # number of demand (read+write) misses 1951system.cpu1.l2cache.demand_misses::cpu1.data 104265 # number of demand (read+write) misses 1952system.cpu1.l2cache.demand_misses::total 126134 # number of demand (read+write) misses 1953system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 422 # number of overall misses 1954system.cpu1.l2cache.overall_misses::cpu1.itb.walker 327 # number of overall misses 1955system.cpu1.l2cache.overall_misses::cpu1.inst 21120 # number of overall misses 1956system.cpu1.l2cache.overall_misses::cpu1.data 104265 # number of overall misses 1957system.cpu1.l2cache.overall_misses::total 126134 # number of overall misses 1958system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8582000 # number of ReadReq miss cycles 1959system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6568500 # number of ReadReq miss cycles 1960system.cpu1.l2cache.ReadReq_miss_latency::total 15150500 # number of ReadReq miss cycles 1961system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13749500 # number of UpgradeReq miss cycles 1962system.cpu1.l2cache.UpgradeReq_miss_latency::total 13749500 # number of UpgradeReq miss cycles 1963system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16999500 # number of SCUpgradeReq miss cycles 1964system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16999500 # number of SCUpgradeReq miss cycles 1965system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1709500 # number of SCUpgradeFailReq miss cycles 1966system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1709500 # number of SCUpgradeFailReq miss cycles 1967system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1487134000 # number of ReadExReq miss cycles 1968system.cpu1.l2cache.ReadExReq_miss_latency::total 1487134000 # number of ReadExReq miss cycles 1969system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 835278500 # number of ReadCleanReq miss cycles 1970system.cpu1.l2cache.ReadCleanReq_miss_latency::total 835278500 # number of ReadCleanReq miss cycles 1971system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1591067500 # number of ReadSharedReq miss cycles 1972system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1591067500 # number of ReadSharedReq miss cycles 1973system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8582000 # number of demand (read+write) miss cycles 1974system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6568500 # number of demand (read+write) miss cycles 1975system.cpu1.l2cache.demand_miss_latency::cpu1.inst 835278500 # number of demand (read+write) miss cycles 1976system.cpu1.l2cache.demand_miss_latency::cpu1.data 3078201500 # number of demand (read+write) miss cycles 1977system.cpu1.l2cache.demand_miss_latency::total 3928630500 # number of demand (read+write) miss cycles 1978system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8582000 # number of overall miss cycles 1979system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6568500 # number of overall miss cycles 1980system.cpu1.l2cache.overall_miss_latency::cpu1.inst 835278500 # number of overall miss cycles 1981system.cpu1.l2cache.overall_miss_latency::cpu1.data 3078201500 # number of overall miss cycles 1982system.cpu1.l2cache.overall_miss_latency::total 3928630500 # number of overall miss cycles 1983system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3869 # number of ReadReq accesses(hits+misses) 1984system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2204 # number of ReadReq accesses(hits+misses) 1985system.cpu1.l2cache.ReadReq_accesses::total 6073 # number of ReadReq accesses(hits+misses) 1986system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114448 # number of WritebackDirty accesses(hits+misses) 1987system.cpu1.l2cache.WritebackDirty_accesses::total 114448 # number of WritebackDirty accesses(hits+misses) 1988system.cpu1.l2cache.WritebackClean_accesses::writebacks 567034 # number of WritebackClean accesses(hits+misses) 1989system.cpu1.l2cache.WritebackClean_accesses::total 567034 # number of WritebackClean accesses(hits+misses) 1990system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29541 # number of UpgradeReq accesses(hits+misses) 1991system.cpu1.l2cache.UpgradeReq_accesses::total 29541 # number of UpgradeReq accesses(hits+misses) 1992system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23233 # number of SCUpgradeReq accesses(hits+misses) 1993system.cpu1.l2cache.SCUpgradeReq_accesses::total 23233 # number of SCUpgradeReq accesses(hits+misses) 1994system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1995system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1996system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62327 # number of ReadExReq accesses(hits+misses) 1997system.cpu1.l2cache.ReadExReq_accesses::total 62327 # number of ReadExReq accesses(hits+misses) 1998system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506276 # number of ReadCleanReq accesses(hits+misses) 1999system.cpu1.l2cache.ReadCleanReq_accesses::total 506276 # number of ReadCleanReq accesses(hits+misses) 2000system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168028 # number of ReadSharedReq accesses(hits+misses) 2001system.cpu1.l2cache.ReadSharedReq_accesses::total 168028 # number of ReadSharedReq accesses(hits+misses) 2002system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3869 # number of demand (read+write) accesses 2003system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2204 # number of demand (read+write) accesses 2004system.cpu1.l2cache.demand_accesses::cpu1.inst 506276 # number of demand (read+write) accesses 2005system.cpu1.l2cache.demand_accesses::cpu1.data 230355 # number of demand (read+write) accesses 2006system.cpu1.l2cache.demand_accesses::total 742704 # number of demand (read+write) accesses 2007system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3869 # number of overall (read+write) accesses 2008system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2204 # number of overall (read+write) accesses 2009system.cpu1.l2cache.overall_accesses::cpu1.inst 506276 # number of overall (read+write) accesses 2010system.cpu1.l2cache.overall_accesses::cpu1.data 230355 # number of overall (read+write) accesses 2011system.cpu1.l2cache.overall_accesses::total 742704 # number of overall (read+write) accesses 2012system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for ReadReq accesses 2013system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.148367 # miss rate for ReadReq accesses 2014system.cpu1.l2cache.ReadReq_miss_rate::total 0.123333 # miss rate for ReadReq accesses 2015system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2016system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2017system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2018system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2019system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2020system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2021system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555955 # miss rate for ReadExReq accesses 2022system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555955 # miss rate for ReadExReq accesses 2023system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041716 # miss rate for ReadCleanReq accesses 2024system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041716 # miss rate for ReadCleanReq accesses 2025system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414300 # miss rate for ReadSharedReq accesses 2026system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414300 # miss rate for ReadSharedReq accesses 2027system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for demand accesses 2028system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.148367 # miss rate for demand accesses 2029system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041716 # miss rate for demand accesses 2030system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452627 # miss rate for demand accesses 2031system.cpu1.l2cache.demand_miss_rate::total 0.169831 # miss rate for demand accesses 2032system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for overall accesses 2033system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.148367 # miss rate for overall accesses 2034system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041716 # miss rate for overall accesses 2035system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452627 # miss rate for overall accesses 2036system.cpu1.l2cache.overall_miss_rate::total 0.169831 # miss rate for overall accesses 2037system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average ReadReq miss latency 2038system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963 # average ReadReq miss latency 2039system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849 # average ReadReq miss latency 2040system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 465.437866 # average UpgradeReq miss latency 2041system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 465.437866 # average UpgradeReq miss latency 2042system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 731.696294 # average SCUpgradeReq miss latency 2043system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 731.696294 # average SCUpgradeReq miss latency 2044system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 854750 # average SCUpgradeFailReq miss latency 2045system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 854750 # average SCUpgradeFailReq miss latency 2046system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559 # average ReadExReq miss latency 2047system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559 # average ReadExReq miss latency 2048system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402 # average ReadCleanReq miss latency 2049system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402 # average ReadCleanReq miss latency 2050system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846 # average ReadSharedReq miss latency 2051system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846 # average ReadSharedReq miss latency 2052system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency 2053system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency 2054system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency 2055system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency 2056system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105 # average overall miss latency 2057system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency 2058system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency 2059system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency 2060system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency 2061system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105 # average overall miss latency 2062system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2063system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2064system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2065system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2066system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2067system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2068system.cpu1.l2cache.unused_prefetches 833 # number of HardPF blocks evicted w/o reference 2069system.cpu1.l2cache.writebacks::writebacks 32020 # number of writebacks 2070system.cpu1.l2cache.writebacks::total 32020 # number of writebacks 2071system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 87 # number of ReadExReq MSHR hits 2072system.cpu1.l2cache.ReadExReq_mshr_hits::total 87 # number of ReadExReq MSHR hits 2073system.cpu1.l2cache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits 2074system.cpu1.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits 2075system.cpu1.l2cache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits 2076system.cpu1.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits 2077system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 422 # number of ReadReq MSHR misses 2078system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 327 # number of ReadReq MSHR misses 2079system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses 2080system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of HardPFReq MSHR misses 2081system.cpu1.l2cache.HardPFReq_mshr_misses::total 25249 # number of HardPFReq MSHR misses 2082system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29541 # number of UpgradeReq MSHR misses 2083system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29541 # number of UpgradeReq MSHR misses 2084system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23233 # number of SCUpgradeReq MSHR misses 2085system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23233 # number of SCUpgradeReq MSHR misses 2086system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2087system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2088system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34564 # number of ReadExReq MSHR misses 2089system.cpu1.l2cache.ReadExReq_mshr_misses::total 34564 # number of ReadExReq MSHR misses 2090system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21120 # number of ReadCleanReq MSHR misses 2091system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21120 # number of ReadCleanReq MSHR misses 2092system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69614 # number of ReadSharedReq MSHR misses 2093system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69614 # number of ReadSharedReq MSHR misses 2094system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 422 # number of demand (read+write) MSHR misses 2095system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 327 # number of demand (read+write) MSHR misses 2096system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21120 # number of demand (read+write) MSHR misses 2097system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104178 # number of demand (read+write) MSHR misses 2098system.cpu1.l2cache.demand_mshr_misses::total 126047 # number of demand (read+write) MSHR misses 2099system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 422 # number of overall MSHR misses 2100system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 327 # number of overall MSHR misses 2101system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21120 # number of overall MSHR misses 2102system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104178 # number of overall MSHR misses 2103system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of overall MSHR misses 2104system.cpu1.l2cache.overall_mshr_misses::total 151296 # number of overall MSHR misses 2105system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2106system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable 2107system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3273 # number of ReadReq MSHR uncacheable 2108system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable 2109system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable 2110system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2111system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses 2112system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses 2113system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles 2114system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles 2115system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles 2116system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles 2117system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles 2118system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles 2119system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles 2120system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles 2121system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles 2122system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles 2123system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles 2124system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles 2125system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles 2126system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles 2127system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles 2128system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles 2129system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles 2130system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles 2131system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles 2132system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles 2133system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles 2134system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles 2135system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles 2136system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles 2137system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles 2138system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles 2139system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles 2140system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles 2141system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles 2142system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles 2143system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles 2144system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles 2145system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles 2146system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles 2147system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses 2148system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses 2149system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses 2150system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2151system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2152system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2153system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2154system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2155system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2156system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2157system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2158system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses 2159system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses 2160system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses 2161system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses 2162system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses 2163system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses 2164system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses 2165system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses 2166system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses 2167system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses 2168system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses 2169system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses 2170system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses 2171system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses 2172system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses 2173system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2174system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses 2175system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency 2176system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency 2177system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency 2178system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency 2179system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency 2180system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency 2181system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency 2182system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency 2183system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency 2184system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency 2185system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency 2186system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency 2187system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency 2188system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency 2189system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency 2190system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency 2191system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency 2192system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency 2193system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency 2194system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency 2195system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency 2196system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency 2197system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency 2198system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency 2199system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency 2200system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency 2201system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency 2202system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency 2203system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency 2204system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency 2205system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency 2206system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency 2207system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency 2208system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency 2209system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter. 2210system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2211system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2212system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter. 2213system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2214system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2215system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2216system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution 2217system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution 2218system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution 2219system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution 2220system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution 2221system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution 2222system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution 2223system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution 2224system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution 2225system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution 2226system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution 2227system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 2228system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution 2229system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution 2230system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution 2231system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution 2232system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution 2233system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution 2234system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes) 2235system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes) 2236system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes) 2237system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes) 2238system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes) 2239system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes) 2240system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes) 2241system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes) 2242system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes) 2243system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes) 2244system.cpu1.toL2Bus.snoops 331491 # Total snoops (count) 2245system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes) 2246system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram 2247system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram 2248system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram 2249system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2250system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram 2251system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram 2252system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram 2253system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2254system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2255system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2256system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram 2257system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks) 2258system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2259system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks) 2260system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2261system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks) 2262system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2263system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks) 2264system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2265system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2266system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2267system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks) 2268system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2269system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2270system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2271system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2272system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2273system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2274system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2276system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2278system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2279system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2280system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2281system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2282system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2283system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2284system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2285system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2287system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2288system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2289system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2290system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2291system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2292system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2293system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2294system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2299system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2300system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2301system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2302system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2303system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2304system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2305system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2306system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2307system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2308system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2310system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2311system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2312system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2313system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2314system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2315system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2316system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2317system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks) 2321system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2322system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 2323system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2324system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 2325system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2326system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) 2327system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2328system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) 2329system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2330system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) 2331system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2332system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) 2333system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2334system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) 2335system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2336system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2337system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2338system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 2339system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2340system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2341system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2342system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 2343system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2344system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2345system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2346system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 2347system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2348system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2349system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2350system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2351system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2353system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks) 2355system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks) 2357system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks) 2359system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2360system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2361system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2362system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2363system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2364system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2365system.iocache.tags.replacements 36445 # number of replacements 2366system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use 2367system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2368system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2369system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2370system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit. 2371system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor 2372system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy 2373system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy 2374system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2375system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2376system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2377system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2378system.iocache.tags.data_accesses 328311 # Number of data accesses 2379system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2380system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2381system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2382system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2383system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2384system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2385system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2386system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2387system.iocache.overall_misses::total 36479 # number of overall misses 2388system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles 2389system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles 2390system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles 2391system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles 2392system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles 2393system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles 2394system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles 2395system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles 2396system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2397system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2398system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2399system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2400system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2401system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2402system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2403system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2404system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2405system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2406system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2407system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2408system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2409system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2410system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2411system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2412system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency 2413system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency 2414system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency 2415system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency 2416system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency 2417system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency 2418system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency 2419system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency 2420system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked 2421system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2422system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked 2423system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2424system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 2425system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2426system.iocache.writebacks::writebacks 36190 # number of writebacks 2427system.iocache.writebacks::total 36190 # number of writebacks 2428system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2429system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2430system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2431system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2432system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2433system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2434system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2435system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2436system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles 2437system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles 2438system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles 2439system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles 2440system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles 2441system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles 2442system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles 2443system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles 2444system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2445system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2446system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2447system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2448system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2449system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2450system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2451system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2452system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471 # average ReadReq mshr miss latency 2453system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471 # average ReadReq mshr miss latency 2454system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048 # average WriteLineReq mshr miss latency 2455system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048 # average WriteLineReq mshr miss latency 2456system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency 2457system.iocache.demand_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency 2458system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency 2459system.iocache.overall_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency 2460system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2461system.l2c.tags.replacements 136024 # number of replacements 2462system.l2c.tags.tagsinuse 65074.400284 # Cycle average of tags in use 2463system.l2c.tags.total_refs 524979 # Total number of references to valid blocks. 2464system.l2c.tags.sampled_refs 201414 # Sample count of references to valid blocks. 2465system.l2c.tags.avg_refs 2.606467 # Average number of references to valid blocks. 2466system.l2c.tags.warmup_cycle 103030494000 # Cycle when the warmup percentage was hit. 2467system.l2c.tags.occ_blocks::writebacks 6378.541377 # Average occupied blocks per requestor 2468system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.901261 # Average occupied blocks per requestor 2469system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045973 # Average occupied blocks per requestor 2470system.l2c.tags.occ_blocks::cpu0.inst 7223.294710 # Average occupied blocks per requestor 2471system.l2c.tags.occ_blocks::cpu0.data 6923.893951 # Average occupied blocks per requestor 2472system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor 2473system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor 2474system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor 2475system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor 2476system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy 2477system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 2478system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2479system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy 2480system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy 2481system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy 2482system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy 2483system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy 2484system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy 2485system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy 2486system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id 2487system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2488system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id 2489system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 2490system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id 2491system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id 2492system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id 2493system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2494system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2495system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 2496system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 2497system.l2c.tags.age_task_id_blocks_1024::3 1178 # Occupied blocks per task id 2498system.l2c.tags.age_task_id_blocks_1024::4 29816 # Occupied blocks per task id 2499system.l2c.tags.occ_task_id_percent::1022 0.523697 # Percentage of cache occupancy per task id 2500system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2501system.l2c.tags.occ_task_id_percent::1024 0.473999 # Percentage of cache occupancy per task id 2502system.l2c.tags.tag_accesses 6089608 # Number of tag accesses 2503system.l2c.tags.data_accesses 6089608 # Number of data accesses 2504system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2505system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits 2506system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits 2507system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits 2508system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits 2509system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits 2510system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits 2511system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits 2512system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits 2513system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits 2514system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits 2515system.l2c.ReadExReq_hits::total 5419 # number of ReadExReq hits 2516system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 142 # number of ReadSharedReq hits 2517system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits 2518system.l2c.ReadSharedReq_hits::cpu0.inst 44259 # number of ReadSharedReq hits 2519system.l2c.ReadSharedReq_hits::cpu0.data 52827 # number of ReadSharedReq hits 2520system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45774 # number of ReadSharedReq hits 2521system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits 2522system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits 2523system.l2c.ReadSharedReq_hits::cpu1.inst 18793 # number of ReadSharedReq hits 2524system.l2c.ReadSharedReq_hits::cpu1.data 10825 # number of ReadSharedReq hits 2525system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5311 # number of ReadSharedReq hits 2526system.l2c.ReadSharedReq_hits::total 178070 # number of ReadSharedReq hits 2527system.l2c.demand_hits::cpu0.dtb.walker 142 # number of demand (read+write) hits 2528system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits 2529system.l2c.demand_hits::cpu0.inst 44259 # number of demand (read+write) hits 2530system.l2c.demand_hits::cpu0.data 56833 # number of demand (read+write) hits 2531system.l2c.demand_hits::cpu0.l2cache.prefetcher 45774 # number of demand (read+write) hits 2532system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits 2533system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits 2534system.l2c.demand_hits::cpu1.inst 18793 # number of demand (read+write) hits 2535system.l2c.demand_hits::cpu1.data 12238 # number of demand (read+write) hits 2536system.l2c.demand_hits::cpu1.l2cache.prefetcher 5311 # number of demand (read+write) hits 2537system.l2c.demand_hits::total 183489 # number of demand (read+write) hits 2538system.l2c.overall_hits::cpu0.dtb.walker 142 # number of overall hits 2539system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits 2540system.l2c.overall_hits::cpu0.inst 44259 # number of overall hits 2541system.l2c.overall_hits::cpu0.data 56833 # number of overall hits 2542system.l2c.overall_hits::cpu0.l2cache.prefetcher 45774 # number of overall hits 2543system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits 2544system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits 2545system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits 2546system.l2c.overall_hits::cpu1.data 12238 # number of overall hits 2547system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits 2548system.l2c.overall_hits::total 183489 # number of overall hits 2549system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses 2550system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses 2551system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses 2552system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses 2553system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses 2554system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses 2555system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses 2556system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses 2557system.l2c.ReadExReq_misses::total 19232 # number of ReadExReq misses 2558system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 9 # number of ReadSharedReq misses 2559system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2560system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses 2561system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses 2562system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses 2563system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses 2564system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses 2565system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses 2566system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses 2567system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses 2568system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2569system.l2c.demand_misses::cpu0.inst 17886 # number of demand (read+write) misses 2570system.l2c.demand_misses::cpu0.data 20308 # number of demand (read+write) misses 2571system.l2c.demand_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) misses 2572system.l2c.demand_misses::cpu1.inst 2327 # number of demand (read+write) misses 2573system.l2c.demand_misses::cpu1.data 8890 # number of demand (read+write) misses 2574system.l2c.demand_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) misses 2575system.l2c.demand_misses::total 189076 # number of demand (read+write) misses 2576system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses 2577system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2578system.l2c.overall_misses::cpu0.inst 17886 # number of overall misses 2579system.l2c.overall_misses::cpu0.data 20308 # number of overall misses 2580system.l2c.overall_misses::cpu0.l2cache.prefetcher 133589 # number of overall misses 2581system.l2c.overall_misses::cpu1.inst 2327 # number of overall misses 2582system.l2c.overall_misses::cpu1.data 8890 # number of overall misses 2583system.l2c.overall_misses::cpu1.l2cache.prefetcher 6065 # number of overall misses 2584system.l2c.overall_misses::total 189076 # number of overall misses 2585system.l2c.UpgradeReq_miss_latency::cpu0.data 9921500 # number of UpgradeReq miss cycles 2586system.l2c.UpgradeReq_miss_latency::cpu1.data 813500 # number of UpgradeReq miss cycles 2587system.l2c.UpgradeReq_miss_latency::total 10735000 # number of UpgradeReq miss cycles 2588system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles 2589system.l2c.SCUpgradeReq_miss_latency::cpu1.data 361000 # number of SCUpgradeReq miss cycles 2590system.l2c.SCUpgradeReq_miss_latency::total 975000 # number of SCUpgradeReq miss cycles 2591system.l2c.ReadExReq_miss_latency::cpu0.data 1635531500 # number of ReadExReq miss cycles 2592system.l2c.ReadExReq_miss_latency::cpu1.data 824298500 # number of ReadExReq miss cycles 2593system.l2c.ReadExReq_miss_latency::total 2459830000 # number of ReadExReq miss cycles 2594system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1956500 # number of ReadSharedReq miss cycles 2595system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180000 # number of ReadSharedReq miss cycles 2596system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1955907500 # number of ReadSharedReq miss cycles 2597system.l2c.ReadSharedReq_miss_latency::cpu0.data 1124374000 # number of ReadSharedReq miss cycles 2598system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of ReadSharedReq miss cycles 2599system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261946000 # number of ReadSharedReq miss cycles 2600system.l2c.ReadSharedReq_miss_latency::cpu1.data 108772000 # number of ReadSharedReq miss cycles 2601system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of ReadSharedReq miss cycles 2602system.l2c.ReadSharedReq_miss_latency::total 20157534022 # number of ReadSharedReq miss cycles 2603system.l2c.demand_miss_latency::cpu0.dtb.walker 1956500 # number of demand (read+write) miss cycles 2604system.l2c.demand_miss_latency::cpu0.itb.walker 180000 # number of demand (read+write) miss cycles 2605system.l2c.demand_miss_latency::cpu0.inst 1955907500 # number of demand (read+write) miss cycles 2606system.l2c.demand_miss_latency::cpu0.data 2759905500 # number of demand (read+write) miss cycles 2607system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of demand (read+write) miss cycles 2608system.l2c.demand_miss_latency::cpu1.inst 261946000 # number of demand (read+write) miss cycles 2609system.l2c.demand_miss_latency::cpu1.data 933070500 # number of demand (read+write) miss cycles 2610system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of demand (read+write) miss cycles 2611system.l2c.demand_miss_latency::total 22617364022 # number of demand (read+write) miss cycles 2612system.l2c.overall_miss_latency::cpu0.dtb.walker 1956500 # number of overall miss cycles 2613system.l2c.overall_miss_latency::cpu0.itb.walker 180000 # number of overall miss cycles 2614system.l2c.overall_miss_latency::cpu0.inst 1955907500 # number of overall miss cycles 2615system.l2c.overall_miss_latency::cpu0.data 2759905500 # number of overall miss cycles 2616system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of overall miss cycles 2617system.l2c.overall_miss_latency::cpu1.inst 261946000 # number of overall miss cycles 2618system.l2c.overall_miss_latency::cpu1.data 933070500 # number of overall miss cycles 2619system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of overall miss cycles 2620system.l2c.overall_miss_latency::total 22617364022 # number of overall miss cycles 2621system.l2c.WritebackDirty_accesses::writebacks 259449 # number of WritebackDirty accesses(hits+misses) 2622system.l2c.WritebackDirty_accesses::total 259449 # number of WritebackDirty accesses(hits+misses) 2623system.l2c.UpgradeReq_accesses::cpu0.data 40695 # number of UpgradeReq accesses(hits+misses) 2624system.l2c.UpgradeReq_accesses::cpu1.data 5158 # number of UpgradeReq accesses(hits+misses) 2625system.l2c.UpgradeReq_accesses::total 45853 # number of UpgradeReq accesses(hits+misses) 2626system.l2c.SCUpgradeReq_accesses::cpu0.data 2504 # number of SCUpgradeReq accesses(hits+misses) 2627system.l2c.SCUpgradeReq_accesses::cpu1.data 2310 # number of SCUpgradeReq accesses(hits+misses) 2628system.l2c.SCUpgradeReq_accesses::total 4814 # number of SCUpgradeReq accesses(hits+misses) 2629system.l2c.ReadExReq_accesses::cpu0.data 15223 # number of ReadExReq accesses(hits+misses) 2630system.l2c.ReadExReq_accesses::cpu1.data 9428 # number of ReadExReq accesses(hits+misses) 2631system.l2c.ReadExReq_accesses::total 24651 # number of ReadExReq accesses(hits+misses) 2632system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 151 # number of ReadSharedReq accesses(hits+misses) 2633system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses) 2634system.l2c.ReadSharedReq_accesses::cpu0.inst 62145 # number of ReadSharedReq accesses(hits+misses) 2635system.l2c.ReadSharedReq_accesses::cpu0.data 61918 # number of ReadSharedReq accesses(hits+misses) 2636system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179363 # number of ReadSharedReq accesses(hits+misses) 2637system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses) 2638system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) 2639system.l2c.ReadSharedReq_accesses::cpu1.inst 21120 # number of ReadSharedReq accesses(hits+misses) 2640system.l2c.ReadSharedReq_accesses::cpu1.data 11700 # number of ReadSharedReq accesses(hits+misses) 2641system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11376 # number of ReadSharedReq accesses(hits+misses) 2642system.l2c.ReadSharedReq_accesses::total 347914 # number of ReadSharedReq accesses(hits+misses) 2643system.l2c.demand_accesses::cpu0.dtb.walker 151 # number of demand (read+write) accesses 2644system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses 2645system.l2c.demand_accesses::cpu0.inst 62145 # number of demand (read+write) accesses 2646system.l2c.demand_accesses::cpu0.data 77141 # number of demand (read+write) accesses 2647system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179363 # number of demand (read+write) accesses 2648system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses 2649system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses 2650system.l2c.demand_accesses::cpu1.inst 21120 # number of demand (read+write) accesses 2651system.l2c.demand_accesses::cpu1.data 21128 # number of demand (read+write) accesses 2652system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11376 # number of demand (read+write) accesses 2653system.l2c.demand_accesses::total 372565 # number of demand (read+write) accesses 2654system.l2c.overall_accesses::cpu0.dtb.walker 151 # number of overall (read+write) accesses 2655system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses 2656system.l2c.overall_accesses::cpu0.inst 62145 # number of overall (read+write) accesses 2657system.l2c.overall_accesses::cpu0.data 77141 # number of overall (read+write) accesses 2658system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179363 # number of overall (read+write) accesses 2659system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses 2660system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses 2661system.l2c.overall_accesses::cpu1.inst 21120 # number of overall (read+write) accesses 2662system.l2c.overall_accesses::cpu1.data 21128 # number of overall (read+write) accesses 2663system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11376 # number of overall (read+write) accesses 2664system.l2c.overall_accesses::total 372565 # number of overall (read+write) accesses 2665system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014547 # miss rate for UpgradeReq accesses 2666system.l2c.UpgradeReq_miss_rate::cpu1.data 0.048856 # miss rate for UpgradeReq accesses 2667system.l2c.UpgradeReq_miss_rate::total 0.018407 # miss rate for UpgradeReq accesses 2668system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.047125 # miss rate for SCUpgradeReq accesses 2669system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.039827 # miss rate for SCUpgradeReq accesses 2670system.l2c.SCUpgradeReq_miss_rate::total 0.043623 # miss rate for SCUpgradeReq accesses 2671system.l2c.ReadExReq_miss_rate::cpu0.data 0.736846 # miss rate for ReadExReq accesses 2672system.l2c.ReadExReq_miss_rate::cpu1.data 0.850127 # miss rate for ReadExReq accesses 2673system.l2c.ReadExReq_miss_rate::total 0.780171 # miss rate for ReadExReq accesses 2674system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for ReadSharedReq accesses 2675system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.024096 # miss rate for ReadSharedReq accesses 2676system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287811 # miss rate for ReadSharedReq accesses 2677system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146823 # miss rate for ReadSharedReq accesses 2678system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for ReadSharedReq accesses 2679system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110180 # miss rate for ReadSharedReq accesses 2680system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.074786 # miss rate for ReadSharedReq accesses 2681system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for ReadSharedReq accesses 2682system.l2c.ReadSharedReq_miss_rate::total 0.488178 # miss rate for ReadSharedReq accesses 2683system.l2c.demand_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for demand accesses 2684system.l2c.demand_miss_rate::cpu0.itb.walker 0.024096 # miss rate for demand accesses 2685system.l2c.demand_miss_rate::cpu0.inst 0.287811 # miss rate for demand accesses 2686system.l2c.demand_miss_rate::cpu0.data 0.263258 # miss rate for demand accesses 2687system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for demand accesses 2688system.l2c.demand_miss_rate::cpu1.inst 0.110180 # miss rate for demand accesses 2689system.l2c.demand_miss_rate::cpu1.data 0.420769 # miss rate for demand accesses 2690system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for demand accesses 2691system.l2c.demand_miss_rate::total 0.507498 # miss rate for demand accesses 2692system.l2c.overall_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for overall accesses 2693system.l2c.overall_miss_rate::cpu0.itb.walker 0.024096 # miss rate for overall accesses 2694system.l2c.overall_miss_rate::cpu0.inst 0.287811 # miss rate for overall accesses 2695system.l2c.overall_miss_rate::cpu0.data 0.263258 # miss rate for overall accesses 2696system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for overall accesses 2697system.l2c.overall_miss_rate::cpu1.inst 0.110180 # miss rate for overall accesses 2698system.l2c.overall_miss_rate::cpu1.data 0.420769 # miss rate for overall accesses 2699system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for overall accesses 2700system.l2c.overall_miss_rate::total 0.507498 # miss rate for overall accesses 2701system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541 # average UpgradeReq miss latency 2702system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3228.174603 # average UpgradeReq miss latency 2703system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313 # average UpgradeReq miss latency 2704system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5203.389831 # average SCUpgradeReq miss latency 2705system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3923.913043 # average SCUpgradeReq miss latency 2706system.l2c.SCUpgradeReq_avg_miss_latency::total 4642.857143 # average SCUpgradeReq miss latency 2707system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072 # average ReadExReq miss latency 2708system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102 # average ReadExReq miss latency 2709system.l2c.ReadExReq_avg_miss_latency::total 127902.974210 # average ReadExReq miss latency 2710system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average ReadSharedReq miss latency 2711system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency 2712system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768 # average ReadSharedReq miss latency 2713system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201 # average ReadSharedReq miss latency 2714system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average ReadSharedReq miss latency 2715system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451 # average ReadSharedReq miss latency 2716system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143 # average ReadSharedReq miss latency 2717system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average ReadSharedReq miss latency 2718system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315 # average ReadSharedReq miss latency 2719system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency 2720system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2721system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency 2722system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency 2723system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency 2724system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency 2725system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency 2726system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency 2727system.l2c.demand_avg_miss_latency::total 119620.491347 # average overall miss latency 2728system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency 2729system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2730system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency 2731system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency 2732system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency 2733system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency 2734system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency 2735system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency 2736system.l2c.overall_avg_miss_latency::total 119620.491347 # average overall miss latency 2737system.l2c.blocked_cycles::no_mshrs 873 # number of cycles access was blocked 2738system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2739system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 2740system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2741system.l2c.avg_blocked_cycles::no_mshrs 109.125000 # average number of cycles each access was blocked 2742system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2743system.l2c.writebacks::writebacks 99972 # number of writebacks 2744system.l2c.writebacks::total 99972 # number of writebacks 2745system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7 # number of ReadSharedReq MSHR hits 2746system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits 2747system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits 2748system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 2749system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits 2750system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 2751system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 2752system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits 2753system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits 2754system.l2c.CleanEvict_mshr_misses::writebacks 3644 # number of CleanEvict MSHR misses 2755system.l2c.CleanEvict_mshr_misses::total 3644 # number of CleanEvict MSHR misses 2756system.l2c.UpgradeReq_mshr_misses::cpu0.data 592 # number of UpgradeReq MSHR misses 2757system.l2c.UpgradeReq_mshr_misses::cpu1.data 252 # number of UpgradeReq MSHR misses 2758system.l2c.UpgradeReq_mshr_misses::total 844 # number of UpgradeReq MSHR misses 2759system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 118 # number of SCUpgradeReq MSHR misses 2760system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 92 # number of SCUpgradeReq MSHR misses 2761system.l2c.SCUpgradeReq_mshr_misses::total 210 # number of SCUpgradeReq MSHR misses 2762system.l2c.ReadExReq_mshr_misses::cpu0.data 11217 # number of ReadExReq MSHR misses 2763system.l2c.ReadExReq_mshr_misses::cpu1.data 8015 # number of ReadExReq MSHR misses 2764system.l2c.ReadExReq_mshr_misses::total 19232 # number of ReadExReq MSHR misses 2765system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadSharedReq MSHR misses 2766system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2767system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17879 # number of ReadSharedReq MSHR misses 2768system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9091 # number of ReadSharedReq MSHR misses 2769system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq MSHR misses 2770system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2318 # number of ReadSharedReq MSHR misses 2771system.l2c.ReadSharedReq_mshr_misses::cpu1.data 875 # number of ReadSharedReq MSHR misses 2772system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq MSHR misses 2773system.l2c.ReadSharedReq_mshr_misses::total 169828 # number of ReadSharedReq MSHR misses 2774system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses 2775system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2776system.l2c.demand_mshr_misses::cpu0.inst 17879 # number of demand (read+write) MSHR misses 2777system.l2c.demand_mshr_misses::cpu0.data 20308 # number of demand (read+write) MSHR misses 2778system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) MSHR misses 2779system.l2c.demand_mshr_misses::cpu1.inst 2318 # number of demand (read+write) MSHR misses 2780system.l2c.demand_mshr_misses::cpu1.data 8890 # number of demand (read+write) MSHR misses 2781system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) MSHR misses 2782system.l2c.demand_mshr_misses::total 189060 # number of demand (read+write) MSHR misses 2783system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses 2784system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2785system.l2c.overall_mshr_misses::cpu0.inst 17879 # number of overall MSHR misses 2786system.l2c.overall_mshr_misses::cpu0.data 20308 # number of overall MSHR misses 2787system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of overall MSHR misses 2788system.l2c.overall_mshr_misses::cpu1.inst 2318 # number of overall MSHR misses 2789system.l2c.overall_mshr_misses::cpu1.data 8890 # number of overall MSHR misses 2790system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of overall MSHR misses 2791system.l2c.overall_mshr_misses::total 189060 # number of overall MSHR misses 2792system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2793system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable 2794system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2795system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3093 # number of ReadReq MSHR uncacheable 2796system.l2c.ReadReq_mshr_uncacheable::total 44082 # number of ReadReq MSHR uncacheable 2797system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable 2798system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable 2799system.l2c.WriteReq_mshr_uncacheable::total 30915 # number of WriteReq MSHR uncacheable 2800system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2801system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses 2802system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2803system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5544 # number of overall MSHR uncacheable misses 2804system.l2c.overall_mshr_uncacheable_misses::total 74997 # number of overall MSHR uncacheable misses 2805system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13698000 # number of UpgradeReq MSHR miss cycles 2806system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5474500 # number of UpgradeReq MSHR miss cycles 2807system.l2c.UpgradeReq_mshr_miss_latency::total 19172500 # number of UpgradeReq MSHR miss cycles 2808system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3092000 # number of SCUpgradeReq MSHR miss cycles 2809system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2171500 # number of SCUpgradeReq MSHR miss cycles 2810system.l2c.SCUpgradeReq_mshr_miss_latency::total 5263500 # number of SCUpgradeReq MSHR miss cycles 2811system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1523361500 # number of ReadExReq MSHR miss cycles 2812system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 744148500 # number of ReadExReq MSHR miss cycles 2813system.l2c.ReadExReq_mshr_miss_latency::total 2267510000 # number of ReadExReq MSHR miss cycles 2814system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of ReadSharedReq MSHR miss cycles 2815system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadSharedReq MSHR miss cycles 2816system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1775966000 # number of ReadSharedReq MSHR miss cycles 2817system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1033464000 # number of ReadSharedReq MSHR miss cycles 2818system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of ReadSharedReq MSHR miss cycles 2819system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 238288500 # number of ReadSharedReq MSHR miss cycles 2820system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 100021501 # number of ReadSharedReq MSHR miss cycles 2821system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of ReadSharedReq MSHR miss cycles 2822system.l2c.ReadSharedReq_mshr_miss_latency::total 18457620033 # number of ReadSharedReq MSHR miss cycles 2823system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of demand (read+write) MSHR miss cycles 2824system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles 2825system.l2c.demand_mshr_miss_latency::cpu0.inst 1775966000 # number of demand (read+write) MSHR miss cycles 2826system.l2c.demand_mshr_miss_latency::cpu0.data 2556825500 # number of demand (read+write) MSHR miss cycles 2827system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of demand (read+write) MSHR miss cycles 2828system.l2c.demand_mshr_miss_latency::cpu1.inst 238288500 # number of demand (read+write) MSHR miss cycles 2829system.l2c.demand_mshr_miss_latency::cpu1.data 844170001 # number of demand (read+write) MSHR miss cycles 2830system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of demand (read+write) MSHR miss cycles 2831system.l2c.demand_mshr_miss_latency::total 20725130033 # number of demand (read+write) MSHR miss cycles 2832system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of overall MSHR miss cycles 2833system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles 2834system.l2c.overall_mshr_miss_latency::cpu0.inst 1775966000 # number of overall MSHR miss cycles 2835system.l2c.overall_mshr_miss_latency::cpu0.data 2556825500 # number of overall MSHR miss cycles 2836system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of overall MSHR miss cycles 2837system.l2c.overall_mshr_miss_latency::cpu1.inst 238288500 # number of overall MSHR miss cycles 2838system.l2c.overall_mshr_miss_latency::cpu1.data 844170001 # number of overall MSHR miss cycles 2839system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of overall MSHR miss cycles 2840system.l2c.overall_mshr_miss_latency::total 20725130033 # number of overall MSHR miss cycles 2841system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles 2842system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805450500 # number of ReadReq MSHR uncacheable cycles 2843system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12497000 # number of ReadReq MSHR uncacheable cycles 2844system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362875500 # number of ReadReq MSHR uncacheable cycles 2845system.l2c.ReadReq_mshr_uncacheable_latency::total 6814067000 # number of ReadReq MSHR uncacheable cycles 2846system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles 2847system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805450500 # number of overall MSHR uncacheable cycles 2848system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12497000 # number of overall MSHR uncacheable cycles 2849system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362875500 # number of overall MSHR uncacheable cycles 2850system.l2c.overall_mshr_uncacheable_latency::total 6814067000 # number of overall MSHR uncacheable cycles 2851system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2852system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2853system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses 2854system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses 2855system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses 2856system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses 2857system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses 2858system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses 2859system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses 2860system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses 2861system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses 2862system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses 2863system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses 2864system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses 2865system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses 2866system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses 2867system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses 2868system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses 2869system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses 2870system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses 2871system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses 2872system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses 2873system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses 2874system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses 2875system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses 2876system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses 2877system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses 2878system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses 2879system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses 2880system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses 2881system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses 2882system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses 2883system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses 2884system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses 2885system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses 2886system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses 2887system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses 2888system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses 2889system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency 2890system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency 2891system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency 2892system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency 2893system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency 2894system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency 2895system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency 2896system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency 2897system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency 2898system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency 2899system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency 2900system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency 2901system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency 2902system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency 2903system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency 2904system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency 2905system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency 2906system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency 2907system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency 2908system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2909system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency 2910system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency 2911system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency 2912system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency 2913system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency 2914system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency 2915system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency 2916system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency 2917system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2918system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency 2919system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency 2920system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency 2921system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency 2922system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency 2923system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency 2924system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency 2925system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency 2926system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency 2927system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency 2928system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency 2929system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency 2930system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency 2931system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency 2932system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency 2933system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency 2934system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency 2935system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter. 2936system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2937system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2938system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2939system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2940system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2941system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2942system.membus.trans_dist::ReadReq 44082 # Transaction distribution 2943system.membus.trans_dist::ReadResp 214165 # Transaction distribution 2944system.membus.trans_dist::WriteReq 30915 # Transaction distribution 2945system.membus.trans_dist::WriteResp 30915 # Transaction distribution 2946system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution 2947system.membus.trans_dist::CleanEvict 16178 # Transaction distribution 2948system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution 2949system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution 2950system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 2951system.membus.trans_dist::ReadExReq 39788 # Transaction distribution 2952system.membus.trans_dist::ReadExResp 19211 # Transaction distribution 2953system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution 2954system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2955system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2956system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2957system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) 2958system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes) 2959system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes) 2960system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) 2961system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) 2962system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes) 2963system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2964system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2965system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) 2966system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes) 2967system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes) 2968system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2969system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2970system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes) 2971system.membus.snoops 123440 # Total snoops (count) 2972system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) 2973system.membus.snoop_fanout::samples 424426 # Request fanout histogram 2974system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram 2975system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram 2976system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2977system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram 2978system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram 2979system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2980system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2981system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2982system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2983system.membus.snoop_fanout::total 424426 # Request fanout histogram 2984system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks) 2985system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2986system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2987system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2988system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks) 2989system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2990system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks) 2991system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2992system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks) 2993system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2994system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks) 2995system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2996system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2997system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2998system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2999system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3000system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3001system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3002system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3003system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3004system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3005system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3006system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3007system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3008system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3009system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3010system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3011system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3012system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3013system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3014system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3015system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3016system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3017system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3018system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3019system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3020system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3021system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3022system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3023system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3024system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3025system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3026system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3027system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3028system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3029system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3030system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3031system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3032system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3033system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3034system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3035system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3036system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3037system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3038system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3039system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3040system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3041system.realview.ethernet.droppedPackets 0 # number of packets dropped 3042system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3043system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3044system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3045system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3046system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3047system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3048system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3049system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3050system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3051system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3052system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3053system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3054system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3055system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3056system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3057system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3058system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3059system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3060system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3061system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3062system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3063system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3064system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3065system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter. 3066system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3067system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3068system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter. 3069system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3070system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3071system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3072system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution 3073system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution 3074system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution 3075system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution 3076system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution 3077system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution 3078system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution 3079system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution 3080system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution 3081system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution 3082system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution 3083system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution 3084system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution 3085system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution 3086system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution 3087system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes) 3088system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes) 3089system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes) 3090system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes) 3091system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes) 3092system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes) 3093system.toL2Bus.snoops 388372 # Total snoops (count) 3094system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes) 3095system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram 3096system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram 3097system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram 3098system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3099system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram 3100system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram 3101system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram 3102system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3103system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3104system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3105system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram 3106system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks) 3107system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3108system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks) 3109system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3110system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks) 3111system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3112system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks) 3113system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3114 3115---------- End Simulation Statistics ----------	1586system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1587system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1588system.cpu1.op_class::total 20100990 # Class of executed instruction 1589system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1590system.cpu1.dcache.tags.replacements 186832 # number of replacements 1591system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use 1592system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks. 1593system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks. 1594system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks. 1595system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit. 1596system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor 1597system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy 1598system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy 1599system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 1600system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id 1601system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id 1602system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id 1603system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses 1604system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses 1605system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1606system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits 1607system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits 1608system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits 1609system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits 1610system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits 1611system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits 1612system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits 1613system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits 1614system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits 1615system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits 1616system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits 1617system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits 1618system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits 1619system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits 1620system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses 1621system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses 1622system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses 1623system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses 1624system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses 1625system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses 1626system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses 1627system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses 1628system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses 1629system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses 1630system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses 1631system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses 1632system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses 1633system.cpu1.dcache.overall_misses::total 255886 # number of overall misses 1634system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles 1635system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles 1636system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles 1637system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles 1638system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles 1639system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles 1640system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles 1641system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles 1642system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles 1643system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles 1644system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles 1645system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles 1646system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles 1647system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles 1648system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses) 1649system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses) 1650system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses) 1651system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses) 1652system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses) 1653system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses) 1654system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses) 1655system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses) 1656system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses) 1657system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses) 1658system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses 1659system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses 1660system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses 1661system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses 1662system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses 1663system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses 1664system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses 1665system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses 1666system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses 1667system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses 1668system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses 1669system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses 1670system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses 1671system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses 1672system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses 1673system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses 1674system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses 1675system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses 1676system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency 1677system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency 1678system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency 1679system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency 1680system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency 1681system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency 1682system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency 1683system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency 1684system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1685system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1686system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency 1687system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency 1688system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency 1689system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency 1690system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1691system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1692system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1693system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1694system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1695system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1696system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks 1697system.cpu1.dcache.writebacks::total 186832 # number of writebacks 1698system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits 1699system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits 1700system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits 1701system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits 1702system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits 1703system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits 1704system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits 1705system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits 1706system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses 1707system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses 1708system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses 1709system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses 1710system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses 1711system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses 1712system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses 1713system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses 1714system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses 1715system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses 1716system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses 1717system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses 1718system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses 1719system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses 1720system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable 1721system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable 1722system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable 1723system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable 1724system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses 1725system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses 1726system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles 1727system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles 1728system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles 1729system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles 1730system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles 1731system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles 1732system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles 1733system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles 1734system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles 1735system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles 1736system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles 1737system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles 1738system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles 1739system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles 1740system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles 1741system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles 1742system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles 1743system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles 1744system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles 1745system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles 1746system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses 1747system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses 1748system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses 1749system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses 1750system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses 1751system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses 1752system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses 1753system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses 1754system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses 1755system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses 1756system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses 1757system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses 1758system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses 1759system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses 1760system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency 1761system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency 1762system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency 1763system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency 1764system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency 1765system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency 1766system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency 1767system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency 1768system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency 1769system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency 1770system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1771system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1772system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency 1773system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency 1774system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency 1775system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency 1776system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency 1777system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency 1778system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency 1779system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency 1780system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1781system.cpu1.icache.tags.replacements 505764 # number of replacements 1782system.cpu1.icache.tags.tagsinuse 498.454577 # Cycle average of tags in use 1783system.cpu1.icache.tags.total_refs 16059144 # Total number of references to valid blocks. 1784system.cpu1.icache.tags.sampled_refs 506276 # Sample count of references to valid blocks. 1785system.cpu1.icache.tags.avg_refs 31.720137 # Average number of references to valid blocks. 1786system.cpu1.icache.tags.warmup_cycle 85411536000 # Cycle when the warmup percentage was hit. 1787system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.454577 # Average occupied blocks per requestor 1788system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973544 # Average percentage of cache occupancy 1789system.cpu1.icache.tags.occ_percent::total 0.973544 # Average percentage of cache occupancy 1790system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1791system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1792system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id 1793system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1794system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1795system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses 1796system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses 1797system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1798system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits 1799system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits 1800system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits 1801system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits 1802system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits 1803system.cpu1.icache.overall_hits::total 16059144 # number of overall hits 1804system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses 1805system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses 1806system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses 1807system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses 1808system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses 1809system.cpu1.icache.overall_misses::total 506276 # number of overall misses 1810system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles 1811system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles 1812system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles 1813system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles 1814system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles 1815system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles 1816system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses) 1817system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses) 1818system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses 1819system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses 1820system.cpu1.icache.overall_accesses::cpu1.inst 16565420 # number of overall (read+write) accesses 1821system.cpu1.icache.overall_accesses::total 16565420 # number of overall (read+write) accesses 1822system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030562 # miss rate for ReadReq accesses 1823system.cpu1.icache.ReadReq_miss_rate::total 0.030562 # miss rate for ReadReq accesses 1824system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030562 # miss rate for demand accesses 1825system.cpu1.icache.demand_miss_rate::total 0.030562 # miss rate for demand accesses 1826system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030562 # miss rate for overall accesses 1827system.cpu1.icache.overall_miss_rate::total 0.030562 # miss rate for overall accesses 1828system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9427.881235 # average ReadReq miss latency 1829system.cpu1.icache.ReadReq_avg_miss_latency::total 9427.881235 # average ReadReq miss latency 1830system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency 1831system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency 1832system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency 1833system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency 1834system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1835system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1836system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1837system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1838system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1839system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1840system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks 1841system.cpu1.icache.writebacks::total 505764 # number of writebacks 1842system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses 1843system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses 1844system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses 1845system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses 1846system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses 1847system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses 1848system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1849system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1850system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1851system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1852system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles 1853system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles 1854system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles 1855system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles 1856system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles 1857system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles 1858system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles 1859system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles 1860system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles 1861system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles 1862system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses 1863system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses 1864system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses 1865system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses 1866system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses 1867system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses 1868system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency 1869system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency 1870system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency 1871system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency 1872system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency 1873system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency 1874system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency 1875system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency 1876system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency 1877system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency 1878system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1879system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued 1880system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified 1881system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1882system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1883system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1884system.cpu1.l2cache.prefetcher.pfSpanPage 59073 # number of prefetches not generated due to page crossing 1885system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1886system.cpu1.l2cache.tags.replacements 42341 # number of replacements 1887system.cpu1.l2cache.tags.tagsinuse 14550.545082 # Cycle average of tags in use 1888system.cpu1.l2cache.tags.total_refs 605184 # Total number of references to valid blocks. 1889system.cpu1.l2cache.tags.sampled_refs 56718 # Sample count of references to valid blocks. 1890system.cpu1.l2cache.tags.avg_refs 10.670052 # Average number of references to valid blocks. 1891system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1892system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor 1893system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor 1894system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor 1895system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor 1896system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy 1897system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy 1898system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy 1899system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy 1900system.cpu1.l2cache.tags.occ_percent::total 0.888095 # Average percentage of cache occupancy 1901system.cpu1.l2cache.tags.occ_task_id_blocks::1022 333 # Occupied blocks per task id 1902system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id 1903system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id 1904system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 1905system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id 1906system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id 1907system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1908system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1909system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id 1910system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2799 # Occupied blocks per task id 1911system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10333 # Occupied blocks per task id 1912system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020325 # Percentage of cache occupancy per task id 1913system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id 1914system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id 1915system.cpu1.l2cache.tags.tag_accesses 24327160 # Number of tag accesses 1916system.cpu1.l2cache.tags.data_accesses 24327160 # Number of data accesses 1917system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 1918system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3447 # number of ReadReq hits 1919system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1877 # number of ReadReq hits 1920system.cpu1.l2cache.ReadReq_hits::total 5324 # number of ReadReq hits 1921system.cpu1.l2cache.WritebackDirty_hits::writebacks 114448 # number of WritebackDirty hits 1922system.cpu1.l2cache.WritebackDirty_hits::total 114448 # number of WritebackDirty hits 1923system.cpu1.l2cache.WritebackClean_hits::writebacks 567034 # number of WritebackClean hits 1924system.cpu1.l2cache.WritebackClean_hits::total 567034 # number of WritebackClean hits 1925system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27676 # number of ReadExReq hits 1926system.cpu1.l2cache.ReadExReq_hits::total 27676 # number of ReadExReq hits 1927system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 485156 # number of ReadCleanReq hits 1928system.cpu1.l2cache.ReadCleanReq_hits::total 485156 # number of ReadCleanReq hits 1929system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98414 # number of ReadSharedReq hits 1930system.cpu1.l2cache.ReadSharedReq_hits::total 98414 # number of ReadSharedReq hits 1931system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3447 # number of demand (read+write) hits 1932system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1877 # number of demand (read+write) hits 1933system.cpu1.l2cache.demand_hits::cpu1.inst 485156 # number of demand (read+write) hits 1934system.cpu1.l2cache.demand_hits::cpu1.data 126090 # number of demand (read+write) hits 1935system.cpu1.l2cache.demand_hits::total 616570 # number of demand (read+write) hits 1936system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3447 # number of overall hits 1937system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1877 # number of overall hits 1938system.cpu1.l2cache.overall_hits::cpu1.inst 485156 # number of overall hits 1939system.cpu1.l2cache.overall_hits::cpu1.data 126090 # number of overall hits 1940system.cpu1.l2cache.overall_hits::total 616570 # number of overall hits 1941system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 422 # number of ReadReq misses 1942system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 327 # number of ReadReq misses 1943system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses 1944system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29541 # number of UpgradeReq misses 1945system.cpu1.l2cache.UpgradeReq_misses::total 29541 # number of UpgradeReq misses 1946system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23233 # number of SCUpgradeReq misses 1947system.cpu1.l2cache.SCUpgradeReq_misses::total 23233 # number of SCUpgradeReq misses 1948system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses 1949system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 1950system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34651 # number of ReadExReq misses 1951system.cpu1.l2cache.ReadExReq_misses::total 34651 # number of ReadExReq misses 1952system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21120 # number of ReadCleanReq misses 1953system.cpu1.l2cache.ReadCleanReq_misses::total 21120 # number of ReadCleanReq misses 1954system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69614 # number of ReadSharedReq misses 1955system.cpu1.l2cache.ReadSharedReq_misses::total 69614 # number of ReadSharedReq misses 1956system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 422 # number of demand (read+write) misses 1957system.cpu1.l2cache.demand_misses::cpu1.itb.walker 327 # number of demand (read+write) misses 1958system.cpu1.l2cache.demand_misses::cpu1.inst 21120 # number of demand (read+write) misses 1959system.cpu1.l2cache.demand_misses::cpu1.data 104265 # number of demand (read+write) misses 1960system.cpu1.l2cache.demand_misses::total 126134 # number of demand (read+write) misses 1961system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 422 # number of overall misses 1962system.cpu1.l2cache.overall_misses::cpu1.itb.walker 327 # number of overall misses 1963system.cpu1.l2cache.overall_misses::cpu1.inst 21120 # number of overall misses 1964system.cpu1.l2cache.overall_misses::cpu1.data 104265 # number of overall misses 1965system.cpu1.l2cache.overall_misses::total 126134 # number of overall misses 1966system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8582000 # number of ReadReq miss cycles 1967system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6568500 # number of ReadReq miss cycles 1968system.cpu1.l2cache.ReadReq_miss_latency::total 15150500 # number of ReadReq miss cycles 1969system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13749500 # number of UpgradeReq miss cycles 1970system.cpu1.l2cache.UpgradeReq_miss_latency::total 13749500 # number of UpgradeReq miss cycles 1971system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16999500 # number of SCUpgradeReq miss cycles 1972system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16999500 # number of SCUpgradeReq miss cycles 1973system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1709500 # number of SCUpgradeFailReq miss cycles 1974system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1709500 # number of SCUpgradeFailReq miss cycles 1975system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1487134000 # number of ReadExReq miss cycles 1976system.cpu1.l2cache.ReadExReq_miss_latency::total 1487134000 # number of ReadExReq miss cycles 1977system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 835278500 # number of ReadCleanReq miss cycles 1978system.cpu1.l2cache.ReadCleanReq_miss_latency::total 835278500 # number of ReadCleanReq miss cycles 1979system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1591067500 # number of ReadSharedReq miss cycles 1980system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1591067500 # number of ReadSharedReq miss cycles 1981system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8582000 # number of demand (read+write) miss cycles 1982system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6568500 # number of demand (read+write) miss cycles 1983system.cpu1.l2cache.demand_miss_latency::cpu1.inst 835278500 # number of demand (read+write) miss cycles 1984system.cpu1.l2cache.demand_miss_latency::cpu1.data 3078201500 # number of demand (read+write) miss cycles 1985system.cpu1.l2cache.demand_miss_latency::total 3928630500 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8582000 # number of overall miss cycles 1987system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6568500 # number of overall miss cycles 1988system.cpu1.l2cache.overall_miss_latency::cpu1.inst 835278500 # number of overall miss cycles 1989system.cpu1.l2cache.overall_miss_latency::cpu1.data 3078201500 # number of overall miss cycles 1990system.cpu1.l2cache.overall_miss_latency::total 3928630500 # number of overall miss cycles 1991system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3869 # number of ReadReq accesses(hits+misses) 1992system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2204 # number of ReadReq accesses(hits+misses) 1993system.cpu1.l2cache.ReadReq_accesses::total 6073 # number of ReadReq accesses(hits+misses) 1994system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114448 # number of WritebackDirty accesses(hits+misses) 1995system.cpu1.l2cache.WritebackDirty_accesses::total 114448 # number of WritebackDirty accesses(hits+misses) 1996system.cpu1.l2cache.WritebackClean_accesses::writebacks 567034 # number of WritebackClean accesses(hits+misses) 1997system.cpu1.l2cache.WritebackClean_accesses::total 567034 # number of WritebackClean accesses(hits+misses) 1998system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29541 # number of UpgradeReq accesses(hits+misses) 1999system.cpu1.l2cache.UpgradeReq_accesses::total 29541 # number of UpgradeReq accesses(hits+misses) 2000system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23233 # number of SCUpgradeReq accesses(hits+misses) 2001system.cpu1.l2cache.SCUpgradeReq_accesses::total 23233 # number of SCUpgradeReq accesses(hits+misses) 2002system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 2003system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 2004system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62327 # number of ReadExReq accesses(hits+misses) 2005system.cpu1.l2cache.ReadExReq_accesses::total 62327 # number of ReadExReq accesses(hits+misses) 2006system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506276 # number of ReadCleanReq accesses(hits+misses) 2007system.cpu1.l2cache.ReadCleanReq_accesses::total 506276 # number of ReadCleanReq accesses(hits+misses) 2008system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168028 # number of ReadSharedReq accesses(hits+misses) 2009system.cpu1.l2cache.ReadSharedReq_accesses::total 168028 # number of ReadSharedReq accesses(hits+misses) 2010system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3869 # number of demand (read+write) accesses 2011system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2204 # number of demand (read+write) accesses 2012system.cpu1.l2cache.demand_accesses::cpu1.inst 506276 # number of demand (read+write) accesses 2013system.cpu1.l2cache.demand_accesses::cpu1.data 230355 # number of demand (read+write) accesses 2014system.cpu1.l2cache.demand_accesses::total 742704 # number of demand (read+write) accesses 2015system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3869 # number of overall (read+write) accesses 2016system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2204 # number of overall (read+write) accesses 2017system.cpu1.l2cache.overall_accesses::cpu1.inst 506276 # number of overall (read+write) accesses 2018system.cpu1.l2cache.overall_accesses::cpu1.data 230355 # number of overall (read+write) accesses 2019system.cpu1.l2cache.overall_accesses::total 742704 # number of overall (read+write) accesses 2020system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for ReadReq accesses 2021system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.148367 # miss rate for ReadReq accesses 2022system.cpu1.l2cache.ReadReq_miss_rate::total 0.123333 # miss rate for ReadReq accesses 2023system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2024system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2025system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2026system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2027system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2028system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2029system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555955 # miss rate for ReadExReq accesses 2030system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555955 # miss rate for ReadExReq accesses 2031system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041716 # miss rate for ReadCleanReq accesses 2032system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041716 # miss rate for ReadCleanReq accesses 2033system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414300 # miss rate for ReadSharedReq accesses 2034system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414300 # miss rate for ReadSharedReq accesses 2035system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for demand accesses 2036system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.148367 # miss rate for demand accesses 2037system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041716 # miss rate for demand accesses 2038system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452627 # miss rate for demand accesses 2039system.cpu1.l2cache.demand_miss_rate::total 0.169831 # miss rate for demand accesses 2040system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109072 # miss rate for overall accesses 2041system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.148367 # miss rate for overall accesses 2042system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041716 # miss rate for overall accesses 2043system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452627 # miss rate for overall accesses 2044system.cpu1.l2cache.overall_miss_rate::total 0.169831 # miss rate for overall accesses 2045system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average ReadReq miss latency 2046system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963 # average ReadReq miss latency 2047system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849 # average ReadReq miss latency 2048system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 465.437866 # average UpgradeReq miss latency 2049system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 465.437866 # average UpgradeReq miss latency 2050system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 731.696294 # average SCUpgradeReq miss latency 2051system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 731.696294 # average SCUpgradeReq miss latency 2052system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 854750 # average SCUpgradeFailReq miss latency 2053system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 854750 # average SCUpgradeFailReq miss latency 2054system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559 # average ReadExReq miss latency 2055system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559 # average ReadExReq miss latency 2056system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402 # average ReadCleanReq miss latency 2057system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402 # average ReadCleanReq miss latency 2058system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846 # average ReadSharedReq miss latency 2059system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846 # average ReadSharedReq miss latency 2060system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency 2061system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency 2062system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency 2063system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency 2064system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105 # average overall miss latency 2065system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891 # average overall miss latency 2066system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963 # average overall miss latency 2067system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402 # average overall miss latency 2068system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816 # average overall miss latency 2069system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105 # average overall miss latency 2070system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2071system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2072system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2073system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2074system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2075system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2076system.cpu1.l2cache.unused_prefetches 833 # number of HardPF blocks evicted w/o reference 2077system.cpu1.l2cache.writebacks::writebacks 32020 # number of writebacks 2078system.cpu1.l2cache.writebacks::total 32020 # number of writebacks 2079system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 87 # number of ReadExReq MSHR hits 2080system.cpu1.l2cache.ReadExReq_mshr_hits::total 87 # number of ReadExReq MSHR hits 2081system.cpu1.l2cache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits 2082system.cpu1.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits 2083system.cpu1.l2cache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits 2084system.cpu1.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits 2085system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 422 # number of ReadReq MSHR misses 2086system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 327 # number of ReadReq MSHR misses 2087system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses 2088system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of HardPFReq MSHR misses 2089system.cpu1.l2cache.HardPFReq_mshr_misses::total 25249 # number of HardPFReq MSHR misses 2090system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29541 # number of UpgradeReq MSHR misses 2091system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29541 # number of UpgradeReq MSHR misses 2092system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23233 # number of SCUpgradeReq MSHR misses 2093system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23233 # number of SCUpgradeReq MSHR misses 2094system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses 2095system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 2096system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34564 # number of ReadExReq MSHR misses 2097system.cpu1.l2cache.ReadExReq_mshr_misses::total 34564 # number of ReadExReq MSHR misses 2098system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21120 # number of ReadCleanReq MSHR misses 2099system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21120 # number of ReadCleanReq MSHR misses 2100system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69614 # number of ReadSharedReq MSHR misses 2101system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69614 # number of ReadSharedReq MSHR misses 2102system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 422 # number of demand (read+write) MSHR misses 2103system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 327 # number of demand (read+write) MSHR misses 2104system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21120 # number of demand (read+write) MSHR misses 2105system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104178 # number of demand (read+write) MSHR misses 2106system.cpu1.l2cache.demand_mshr_misses::total 126047 # number of demand (read+write) MSHR misses 2107system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 422 # number of overall MSHR misses 2108system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 327 # number of overall MSHR misses 2109system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21120 # number of overall MSHR misses 2110system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104178 # number of overall MSHR misses 2111system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25249 # number of overall MSHR misses 2112system.cpu1.l2cache.overall_mshr_misses::total 151296 # number of overall MSHR misses 2113system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2114system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable 2115system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3273 # number of ReadReq MSHR uncacheable 2116system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable 2117system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable 2118system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2119system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses 2120system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses 2121system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles 2122system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles 2123system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles 2124system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles 2125system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles 2126system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles 2127system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles 2128system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles 2129system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles 2130system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles 2131system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles 2132system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles 2133system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles 2134system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles 2135system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles 2136system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles 2137system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles 2138system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles 2139system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles 2140system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles 2141system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles 2142system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles 2143system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles 2144system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles 2145system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles 2146system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles 2147system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles 2148system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles 2149system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles 2150system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles 2151system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles 2152system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles 2153system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles 2154system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles 2155system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses 2156system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses 2157system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses 2158system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2159system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2160system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2161system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2162system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2163system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2164system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2165system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2166system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses 2167system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses 2168system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses 2169system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses 2170system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses 2171system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses 2172system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses 2173system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses 2174system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses 2175system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses 2176system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses 2177system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses 2178system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses 2179system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses 2180system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses 2181system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2182system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses 2183system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency 2184system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency 2185system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency 2186system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency 2187system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency 2188system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency 2189system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency 2190system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency 2191system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency 2192system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency 2193system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency 2194system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency 2195system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency 2196system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency 2197system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency 2198system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency 2199system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency 2200system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency 2201system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency 2202system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency 2203system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency 2204system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency 2205system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency 2206system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency 2207system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency 2208system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency 2209system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency 2210system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency 2211system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency 2212system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency 2213system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency 2214system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency 2215system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency 2216system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency 2217system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter. 2218system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2219system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2220system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter. 2221system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2222system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2223system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2224system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution 2225system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution 2226system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution 2227system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution 2228system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution 2229system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution 2230system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution 2231system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution 2232system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution 2233system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution 2234system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution 2235system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution 2236system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution 2237system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution 2238system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution 2239system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution 2240system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution 2241system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution 2242system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes) 2243system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes) 2244system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes) 2245system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes) 2246system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes) 2247system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes) 2248system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes) 2249system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes) 2250system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes) 2251system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes) 2252system.cpu1.toL2Bus.snoops 331491 # Total snoops (count) 2253system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes) 2254system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram 2255system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram 2256system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram 2257system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2258system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram 2259system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram 2260system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram 2261system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2262system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2263system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2264system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram 2265system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks) 2266system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2267system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks) 2268system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2269system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks) 2270system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2271system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks) 2272system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2273system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2274system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2275system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks) 2276system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2277system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2278system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2279system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2280system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2281system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2282system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2283system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2284system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2285system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2286system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2287system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2288system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2289system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2290system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2291system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2292system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2293system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2294system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2295system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2296system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2297system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2298system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2299system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2300system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2301system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2302system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2303system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2304system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2305system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2306system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2307system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2308system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2309system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2310system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2311system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2312system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2313system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2314system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2315system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2316system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2317system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2318system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2319system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2320system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2321system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2322system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2323system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2324system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2325system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2326system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2327system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2328system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks) 2329system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2330system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 2331system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2332system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 2333system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2334system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) 2335system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2336system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) 2337system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2338system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) 2339system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2340system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) 2341system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2342system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) 2343system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2344system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 2345system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2346system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) 2347system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2348system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2349system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2350system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 2351system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2352system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 2353system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2354system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 2355system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2357system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2359system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) 2361system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks) 2363system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks) 2365system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks) 2367system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2368system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2369system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2370system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2371system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2372system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2373system.iocache.tags.replacements 36445 # number of replacements 2374system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use 2375system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2376system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2377system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2378system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit. 2379system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor 2380system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy 2381system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy 2382system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2383system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2384system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2385system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2386system.iocache.tags.data_accesses 328311 # Number of data accesses 2387system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2388system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2389system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2390system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2391system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2392system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2393system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2394system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2395system.iocache.overall_misses::total 36479 # number of overall misses 2396system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles 2397system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles 2398system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles 2399system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles 2400system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles 2401system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles 2402system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles 2403system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles 2404system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2405system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2406system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2407system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2408system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2409system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2410system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2411system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2412system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2413system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2414system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2415system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2416system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2417system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2418system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2419system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2420system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency 2421system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency 2422system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency 2423system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency 2424system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency 2425system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency 2426system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency 2427system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency 2428system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked 2429system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2430system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked 2431system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2432system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked 2433system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2434system.iocache.writebacks::writebacks 36190 # number of writebacks 2435system.iocache.writebacks::total 36190 # number of writebacks 2436system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2437system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2438system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2439system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2440system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2441system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2442system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2443system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2444system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles 2445system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles 2446system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles 2447system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles 2448system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles 2449system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles 2450system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles 2451system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles 2452system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2453system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2454system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2455system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2456system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2457system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2458system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2459system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2460system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471 # average ReadReq mshr miss latency 2461system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471 # average ReadReq mshr miss latency 2462system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048 # average WriteLineReq mshr miss latency 2463system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048 # average WriteLineReq mshr miss latency 2464system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency 2465system.iocache.demand_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency 2466system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046 # average overall mshr miss latency 2467system.iocache.overall_avg_mshr_miss_latency::total 71432.341046 # average overall mshr miss latency 2468system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2469system.l2c.tags.replacements 136024 # number of replacements 2470system.l2c.tags.tagsinuse 65074.400284 # Cycle average of tags in use 2471system.l2c.tags.total_refs 524979 # Total number of references to valid blocks. 2472system.l2c.tags.sampled_refs 201414 # Sample count of references to valid blocks. 2473system.l2c.tags.avg_refs 2.606467 # Average number of references to valid blocks. 2474system.l2c.tags.warmup_cycle 103030494000 # Cycle when the warmup percentage was hit. 2475system.l2c.tags.occ_blocks::writebacks 6378.541377 # Average occupied blocks per requestor 2476system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.901261 # Average occupied blocks per requestor 2477system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045973 # Average occupied blocks per requestor 2478system.l2c.tags.occ_blocks::cpu0.inst 7223.294710 # Average occupied blocks per requestor 2479system.l2c.tags.occ_blocks::cpu0.data 6923.893951 # Average occupied blocks per requestor 2480system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor 2481system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor 2482system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor 2483system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor 2484system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy 2485system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 2486system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2487system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy 2488system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy 2489system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy 2490system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy 2491system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy 2492system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy 2493system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy 2494system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id 2495system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2496system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id 2497system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 2498system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id 2499system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id 2500system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id 2501system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2502system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 2503system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 2504system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 2505system.l2c.tags.age_task_id_blocks_1024::3 1178 # Occupied blocks per task id 2506system.l2c.tags.age_task_id_blocks_1024::4 29816 # Occupied blocks per task id 2507system.l2c.tags.occ_task_id_percent::1022 0.523697 # Percentage of cache occupancy per task id 2508system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2509system.l2c.tags.occ_task_id_percent::1024 0.473999 # Percentage of cache occupancy per task id 2510system.l2c.tags.tag_accesses 6089608 # Number of tag accesses 2511system.l2c.tags.data_accesses 6089608 # Number of data accesses 2512system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2513system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits 2514system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits 2515system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits 2516system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits 2517system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits 2518system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits 2519system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits 2520system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits 2521system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits 2522system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits 2523system.l2c.ReadExReq_hits::total 5419 # number of ReadExReq hits 2524system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 142 # number of ReadSharedReq hits 2525system.l2c.ReadSharedReq_hits::cpu0.itb.walker 81 # number of ReadSharedReq hits 2526system.l2c.ReadSharedReq_hits::cpu0.inst 44259 # number of ReadSharedReq hits 2527system.l2c.ReadSharedReq_hits::cpu0.data 52827 # number of ReadSharedReq hits 2528system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45774 # number of ReadSharedReq hits 2529system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits 2530system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits 2531system.l2c.ReadSharedReq_hits::cpu1.inst 18793 # number of ReadSharedReq hits 2532system.l2c.ReadSharedReq_hits::cpu1.data 10825 # number of ReadSharedReq hits 2533system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5311 # number of ReadSharedReq hits 2534system.l2c.ReadSharedReq_hits::total 178070 # number of ReadSharedReq hits 2535system.l2c.demand_hits::cpu0.dtb.walker 142 # number of demand (read+write) hits 2536system.l2c.demand_hits::cpu0.itb.walker 81 # number of demand (read+write) hits 2537system.l2c.demand_hits::cpu0.inst 44259 # number of demand (read+write) hits 2538system.l2c.demand_hits::cpu0.data 56833 # number of demand (read+write) hits 2539system.l2c.demand_hits::cpu0.l2cache.prefetcher 45774 # number of demand (read+write) hits 2540system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits 2541system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits 2542system.l2c.demand_hits::cpu1.inst 18793 # number of demand (read+write) hits 2543system.l2c.demand_hits::cpu1.data 12238 # number of demand (read+write) hits 2544system.l2c.demand_hits::cpu1.l2cache.prefetcher 5311 # number of demand (read+write) hits 2545system.l2c.demand_hits::total 183489 # number of demand (read+write) hits 2546system.l2c.overall_hits::cpu0.dtb.walker 142 # number of overall hits 2547system.l2c.overall_hits::cpu0.itb.walker 81 # number of overall hits 2548system.l2c.overall_hits::cpu0.inst 44259 # number of overall hits 2549system.l2c.overall_hits::cpu0.data 56833 # number of overall hits 2550system.l2c.overall_hits::cpu0.l2cache.prefetcher 45774 # number of overall hits 2551system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits 2552system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits 2553system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits 2554system.l2c.overall_hits::cpu1.data 12238 # number of overall hits 2555system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits 2556system.l2c.overall_hits::total 183489 # number of overall hits 2557system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses 2558system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses 2559system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses 2560system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses 2561system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses 2562system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses 2563system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses 2564system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses 2565system.l2c.ReadExReq_misses::total 19232 # number of ReadExReq misses 2566system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 9 # number of ReadSharedReq misses 2567system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2568system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses 2569system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses 2570system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses 2571system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses 2572system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses 2573system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses 2574system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses 2575system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses 2576system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2577system.l2c.demand_misses::cpu0.inst 17886 # number of demand (read+write) misses 2578system.l2c.demand_misses::cpu0.data 20308 # number of demand (read+write) misses 2579system.l2c.demand_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) misses 2580system.l2c.demand_misses::cpu1.inst 2327 # number of demand (read+write) misses 2581system.l2c.demand_misses::cpu1.data 8890 # number of demand (read+write) misses 2582system.l2c.demand_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) misses 2583system.l2c.demand_misses::total 189076 # number of demand (read+write) misses 2584system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses 2585system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2586system.l2c.overall_misses::cpu0.inst 17886 # number of overall misses 2587system.l2c.overall_misses::cpu0.data 20308 # number of overall misses 2588system.l2c.overall_misses::cpu0.l2cache.prefetcher 133589 # number of overall misses 2589system.l2c.overall_misses::cpu1.inst 2327 # number of overall misses 2590system.l2c.overall_misses::cpu1.data 8890 # number of overall misses 2591system.l2c.overall_misses::cpu1.l2cache.prefetcher 6065 # number of overall misses 2592system.l2c.overall_misses::total 189076 # number of overall misses 2593system.l2c.UpgradeReq_miss_latency::cpu0.data 9921500 # number of UpgradeReq miss cycles 2594system.l2c.UpgradeReq_miss_latency::cpu1.data 813500 # number of UpgradeReq miss cycles 2595system.l2c.UpgradeReq_miss_latency::total 10735000 # number of UpgradeReq miss cycles 2596system.l2c.SCUpgradeReq_miss_latency::cpu0.data 614000 # number of SCUpgradeReq miss cycles 2597system.l2c.SCUpgradeReq_miss_latency::cpu1.data 361000 # number of SCUpgradeReq miss cycles 2598system.l2c.SCUpgradeReq_miss_latency::total 975000 # number of SCUpgradeReq miss cycles 2599system.l2c.ReadExReq_miss_latency::cpu0.data 1635531500 # number of ReadExReq miss cycles 2600system.l2c.ReadExReq_miss_latency::cpu1.data 824298500 # number of ReadExReq miss cycles 2601system.l2c.ReadExReq_miss_latency::total 2459830000 # number of ReadExReq miss cycles 2602system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1956500 # number of ReadSharedReq miss cycles 2603system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180000 # number of ReadSharedReq miss cycles 2604system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1955907500 # number of ReadSharedReq miss cycles 2605system.l2c.ReadSharedReq_miss_latency::cpu0.data 1124374000 # number of ReadSharedReq miss cycles 2606system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of ReadSharedReq miss cycles 2607system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261946000 # number of ReadSharedReq miss cycles 2608system.l2c.ReadSharedReq_miss_latency::cpu1.data 108772000 # number of ReadSharedReq miss cycles 2609system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of ReadSharedReq miss cycles 2610system.l2c.ReadSharedReq_miss_latency::total 20157534022 # number of ReadSharedReq miss cycles 2611system.l2c.demand_miss_latency::cpu0.dtb.walker 1956500 # number of demand (read+write) miss cycles 2612system.l2c.demand_miss_latency::cpu0.itb.walker 180000 # number of demand (read+write) miss cycles 2613system.l2c.demand_miss_latency::cpu0.inst 1955907500 # number of demand (read+write) miss cycles 2614system.l2c.demand_miss_latency::cpu0.data 2759905500 # number of demand (read+write) miss cycles 2615system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of demand (read+write) miss cycles 2616system.l2c.demand_miss_latency::cpu1.inst 261946000 # number of demand (read+write) miss cycles 2617system.l2c.demand_miss_latency::cpu1.data 933070500 # number of demand (read+write) miss cycles 2618system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of demand (read+write) miss cycles 2619system.l2c.demand_miss_latency::total 22617364022 # number of demand (read+write) miss cycles 2620system.l2c.overall_miss_latency::cpu0.dtb.walker 1956500 # number of overall miss cycles 2621system.l2c.overall_miss_latency::cpu0.itb.walker 180000 # number of overall miss cycles 2622system.l2c.overall_miss_latency::cpu0.inst 1955907500 # number of overall miss cycles 2623system.l2c.overall_miss_latency::cpu0.data 2759905500 # number of overall miss cycles 2624system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15941458655 # number of overall miss cycles 2625system.l2c.overall_miss_latency::cpu1.inst 261946000 # number of overall miss cycles 2626system.l2c.overall_miss_latency::cpu1.data 933070500 # number of overall miss cycles 2627system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 762939367 # number of overall miss cycles 2628system.l2c.overall_miss_latency::total 22617364022 # number of overall miss cycles 2629system.l2c.WritebackDirty_accesses::writebacks 259449 # number of WritebackDirty accesses(hits+misses) 2630system.l2c.WritebackDirty_accesses::total 259449 # number of WritebackDirty accesses(hits+misses) 2631system.l2c.UpgradeReq_accesses::cpu0.data 40695 # number of UpgradeReq accesses(hits+misses) 2632system.l2c.UpgradeReq_accesses::cpu1.data 5158 # number of UpgradeReq accesses(hits+misses) 2633system.l2c.UpgradeReq_accesses::total 45853 # number of UpgradeReq accesses(hits+misses) 2634system.l2c.SCUpgradeReq_accesses::cpu0.data 2504 # number of SCUpgradeReq accesses(hits+misses) 2635system.l2c.SCUpgradeReq_accesses::cpu1.data 2310 # number of SCUpgradeReq accesses(hits+misses) 2636system.l2c.SCUpgradeReq_accesses::total 4814 # number of SCUpgradeReq accesses(hits+misses) 2637system.l2c.ReadExReq_accesses::cpu0.data 15223 # number of ReadExReq accesses(hits+misses) 2638system.l2c.ReadExReq_accesses::cpu1.data 9428 # number of ReadExReq accesses(hits+misses) 2639system.l2c.ReadExReq_accesses::total 24651 # number of ReadExReq accesses(hits+misses) 2640system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 151 # number of ReadSharedReq accesses(hits+misses) 2641system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses) 2642system.l2c.ReadSharedReq_accesses::cpu0.inst 62145 # number of ReadSharedReq accesses(hits+misses) 2643system.l2c.ReadSharedReq_accesses::cpu0.data 61918 # number of ReadSharedReq accesses(hits+misses) 2644system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179363 # number of ReadSharedReq accesses(hits+misses) 2645system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses) 2646system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) 2647system.l2c.ReadSharedReq_accesses::cpu1.inst 21120 # number of ReadSharedReq accesses(hits+misses) 2648system.l2c.ReadSharedReq_accesses::cpu1.data 11700 # number of ReadSharedReq accesses(hits+misses) 2649system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11376 # number of ReadSharedReq accesses(hits+misses) 2650system.l2c.ReadSharedReq_accesses::total 347914 # number of ReadSharedReq accesses(hits+misses) 2651system.l2c.demand_accesses::cpu0.dtb.walker 151 # number of demand (read+write) accesses 2652system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses 2653system.l2c.demand_accesses::cpu0.inst 62145 # number of demand (read+write) accesses 2654system.l2c.demand_accesses::cpu0.data 77141 # number of demand (read+write) accesses 2655system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179363 # number of demand (read+write) accesses 2656system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses 2657system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses 2658system.l2c.demand_accesses::cpu1.inst 21120 # number of demand (read+write) accesses 2659system.l2c.demand_accesses::cpu1.data 21128 # number of demand (read+write) accesses 2660system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11376 # number of demand (read+write) accesses 2661system.l2c.demand_accesses::total 372565 # number of demand (read+write) accesses 2662system.l2c.overall_accesses::cpu0.dtb.walker 151 # number of overall (read+write) accesses 2663system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses 2664system.l2c.overall_accesses::cpu0.inst 62145 # number of overall (read+write) accesses 2665system.l2c.overall_accesses::cpu0.data 77141 # number of overall (read+write) accesses 2666system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179363 # number of overall (read+write) accesses 2667system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses 2668system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses 2669system.l2c.overall_accesses::cpu1.inst 21120 # number of overall (read+write) accesses 2670system.l2c.overall_accesses::cpu1.data 21128 # number of overall (read+write) accesses 2671system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11376 # number of overall (read+write) accesses 2672system.l2c.overall_accesses::total 372565 # number of overall (read+write) accesses 2673system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014547 # miss rate for UpgradeReq accesses 2674system.l2c.UpgradeReq_miss_rate::cpu1.data 0.048856 # miss rate for UpgradeReq accesses 2675system.l2c.UpgradeReq_miss_rate::total 0.018407 # miss rate for UpgradeReq accesses 2676system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.047125 # miss rate for SCUpgradeReq accesses 2677system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.039827 # miss rate for SCUpgradeReq accesses 2678system.l2c.SCUpgradeReq_miss_rate::total 0.043623 # miss rate for SCUpgradeReq accesses 2679system.l2c.ReadExReq_miss_rate::cpu0.data 0.736846 # miss rate for ReadExReq accesses 2680system.l2c.ReadExReq_miss_rate::cpu1.data 0.850127 # miss rate for ReadExReq accesses 2681system.l2c.ReadExReq_miss_rate::total 0.780171 # miss rate for ReadExReq accesses 2682system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for ReadSharedReq accesses 2683system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.024096 # miss rate for ReadSharedReq accesses 2684system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287811 # miss rate for ReadSharedReq accesses 2685system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146823 # miss rate for ReadSharedReq accesses 2686system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for ReadSharedReq accesses 2687system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.110180 # miss rate for ReadSharedReq accesses 2688system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.074786 # miss rate for ReadSharedReq accesses 2689system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for ReadSharedReq accesses 2690system.l2c.ReadSharedReq_miss_rate::total 0.488178 # miss rate for ReadSharedReq accesses 2691system.l2c.demand_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for demand accesses 2692system.l2c.demand_miss_rate::cpu0.itb.walker 0.024096 # miss rate for demand accesses 2693system.l2c.demand_miss_rate::cpu0.inst 0.287811 # miss rate for demand accesses 2694system.l2c.demand_miss_rate::cpu0.data 0.263258 # miss rate for demand accesses 2695system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for demand accesses 2696system.l2c.demand_miss_rate::cpu1.inst 0.110180 # miss rate for demand accesses 2697system.l2c.demand_miss_rate::cpu1.data 0.420769 # miss rate for demand accesses 2698system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for demand accesses 2699system.l2c.demand_miss_rate::total 0.507498 # miss rate for demand accesses 2700system.l2c.overall_miss_rate::cpu0.dtb.walker 0.059603 # miss rate for overall accesses 2701system.l2c.overall_miss_rate::cpu0.itb.walker 0.024096 # miss rate for overall accesses 2702system.l2c.overall_miss_rate::cpu0.inst 0.287811 # miss rate for overall accesses 2703system.l2c.overall_miss_rate::cpu0.data 0.263258 # miss rate for overall accesses 2704system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744797 # miss rate for overall accesses 2705system.l2c.overall_miss_rate::cpu1.inst 0.110180 # miss rate for overall accesses 2706system.l2c.overall_miss_rate::cpu1.data 0.420769 # miss rate for overall accesses 2707system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.533140 # miss rate for overall accesses 2708system.l2c.overall_miss_rate::total 0.507498 # miss rate for overall accesses 2709system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541 # average UpgradeReq miss latency 2710system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3228.174603 # average UpgradeReq miss latency 2711system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313 # average UpgradeReq miss latency 2712system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5203.389831 # average SCUpgradeReq miss latency 2713system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3923.913043 # average SCUpgradeReq miss latency 2714system.l2c.SCUpgradeReq_avg_miss_latency::total 4642.857143 # average SCUpgradeReq miss latency 2715system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072 # average ReadExReq miss latency 2716system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102 # average ReadExReq miss latency 2717system.l2c.ReadExReq_avg_miss_latency::total 127902.974210 # average ReadExReq miss latency 2718system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average ReadSharedReq miss latency 2719system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency 2720system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768 # average ReadSharedReq miss latency 2721system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201 # average ReadSharedReq miss latency 2722system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average ReadSharedReq miss latency 2723system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451 # average ReadSharedReq miss latency 2724system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143 # average ReadSharedReq miss latency 2725system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average ReadSharedReq miss latency 2726system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315 # average ReadSharedReq miss latency 2727system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency 2728system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2729system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency 2730system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency 2731system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency 2732system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency 2733system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency 2734system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency 2735system.l2c.demand_avg_miss_latency::total 119620.491347 # average overall miss latency 2736system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889 # average overall miss latency 2737system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency 2738system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768 # average overall miss latency 2739system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373 # average overall miss latency 2740system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571 # average overall miss latency 2741system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451 # average overall miss latency 2742system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586 # average overall miss latency 2743system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054 # average overall miss latency 2744system.l2c.overall_avg_miss_latency::total 119620.491347 # average overall miss latency 2745system.l2c.blocked_cycles::no_mshrs 873 # number of cycles access was blocked 2746system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2747system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked 2748system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2749system.l2c.avg_blocked_cycles::no_mshrs 109.125000 # average number of cycles each access was blocked 2750system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2751system.l2c.writebacks::writebacks 99972 # number of writebacks 2752system.l2c.writebacks::total 99972 # number of writebacks 2753system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 7 # number of ReadSharedReq MSHR hits 2754system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits 2755system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits 2756system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 2757system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits 2758system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 2759system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 2760system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits 2761system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits 2762system.l2c.CleanEvict_mshr_misses::writebacks 3644 # number of CleanEvict MSHR misses 2763system.l2c.CleanEvict_mshr_misses::total 3644 # number of CleanEvict MSHR misses 2764system.l2c.UpgradeReq_mshr_misses::cpu0.data 592 # number of UpgradeReq MSHR misses 2765system.l2c.UpgradeReq_mshr_misses::cpu1.data 252 # number of UpgradeReq MSHR misses 2766system.l2c.UpgradeReq_mshr_misses::total 844 # number of UpgradeReq MSHR misses 2767system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 118 # number of SCUpgradeReq MSHR misses 2768system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 92 # number of SCUpgradeReq MSHR misses 2769system.l2c.SCUpgradeReq_mshr_misses::total 210 # number of SCUpgradeReq MSHR misses 2770system.l2c.ReadExReq_mshr_misses::cpu0.data 11217 # number of ReadExReq MSHR misses 2771system.l2c.ReadExReq_mshr_misses::cpu1.data 8015 # number of ReadExReq MSHR misses 2772system.l2c.ReadExReq_mshr_misses::total 19232 # number of ReadExReq MSHR misses 2773system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadSharedReq MSHR misses 2774system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2775system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17879 # number of ReadSharedReq MSHR misses 2776system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9091 # number of ReadSharedReq MSHR misses 2777system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq MSHR misses 2778system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2318 # number of ReadSharedReq MSHR misses 2779system.l2c.ReadSharedReq_mshr_misses::cpu1.data 875 # number of ReadSharedReq MSHR misses 2780system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq MSHR misses 2781system.l2c.ReadSharedReq_mshr_misses::total 169828 # number of ReadSharedReq MSHR misses 2782system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses 2783system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2784system.l2c.demand_mshr_misses::cpu0.inst 17879 # number of demand (read+write) MSHR misses 2785system.l2c.demand_mshr_misses::cpu0.data 20308 # number of demand (read+write) MSHR misses 2786system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of demand (read+write) MSHR misses 2787system.l2c.demand_mshr_misses::cpu1.inst 2318 # number of demand (read+write) MSHR misses 2788system.l2c.demand_mshr_misses::cpu1.data 8890 # number of demand (read+write) MSHR misses 2789system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of demand (read+write) MSHR misses 2790system.l2c.demand_mshr_misses::total 189060 # number of demand (read+write) MSHR misses 2791system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses 2792system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2793system.l2c.overall_mshr_misses::cpu0.inst 17879 # number of overall MSHR misses 2794system.l2c.overall_mshr_misses::cpu0.data 20308 # number of overall MSHR misses 2795system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133589 # number of overall MSHR misses 2796system.l2c.overall_mshr_misses::cpu1.inst 2318 # number of overall MSHR misses 2797system.l2c.overall_mshr_misses::cpu1.data 8890 # number of overall MSHR misses 2798system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6065 # number of overall MSHR misses 2799system.l2c.overall_mshr_misses::total 189060 # number of overall MSHR misses 2800system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2801system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable 2802system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2803system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3093 # number of ReadReq MSHR uncacheable 2804system.l2c.ReadReq_mshr_uncacheable::total 44082 # number of ReadReq MSHR uncacheable 2805system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable 2806system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable 2807system.l2c.WriteReq_mshr_uncacheable::total 30915 # number of WriteReq MSHR uncacheable 2808system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2809system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses 2810system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2811system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5544 # number of overall MSHR uncacheable misses 2812system.l2c.overall_mshr_uncacheable_misses::total 74997 # number of overall MSHR uncacheable misses 2813system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13698000 # number of UpgradeReq MSHR miss cycles 2814system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5474500 # number of UpgradeReq MSHR miss cycles 2815system.l2c.UpgradeReq_mshr_miss_latency::total 19172500 # number of UpgradeReq MSHR miss cycles 2816system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3092000 # number of SCUpgradeReq MSHR miss cycles 2817system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2171500 # number of SCUpgradeReq MSHR miss cycles 2818system.l2c.SCUpgradeReq_mshr_miss_latency::total 5263500 # number of SCUpgradeReq MSHR miss cycles 2819system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1523361500 # number of ReadExReq MSHR miss cycles 2820system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 744148500 # number of ReadExReq MSHR miss cycles 2821system.l2c.ReadExReq_mshr_miss_latency::total 2267510000 # number of ReadExReq MSHR miss cycles 2822system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of ReadSharedReq MSHR miss cycles 2823system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 160000 # number of ReadSharedReq MSHR miss cycles 2824system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1775966000 # number of ReadSharedReq MSHR miss cycles 2825system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1033464000 # number of ReadSharedReq MSHR miss cycles 2826system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of ReadSharedReq MSHR miss cycles 2827system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 238288500 # number of ReadSharedReq MSHR miss cycles 2828system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 100021501 # number of ReadSharedReq MSHR miss cycles 2829system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of ReadSharedReq MSHR miss cycles 2830system.l2c.ReadSharedReq_mshr_miss_latency::total 18457620033 # number of ReadSharedReq MSHR miss cycles 2831system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of demand (read+write) MSHR miss cycles 2832system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 160000 # number of demand (read+write) MSHR miss cycles 2833system.l2c.demand_mshr_miss_latency::cpu0.inst 1775966000 # number of demand (read+write) MSHR miss cycles 2834system.l2c.demand_mshr_miss_latency::cpu0.data 2556825500 # number of demand (read+write) MSHR miss cycles 2835system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of demand (read+write) MSHR miss cycles 2836system.l2c.demand_mshr_miss_latency::cpu1.inst 238288500 # number of demand (read+write) MSHR miss cycles 2837system.l2c.demand_mshr_miss_latency::cpu1.data 844170001 # number of demand (read+write) MSHR miss cycles 2838system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of demand (read+write) MSHR miss cycles 2839system.l2c.demand_mshr_miss_latency::total 20725130033 # number of demand (read+write) MSHR miss cycles 2840system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1866500 # number of overall MSHR miss cycles 2841system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 160000 # number of overall MSHR miss cycles 2842system.l2c.overall_mshr_miss_latency::cpu0.inst 1775966000 # number of overall MSHR miss cycles 2843system.l2c.overall_mshr_miss_latency::cpu0.data 2556825500 # number of overall MSHR miss cycles 2844system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14605564664 # number of overall MSHR miss cycles 2845system.l2c.overall_mshr_miss_latency::cpu1.inst 238288500 # number of overall MSHR miss cycles 2846system.l2c.overall_mshr_miss_latency::cpu1.data 844170001 # number of overall MSHR miss cycles 2847system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 702288868 # number of overall MSHR miss cycles 2848system.l2c.overall_mshr_miss_latency::total 20725130033 # number of overall MSHR miss cycles 2849system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles 2850system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5805450500 # number of ReadReq MSHR uncacheable cycles 2851system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12497000 # number of ReadReq MSHR uncacheable cycles 2852system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362875500 # number of ReadReq MSHR uncacheable cycles 2853system.l2c.ReadReq_mshr_uncacheable_latency::total 6814067000 # number of ReadReq MSHR uncacheable cycles 2854system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles 2855system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5805450500 # number of overall MSHR uncacheable cycles 2856system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12497000 # number of overall MSHR uncacheable cycles 2857system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362875500 # number of overall MSHR uncacheable cycles 2858system.l2c.overall_mshr_uncacheable_latency::total 6814067000 # number of overall MSHR uncacheable cycles 2859system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2860system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2861system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses 2862system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses 2863system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses 2864system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses 2865system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses 2866system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses 2867system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses 2868system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses 2869system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses 2870system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses 2871system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses 2872system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses 2877system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses 2878system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses 2879system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses 2880system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses 2881system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses 2882system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses 2883system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses 2884system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses 2885system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses 2886system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses 2887system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses 2888system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses 2889system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses 2890system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses 2891system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses 2892system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses 2893system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses 2894system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses 2895system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses 2896system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses 2897system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency 2898system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency 2899system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency 2900system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency 2901system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency 2902system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency 2903system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency 2904system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency 2905system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency 2906system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency 2907system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency 2908system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency 2909system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency 2910system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency 2911system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency 2912system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency 2913system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency 2914system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency 2915system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency 2916system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2917system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency 2918system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency 2919system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency 2920system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency 2921system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency 2922system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency 2923system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency 2924system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency 2925system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency 2926system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency 2927system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency 2928system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency 2929system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency 2930system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency 2931system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency 2932system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency 2933system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency 2934system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency 2935system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency 2936system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency 2937system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency 2938system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency 2939system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency 2940system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency 2941system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency 2942system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency 2943system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter. 2944system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2945system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2946system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2947system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2948system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2949system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 2950system.membus.trans_dist::ReadReq 44082 # Transaction distribution 2951system.membus.trans_dist::ReadResp 214165 # Transaction distribution 2952system.membus.trans_dist::WriteReq 30915 # Transaction distribution 2953system.membus.trans_dist::WriteResp 30915 # Transaction distribution 2954system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution 2955system.membus.trans_dist::CleanEvict 16178 # Transaction distribution 2956system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution 2957system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution 2958system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 2959system.membus.trans_dist::ReadExReq 39788 # Transaction distribution 2960system.membus.trans_dist::ReadExResp 19211 # Transaction distribution 2961system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution 2962system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2963system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2964system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2965system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) 2966system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes) 2967system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes) 2968system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) 2969system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) 2970system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes) 2971system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2972system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2973system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) 2974system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes) 2975system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes) 2976system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2977system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2978system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes) 2979system.membus.snoops 123440 # Total snoops (count) 2980system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) 2981system.membus.snoop_fanout::samples 424426 # Request fanout histogram 2982system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram 2983system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram 2984system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2985system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram 2986system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram 2987system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2988system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2989system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2990system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2991system.membus.snoop_fanout::total 424426 # Request fanout histogram 2992system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks) 2993system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2994system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2995system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2996system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks) 2997system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2998system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks) 2999system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3000system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks) 3001system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3002system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks) 3003system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3004system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3005system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3006system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3007system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3008system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3009system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3010system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3011system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3012system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3013system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3014system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3015system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3016system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3017system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3018system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3019system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3020system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3021system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3022system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3023system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3024system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3025system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3026system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3027system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3028system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3029system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3030system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3031system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3032system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3033system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3034system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3035system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3036system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3037system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3038system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3039system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3040system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3041system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3042system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3043system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3044system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3045system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3046system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3047system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3048system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3049system.realview.ethernet.droppedPackets 0 # number of packets dropped 3050system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3051system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3052system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3053system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3054system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3055system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3056system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3057system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3058system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3059system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3060system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3061system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3062system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3063system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3064system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3065system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3066system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3067system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3068system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3069system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3070system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3071system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3072system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3073system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter. 3074system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3075system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3076system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter. 3077system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3078system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3079system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 3080system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution 3081system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution 3082system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution 3083system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution 3084system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution 3085system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution 3086system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution 3087system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution 3088system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution 3089system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution 3090system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution 3091system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution 3092system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution 3093system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution 3094system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution 3095system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes) 3096system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes) 3097system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes) 3098system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes) 3099system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes) 3100system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes) 3101system.toL2Bus.snoops 388372 # Total snoops (count) 3102system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes) 3103system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram 3104system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram 3105system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram 3106system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3107system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram 3108system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram 3109system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram 3110system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3111system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3112system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3113system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram 3114system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks) 3115system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3116system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks) 3117system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3118system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks) 3119system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3120system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks) 3121system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3122 3123---------- End Simulation Statistics ----------